Die stitching and harvesting of array structures

Abstract

This application relates to die stitching and harvesting of array structures. More specifically, the present invention describes a multi-die structure with die-to-die wiring. In one embodiment, each die is patterned into the same semiconductor substrate, and the dies can be interconnected with die-to-die wiring during back-end wafer processing. Partial metal seals can be formed to accommodate this die-to-die wiring, programmable dicing, and various combinations of full metal seals and partial metal seals can be formed. This can also be extended to three-dimensional structures formed using stacked wafers or chip-on-wafer technology.

Description

Technical Field

[0001] Embodiments described herein relate to integrated circuit (IC) fabrication and the interconnection of multiple dies. Background Art

[0002] Microelectronics manufacturing of ICs is typically performed using a sequence of deposition and patterning of circuit elements in a layer-by-layer sequence, where a stepper (or scanner) is used to pass light through the reticle, forming an image of the reticle pattern on the layer below. Rather than exposing the entire wafer, the stepper moves across the wafer from one die area location to another. This allows for higher resolution and critical dimensions to be achieved by working on a limited area. The die can then be cut from the wafer and further packaged.

[0003] A multi-chip module (MCM) is typically an electronic component in which multiple dies are integrated on a substrate. Various embodiments of MCM include 2D, 2.5D, and 3D packaging. Generally speaking, a 2D package module includes multiple dies arranged side by side on a package substrate. In 2.5D packaging technology, multiple dies are bonded to an interposer using microbumps. The interposer is then bonded to the package substrate. The interposer may include wiring for interconnecting adjacent dies. Therefore, the dies in a 2.5D package can be directly connected to the interposer and connected to each other through wiring within the interposer. Generally speaking, a 3D package module includes multiple dies stacked vertically on top of each other. Therefore, the dies in a 3D package can be directly connected to each other, with the bottom die directly connected to the package substrate. The top die in a 3D package can be connected to the package substrate using various configurations, including wirebonds and through-silicon vias (TSVs) passing through the bottom die.

[0004] Recently, U.S. Patent 10,438,896 proposed connecting adjacent dies formed on the same substrate via pin routing. Thus, die-to-die routing can be performed to connect adjacent die areas within the same substrate using the back-end-of-line (BEOL) stacking structure typically reserved for interconnecting individual dies. This allows for clusters of dies to be cut from the same wafer. Furthermore, these clusters can be larger than a single reticle. These clusters can then be integrated into various modules or semiconductor packages. Summary of the Invention

[0005] The present invention describes a multi-device structure in which devices including die and other components are harvested from an array structure. Adjacent devices within a harvested die set or component set can be co-located or connected together with die-to-die or component-to-component wiring. Partial metal seals can also be formed to accommodate die-to-die wiring or component-to-component wiring, and various combinations of full metal seals and partial metal seals can be formed. Programmable dicing technology can also be used to selectively scribe custom die / component sets at high density and is not limited to specific scribe line sizes or shapes. In addition, programmable dicing technology can also be used to scribe unique structures, where additional areas or structures can be included in the scribed die set adjacent to the partial metal seal to provide further protection from the environment (e.g., moisture, ions), stress, and microcracks. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A to Figure 1B is a schematic top-view layout plan view of a wafer including an array of front-end-of-line (FEOL) die areas with adjacent FEOL die areas interconnected with die-to-die wiring according to an embodiment.

[0007] Figure 1C is a schematic top-view layout plan view of a wafer including an array of FEOL die area sets interconnected with die-to-die wiring according to one embodiment.

[0008] Figure 2 is a schematic top view illustration of multiple adjacent FEOL die areas with die-to-die wiring extending through a portion of the metal seal ring around the FEOL die areas, according to an embodiment.

[0009] Figure 3 is a schematic cross-sectional side view illustration of a stitched die structure according to one embodiment.

[0010] Figure 4 is a schematic cross-sectional side view illustration of a chip including a stitched die structure according to one embodiment.

[0011] Figure 5A is a flow chart of a method of testing and scribing a die having preformed die-to-die routing extending through a portion of a metal seal ring, according to an embodiment.

[0012] Figure 5B is a schematic top view illustration of a die including scribed die-to-die routing according to one embodiment.

[0013] Figure 6A is a flow chart of a method of testing and scribing a die having a full metal seal ring according to an embodiment.

[0014] Figure 6Bis a schematic top view illustration of a die including a full metal seal ring according to one embodiment.

[0015] Figure 7 is a scaled schematic top view illustration of a multi-component device having connected co-located components according to one embodiment.

[0016] Figure 8A is a schematic cross-sectional side view illustration of a chip including a plurality of multi-component devices according to one embodiment.

[0017] Figure 8B is a schematic cross-sectional side view illustration of a package including a plurality of multi-component devices according to one embodiment.

[0018] Figure 9 is a schematic bottom view illustration of multiple multi-component devices mounted on the underside of a die or package according to one embodiment.

[0019] Figure 10 is a schematic top view illustration of an irregularly shaped, multi-component device mounted on the underside of a die or package according to one embodiment.

[0020] Figure 11 is a schematic top view illustration of an irregularly shaped multi-component device scribe area from a component wafer according to one embodiment.

[0021] Figure 12A is a schematic top-view illustration of a scaled multi-die set with co-located dies and dies connected with die-to-die wiring, according to one embodiment.

[0022] Figure 12B is a schematic top view illustration of multi-die set scaling with die-to-die routing according to one embodiment.

[0023] Figure 13A is a schematic top view illustration of a scaled multi-die set with co-located dies, dies connected with die-to-die wiring, and stacked dies, according to one embodiment.

[0024] Figure 13B is a schematic cross-sectional side view illustration of a stacked wafer stacked die set according to one embodiment.

[0025] Figure 13C is a schematic cross-sectional side view illustration of a chip including a stacked wafer stacked die set according to one embodiment.

[0026] Figure 13D is a schematic top view illustration of a set of chip stacked dies on a wafer according to one embodiment.

[0027] Figure 13E is a schematic top-view illustration of various possible outcomes for selecting a stitched die set on which to mount chips on a wafer, according to one embodiment.

[0028] Figure 13F is a schematic cross-sectional side view illustration of a package including a set of chip stacked die on a wafer according to one embodiment.

[0029] Figure 13G is a schematic cross-sectional side view illustration of a package including a set of chip stacked die on a wafer according to one embodiment.

[0030] Figure 14A is a schematic top-down diagram of a memory system with various examples of memory bandwidth and capacity scaling, according to one embodiment.

[0031] Figure 14B According to an embodiment Figure 14A Schematic cross-sectional side view illustration of a memory system.

[0032] FIG. 15A to FIG. 15B is a close-up schematic top view illustration of harvesting networking dies from a wafer, according to an embodiment.

[0033] Figure 15C is a close-up schematic top view illustration of a set of network die areas according to one embodiment.

[0034] Figure 15D is a close-up schematic top view illustration of an array of network dies on a wafer according to one embodiment.

[0035] Figure 15E is an illustration of a module including multiple logic chips arranged around a harvested single die set network chip, according to one embodiment.

[0036] Figure 15F is an illustration of a module including multiple logic chips arranged around a harvested multi-die set network chip, according to one embodiment.

[0037] Figure 15G is a schematic top view layout plan of harvesting network dies from a wafer according to one embodiment.

[0038] Figure 15H is a schematic top-view illustration of a die set including multiple network dies, according to one embodiment.

[0039] Figure 16A is a schematic top view illustration of logic and memory scaling with stitched interface strips according to one embodiment.

[0040] Figure 16B is a schematic top view illustration of a scribed interface bar according to one embodiment.

[0041] Figure 16C is a schematic cross-sectional side view illustration of a stitched interfacing strip according to one embodiment.

[0042] Figure 17A is a schematic cross-sectional side view illustration of a module including multiple dies mounted on an interposer having connection routing areas according to one embodiment.

[0043] Figure 17B is a schematic top view illustration of a scribe line area on an interposer substrate having a connection routing area according to one embodiment.

[0044] Figure 18 is a flow chart of a method of testing and scribing dies using programmable dicing, according to an embodiment.

[0045] Figure 19A is a schematic top view illustration of a set of dies before scribing, wherein the set of FEOL die areas are interconnected with die-to-die wiring through a partial metal seal ring, according to one embodiment.

[0046] Figure 19B is a schematic top view illustration of scribe lines through die-to-die routing between adjacent FEOL die areas according to one embodiment.

[0047] Figure 20A is a schematic top view illustration of a die set before scribing, wherein service structures are positioned in the unscribed scribe area between adjacent FEOL die areas, according to one embodiment.

[0048] Figure 20B is a schematic top view illustration of a scribe-line die set according to one embodiment, wherein service structures are positioned in scribe-line regions between adjacent FEOL die areas.

[0049] Figure 21 is a schematic top view illustration of a set of scribed dies, according to one embodiment, with scribe lines on opposite sides of input / output regions of adjacent FEOL die areas.

[0050] Figure 22 is a schematic side view illustration of a chip mounted on a wiring substrate including overlying bond pads according to one embodiment.

[0051] Figure 23 According to one embodiment, a device comprising a circuit board mounted on a wiring substrate Figure 21Schematic side view illustration of a chip of a scribed die set with conductive bumps located under additional input / output areas. DETAILED DESCRIPTION

[0052] The embodiments describe a multi-device structure obtained by harvesting an array structure and co-locating adjacent devices or using stitching technology to connect adjacent devices. The harvesting can include slicing the number of units required, or even having more units than required, and accepting one or more failed units. In addition, redundancy can be added by including one or more additional units (bare die) or complete subsystems. In the event of a unit failure, the good unit can be exchanged. Redundancy can be at the time of manufacturing or can be exchanged in the field. Various applications include harvesting engines such as graphics processing units (GPUs), central processing units (CPUs), signal processing engines, neural engines (e.g., neural network processing engines), artificial intelligence (AI) engines, networks, caches, etc.; memory devices such as static random access memory (SRAM), magnetic random access memory (MRAM), non-volatile random access memory (NVRAM), dynamic random access memory (DRAM), NAND and cache memory; other components such as capacitors, inductors, resistors, power management integrated circuits (ICs), etc., including interface strips for logic or memory expansion, and interposer substrates. Array harvesting can also be extended to other applications, including solar energy, displays, probe pin arrays for automated test equipment (ATE), field-programmable gate arrays (FPGAs), and more.

[0053] In one aspect, embodiments describe a multi-die structure that includes a combination of partial metal seals (e.g., partial metal seal rings) and full rings around certain edges or over front-end-of-line (FEOL) die areas. In this way, partial metal seals can be positioned in areas where die-to-die or component-to-component interconnects can be achieved, while full metal seals or metal seal rings can be located around edges where such connections are not desired. According to some embodiments, die-to-die wiring (interconnects) or component-to-component wiring (interconnects) can be pre-formed and then the desired set of dies can be scribed from the source wafer. Scribing can optionally include cutting through the die-to-die wiring.

[0054] On the other hand, embodiments describe programmable dicing techniques where conventional dicing techniques such as blade sawing will not work. For example, this may include laser assisted dicing or chemical etching dicing flows to carve out specific die set areas that may also be irregularly shaped. The laser technology may be ablation based (evaporating material) or stealth (damaging the semiconductor wafer and then breaking it). The chemical may be wet etching or plasma etching, especially if the semiconductor wafer (silicon) is deep (e.g., greater than 50 μm). Therefore, such programmable dicing techniques may be beneficial for harvesting array structures. In addition, such programmable dicing techniques may be beneficial for dicing through unconventional FEOL die areas. For example, dicing may be performed through a portion of the adjacent FEOL die area of ​​the die to be discarded in order to increase the chip edge to active area distance of the harvested die and provide further protection against moisture, ions, cracks, where a partial metal sealing ring may be present.

[0055] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and constructions. In the following description, many specific details such as specific configurations, dimensions, and processes are shown to provide a thorough understanding of the embodiments. In other cases, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. References to "one embodiment" throughout the specification refer to specific features, structures, constructions, or characteristics described in conjunction with the embodiments being included in at least one embodiment. Therefore, the phrase "in one embodiment" appearing in multiple places throughout the specification does not necessarily refer to the same embodiment. In addition, specific features, structures, constructions, or characteristics may be combined in one or more embodiments in any appropriate manner.

[0056] As used herein, the terms "on," "over," "to," "between," "spanning," and "over" may refer to the relative position of one layer relative to other layers. A layer that is "on," "over," "spanning," or "on" relative to another layer, or bonded "to," or "in contact with" another layer may be directly in contact with the other layer or may have one or more intervening layers. A layer that is "between" multiple layers may be directly in contact with the multiple layers or may have one or more intervening layers.

[0057] Now see the attached Figure 1A to Figure 1B , provides a schematic top view layout plan view of a wafer 102 (e.g., silicon) including an array of dies 104, wherein adjacent FEOL die areas 110 of the dies 104 may be interconnected with die-to-die wiring 130. Figure 1A to Figure 1B) may include different circuit blocks from one another. Each die region 110 may represent a complete system or a subsystem. Adjacent die regions 100 may perform the same or different functions. As a non-limiting example, in one embodiment, the die regions 110 interconnected by die-to-die wiring may include a digital die region that is bundled with a die region utilizing another function, such as analog, wireless (e.g., radio frequency, RF), or wireless input / output. The bundled die regions 110 may be formed using the same processing node, regardless of whether they have the same or different functions. Regardless of whether each die 104 and die region 110 comprises a complete system or a bundled subsystem, the die-to-die wiring 130 may be inter-die wiring (different systems) or intra-die wiring (different or the same subsystem within the same system). For example, the intra-die-to-die wiring may connect different subsystems within a system on chip or a SOC, where the inter-die-to-die wiring may connect different SOCs, but this is illustrative and embodiments are not limited to SOCs.

[0058] In accordance with an embodiment, any or all FEOL die area edges may be configured to include die-to-die wiring 130. In addition, each FEOL die area 110 may be surrounded by a metal seal 122 (e.g., a metal seal ring), which may be a partial metal seal or a full metal seal. In an embodiment, a partial metal seal (or partial metal seal ring) may be provided around or over the edge of the FEOL die area where die-to-die wiring 130 may be formed. Figure 1A As shown, the dicing or scribing lanes can be located anywhere to accommodate yield (e.g., bad die) or demand (e.g., a larger die set is required). Figure 1B As shown, harvesting techniques according to embodiments can be advantageously used to improve wafer utilization and harvest more dies or components. This can be achieved, for example, by being able to harvest sets of dies of different or irregular shapes and utilizing programmable dicing methods. It should be understood that while the following description specifically relates to interconnecting adjacent FEOL die regions with die-to-die wiring 130, such configurations are also applicable to interconnecting adjacent component regions with component-to-component wiring.

[0059] Figure 1C is a schematic top view layout plan view of a wafer including an array of pre-arranged die sets 100 interconnected with die-to-die wiring 130 according to one embodiment. Figure 1A to Figure 1B The array of FEOL chip areas 110 shown in FIG. 1 allows for complete flexibility by scribing any combination of interconnected sets of dies, but such as Figure 1CThe illustrated embodiment also contemplates the arrangement of specific die sets connected using die-to-die wiring. In such an embodiment, a full metal seal ring 122B may be provided around the die set 100, while a partial metal seal 122A may be provided between adjacent FEOL die areas 110 within the die set 100. Such a configuration may allow for a fully metal sealed scribed die set while still allowing the flexibility of scribing with die-to-die wiring 130 between adjacent FEOL die areas to facilitate improved wafer utilization. For example, such scribing may be performed to harvest a single die 104 in the die set 100, remove bad die 104, or harvest irregularly shaped or custom quantities of die 104. Figure 1A compared to, Figure 1C The embodiment shown in FIG can be within the reticle for smaller systems. Staying within the reticle allows for simpler stitching interconnects. Slices can also be routed die-to-die 130 between die areas.

[0060] To illustrate the flexibility of integrated partial and full metal seals, refer to Figure 2 As shown, die-to-die wiring 130 may extend through partial metal seals 122A between adjacent FEOL die regions 110A, 110B, 110C, 110D of the dies 104A, 104B, 104C, 104D, and full metal seals 122B may optionally be arranged near the edges of the FEOL die regions 110A, 110B, 110C, 110D that are not interconnected with the die-to-die wiring 130. Each die may include a FEOL die region that includes a device region 112 and one or more input / output regions 114. Metal seals according to embodiments may provide physical protection (e.g., against the environment (e.g., moisture, ions), stress, microcracks, delamination) and / or electrical protection (e.g., electromagnetic interference, electrostatic discharge). Thus, a partial metal seal 122A may be incorporated to provide design flexibility for interconnected die sets, while a full metal seal 122B may be incorporated to provide more robust physical and / or electrical protection to the die set 100 .

[0061] Figure 2 It is also shown that the die set 100 may include dies having different shapes (eg, different sizes of FEOL die areas 110) and the same or different die types and functions. Figure 1A to Figure 1BAs described above, the individual FEOL die regions 110A, 110B, 110C, 110D and dies 104A, 104B, 104C, 104D may include circuit blocks that are different from each other. Each die region may represent a complete system or subsystem. Adjacent die regions may perform the same or different functions. As a non-limiting example, in one embodiment, the die regions 110A, 110B (e.g., interconnected with die-to-die wiring) may include a digital die region that is bundled to the die region using another function (such as analog, wireless (e.g., radio frequency, RF) or wireless input / output). Regardless of whether they have the same or different functions, the bundled die regions can be formed using the same processing node. Regardless of whether each die and die region comprises a complete system or a bundled subsystem, the die-to-die wiring 130 can be inter-die wiring (different systems) or intra-die wiring (different or the same subsystem within the same system). For example, die-to-intra-die wiring can connect different subsystems within a system on chip, an SOC, where die-to-inter-die wiring can connect different SOCs, but this is exemplary and the embodiments are not limited to SOCs. In one embodiment, the die set 100 includes digital and analog or wireless die areas 110. In one embodiment, the different dies 104 with the die set 100 can include multiple engines, such as graphics processing units (GPUs), central processing units (CPUs), neural engines (such as neural network processing engines), artificial intelligence (AI) engines, signal processors, networks, caches, and combinations thereof. However, the embodiments are not limited to engines and may include memory devices such as SRAM, MRAM, DRAM, NVRAM, NAND, cache memory, or other components such as capacitors, inductors, resistors, power management integrated circuits (ICs), etc.

[0062] Now refer to Figure 3 Combine Figure 2 , provides a schematic cross-sectional side view illustration of a stitched die structure according to one embodiment. As shown, each FEOL die region 110A, 110B is formed in the same (semiconductor) substrate 101, such as a silicon wafer. Each FEOL die region 110A, 110B may include active and passive devices of the die. A back-end of the line (BEOL) stacking structure 120 is then formed above the semiconductor substrate 101 to provide electrical interconnects and metal sealing structures. The BEOL stacking structure 120 generally meets the connectivity requirements of the die. According to an embodiment, the connectivity of the BEOL stacking structure 120 is expanded to connect different dies. The BEOL stacking structure 120 can be manufactured using conventional materials, including metal wiring layers (e.g., copper, aluminum, etc.) and insulating interlayer dielectrics (ILDs), such as oxides (e.g., silicon oxide, carbon-doped oxide, etc.), nitrides (e.g., silicon nitride), low-k materials, etc.

[0063] The die-to-die wiring 130 may include die wiring 135 from each die connected to the stitching wiring 136. According to an embodiment, the die wiring 135 may be formed by one or more vias 132 and metal layers 134 within the BEOL stacking structure 120. In the specific embodiment shown, the die-to-die wiring 130 includes multiple wirings formed within multiple metal layers. According to an embodiment, the die-to-die wiring 130 may be formed within the lower metal layer M_low, the upper metal layer M_high, the middle level metal layer M_mid, and combinations thereof. Generally speaking, the lower metal layer M_low has a finer line width and spacing. In addition, the interlayer dielectric (ILD) for the lower metal layer and the middle level metal layer may be formed of a low-k material, which allows for faster moisture transport. Therefore, when using finer wiring layers, according to an embodiment, additional precautions may be taken, such as passivation of the edges of the sliced ​​chips. This may be due to the connections being made between devices. The upper metal layer M_high may have a coarser line width and line spacing, wherein the middle level metal layer M_mid has an intermediate line width and spacing. In one embodiment, the upper metal layer M_high may be used primarily for die-to-die wiring 130 for lower resistance wiring and potentially for greater flexibility to form a customized die set with dynamic die-to-die wiring 130 after testing. According to an embodiment, the die-to-die wiring 130 extends through one or more openings 123 in the partial metal seal 122A to electrically connect the die 104. The BEOL stacking structure 120 may additionally include a plurality of contact pads 140, such as but not limited to under bump metallurgy pads, which may be electrically connected to the first die 104A and the second die 104B, and optionally the metal seals 122A, 122B.

[0064] Still see Figures 2 to 3 , a die set 100 including a stitched multi-die structure according to an embodiment may include a first front-end-of-line (FEOL) die region 110A of a first die 104A patterned into a semiconductor substrate 101 and a second FEOL die region 110B of a second die 104B patterned into the semiconductor substrate 101, wherein the second FEOL die region 110B is separated from the first FEOL die region 110A. The first FEOL die region may include a first input / output region 114, and the second FEOL die region may include a second input / output region 114. The BEOL stacking structure 120 further spans the first FEOL die region 110A and the second FEOL die region 110B. As these two Figures 2 to 3As shown, the first partial metal seal 122A may be adjacent to the first input / output region 114 of the first FEOL die region 110A, and the second partial metal seal 122A may be adjacent to the second input / output region 114 of the second FEOL die region 110B. Figure 2 and Figure 3 As shown, die-to-die wiring 130 connects the first input / output area 114 and the second input / output area 114 and extends through a first opening 123 in the first partial metal seal 122A and a second opening 123 in the second partial metal seal 122A. In one embodiment, opening 123 is a lateral opening. For example, opening 123 can be similar to a door opening in a fence. In one embodiment, opening 123 is a vertical opening. For example, for illustrative purposes, opening 123 can be similar to a window between the floor and ceiling in a wall, or similar to an open kitchen serving counter. Opening 123 can have different shapes, as well as a combination of lateral and vertical characteristics.

[0065] like Figure 2 As shown, each die 104 may include a partial metal seal 122A adjacent to a portion or side / perimeter of the die, adjacent to multiple sides, or around all sides. Each die 104 may include a combination of full metal seals 122B and partial metal seals 122A to accommodate die-to-die wiring 130. In addition, a larger full metal seal 122B may be formed around multiple dies, such as in Figure 1C , wherein a full metal seal ring 122B is provided around the die set 100, while a partial metal seal 122A is provided between adjacent FEOL die areas 110 within the die set 100 that may be stitched together. Various combinations are possible.

[0066] Figure 4 is a schematic cross-sectional side view illustration of a chip 150 including a stitched die structure according to one embodiment. The specific embodiment shown includes similar Figure 3 and Figure 1C The die set 100 may be sliced ​​from a semiconductor wafer 102. The chips 150 may be further packaged, or a plurality of conductive bumps (eg, solder) 142 may be provided to the contact pads 140. Figure 4 The diagram is different from Figure 3 , and shows a more conventional damascene structure for vias 132 and metal layers 134 within the BEOL buildup structure 120. Additionally, vertical openings 123 are shown within the partial metal seal 122A to accommodate die-to-die wiring 130.

[0067] Figure 5Ais a flow chart of a method of testing and scribing a die having preformed die-to-die wiring 130 extending through a portion of the metal seal 122A according to an embodiment. Figures 1A to 1C and Figure 2 , an exemplary arrangement is provided with different arrangements of partial metal seals 122A and full metal seals 122B. In an exemplary manufacturing sequence of operation 5010, the BEOL stacking structure 120 is formed to include pre-formed die-to-die wiring 130 extending through the partial metal seal 122A. The individual dies 104 can then be tested in operation 5020. Testing can be performed at the wafer level using a contact circuit probe with die test pads, which can be interspersed with contact pads 140. In this arrangement, the partial metal seal 122A can allow connectivity between the die and the test engine on the wafer to enhance testing. According to an embodiment, testing can be used to merge dies into groups, for example, to identify good and bad die clusters. Then, at operation 5030, the set of dies 100 within the good cluster can be dynamically divided into designated stitched die structures.

[0068] Until this time, Figure 2 and 3 The illustrated die set 100 does not show scribing through the die-to-die wiring 130. However, scribing or cutting may also be performed through the die-to-die wiring 130 when scribing the die set 100 or the individual dies 104. Figure 5B is a schematic top view illustration of a chip 150 including harvested dies 104 with scribed die-to-die wiring 130 according to one embodiment. Figure 5B As shown, scribing may be accompanied by cutting through the die-to-die wiring 130, or more specifically cutting through the stitch wiring 136, or optionally cutting through the die wiring 135, or both. The scribing performed through the die-to-die wiring 130 may then result in the terminal ends 137 of the die-to-die wiring (which are now not connected between the dies), which will therefore be along the sliced ​​edge 152 of the resulting chip 150 or package. However, since this cut portion of the die-to-die wiring 130 will not be used, this may not affect the performance of the stitched die 104. In one embodiment, the cut die-to-die wiring 130 lines (and associated power networks) are electrically isolated. Isolation may include being tri-stated, or otherwise disconnected from the core circuitry of the die. After slicing, the die 104 or die set 100 can be further integrated into discrete chips 150 or subjected to further packaging sequences.

[0069] In one embodiment, the chip 150 structure may include a semiconductor substrate 101, a first FEOL die region 110 (eg, 110A, 110B) of a first die 104 patterned into the semiconductor substrate 101, and a second FEOL die region 110 (eg, 110A, 110B) of a first die 104 patterned into the semiconductor substrate 101. Figure 2), wherein the first FEOL die region 110 includes a first device region 112 and a first input / output region 114. The BEOL stacking structure 120 spans the first device region 112 and the first input / output region 114, and the chip edge 152 is adjacent to the first input / output region 114. In this example, it can be assumed that the dicing is performed at Figure 2 According to an embodiment, the BEOL stacking structure 120 includes a die-to-die wiring 130 connected between the first input / output region 114 at the chip edge 152 and the terminal end 137 of the die-to-die wiring 130 (see Figure 5B In one embodiment, the first input / output region 114 connected to the die-to-die wiring 130 is isolated in the off state. Isolation can include being tri-stated or otherwise disconnected from the core circuitry of the die. As shown, the BEOL stacking structure 120 can include a first partial metal seal 122A adjacent to the first input / output region 114, wherein the die-to-die wiring 130 extends through a first opening 123 in the first partial metal seal 122A.

[0070] Die-to-die wiring 130 may be included along one, multiple, or all die edges. In one embodiment, the second FEOL die region 110 (e.g., 110C, Figure 2 ) may also be patterned into the same semiconductor substrate 101, wherein the second FEOL die region 110 includes a second device region 112 and a second input / output region 114. In one embodiment, the first FEOL die region 110 (e.g., 110A) includes the third input / output region 114, and the BEOL stacking structure 120 spans the second FEOL die region 110 (e.g., 110C), the second input / output region 114, and the third input / output region 114, and the BEOL stacking structure 120 further includes a second die-to-die wiring 130 connected between the second input / output region and the third input / output region. Furthermore, a second partial metal seal 122A may be adjacent to the second input / output region 114, and a third partial metal seal 122A may be adjacent to the third input / output region 114, wherein the second die-to-die wiring 130 extends through a second opening 123 in the second partial metal seal 122A and through a third opening 123 in the third partial metal seal 122A.

[0071] Thus far, embodiments have been described in which the die-to-die wiring 130 and the metal seal are pre-formed. In an alternative processing sequence, the custom seal ring can be formed after die testing. Figure 6Ais a flow chart of a method of testing and scribing a die having a full metal seal 122B according to an embodiment. Figure 6B is a schematic top view illustration of a die 104 including a full metal seal 122B according to one embodiment, which may be used Figure 6A At operation 6010, only a portion of the BEOL stacking structure 120 is formed. That is, a significant portion of the metal wiring is formed, but processing has not yet continued to the point of fabricating the bond pads. At this stage, the metal wiring has not yet been processed to the extent of conventional wafer testing methods. In operation 6020, clusters of dies are merged (e.g., identified as good or bad) based on process data. For example, the process data may be based on early electrical test data from the front-end of the line (FEOL) and / or early BEOL manufacturing stages, optical test data, and yield trends of wafer die locations. The data may include electrical test or optical inspection data. For example, the electrical test data may include probing (touch) tests to determine the electrical quality of transistors or interconnects, simple circuits (e.g., ring oscillators, etc.). Probing touch tests may be accompanied by subsequent cleaning / repair operations. Non-contact testing may also be used to merge dies. Exemplary non-contact testing methods include optical inspection, systematic (e.g., wafer maps), and historical trends, as well as project yields for identifying sets of dies. Contactless testing may include radio frequency or optical probes, or probing at a remote location using a test signal propagated to the die under test. Based on this information, the formation of the BEOL stacking structure 120 is completed at operation 6030 to include die-to-die wiring 130 between the designated die sets. The die 104 within the bad cluster may not be interconnected. Specifically, the stitching wiring 136 may not be formed over the pre-formed die wiring 135, as shown in FIG. Figure 6B As shown, the preformed die wiring can remain unconnected and buried inside the BEOL buildup structure 120. In some embodiments, the full metal seal 122B surrounds only the designated die set or die sets that will become the stitched die sets 100 in operation 6040. Figure 6B The single die set shown is formed. In this way, the unoriented layers of the BEOL buildup structure 120 can then be used to form customized metal seals, wiring, and die sets. The die set 100 is then scribed at operation 6050.

[0072] The harvesting method according to the embodiment can be used to integrate various array structures of other components that can be active or passive, such as capacitors, inductors, resistors, power management integrated circuits (ICs), etc., including interface strips for logic or memory expansion. Active structures include silicon-based structures as well as other types of materials suitable for electronic devices, such as GaAs, InP, etc. Array harvesting can also be extended to other applications, including solar energy, displays, probe pin arrays for automated test equipment (ATE), field programmable gate arrays (FPGAs), etc.

[0073] Figure 7 is a scaled schematic top view illustration of a multi-component device with connected / stitched co-located components 210 according to one embodiment. Figure 7 The general idea is similar to Figures 1A to 1C , wherein a multi-component device 200 is shown that can be harvested from a substrate that includes an array of components 210. Similarly, the components can have pre-made component-to-component wiring 230, or can have custom component-to-component wiring as previously described in conjunction with the die set 100. Multiple components 210 can be interconnected in the multi-component device 200 using component-to-component wiring 230, for example for capacity scaling. For example, where the components 210 are passive devices such as resistors, capacitors, or inductors, the components 210 can be appropriately connected to obtain desired characteristics (e.g., connecting capacitors in parallel to increase capacitance). Physical characteristics such as aspect ratio or other desired non-rectangular shapes may be feasible. Similarly, other passive characteristics can be appropriately tailed, such as inductance, resistance, etc. In such an embodiment, the multi-component device 200 may have a shared terminal 205 (see Figures 8A to 8B ) for mounting on a chip or package having microbumps 190. Alternatively, each of the components 210 may be co-located and not electrically connected to each other. In this case, the components 210 within the multi-component device 200 may each have its own terminals 205. As shown, component harvesting can be used to select different sizes or shapes of components and component sets.

[0074] Now see Figure 8A , provides a schematic cross-sectional side view illustration of chip 150, such as previously described with respect to Figure 4 The chip includes a plurality of multi-component devices 200 according to embodiments. As shown, the multi-component devices 200 can be mounted on the underside 121 of the BEOL stacking structure 120 adjacent to the conductive bumps 142. The multi-component devices 200 can have different sizes and / or shapes depending on their functions. For example, the size and shape can be selected based on the function, capacity, or matching area of ​​the circuit blocks (also known as intellectual property (IP) blocks or functional blocks) within the chip.

[0075] Figure 8B is a schematic cross-sectional side view illustration of a package 250 including a plurality of multi-component devices 200 according to one embodiment. In the exemplary embodiment shown, the package 250 may include one or more chips 150 encapsulated in a molding compound layer 160. A redistribution layer (RDL) 170 may then be formed over the active sides of the chips 150 and the molding compound layer 160. The redistribution layer may include a plurality of dielectric layers 173 and electrical routing layers 175 (e.g., copper, aluminum, etc.) and a plurality of bonding pads 172 on the underside 171 of the RDL 170. Similar to Figure 8A In the chip 150 structure, one or more multi-component devices 200 may be mounted on the underside 171 of the RDL 170 adjacent to conductive bumps 174 (eg, solder bumps).

[0076] Figure 9 2 is a schematic bottom view illustration of a plurality of multi-component devices 200 mounted on the underside 121, 171 of a chip 150 or package 250 according to an embodiment. As shown, each multi-component device 200 can be of different size or shape. Each multi-component device 200 can further include a set of co-located components 210, which can be connected together or not.

[0077] In an embodiment, an electronic structure (e.g., a chip, a package) includes a wiring layer (e.g., a BEOL stack-up structure 120 or an RDL 170), and one or more dies on the top side of the wiring layer. For example, the dies may be within one or more chips 150. A plurality of conductive bumps 142, 174 are on the underside of the wiring layer, and a multi-component device 200 is bonded to the underside of the wiring layer, laterally adjacent to the plurality of conductive bumps. According to an embodiment, the multi-component device 200 includes a plurality of co-located components 210. Each component 210 may optionally be formed in the same substrate, such as the silicon wafer 102 used for the FEOL die area 110 described previously. In one embodiment, each component 210 in the plurality of co-located components includes separate (distinct) terminals. In one embodiment, the plurality of co-located components includes component-to-component wiring 230. In one embodiment, the components 210 may be passive components, such as capacitors, inductors, or resistors. The components 210 may be other devices, such as a power management IC.

[0078] Now see Figure 10, provides a schematic top view illustration of an irregularly shaped multi-component device 200 mounted on the underside of a die or package, according to an embodiment. As shown, the FEOL die area 110 of the die or die within the package may include multiple circuit blocks 151 to perform different functions. According to an embodiment, the components 210 may be harvested to a specific shape or size to accommodate or fit within the area of ​​a designated circuit block 151, which may have an irregular shape (e.g., non-rectangular). In this way, the multi-component device 200 does not have to overlap with the area of ​​adjacent circuit blocks. In one embodiment, the multi-component device 200 is bonded to the underside of a wiring layer below a circuit block, the circuit block having an area equivalent to the non-rectangular area of ​​the multi-component device 200. In a specific embodiment, the multi-component device 200 includes multiple power management ICs below a high-power consuming circuit block (such as a CPU, GPU, etc.). Therefore, when stitched together, each additional component 210 can be used to provide additional current flow to the corresponding circuit block. Therefore, additional current sources can be scaled by stitching multiple components 210 together. In the exemplary embodiment shown, the circuit block and corresponding multi-component device 200 have an L-shape, but this is provided for illustrative purposes and multi-component devices 200 according to embodiments may take on a variety of irregular shapes. Figure 11 is a schematic top view illustration of a method for harvesting an irregularly shaped multi-component device 200 from a component substrate (eg, wafer) 202, according to an embodiment.

[0079] Again a brief reference Figure 7 , the general principles of device scaling apply to all implementations. Figure 12A FIG2 is a schematic top view of a scaled representation of a multi-die set 100 having co-located dies 104 and die 104 connected with die-to-die wiring 130, according to an embodiment. By way of example, the following description is provided with respect to a memory application, but this is intended to be exemplary and the embodiments are not limited thereto. As shown, the harvesting technique can be used to harvest die sets 100 to expand capacity and / or bandwidth in a memory environment. This is applicable to a variety of memory applications, such as SRAM, MRAM, DRAM, NVRAM, NAND, cache memory, and the like. As shown, each die 104 can include a FEOL die area, which includes a device area 112 and one or more input / output areas 114. Capacity can be increased by stitching a series of die 104 together using die-to-die wiring 130. Bandwidth can be increased by including additional rows of die 104 within a die set 104. In this way, the capacity and bandwidth of a particular die set 100 can be harvested from a wafer 102 (or wafer stack) to meet product requirements, and multiple product requirements can be harvested from the same source wafer 102.

[0080] Although die-to-die wiring 130 is shown only within a row of dies 104, it should be understood that die-to-die wiring 130 may also be included vertically between dies 104 in different rows, for example, as initially described in FIG. Figure 1A Furthermore, the harvesting techniques described herein are not limited to a particular arrangement of die 104 or area having a fixed row / column ratio. It should be understood that Figure 12A The particular illustration in FIG shows an input / output region 114 on a single side of the die 104. This may represent the general direction of placement of external output logic. However, the input / output region 114 may be located at other die edges, and in particular, where there is die-to-die wiring 130. Thus, Figure 12A The simplified illustrations in the other similar figures herein should be understood to illustrate the potential directionality of the stitching structure, not the absence of the input / output region 114. Depending on the embodiment, the dies, die-to-die wiring 130, partial metal seals, and full metal seals can be designed for flexibility in harvesting. For example, a 1x die (with its own input / output region) can be harvested to multiple dies. For example, in Figure 12A In the embodiment shown, this can include 2x dies (each die having its own input / output area for external communication), or a single input / output area for external communication of the die set. In both cases, the 2x dies are connected internally. Similarly, Figure 12A This extension is shown for 4x dies that are connected internally.Various arrangements are possible for selecting which input / output regions are used for external communications with the set of connected dies.

[0081] Figure 12B is a schematic top view illustration of scaling a multi-die set with die-to-die routing, according to one embodiment. In this embodiment, capacity can be increased by stitching together multiple dies 104 in the same column rather than in a row. In this case, the input / output area 114 can be closed, allowing the lower die 104 to be configured to communicate with an external controller through, for example, the upper die 104. Thus, a variety of size and area arrangements are possible.

[0082] According to an embodiment, capacity may also be increased through vertical stacking of dies 104 . Figure 13A is a schematic top view illustration of a scaled multi-die set with co-located dies, dies connected with die-to-die wiring, and stacked dies, according to one embodiment. Figure 13A Basically similar to Figure 12A, in which stacked dies 104 are added to increase capacity. In addition, various die-to-die wiring 130 configurations are possible. For schematic illustration, die-to-die wiring 130 is shown between the topmost die 104. According to the embodiment, die-to-die wiring 130 can also be provided between adjacent dies 104 (row and / or column) within the same die level. In the exemplary embodiment shown, there are four die levels. Therefore, the die 104 within each die level can be connected to each other using die-to-die wiring 130. The die 104 within different die levels can also be connected to each other in various ways, depending on the die stacking manufacturing technology implemented, such as stacked wafer (WoW) and chip on wafer (CoW). As previously described, the stacked die area 110 and the die 104 may include different circuit blocks from each other. Each die area can represent a complete system or subsystem. Adjacent die areas can perform the same or different functions.

[0083] Figure 13B is a schematic cross-sectional side view of a WoW stacked die set 100 according to one embodiment. Figure 13C is a schematic cross-sectional side view illustration of a chip 150 including a WoW stacked die set according to one embodiment. Figures 13B to 13C Similar to Figures 3 and 4 , where a WoW stacked die set is added. In such an embodiment, multiple wafers may be processed to include an array of FEOL die regions 110 and BEOL stacked structures 120. The wafers may then be bonded front to back, face to face, or back to back (e.g., hybrid). Figure 13B In the illustrated embodiment, wafers are bonded from the backside to the frontside, with the semiconductor substrate 101 of the first wafer bonded to a BEOL stacking structure 120 formed on a second wafer. The first semiconductor substrate 101 and the first BEOL stacking structure 120 together can form a first die level 111, and the second semiconductor substrate 101 and the second BEOL stacking structure can form a second die level 113. This process can be repeated to provide additional die levels. Furthermore, different combinations of front-to-back, face-to-face, or back-to-back bonding are contemplated.

[0084] WoW bonding according to the embodiment may include hybrid bonding, which may include both oxide-oxide and metal-metal bonding interfaces. Thus, the oxide layer on the back side of the first semiconductor substrate 101 may be bonded to the oxide layer in the second BEOL stacking structure 120. In addition, the metal contact pads 140 of the second BEOL stacking structure may be bonded to the metal contact pads 119 on the back side of the first semiconductor substrate 101. In addition, the semiconductor substrate 101 may include through-silicon vias 117, which may be connected to the contact pads 119 to accommodate vertical interconnection. Similar to the previous description, WoW and CoW die stacking can be harvested in 1X, 2X, 4X, etc. stacked die sets, with flexibility in selecting which input / output areas are used for external communication with the connected stacked die sets.

[0085] Now see Figure 13D , provides a schematic top view illustration of a CoW stacked die set 100 according to one embodiment. In the illustrated embodiment, one or more additional dies 350 may be bonded to one or more dies 104 in the stitched die set 100. Such techniques may also be used for partial die recovery. As also shown, the first level of dies may include die 104A and die 104B, wherein die 104B may be the same or different from die 104A (e.g., perform a different function), and dies 104A and 350 together may perform a useful function. As previously described, the die regions and dies 104A, 104B, 350 may include different circuit blocks from one another. Each die region / die may represent a complete system or subsystem. Adjacent and stacked die regions / dies may perform the same or different functions.

[0086] By way of illustration, as previously described herein, various possible outcomes of stitching die 104 arrangements are described in Figure 13E For result (A), the left die 104A is good, while the connected right die 104B is determined to be bad after testing. This is reversed in result (B), where the left die 104A is bad, while the connected right die 104B is good. For result (C), both dies 104A, 104B are determined to be good. In this specific example, it is assumed that the input / output area 114 of the left die 104A will be pre-selected to interface with a logic chip, such as a reference chip. Figure 14AThe embodiments shown and described are consistent. Therefore, it may be necessary to make the left die 104A functional for operating the die set 100. For result (A), the additional die 350 can be bonded to the left die 104A. The combination of dies 104A and 350 can then be sliced ​​and harvested. This avoids the total loss of the die set 100. However, for result (B), the die set 100 is not recoverable. For example, for result (C), the additional die 350 can be used to increase the capacity of the die set 100. It should be understood that although the exemplary embodiment is described with respect to two lower stitched dies 104A, 104B and an additional top die 350, this is provided for illustrative purposes and the embodiments are not limited thereto. In addition, the dies 104A, 104B can be a variety of types of dies, including XRAM, logic components, etc.

[0087] According to an embodiment, die 350 may be mounted face down onto wafer 102 comprising stitched die set 100. Additional packaging solutions may then be employed. Figure 13F is a schematic cross-sectional side view illustration of a package 250 including a chip-on-wafer stacked die set 100 according to an embodiment.

[0088] In one embodiment, the die 350 may be hybrid bonded to the BEOL buildup 120 across the stitched dies 104A, 104B, which may include metal-metal bonding between the contact pads 140 of the BEOL buildup 120 and the contact pads 354 of the die 350 , as well as oxide-oxide bonding.

[0089] In one embodiment, the die 350 may then be encapsulated in an encapsulation material 180 (e.g., an inorganic dielectric such as an oxide). Through-oxide vias may then be formed to form vertical interconnects 182. Alternatively, conductive pillars may be formed, or a printed circuit board (PCB) strip may be placed adjacent to the die 350 for use with the vertical interconnects 182 prior to molding. The package RDL 170 may then be formed, for example, as previously described with respect to Figure 8B According to an embodiment, the die 350 may optionally include TSVs 352 for backside connection to the RDL 170 .

[0090] In some cases, package 250 may be scribed to cut through die-to-die wiring 130, such as Figure 13G This may occur, for example, if the second die 104 is found to be a bad die, as previously described with reference to Figure 13E The results are as described in (A).

[0091] Up to this point, various components and chip harvesting structures have been described, in which various combinations of components or die sets can be obtained to meet specific applications. For example, die sets can be connected with die-to-die wiring or stacking to form various engine combinations, logic expansion, capacity expansion, bandwidth expansion, and die recovery. Various specific applications will now be described. However, it should be understood that although some of the following examples may be described with respect to specific applications (such as memory expansion), it should be understood that these are exemplary applications and the embodiments are not limited thereto.

[0092] Now see Figure 14A , is a schematic top view illustration of a memory system 400 with various examples of memory bandwidth and capacity scaling, according to one embodiment. Figure 14B According to an embodiment Figure 14A 4 is a schematic cross-sectional side view illustration of a memory system 400. As shown, the memory system 400 may include one or more chips 150 (or packages) arranged around a logic chip 402 (or package). Each chip 150 may include one or more dies 104 stitched together using die-to-die wiring 130. Each of the dies 104 within the chip 150 may be the same type of die, or different types of dies. For example, the die 104 closest to the logic chip 402 may be configured to handle communications with the logic chip 402. For example, the first die 104 may be a memory cache or a controller memory die, which may include a buffer for dividing signals for further communication with additional dies 104 further down the chain with the chip 150. As previously described, the stacked die area 110 and the die 104 may include different circuit blocks from each other. Each die area may represent a complete system or subsystem. Adjacent die areas may perform the same or different functions.

[0093] exist Figure 14B In the exemplary embodiment shown, chip 150 and logic chip 402 can be mounted on a wiring substrate 550 that includes electrical routing 552 with conductive bumps 174 (e.g., solder). As shown, the input / output region 114 of chip 150 adjacent to logic chip 402 can be used as external input / output to communicate with logic chip 402 via wiring substrate 550. It should be understood that other packaging solutions are possible and embodiments are not limited thereto.

[0094] Now see Figure 14A and Figure 3In one embodiment, the multi-die structure includes a chip 150 including a first front-end-of-line (FEOL) die region 110A (e.g., closest to a main logic chip 402 including controller functionality) of a first die 104A patterned into a semiconductor substrate 101 and a second FEOL die region 110B of a second die 104B patterned into the semiconductor substrate 101, the second FEOL die region 110B being separate from the first FEOL die region 110C. The first FEOL die region 110A may include a first-first side 191 and a first-second side 192 opposite to the first-first side, and a first input / output region 114A adjacent to the first-first side 191, and the second FEOL die region 110B may include a second-first side 193 and a second-second side 194 opposite to the second-first side, and a second input / output region adjacent to the second-first side 193, wherein the first-second side 192 of the first FEOL die region 110A is adjacent to the second-first side 193 of the second FEOL die region 110B. A back-end of line (BEOL) buildup structure 120 spans the first FEOL die region 110A and the second FEOL die region 110B, as shown in FIG. Figure 3 As shown, the BEOL buildup structure 120 includes a die-to-die wiring 130 connecting the second input / output region 114B and the first FEOL die region 110A (eg, connected to a corresponding input / output region of the first FEOL die region 110A).

[0095] Additional dies can be stitched together for additional memory expansion. For example, a third FEOL die region of a third die 104C can also be patterned into the semiconductor substrate 101, wherein the third FEOL die region is separate from the first FEOL die region 110A and the second FEOL die region 110B. Similarly, the third FEOL die region can include a third-first side 195 and a third-second side 196 opposite the third-first side 195, and a third input / output region 114C adjacent to the third-first side 195, wherein the second-second side 194 of the second FEOL die region 110B is adjacent to the third-first side 195 of the second FEOL die region. Similarly, the BEOL stacking structure 120 spans the third FEOL die region and includes second die-to-die wiring 130 connecting the third input / output region 114C and the second FEOL die region 110B (e.g., to the corresponding input / output region of the first FEOL die region 110A). As shown, a fourth die 104D having a fourth input / output region 114D may additionally be tied to a third die 104C, and so on.

[0096] It should be understood that an actual memory system will likely have more balanced memory, and the illustration of different sized chips 150 is for illustrative purposes only to illustrate the possibility of memory scaling with a harvested set of dies.

[0097] Additional strings of stitched dies can also be placed adjacent to each other, for example, for bandwidth expansion. Figure 14A The top chip 150 includes the six dies 104 as previously described, including a first die 104A', a second die 104B', and a third die 104C' similar to and arranged side by side as the first die 104A, the second die 104B, and the third die 104C, and so on, wherein the input / output areas are aligned with the logic chip 402 and are located near the logic chip and are electrically connected to the logic chip.

[0098] Depending on the embodiment, the dies of memory system 400 may be any one or combination of cache memory, NAND, SRAM, MRAM, NVRAM, DRAM, or other "X" RAM.

[0099] In a specific embodiment, the first die having external input / output area 114 is a memory cache die, and subsequent die are other types of memory die (e.g., XRAM). In one embodiment, the first die 104A includes input / output (e.g., data) buffers that are not included in the subsequent stitching dies (104B, 104C, 104D, etc.). Thus, the chip 150 can function somewhat similarly to a quad die package (QDP) load reduction arrangement that uses data buffer chips to reduce and minimize the load on the server memory bus, but the die 104 can be connected in series in this embodiment. Alternatively, in the case where the die are of the same type, similar input / output buffers can be included in the die but not operated, where the internal links provide communication between the die.

[0100] In one embodiment, die 104A, 104A' can be controller memory dies configured to communicate with logic chip 402, and the following stitching dies (104B, 104C, 104D, 104B', 104C', 104D', etc.) are service memory dies configured to communicate with the logic chip through the controller memory die. Thus, the function of chip 150 can be somewhat similar to a 3D stacked registered memory module.

[0101] Similar to the previous description, the chip 150 may include a partial metal seal 122A along the edge of the die, where die-to-die wiring 130 is present. For example, a first partial metal seal 122A may be positioned adjacent to the first-second side 192 of the first FEOL die region 110A, and a second partial metal seal 122A may be positioned adjacent to the second-first side 193 of the second FEOL die region 110B, with the die-to-die wiring 130 extending through a first opening in the first partial metal seal and a second opening in the second partial metal seal. This arrangement may be provided for all die-to-die wiring 130.

[0102] The memory system 400 according to the embodiment may also include a stacked die set that is additionally combined with a stitched die set. Thus, stitching may occur between any or all die levels in the stacked die set. In addition, the stacked die set may include a stacked die set as previously described with reference to FIG. Figures 13A to 13G The CoW or WoW die stacking.

[0103] In one embodiment, WoW die stacking can be used to form a multi-die structure in a memory system 400, wherein a semiconductor substrate, a first FEOL die region, a second FEOL die region, and a BEOL stacking structure form a first die level 111, and a second die level 113 hybrid bonded to the first die level 111. The second die level 113 may include a third front-end-of-line (FEOL) die region of a third die patterned into a second semiconductor substrate and a fourth FEOL die region of a fourth die patterned into the second semiconductor substrate, wherein the fourth FEOL die region is separated from the third FEOL die region similar to the first die level. For example, the first die level and the second die level may include stacked memory dies, such as Figure 13A shown.

[0104] In one embodiment, CoW die stacking can be utilized to form a multi-die structure in the memory system 400, wherein the second die is hybrid-bonded face-to-face with the BEOL stacking structure, and an encapsulation material (e.g., an inorganic dielectric) laterally surrounds the second die on the BEOL stacking structure, as shown in FIG. Figures 13F to 13G For example, the second chip can be as shown. Figure 13A Additional memory die is shown. Hybrid bonding can also be performed from front to back or back to back instead of face to face.

[0105] In another exemplary implementation, the die harvesting technique can be used in a scalable network system. FIG. 15A to FIG. 15B, is a close-up schematic top view illustration of a network die harvested from a wafer, according to an embodiment. Similar to the previously described embodiments, the network die 104 may include a die area 110 including a device area 112 and one or more input / output areas 114 that may be arranged around any edge or corner for connecting to adjacent dies 104. Figure 15A In the specific embodiment shown, a 1X network single die set and a 2X network multi-die set or two 1X network dies can be carved out of a 2x2 die array where a bad die exists. Figure 15B A 4X network die set 100 is shown. Similar to the previous embodiments, a partial metal seal can be formed along the edge of the die 104, where die-to-die wiring 130 exists. In addition, these die sets can include multiple die levels, such as described as Co-on-Waste (CoW) or Wo-on-Waste (WoW). As previously described, the stacked die region 110 and die 104 can include different circuit blocks from each other. Each die region can represent a complete system or subsystem. Adjacent die regions can perform the same or different functions.

[0106] Figure 15C is a close-up schematic top view illustration of network die set 100 according to one embodiment. Figure 15C The die set 100 with Figure 15B The difference lies in the location of the input / output region 114, which is located in the central area of ​​the die set 100, which can reduce power and latency. Figure 15C Also shown are full metal seals 122B and partial metal seals 122A adjacent to the input / output region 114 where the die-to-die wiring 130 is located. At the wafer level, the illustrated network die set 100 can be a repeating pattern across the wafer. In the event of a bad die 104, harvesting can be performed similarly to the other embodiments described herein.

[0107] Now see Figure 15D , provides a close-up schematic top view illustration of an array of network dies 104 on a wafer according to an embodiment. Figure 15D The arrangement is basically similar to Figure 15A The arrangement shown differs in that device area 112 may correspond to the primary network functionality, and additional optional networks or other functionality may be located in secondary area 115. In this case, input / output area 114 is located along the edge of device area 112, where die 104 may be connected with die-to-die wiring 130 extending through a portion of the metal seal.

[0108] Figure 15E is an illustration of a module including multiple logic chips 402 arranged around a harvested single die set network chip 150, according to one embodiment. Figure 15Fis a diagram of a module including multiple logic chips 402 arranged around a harvested multi-die set network chip 402, according to one embodiment. In the illustrated embodiment, Figure 15D The dies 104 are harvested into appropriately sized die sets to provide scaled networking resources. The network chip 150 (or package) can support the logic chip 402 as shown (e.g., SOC), or can also be used to support other functions (other logic, XRAM, etc.) and can be arranged in 3D (e.g., CoW or WOW as described above). Additional chips 404 can also be connected to support alternative functions. Therefore, not all dies or chips connected to the network chip 402 need to be of the same type. It should be understood that Figures 15A to 15F The embodiments shown in FIG. 5 show exemplary rectangular or octagonal network elements, and embodiments may also employ other non-rectangular shapes, such as triangular, hexagonal, circular, etc., as may be used in other systems.

[0109] Alternative arrangements for network die harvesting are Figures 15G to 15H Shown in. Figure 15G is a schematic top view layout plan of harvesting network die 104 from wafer 102 according to one embodiment. Figure 15H is a schematic top view illustration of a die set 100 including a plurality of network dies 104 according to one embodiment. Such implementation is similar to the previous Figures 15A to 15F , except that the network area 116 spans the input / output area 114 on a single side of the die 104. In this case, various die sets 1X, 2X, 4X, 8X, 12X, etc. can be harvested depending on the final application and the wafer 102 yield. In this case, the die 104 on the opposite sides of the network area 116 can be the same or different die types (performing different functions). The network area 116 according to the embodiment may include circuits that enable data to be transmitted from one chip to another. Such networks may be circuit-switched networks or packet-switched networks and may include crossbar functions. Connectivity may be linear, two-dimensional, or other topologies. In addition, the network area may include cache elements or other logic functions. The harvest may include the number of cells required for slicing, or even have more cells than required, and accept one or more failed cells. For example, a harvested die set 100 including 12X dies may include twelve good dies, or ten good dies and two bad dies. In addition, redundancy may be added by including one or more additional cells (die) or complete subsystems. In the event of a cell failure, a good cell may be swapped. Redundancy can be at the time of manufacture or can be swapped in the field.In the illustrated embodiment, the network area 116 is more like a bus, or similar to an interface bar as will be described below, while still being integrated on a chip.

[0110] Suturing and harvesting techniques according to embodiments can be used to form a variety of array structures. Figure 16A Schematic top view diagram of logic and memory scaling with a stitched interface bar 500 according to one embodiment. As shown, interface bar 500A can be used as a connectivity bar to provide modularity to various combinations of logic chips 402, including CPUs, GPUs, networks, caches, signal processors, glue logic components, and systems on chip. Interface bar 500A according to an embodiment can be used to provide high-bandwidth, low-power, scalable connectivity between two or more chips. Using connectivity bars allows input / output (I / O) terminals to be flexibly positioned on the logic die, without having to be at the die / chip edge. In addition, there is flexibility in the starting and ending locations. In some embodiments, interface bar 500A may include active silicon blocks and can provide flexibility and design convenience for logic chip 402. Die set 150 (such as memory chips) can be further coupled to logic chip 402 with interface bar 500B (e.g., memory bars), which can optionally be placed in series to increase memory density. Therefore, depending on the embodiment, the connectivity organization, even bandwidth and latency, can be customized. Furthermore, logic chip 402 does not need to be pre-committed to provide maximum bandwidth and routing resources. Figure 16A The arrangement in can be adjusted to provide storage capacity and / or short logical connectivity.

[0111] Interface bars 500 according to embodiments can be harvested similarly to the dies and components described herein. Figure 16B As shown, a particular section 504 with bar-to-bar wiring 530 can be scribed to obtain a larger or smaller system. Likewise, any bad section 504 can be removed. Figure 16Cis a schematic cross-sectional side view illustration of a stitched interface strip 500 according to one embodiment. As shown, a segment 504 may be provided in a substrate 501 (such as a silicon substrate). The substrate 501 may include active silicon (or other materials) to include features such as logic components, repeaters, flip-flops, caches, memory compressors and decompressors, controllers, local processing elements, and the like. Other non-silicon technologies such as, but not limited to, GaAs, and even optical interconnect technologies (many of which are supported by silicon) may also be used for the substrate 501, if appropriate. The wiring layer 520 may include one or more metal layers and dielectric layers. The wiring layer 520 may be formed using thin-film technology or conventional BEOL processing techniques such as metal damascene. The wiring layer 520 may include wiring layers such as a lower wiring layer, an intermediate wiring layer, and an upper wiring layer. The wiring layers may optionally have different thicknesses, with M_high being the thickest and M_low being the thinnest. In some embodiments, quality of service may be used to organize metal usage based on requirements such as latency and power. In one embodiment, high-priority communications with low latency requirements can be on higher (thicker) layers, while bulk communications with a greater latency range can be in lower (thinner) layers. Wiring layer 531 can extend the substantial length of segment 504 for interconnection, while bar-to-bar wiring 530 is used to connect adjacent segments 504. Wiring layer 520 can terminate at contact pads 540, which can further connect to various package sequences.

[0112] A similar solution can also be used to harvest custom tiled interposer arrays. Figure 17A is a schematic cross-sectional side view illustration of a circuit including multiple chips 150 mounted on an interposer 600 having connection routing areas 630 according to one embodiment. Figure 17B 6 is a schematic top view illustration of a scribed area on an interposer substrate 602 having a connection wiring area 630 according to one embodiment. Similar to the previous embodiment, a segment 604 can be provided in a substrate 601 (such as a silicon substrate) and can be custom generated to form an interposer 600. The interposer 600 may include TSVs 652 for vertical connections. The wiring area 630 can be formed in a wiring layer 620 similar to the wiring layer 520. In an exemplary application, such a configuration can be used to form a field programmable gate array (FPGA), including a chip 150 mounted on the interposer 600 using conductive bumps 174 (e.g., microbumps), wherein the interposer 600 is mounted on a packaging substrate using conductive bumps 674. Ball grid array (BGA) balls 774 can be placed on the opposite side of the packaging substrate 700 for further integration.

[0113] Until such customized harvesting of various array structures has been described. In many cases, conventional slicing techniques including blade slicing and laser ablation can be performed along predetermined saw streets or slicing areas between the arrayed areas. Depending on the embodiment, programmable slicing techniques can also be used to provide additional flexibility in the selection of slicing areas and to support fine slicing with reduced saw street width or reduced material loss. Two such programmable slicing techniques include laser-assisted slicing (which may include laser ablation or stealth slicing, which is cleaner, less damaging and can have smaller scribe lines) and chemical etching slicing (which can be wet or plasma-based).

[0114] Figure 18 18 is a flow chart of a method for testing and scribing dies using programmable dicing according to an embodiment. Beginning at operation 1802, an array wafer including FEOL die areas and routing layers is received to complete die-to-die routing. The wafer can then be tested at operation 1804 to determine good and bad FEOL die areas. This information is then used at operation 1806 to create a map identifying valid die sets 100, and the map information is then stored at operation 1808. The dicing tool then retrieves the map at operation 1810 and can perform programmable dicing at operation 1812, which may include, for example, a laser-assisted dicing flow sequence 1814 or a chemical etch dicing flow sequence 1822.

[0115] At operation 1816, the laser-assisted dicing flow sequence 1814 may optionally include laser grooving the front side of the wafer. For example, this may be the first laser cutting process (e.g., ablation) through the wiring layer / BEOL stack-up structure down to the substrate. Thus, this may include, for example, cutting through the die-to-die wiring 130. This is then followed by a deep laser-assisted dicing operation 1818, in which the laser beam is pulsed on and off to create a damaged crystal structure line. The dies are then separated at operation 1820. This may include cutting to propagate cracks along the laser pattern.

[0116] The chemical etch dicing flow sequence 1822 may include a programmable laser grooving operation 1824 similar to sequence 1814, where a laser is used to cut through the wiring layer / BEOL stacking structure to the substrate. A mask layer may be deposited and patterned using laser cutting (e.g., ablation) through the mask layer and BEOL stacking structure. This avoids additional photolithography operations and can be well defined (e.g., <1 μm edges). Plasma or wet chemical assisted dicing may then be performed at operation 1826, where an etch mask may be photolithographically defined, followed by plasma or wet etching partially or completely through the semiconductor substrate. The dies may then be separated at operation 1828. In the case of performing a partial plasma or wet etch, this may optionally include backgrinding the semiconductor substrate.

[0117] Any programmable dicing technology can be used to achieve fine dicing while reducing material loss. This facilitates the integration of dense array structures. In addition, programmable dicing technology is very flexible with respect to shape, size, or layout constraints. This allows for the freedom to slice die sets of any shape. Consequently, this capability allows for additional reliability margin improvements to be achieved for the sliced ​​die sets through programmable dicing according to embodiments.

[0118] Now see Figure 19A , provides a schematic top view illustration of a die set 100 before scribing according to an embodiment, wherein the FEOL die area 110 is interconnected with the die-to-die wiring 130 via a partial metal seal 122A. A full metal seal 122B is also provided around the die set 100. Thus, this exemplary arrangement can be previously combined with Figure 1C However, it should be understood that this particular configuration is exemplary and that the following structure for reliability margin improvement may be integrated into other die set 100 configurations.

[0119] The die area according to an embodiment may have corresponding service structures 702 for wafer acceptance testing, process statistics, etc. to monitor wafer fabrication processes, alignment, etc. Therefore, these service structures 702 may generally be located along the die edge and reticle edge.

[0120] Still refer to Figure 19A , the service structures 702 may be arranged outside the metal seal (e.g., outside the full metal seal 122B ring). The various service structures may include electrical test pads for testing and incorporating good / bad wafer acceptance testing, or for controlling process statistics for tuning, as well as alignment features, and may be formed as part of the BEOL stacking structure. Figure 19A As shown, one of the FEOL die regions 110 has been tested and found to be defective. The programmable dicing method according to the embodiment can be used to cut out the defective FEOL die region 110, as shown in FIG. Figure 19B As shown, and recover the good die, thus improving the edge. For example, the resulting structure can be similar to Figure 5B Scribing may optionally remove service structure 702. Alternatively, service structure 702 may remain in die set 100 after scribing.

[0121] Now see Figure 20A, provides a schematic top view illustration of a die set 100 prior to scribing according to one embodiment, wherein service structures 702 are positioned in the unscribed scribe area 125 between adjacent FEOL die areas. This may not include all service structures 702, but they may be relocated to the extent possible. In this case, the service structures 702 are located between the FEOL die areas 110, which may result in an increased physical interface (Phy) distance. The service structures 702 may be located above, below, or between (laterally, vertically) the die-to-die wiring 130 lines. Referring now to Figure 20B In the event that one of the dies is defective and a good die is recovered from the die set 100, scribing can be performed between the service structures 702 of each FEOL die area 110. Consequently, the Phy distance increases along the edge of the die to the active device area, which can help increase the reliability and margin of the recovered die because moisture, ions, and cracks will have to travel a longer distance. Thus, the original functionality of the service structures 702 can be preserved, while the increased physical distance can help improve the reliability of the partial metal seal 122A structure. In one embodiment, the scribed die-to-die wiring 130 lines are electrically isolated. Isolation can include being tri-stated or otherwise disconnected from the core circuitry of the die. This applies to both the die-to-die wiring 130 and any supporting power networks.

[0122] Figure 21 A schematic top view illustration of a scribed die set according to one embodiment is shown, with scribe lines on opposite sides of an input / output region 114 adjacent to a FEOL die region 110 according to one embodiment. In such an embodiment, programmable dicing can be used to provide additional protection against moisture, ions, and cracks by including multiple partial metal seals 122A and, optionally, a portion of the adjacent FEOL die region 110, such as the input / output region 114. As shown, dicing passes through the bad die region 110. Thus, space is deducted from the bad die, improving reliability by increasing distance, increasing the number of partial metal seals, and preserving undamaged die-to-die wiring 130. In one embodiment, internal input / output regions 114 in the FEOL die region 110 are isolated in an off state connected to BEOL stacking structure contact pads, which allows external contact to be made to additional input / output regions 114 that remain connected to the die-to-die wiring 130. Isolation in the off state may include being tri-stated, or otherwise disconnecting the external die-to-die wiring 130 from the core circuitry of the die. This may only connect to wires going to the other die. It may not reach contact pads or any other pads. The ability to isolate the buffer (transceiver or receiver) is required in the event that the die-to-die wiring 130 is cut.

[0123] Such a restored die configuration can be designed into end module applications to accommodate the potential of additional chip 150 areas and additional conductive bumps. For example, Figure 22 A normal chip 150 is shown mounted on a wiring substrate 800 that includes one or more additional unopened bond pads 802, which may be covered with an insulating layer 804. In the case where the chip 150 includes a recovered die with additional scribe areas 125 and additional input / output areas 114, the one or more bond pads 802 may be opened by removing the insulating layer, and additional conductive bumps 184 may be applied. In this way, the die-to-die wiring 130 may also be retained.

[0124] In one embodiment, a chip structure includes a semiconductor substrate 101, a first FEOL die region 110A of a first die 104A patterned into the semiconductor substrate 101. The first FEOL die region 110A includes a first device region 112 and a first input / output region 114. A scribe line region 125 is adjacent to the first input / output region 114. A second input / output region 114 is also patterned into the semiconductor substrate and is adjacent to the scribe line region 125 opposite the first input / output region 114. A BEOL stacking structure 120 spans the first device region 112, the first input / output region 114, the scribe line region 125, and the second input / output region 114. The BEOL stacking structure 120 further includes a die-to-die wiring 130 connecting the first input / output region 114 and the second input / output region 114. In one embodiment, a scribed chip edge 152 may be adjacent to the second input / output region 114, as shown in FIG. Figure 23 As shown. Because the die-to-die wiring 130 is retained, the first input / output area can be isolated in an off state (e.g., tri-state) connected to the BEOL stacking structure contact pad 140. This can only be connected to the wire going to the other die. It may not reach the contact pad or any other pad. It is necessary to have the ability to isolate the buffer (transceiver or receiver) in the event that the die-to-die wiring 130 is cut. The partial metal seal 122A can also be positioned adjacent to the first input / output area 114 and the second input / output area 114, wherein the die-to-die wiring 130 extends through a first opening in the first partial metal seal 122A and a second opening in the second partial metal seal 122A. The service structure 702 can also be located in the scribe area 125 between the first input / output area 114 and the second input / output area 114.

[0125] As will become apparent to those skilled in the art upon utilizing various aspects of the embodiments, combinations or variations of the above embodiments are possible for harvesting array structures. Although the embodiments have been described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. Instead, the specific features and acts disclosed should be understood as exemplary embodiments of the claims.

Claims

1. A chip structure, comprising: semiconductor substrates; a first front-end-of-the-line (FEOL) die region of a first die patterned into the semiconductor substrate, the first FEOL die region comprising a first device region and a first input / output region; a back-end-of-the-line (BEOL) stacking structure spanning the first device region and the first input / output region; an edge of the chip adjacent to the first input / output region; wherein the BEOL buildup structure includes die-to-die wiring, the die-to-die wiring being connected between the first input / output region and a terminal end of the die-to-die wiring at an edge of the chip; and in: The semiconductor substrate, the first FEOL die region, and the BEOL stacked structure form a first die level, the chip structure further comprising a second die level hybrid-bonded to the first die level, the second die level comprising a second FEOL die region of a second die patterned into a second semiconductor substrate; or The chip structure further includes a second chip hybrid-bonded to the BEOL stacking structure and a packaging material laterally surrounding the second chip on the BEOL stacking structure. 2 . The chip structure according to claim 1 , wherein the first input / output region connected to the die-to-die wiring is isolated in an off state.

3. The chip structure according to claim 1, wherein: The BEOL stack structure further includes a first portion of a metal seal adjacent to the first input / output region; and The die-to-die wiring extends through a first opening in the first partial metal seal.

4. The chip structure according to claim 1: Also included is a second FEOL die region of a second die patterned into the semiconductor substrate, the second FEOL die region including a second device region and a second input / output region; wherein the first FEOL die region includes a third input / output region; as well as The BEOL stacking structure spans the second device region, the second I / O region, and the third I / O region, and includes a second die-to-die wiring connected between the second I / O region and the third I / O region.

5. The chip structure according to claim 4, wherein: The BEOL stack structure further includes a second portion of a metal seal adjacent to the second input / output region and a third portion of a metal seal adjacent to the third input / output region; as well as The second die-to-die wiring extends through a second opening in the second partial metal seal and through a third opening in the third partial metal seal.

6. A multi-die structure, comprising: a first front-end-of-the-line (FEOL) die region patterned into a first die in a semiconductor substrate and a second FEOL die region patterned into a second die in the semiconductor substrate, the second FEOL die region being separate from the first FEOL die region; wherein the first FEOL die area includes a first input / output area, and the second FEOL die area includes a second input / output area; A back-end-of-the-line (BEOL) stacking structure spanning the first FEOL die region and the second FEOL die region, the BEOL stacking structure comprising: a first portion of a metal seal adjacent to the first input / output region; a second portion of a metal seal, the second portion of the metal seal being adjacent to the second input / output region; a die-to-die wiring connecting the first input / output region and the second input / output region and extending through a first opening in the first partial metal seal and a second opening in the second partial metal seal; and A metal sealing ring completely surrounds the first FEOL die area, the second FEOL die area, and the die-to-die wiring.

7. The multi-die structure according to claim 6, wherein the first die and the second die are each selected from the group consisting of a graphics processing unit (GPU), a central processing unit (CPU), a neural engine, an artificial intelligence (AI) engine, and a signal processor. 8 . The multi-die structure of claim 6 , wherein the BEOL stacking structure further comprises a plurality of service structures between the first input / output region and the second input / output region.

9. A multi-die structure, comprising: Wiring substrate; a logic chip mounted on the wiring substrate; a chip mounted on the wiring substrate adjacent to the logic chip, wherein the chip comprises: a first front-end-of-the-line (FEOL) die region patterned into a first die in a semiconductor substrate and a second FEOL die region patterned into a second die in the semiconductor substrate, the second FEOL die region being separate from the first FEOL die region; wherein the first FEOL die area includes a first input / output area and a third input / output area, and the second FEOL die area includes a second input / output area; A back-end-of-the-line (BEOL) stacking structure spanning the first FEOL die region and the second FEOL die region, the BEOL stacking structure comprising: a first portion of a metal seal adjacent to the first input / output region; a second portion of a metal seal adjacent to the second input / output region; and a die-to-die wiring connecting the first input / output region and the second input / output region and extending through a first opening in the first partial metal seal and a second opening in the second partial metal seal; The third input / output region is located near the logic chip and is electrically connected to the logic chip via wiring on a wiring substrate.

10. The multi-die structure of claim 9, wherein the first die and the second die are each independently selected from the group consisting of static random access memory, magnetic random access memory, non-volatile random access memory, dynamic random access memory, NAND, and cache memory.

11. The multi-die architecture of claim 9, wherein the first die is a memory cache die and the second die is a memory die.

12. The multi-die structure of claim 9, wherein the first die includes a data buffer that is not included in the second die.

13. The multi-die structure of claim 9, wherein the first die is a controller memory die configured to communicate with the logic chip, and the second die is a service memory die configured to communicate with the logic chip through the controller memory die.

14. A multi-die structure, comprising: a first front-end-of-the-line (FEOL) die region patterned into a first die in a semiconductor substrate and a second FEOL die region patterned into a second die in the semiconductor substrate, the second FEOL die region being separate from the first FEOL die region; wherein the first FEOL die area includes a first input / output area, and the second FEOL die area includes a second input / output area; A back-end-of-the-line (BEOL) stacking structure spanning the first FEOL die region and the second FEOL die region, the BEOL stacking structure comprising: a first portion of a metal seal adjacent to the first input / output region; a second portion of a metal seal adjacent to the second input / output region; and a die-to-die wiring connecting the first input / output region and the second input / output region and extending through a first opening in the first partial metal seal and a second opening in the second partial metal seal; wherein the semiconductor substrate, the first FEOL die region, the second FEOL die region and the BEOL stacked structure form a first die level; and a second die level hybrid bonded to the first die level, the second die level including a third front-end-of-line (FEOL) die region of a third die patterned into a second semiconductor substrate and a fourth FEOL die region of a fourth die patterned into the second semiconductor substrate, the fourth FEOL die region being separate from the third FEOL die region.

15. An electronic structure, comprising: Wiring layer; one or more dies, the one or more dies being located on a top side of the wiring layer; a plurality of conductive bumps, the plurality of conductive bumps being located on a lower side of the wiring layer; as well as A multi-component device comprising a plurality of co-located components formed in a common substrate and a terminal side comprising a plurality of terminals bonded to the underside of the wiring layer laterally adjacent to the plurality of conductive bumps, wherein the terminal side of the multi-component device has a non-rectangular area.

16. The electronic structure of claim 15, wherein each component of the plurality of co-located components comprises a separate terminal of the plurality of terminals.

17. The electronic structure of claim 15, wherein the plurality of co-located components include component-to-component wiring.

18. The electronic structure of claim 15, wherein each component is selected from the group consisting of a capacitor, an inductor, a resistor, and a power management integrated circuit.

19. The electronic structure of claim 15, wherein the multi-component device is bonded to an underside of the wiring layer below a circuit block, the circuit block having an area within one of the one or more dies equivalent to the non-rectangular area of ​​the multi-component device.

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