Semiconductor structure, preparation method thereof, memory, storage system and electronic device

Abstract

The application provides a semiconductor structure and a preparation method thereof, a memory, a storage system and an electronic device, relates to the technical field of semiconductor chips, and aims to improve the storage performance of the memory. The preparation method of the semiconductor structure comprises the following steps: forming a laminated structure on a substrate, wherein the laminated structure comprises gate dielectric layers and gate sacrificial layers which are alternately arranged and laminated in sequence; forming a first cover layer on the laminated structure; etching the first cover layer and the laminated structure to form a channel hole; etching the sidewall of the channel hole by using an etching liquid to flatten the sidewall of the channel hole; the acid corrosion resistance of the first cover layer to the etching liquid is smaller than the acid corrosion resistance of the laminated structure to the etching liquid, and the diameter of the channel hole after etching in the first cover layer is greater than or equal to the diameter of the channel hole in the laminated structure; and sequentially forming a functional layer and a dielectric core in the channel hole to form a channel structure. The prepared semiconductor structure is used to realize data reading and writing operations.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method, a memory, a storage system, and an electronic device. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, manufacturing technologies such as planar processes become challenging and costly. This has led to the storage density of planar memories such as 2D (2-dimension) NAND flash memory approaching its upper limit, posing a serious challenge to the semiconductor memory industry.

[0003] Three-dimensional memory (such as 3D NAND flash memory) can overcome the above limitations. Specifically, by stacking memory cells three-dimensionally to form a multi-layer structure, it increases storage density, achieving a storage capacity several times higher than comparable planar memory. The fabrication process of 3D memory requires forming a stacked structure on a substrate and etching the stacked structure to create through-hole channels. However, as the number of layers in the stacked structure increases, the aspect ratio of the through-holes becomes larger, posing challenges to the through-hole formation process. Summary of the Invention

[0004] The embodiments of this application provide a semiconductor structure and its fabrication method, a memory, a storage system, and an electronic device, aiming to improve the storage performance of the memory.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] On one hand, a method for fabricating a semiconductor structure is provided, the method comprising: forming a stacked structure on a substrate, the stacked structure comprising a gate dielectric layer and a gate sacrificial layer alternately stacked in sequence; forming a first capping layer on the stacked structure; etching the first capping layer and the stacked structure to form a channel hole; the channel hole sequentially penetrating the first capping layer and the stacked structure; etching the sidewalls of the channel hole with an etchant to planarize the sidewalls of the channel hole; wherein the acid resistance of the first capping layer to the etchant is less than that of the stacked structure to the etchant, and the diameter of the etched channel hole in the first capping layer is greater than or equal to the diameter of the channel hole in the stacked structure; and sequentially forming a functional layer and a dielectric core within the channel hole to form a channel structure, the functional layer being disposed on the outer wall of the dielectric core.

[0007] In some embodiments, forming a stacked structure on a substrate includes: forming an alternately stacked gate dielectric layer and a gate sacrificial layer on the substrate; forming a second capping layer on the side of the alternately stacked gate dielectric layer and the gate sacrificial layer away from the substrate; the stacked structure further includes the second capping layer.

[0008] In some embodiments, the materials of the first cover layer and the second cover layer are the same; the density of the material of the first cover layer is less than the density of the material of the second cover layer.

[0009] In some embodiments, the materials of the first cover layer and the second cover layer are different.

[0010] In some embodiments, after forming a functional layer and a dielectric core sequentially within a channel via to form a channel structure, the above fabrication method further includes: removing a gate sacrificial layer to form a sacrificial gap; and forming a gate layer within the sacrificial gap to form a stacked structure, the stacked structure including alternating layers of gate dielectric layers and gate layers.

[0011] In some embodiments, before forming the stacked structure on the substrate, the above preparation method further includes forming an etch barrier layer on the substrate.

[0012] In another aspect, a semiconductor structure is provided. This semiconductor structure includes a stacked structure, a first capping layer, a channel via, and a channel structure. The stacked structure includes alternating layers of a gate dielectric layer and a gate layer. The first capping layer is disposed on one side of the stacked structure. The channel via penetrates the first capping layer and the stacked structure. The diameter of the channel via at the first capping layer is greater than or equal to the diameter of the channel via at the stacked structure, and the acid corrosion resistance of the first capping layer is less than that of the gate dielectric layer. The channel structure is disposed within the channel via, and the channel structure includes a dielectric core and a functional layer. The functional layer is disposed on the outer wall of the dielectric core.

[0013] In some embodiments, the diameter of the dielectric core at the first cover layer is greater than or equal to the diameter of the dielectric core at the stacked structure.

[0014] In some embodiments, the semiconductor structure further includes a second capping layer disposed on the side of the first capping layer facing the substrate, and located on the side of the alternately stacked gate dielectric layer and gate layer away from the substrate. The acid corrosion resistance of the first capping layer is less than that of the second capping layer.

[0015] In some embodiments, the thickness of the first cover layer is greater than or equal to the thickness of the second cover layer.

[0016] In some embodiments, the materials of the first cover layer and the second cover layer are the same; the density of the material of the first cover layer is less than the density of the material of the second cover layer.

[0017] In some embodiments, the materials of the first cover layer and the second cover layer are different.

[0018] In some embodiments, the thickness of the first covering layer ranges from 500 Å to 2000 Å.

[0019] In some embodiments, the semiconductor structure further includes a source layer disposed on the side of the stacked structure away from the first capping layer and coupled to a functional layer in the channel structure.

[0020] On the other hand, a three-dimensional memory is provided. This three-dimensional memory includes peripheral circuitry and a semiconductor structure as described in some of the embodiments above, wherein the peripheral circuitry is electrically coupled to the semiconductor structure.

[0021] In another aspect, a storage system is provided. This storage system includes a controller and a three-dimensional memory as described in some of the embodiments above, the controller being electrically coupled to the three-dimensional memory for controlling the storage of data in the three-dimensional memory.

[0022] In another aspect, an electronic device is provided. This electronic device includes a printed circuit board and a storage system as described in some of the embodiments above, the printed circuit board being coupled to the storage system.

[0023] In the process of fabricating the semiconductor structure, the embodiments of this application form a first capping layer on one side of the stacked structure. Since the acid corrosion resistance of the first capping layer is less than that of the stacked structure, when the channel hole is planarized using an etchant, the corrosion rate of the etchant on the first capping layer is greater than that of the etchant on the stacked structure. Therefore, it can be ensured that after the channel hole is planarized using an etchant, the diameter of the channel hole in the first capping layer is greater than or equal to the diameter of the channel hole in the stacked structure. In this way, the top of the channel hole can be enlarged, solving the problem of narrowing at the top of the channel hole when etching to form the channel hole. Because planarizing the vias with an etching solution simultaneously increases the diameter at the top of the via, making it larger than or equal to the diameter at other locations within the via, this avoids the formation of pores within the dielectric core during the sequential formation of the functional layer and dielectric core to create the channel structure. This prevents conductive material from easily entering these pores during subsequent processes when forming the conductive structure above the via, which could affect charge storage and consequently, memory performance. This increases product yield and ensures the storage performance of the 3D memory. Furthermore, planarizing vias with an etching solution is an existing process step in semiconductor structure fabrication. This application utilizes this existing process to enlarge the narrowed top of the vias, i.e., simultaneously planarizing and enlarging the top of the vias with an etching solution, thus eliminating the need for additional steps and reducing fabrication costs.

[0024] It is understood that the beneficial effects of the semiconductor structure, three-dimensional memory, storage system and electronic device provided in the above embodiments of this application can be referred to the beneficial effects of the semiconductor structure preparation method described above, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0026] Figure 1 A structural diagram of an electronic device provided for an embodiment of this application;

[0027] Figure 2a A structural diagram of a storage system provided for an embodiment of this application;

[0028] Figure 2b A structural diagram of a storage system provided for another embodiment of this application;

[0029] Figure 3 A structural diagram of a three-dimensional memory provided for an embodiment of this application;

[0030] Figure 4a A three-dimensional structural diagram of a semiconductor structure provided for an embodiment of this application;

[0031] Figure 4b for Figure 4a A cross-sectional view of a memory cell string along section line AA' in the semiconductor structure shown;

[0032] Figure 4c for Figure 4a Equivalent circuit diagram of a string of memory cells in a semiconductor structure;

[0033] Figure 5 A flowchart illustrating a method for fabricating a semiconductor structure, provided as an embodiment of this application;

[0034] Figure 6 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 1 ;

[0035] Figure 7 A cross-sectional structural diagram 2 is provided for an embodiment of this application, illustrating the process of fabricating a semiconductor structure.

[0036] Figure 8 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 3 ;

[0037] Figure 9 Figure 4 shows a cross-sectional structure during the fabrication of a semiconductor structure, as provided in an embodiment of this application.

[0038] Figure 10a A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 5 ;

[0039] Figure 10b A structural diagram of a stacked structure provided for the prior art;

[0040] Figure 10c A structural diagram illustrating the formation of a channel structure within a channel hole, provided for the purposes of existing technology;

[0041] Figure 10d A structural diagram of a semiconductor structure provided for the prior art;

[0042] Figure 10e A structural diagram of a conductive structure and a dielectric core in a semiconductor structure provided for the prior art;

[0043] Figure 10f A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 6 ;

[0044] Figure 11 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 7 ;

[0045] Figure 12 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 8 ;

[0046] Figure 13 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 9 ;

[0047] Figure 14 A cross-sectional structural diagram (Figure 10) is provided for an embodiment of this application, illustrating the process of fabricating a semiconductor structure.

[0048] Figure 15a A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 11 ;

[0049] Figure 15b Topographical diagrams of semiconductor structures provided for embodiments of this application;

[0050] Figure 16 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 12 ;

[0051] Figure 17 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 13 ;

[0052] Figure 18 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 14 ;

[0053] Figure 19 Figure 15 shows a cross-sectional structure during the fabrication of a semiconductor structure, provided as an embodiment of this application.

[0054] Figure 20 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 16 ;

[0055] Figure 21 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 17 ;

[0056] Figure 22 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 18 ;

[0057] Figure 23 A cross-sectional structure provided in the embodiment of this application during the fabrication of a semiconductor structure. Figure 19 ;

[0058] Figure 24 A cross-sectional view of a semiconductor structure provided for an embodiment of this application;

[0059] Figure 25 A cross-sectional view of a semiconductor structure provided for another embodiment of this application;

[0060] Figure 26 A cross-sectional structure provided for the fabrication of semiconductor structures in related technologies. Figure 1 ;

[0061] Figure 27 A cross-sectional structural diagram 2 is provided for the fabrication of a semiconductor structure in a related technology.

[0062] Figure 28 A cross-sectional structure provided for the fabrication of semiconductor structures in related technologies. Figure 3 ;

[0063] Figure 29 Figure 4 shows a cross-sectional structure during the fabrication of a semiconductor structure, provided for related technologies.

[0064] Figure 30 A cross-sectional structure provided for the fabrication of semiconductor structures in related technologies. Figure 5 ;

[0065] Figure 31 A cross-sectional structure provided for the fabrication of semiconductor structures in related technologies. Figure 6 .

[0066] Reference numerals: 1-Electronic device; 01-Storage system; 02-Printed circuit board; 10-Three-dimensional memory; 11-Controller; 100-Semiconductor structure; 101-Stacked structure; 102-First cover layer; 103-Channel via; 104-Channel structure; 105-Memory cell string; 106-Stacked structure; 107-Second cover layer; 110-Functional layer; 110a-Barrier layer; 110b-Charge storage layer; 110c-Tunneling layer; 110d-Channel layer; 111-Dielectric core; 120-Gate dielectric layer; 121-Gate layer; 1211- Conductor layer; 1212-Gate barrier layer; 122-Gate sacrificial layer; 123-Sacrificial gap; 160-First capping layer; 200-Substrate; 201-Substrate; 201'-Substrate; 201a-Base plate; 201b-First sacrificial layer; 201c-Second sacrificial layer; 202-Peripheral circuit; 203-Etching barrier layer; 204-Array interconnect layer; 205-First interlayer insulating layer; 206-First interconnect conductor layer; 207-Bond interface; 209-Transistor; 210-Peripheral interconnect layer; 211-Second interlayer insulating layer; 212-Second interconnect conductor layer. Detailed Implementation

[0067] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0068] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0069] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0070] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0071] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. For example, the term "electrically coupled" may be used in describing some embodiments to indicate that two or more components are in direct physical contact and electrically connected or are in physical contact and electrically connected through other components. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0072] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0073] In the context of this application, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0074] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0075] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0076] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0077] Embodiments of this application provide an electronic device, which may include, for example, any one of a mobile phone, tablet computer, laptop computer, television, personal digital assistant (PDA), ultra-mobile personal computer (UMPC), netbook, wearable device (e.g., smartwatch, smart bracelet, smart glasses), etc. Embodiments of this application do not limit the type of electronic device.

[0078] Figure 1 An exemplary structural diagram of an electronic device is provided, such as... Figure 1 As shown, the electronic device 1 includes a storage system 01 and a printed circuit board 02, with the printed circuit board 02 coupled to the storage system 01.

[0079] like Figure 2a As shown, the above-mentioned storage system 01 includes a three-dimensional memory 10 and a controller 11. The controller 11 is electrically coupled to the three-dimensional memory 10 and is used to control the three-dimensional memory 10 to store data.

[0080] In some examples, such as Figure 2a As shown, the above-mentioned storage system 01 may include a three-dimensional memory 10. In this case, the storage system 10 may be integrated into a memory card, wherein the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC), secure digital memory card (SD) card, and UFS.

[0081] In other examples, such as Figure 2b As shown, the storage system 01 includes multiple three-dimensional storage devices 10. In this case, the storage system 01 can be integrated into a solid-state drive (SSD).

[0082] refer to Figure 3 The aforementioned three-dimensional memory 10 includes a substrate 200 and a semiconductor structure 100 disposed on one side of the substrate 200. The substrate 200 includes a base plate 201' and peripheral circuitry 202 disposed on the base plate 201'. The peripheral circuitry 202 is electrically coupled to the semiconductor structure 100. The coupling method may be, for example, bonding.

[0083] The material of the substrate 201' can be, for example, single-crystal silicon, or other suitable materials, such as silicon-germanium, germanium, or silicon-on-insulator thin film.

[0084] The peripheral circuitry described above may include transistors. The peripheral circuitry 202 is configured to control and sense the semiconductor structure 100. The peripheral circuitry 202 may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the semiconductor structure 100, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry 202 may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0085] Please refer to Figure 4a , Figure 4b and Figure 4c As shown, Figure 4a A three-dimensional structural diagram of a semiconductor structure 100 provided for some embodiments of this application. Figure 4b for Figure 4a A cross-sectional view of a memory cell string along section line AA' of a semiconductor structure 100. Figure 4c for Figure 4a The equivalent circuit diagram of a memory cell string in a semiconductor structure 100. (Example) Figure 4a As shown, the semiconductor structure 100 may include arrayed strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) 105. Figure 4c As shown, the memory cell string 105 may include multiple transistors T, each transistor T can be configured as a memory cell, and these transistors T are connected together to form a memory cell string. It should be noted that... Figure 4c The number of transistors is only illustrative. The storage cell string 105 of the three-dimensional memory provided in this embodiment may also include other numbers of transistors, such as 4, 16, 32, 64, etc., without specific limitation here.

[0086] Embodiments of this application also provide a semiconductor structure 100 and a method for fabricating the same, which can be applied to the three-dimensional memory 10 described above.

[0087] like Figure 4b As shown, the semiconductor structure 100 provided in the embodiments of this application includes a stacked structure 101 and a source layer SL. The source layer SL can be disposed on one side of the stacked structure 101 and can be electrically coupled to the source end of a plurality of memory cell strings 105.

[0088] Here, the material of the source layer SL may include, for example, one or more of single-crystal silicon, single-crystal germanium, III-V compound semiconductor materials, or II-VI compound semiconductor materials.

[0089] In the case where the semiconductor structure 100 is applied in the three-dimensional memory 10 described above, in some examples, the peripheral circuitry 202 may be disposed on the side of the semiconductor structure 100 away from the source layer SL.

[0090] The aforementioned stacked structure 101 includes a gate dielectric layer 120 and a gate layer 121 that are stacked alternately.

[0091] In some embodiments, the stacked structure 101 includes a plurality of gate dielectric layers 120 and a plurality of gate layers 121 stacked alternately. Among the various gate dielectric layers 120 and gate layers 121 of the stacked structure 101, the layer closest to the source layer SL is the gate dielectric layer 120.

[0092] Here, the number of gate dielectric layer 120 and gate layer 121 is not limited and can be set as needed. It is understood that the more gate dielectric layer 120 and gate layer 121 there are in the stacked structure 101, the higher the integration level, and the more memory cells (e.g., transistors) are formed in the memory cell string 105.

[0093] In some examples, gate layer 121 may include at least one (e.g., multiple) gate lines G for controlling the on-state of transistors in memory cell string 105. For example, at least one (e.g., one; or multiple) gate layer 121 located below along a first direction (e.g., including the gate layer 121 closest to the source layer SL among the multiple gate layers 121) is configured as at least one (e.g., one; or multiple) source select gate SGS, the source select gate SGS being configured to control the on-state of the lowest transistor, thereby controlling the on-state of the source channel in memory cell string 105; at least one (e.g., one; or multiple) gate layer 121 located above (e.g., including multiple gate lines G) The gate layer 121 furthest from the source layer SL in layer 121 is configured as at least one (e.g., one; or, multiple) drain select gate SGD, which is configured to control the conduction state of the uppermost transistor, thereby controlling the conduction state of the drain channels in the memory cell string 105; at least one (e.g., one; or, multiple) gate layer 121 located in the middle of the multiple gate layers 121 is configured as multiple word lines WL, and by writing different voltages on the word lines WL, data writing, reading and erasing of each memory cell (e.g., transistor T) in the memory cell string can be completed.

[0094] like Figure 4b As shown, the semiconductor structure 100 may further include a first capping layer 102, a channel via 103, and a channel structure 104. The first capping layer 102 is disposed on one side of the stacked structure 101, and the channel via 103 penetrates the first capping layer 102 and the stacked structure 101. The channel structure 104 is disposed within the channel via 103, and the channel structure 104 includes a dielectric core 111 and a functional layer 110, with the functional layer 110 disposed on the outer wall of the dielectric core 111. The diameter of the channel via 103 at the first capping layer 102 is greater than or equal to the diameter of the channel via 103 at the stacked structure 101, and the acid corrosion resistance of the first capping layer 102 is less than the acid corrosion resistance of the gate dielectric layer 120.

[0095] In some examples, such as Figure 4bAs shown, the stacked structure 101 further includes a second cover layer 107, which is disposed on the side of the first cover layer 102 facing the substrate 201 and on the side of the alternately stacked gate dielectric layer 120 and gate layer 121 away from the substrate 201; the acid corrosion resistance of the first cover layer 102 is less than that of the second cover layer 107.

[0096] like Figure 4b As shown, the source layer SL can be disposed on the side of the stacked structure 101 away from the first cover layer 102, and the source layer SL is electrically coupled to the functional layer 110 in the channel structure 104.

[0097] like Figure 4a and Figure 4c As shown, a memory cell, i.e., a transistor T (e.g., each transistor T), can be formed by a channel structure 104 and a gate line G surrounding the channel structure 104. The gate line G is configured to control the conduction state of the transistor.

[0098] like Figure 5 As shown, the preparation is as follows Figure 4b The semiconductor structure 100 shown may include steps S10 to S23:

[0099] S10, such as Figure 6 As shown, an etch barrier layer 203 is formed on the substrate 201.

[0100] For example, an etch barrier layer 203 can be formed on the substrate 201 using a thin film deposition process, such as a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and electroplating.

[0101] In some examples, substrate 201 can be a single-layer substrate or a composite substrate with a multilayer structure.

[0102] When the substrate 201 is a single-layer structure, the substrate 201 may include one or more semiconductor materials such as silicon, germanium, gallium arsenide, and indium phosphide; the substrate 201 may also be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0103] When the substrate 201 has a multilayer structure, the substrate 201 may include, for example, a base plate 201a and a first sacrificial layer 201b and a second sacrificial layer 201c sequentially stacked on the base plate 201a.

[0104] The material of the aforementioned substrate 201a may include, for example, one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials; the substrate 201a may also be made of a non-conductive material such as glass, plastic, or sapphire wafer. The material of the first sacrificial layer 201b may include, for example, silicon oxide and / or silicon nitride. The material of the second sacrificial layer 201c may include, for example, one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0105] Based on this, an etch barrier layer 203 can be formed on the substrate 201, or multiple etch barrier layers 203 can be formed. Figure 6 The following is an example of forming two etch barrier layers 203 on a substrate 201, namely etch barrier layer 203a and etch barrier layer 203b.

[0106] It should be noted that step S10 is an optional step; for example, in some examples, step S10 can be omitted.

[0107] S11, such as Figure 7 As shown, a stacked structure 106 is formed on the side of the etch barrier layer 203 away from the substrate 201. The stacked structure 106 includes a gate dielectric layer 120 and a gate sacrificial layer 122 that are stacked alternately in sequence, that is, the gate dielectric layer 120 and the gate sacrificial layer 122 are formed alternately in stacked on the side of the etch barrier layer 203 away from the substrate 201. It can be understood that if step S10 is omitted, step S11 is: forming the stacked structure 106 on the substrate 201.

[0108] In step S11, a thin film deposition process can be used to form alternating layers of gate dielectric layer 120 and gate sacrificial layer 122 on the side of etch barrier layer 203 away from substrate 201. The thin film deposition process may include, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or electroplating.

[0109] There is no limitation on the number of gate dielectric layer 120 and gate sacrificial layer 122 formed in step S11, and they can be set accordingly as needed. For example, the number of gate dielectric layer 120 or gate sacrificial layer 122 can be 6, 8, 12, 64, etc. Figure 7 The illustration is given as an example where both the gate dielectric layer 120 and the gate sacrificial layer 122 formed on the etch barrier layer 203 have six layers.

[0110] In addition, the thickness of the multiple gate dielectric layers 120 can be the same or different. Similarly, the thickness of the multiple gate sacrificial layers 122 can be the same or different, and can be set according to specific process requirements.

[0111] The stacked structure 106 can also be called the initial stacked structure. The purpose of forming the gate sacrificial layer 122 is to form a sacrificial gap between adjacent gate dielectric layers 120 after the gate sacrificial layer 122 is removed in subsequent processes, and then the gate layer 121 can be formed in the sacrificial gap.

[0112] Here, when forming the stacked structure 106, the gate dielectric layer 120 can be formed first, or the gate sacrificial layer 122 can be formed first. Alternatively, when forming the stacked structure 106, the gate dielectric layer 120 can be formed last, or the gate sacrificial layer 122 can be formed last.

[0113] The gate dielectric layer 120 is made of an insulating material, which may be, for example, one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials. Furthermore, the materials of each gate dielectric layer 120 may be the same or different. When the materials of the multiple gate dielectric layers 120 in the stacked structure 101 are the same, the fabrication process of the stacked structure 101 can be simplified when forming multiple gate dielectric layers 120.

[0114] The material of the gate sacrificial layer 122 may include, for example, one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.

[0115] S12, such as Figure 8 As shown, a second capping layer 107 is formed on the side away from the substrate 201 of the stacked alternating gate dielectric layer 120 and gate sacrificial layer 122, and the stacked structure 106 further includes the second capping layer 107.

[0116] It should be noted that step S12 is an optional step; for example, in some examples, step S12 can be omitted.

[0117] It is understood that through steps S11 and S12, a stacked structure 106 can be formed on the etch barrier layer 203. In this case, the stacked structure 106 includes a gate dielectric layer 120 and a gate sacrificial layer 122 stacked alternately, and a second capping layer 107 disposed on the stacked alternately stacked gate dielectric layer 120 and gate sacrificial layer 122. If step S12 is omitted, the stacked structure 106 includes the stacked alternately stacked gate dielectric layer 120 and gate sacrificial layer 122, but does not include the second capping layer 107.

[0118] For example, a thin-film deposition process can be used to form the second capping layer 107. The thin-film deposition process can be referred to the above, and will not be repeated here.

[0119] Here, the material of the second capping layer 107 may include, for example, silicon oxide and / or silicon nitride.

[0120] Based on this, the material of the second cover layer 107 and the material of the gate dielectric layer 120 can be the same or different.

[0121] S13, such as Figure 9 As shown, a first capping layer 102 is formed on the side of the second capping layer 107 away from the substrate 201. It can be understood that if step S12 is omitted, step S13 is: forming the first capping layer 102 on the alternating gate dielectric layer 120 and gate sacrificial layer 122.

[0122] For example, the first capping layer 102 can be formed using a thin film deposition process. The thin film deposition process can be referred to the above, and will not be repeated here.

[0123] Here, the material of the first capping layer 102 may include, for example, silicon oxide and / or silicon nitride.

[0124] It should be noted that the materials of the first covering layer 102 and the second covering layer 107 can be the same or different.

[0125] S14, such as Figure 10a As shown, a channel hole 103 is formed by etching the first capping layer 102 and the stacked structure 106 (the stacked structure 106 includes a second capping layer 107 and a gate dielectric layer 120 and a gate sacrificial layer 122 that are stacked alternately). The channel hole 103 passes through the first capping layer 102 and the stacked structure 106 in sequence, that is, the channel hole 103 passes through the first capping layer 102, the second capping layer 107, and the gate dielectric layer 120 and the gate sacrificial layer 122 that are stacked alternately.

[0126] Understandably, as the number of gate dielectric layer 120 and gate sacrificial layer 122 in the stacked structure 106 increases, the aspect ratio of the channel via 103 becomes larger and larger, which can cause some problems when forming the channel via 103. For example... Figure 10b As shown, the top of the channel hole 103 prepared by the prior art has a narrowing (such as...). Figure 10b (As shown by the dashed circle in the middle), that is, the diameter R at the top of the channel hole 103 is smaller than the diameter R' at other locations of the channel hole 103. Because there is a narrowing at the top of the channel hole 103, therefore... Figure 10c As shown, when a functional layer 110 and a dielectric core 111 are sequentially formed within the channel hole to form a channel structure, pores (such as...) are easily formed inside the dielectric core 111. Figure 10cMiddle position A and Figure 10d (As shown in position A), this allows the conductive material to easily enter the pores of the dielectric core 111 during subsequent processes when a conductive structure is formed above the channel hole. Figure 10e A topographic diagram of the semiconductor structure is shown, from Figure 10e It can be seen that some conductive material will flow into the pores of the dielectric core 111, which will affect the storage performance of the memory.

[0127] In summary, as the aspect ratio of the channel hole 103 increases, during the etching process to form the channel hole 103, if... Figure 10a As shown, the top of the via 103 will have a narrowing, which will affect the storage performance of the memory. Here, a dry etching process or a wet etching process can be used to etch the first capping layer 102 and the stacked structure 106.

[0128] It is understandable that when an etch barrier layer 203 is formed on the substrate 201, the etch barrier layer 203 can be used to prevent etching during the etching process to form the channel hole 103, thereby preventing the etched channel hole 103 from extending further to the substrate 201 and causing damage to the substrate 201, so as to protect the substrate 201.

[0129] Furthermore, when etching the first capping layer 102 and the stacked structure 106 to form the channel hole 103, in order to ensure that the first capping layer 102 and the stacked structure 106 are completely etched, therefore, as Figure 10a As shown, during etching, an over-etching method can be used, that is, to etch away part or all of the etching barrier layer 203, while the etching barrier layer 203 can prevent etching at this time.

[0130] S15, such as Figure 10f As shown, the sidewall of the channel hole 103 is corroded by an etchant to flatten the sidewall of the channel hole 103; wherein, the acid resistance of the first capping layer 102 to the etchant is less than that of the laminated structure 106 to the etchant, therefore, the diameter of the etched channel hole 103 in the first capping layer 102 is greater than or equal to the diameter of the channel hole 103 in the laminated structure 106.

[0131] When the stacked structure 106 includes a second capping layer 107 and alternatingly stacked gate dielectric layers 120 and gate sacrificial layers 122, the acid corrosion resistance of the first capping layer 102 to the etchant is less than that of the gate dielectric layers 120, the gate sacrificial layers 122, and the second capping layer 107. When the stacked structure 106 includes alternatingly stacked gate dielectric layers 120 and gate sacrificial layers 122 but does not include the second capping layer 107, the acid corrosion resistance of the first capping layer 102 to the etchant is less than that of the gate dielectric layers 120 and the gate sacrificial layers 122.

[0132] Here, the corrosive liquid can be, for example, hydrofluoric acid.

[0133] It is understandable that the lower the acid resistance of the film layer to the corrosive liquid, the easier it is for the film layer to be corroded away by the corrosive liquid; conversely, the higher the acid resistance of the film layer, the more difficult it is for the film layer to be corroded away by the corrosive liquid. Based on this, since the acid resistance of the first capping layer 102 to the corrosive liquid is lower than that of the stacked structure 106, when the sidewall of the channel hole 103 is corroded by the corrosive liquid, the corrosion rate of the first capping layer 102 is greater than that of the stacked structure 106. Therefore, the diameter of the channel hole 103 in the first capping layer 102 is greater than or equal to the diameter of the channel hole 103 in the stacked structure 106. When the stacked structure 106 includes a second capping layer 107 and alternatingly stacked gate dielectric layers 120 and gate sacrificial layers 122, the diameter of the channel hole 103 in the first capping layer 102 is greater than or equal to the diameter of the channel hole 103 in the gate dielectric layer 120, the gate sacrificial layer 122, and the second capping layer 107. In the case where the stacked structure 106 includes alternating stacked gate dielectric layer 120 and gate sacrificial layer 122, excluding the second capping layer 107, the diameter of the via 103 in the first capping layer 102 is greater than or equal to the diameter of the via 103 in the gate dielectric layer 120 and the gate sacrificial layer 122.

[0134] Typically, as the number of gate dielectric layer 120 and gate sacrificial layer 122 in the stacked structure 106 increases, the aspect ratio of the channel via becomes larger and larger. Therefore, when etching the channel via, a narrowing occurs at the top of the channel via. However, in this embodiment, while planarizing the channel via etchant, the first capping layer 102 has lower acid resistance to the etchant than the stacked structure 106. Therefore, as... Figure 10f As shown, the diameter of the etched channel hole 103 at the first cover layer 102 is greater than or equal to the diameter of the channel hole 103 at the stacked structure 106, thereby achieving the purpose of enlarging the top of the channel hole 103 and avoiding the problem of narrowing at the top of the channel hole 103 when etching to form the channel hole 103.

[0135] Considering that if the thickness of the first capping layer 102 is too small, even after planarizing the channel hole 103 with the etchant, although the diameter of the etched channel hole 103 in the first capping layer 102 is greater than or equal to the diameter of the channel hole 103 in the stacked structure 106, the stacked structure 106 will still experience a narrowing problem if the thickness of the first capping layer 102 is too small. Therefore, in some examples, the thickness of the first capping layer 102 can range from 500 Å to 2000 Å. For example, the thickness of the first capping layer 102 can range from 700 Å to 1300 Å.

[0136] Here, the thickness of the first capping layer 102 can be, for example, 500 Å, 700 Å, 1300 Å, or 2000 Å.

[0137] In the case where the stacked structure 106 includes a second cover layer 107, if the thickness of the second cover layer 107 is greater than the thickness of the first cover layer 102, when the channel hole 103 is planarized using an etchant, the second cover layer 107 may also experience narrowing because the etchant's corrosion rate on the second cover layer 107 is less than the etchant's corrosion rate on the first cover layer 102. Therefore, in some examples, the thickness of the first cover layer 102 is greater than or equal to the thickness of the second cover layer 107, which can prevent narrowing from occurring at the location of the second cover layer 107.

[0138] When the laminated structure 106 includes a second capping layer 107, in order to make the acid resistance of the first capping layer 102 to the corrosive liquid less than that of the second capping layer 107 to the corrosive liquid, the following two methods can be used:

[0139] The first method involves using the same material for the first cover layer 102 and the second cover layer 107, but with a lower density.

[0140] When the materials of the first cover layer 102 and the second cover layer 107 are the same, the density of the material of the first cover layer 102 is less than the density of the material of the second cover layer 107. This is so that when the channel hole is planarized by the etchant, the corrosion rate of the etchant on the first cover layer 102 is greater than the corrosion rate of the etchant on the second cover layer 107. This results in the diameter of the channel hole 103 after treatment being greater than or equal to the diameter of the channel hole 103 in the second cover layer 107. The constriction at the top of the channel hole 103 is then enlarged.

[0141] The second method involves using materials different from those used for the first covering layer 102 and the second covering layer 107. In this case, the materials of the first covering layer 102 and the second covering layer 107 are not limited, as long as the acid resistance of the first covering layer 102 to the corrosive liquid is less than that of the second covering layer 107.

[0142] Furthermore, when the materials of the first cover layer 102 and the second cover layer 107 are different, this can increase the diversity of material choices for the first cover layer 102 and the second cover layer 107.

[0143] When the stacked structure 106 includes a second capping layer 107, when the channel hole 103 is planarized using an etchant, the etchant will etch the first capping layer 102, the second capping layer 107, and the alternating gate dielectric layer 120 and gate sacrificial layer 122. The diameter of the channel hole 103 at the first capping layer 102 and at the second capping layer 107 will form a gradient change, which can reduce the longitudinal contour change during the etching of the channel hole 103 and help improve the structural stability of the prepared semiconductor structure.

[0144] S16. A functional layer 110 and a dielectric core 111 are sequentially formed in the channel hole 103 to form a channel structure 104. The functional layer 110 is disposed on the outer wall of the dielectric core 111.

[0145] For example, the functional layer 110 may include a barrier layer 110a, a charge storage layer 110b, a tunneling layer 110c, and a channel layer 110d, which are sequentially disposed on the outer wall of the dielectric core 111.

[0146] In some examples, step S16 may include the following steps S161 to S165:

[0147] S161, such as Figure 11 As shown, a barrier layer 110a is formed inside the channel hole 103.

[0148] For example, a thin film deposition process can be used to form a barrier layer 110a within the channel hole 103.

[0149] Here, the material of the barrier layer 110a may include, for example, one or a combination of silicon oxide, silicon nitride, or silicon oxynitride.

[0150] S162, such as Figure 12 As shown, a charge storage layer 110b is formed on the barrier layer 110a.

[0151] For example, a charge storage layer 110b can be formed on the barrier layer 110a using a thin film deposition process.

[0152] Here, the material of the charge storage layer 110b may include, for example, one or more combinations of silicon nitride, silicon oxynitride, and silicon. The charge storage layer 110b can be configured to perform storage operations on memory cells in a memory cell string. When a certain voltage is applied to the channel structure 104 through the gate layer 121, the storage or removal of charge in the charge storage layer 110b can affect the conduction state of the channel structure 104.

[0153] S163, such as Figure 13 As shown, a tunneling layer 110c is formed on the charge storage layer 110b.

[0154] For example, a tunneling layer 110c can be formed on the charge storage layer 110b using a thin film deposition process.

[0155] In some examples, the material of the tunneling layer 110c may include one or more combinations of silicon oxide, silicon nitride, or silicon oxynitride. Electrons or holes in the channel via 103 can tunnel through the tunneling layer 110c to the charge storage layer 110b.

[0156] S164, such as Figure 14 As shown, a channel layer 110d is formed on the tunnel layer 110c.

[0157] For example, a thin film deposition process can be used to form a trench layer 110d on the tunneling layer 110c.

[0158] Here, the material of the channel layer 110d may include, for example, polysilicon (p-Si).

[0159] When the functional layer 110 includes a barrier layer 110a, a charge storage layer 110b, a tunneling layer 110c, and a channel layer 110d, and the barrier layer 110a is made of silicon oxide, the charge storage layer 110b is made of silicon nitride, the tunneling layer 110c is made of silicon oxide, and the channel layer 110d is made of polysilicon, the functional layer 110 can also be called an (oxide-nitride-oxide-polysilicon, ONOP) structural layer.

[0160] S165, such as Figure 15a As shown, a dielectric core 111 is formed within the channel hole 103.

[0161] For example, a thin-film deposition process can be used to form a dielectric core 111 within the channel hole 103.

[0162] Here, the material of the dielectric core 111 may include, for example, one or a combination of silicon oxide, silicon nitride, or silicon oxynitride.

[0163] Figure 15b This is a topographic image of the semiconductor structure after step S165, from... Figure 15b It can be seen that the diameter R1 of the channel hole 103 at the first cover layer 102 is greater than or equal to the diameter R2 of the channel hole 103 at the laminated structure 106.

[0164] In some embodiments, the diameter of the dielectric core 111 at the first cover layer 102 is greater than or equal to the diameter of the dielectric core 111 at the stacked structure 106.

[0165] For example, after the channel layer 110d is formed in step S164, the channel layer 110d forms a receiving cavity. It is understood that the receiving cavity has an opening at the end furthest from the substrate 201. The diameter of the receiving cavity at the first capping layer 102 is greater than or equal to the diameter of the receiving cavity at the stacked structure 106. This avoids the formation of pores inside the dielectric core 111 when it is formed within the receiving cavity, thereby preventing conductive material from easily entering the pores inside the channel hole 103 during subsequent processes when a conductive structure is formed above the channel hole 103.

[0166] The diameter of the dielectric core 111 formed in the receiving cavity at the first cover layer 102 is greater than or equal to the diameter of the dielectric core 111 at the stacked structure 106.

[0167] S17, such as Figure 16 As shown, the functional layer 110 and the dielectric core 111 are ground flat to expose the surface of the first cover layer 102.

[0168] For example, a chemical mechanical polishing (CMP) process can be used to grind the functional layer 110 and the dielectric core 111 to expose the surface of the first cover layer 102, and make the ground surfaces of the functional layer 110 and the dielectric core 111 away from the substrate 201 flush with the surface of the first cover layer 102 away from the substrate 201.

[0169] S18, such as Figure 17 As shown, the gate sacrificial layer 122 is removed to form a sacrificial gap 123.

[0170] It should be noted that before removing the gate sacrificial layer 122, a gate line slit can be formed to pass through the first cover layer 102 and the stacked structure 106 in sequence, so that the gate sacrificial layer 122 between the gate dielectric layers 120 can be exposed through the gate line slit; then, the gate sacrificial layer 122 can be removed through the gate line slit, thereby forming a sacrificial gap 123 at the position where the gate sacrificial layer 122 was originally provided in the stacked structure 106.

[0171] It should be understood that, in order to avoid affecting the gate dielectric layer 120, the first capping layer 102, and the second capping layer 107 during the removal of the gate sacrificial layer 122, the materials of the gate dielectric layer 122, the gate dielectric layer 120, the first capping layer 102, and the second capping layer 107 should be selected to ensure that the gate sacrificial layer 122, the gate dielectric layer 120, the first capping layer 102, and the second capping layer 107 have different corrosion resistances. Thus, in the corrosion process, the gate sacrificial layer 122 can be removed while the gate dielectric layer 120, the first capping layer 102, and the second capping layer are retained.

[0172] S19. A gate layer 121 is formed in the sacrificial gap 123 to form a stacked structure 101, the stacked structure 101 including a second cover layer 107 and a gate dielectric layer 120 and a gate layer 121 stacked alternately.

[0173] It should be noted that, in some examples, the method for fabricating the semiconductor structure may further include, before step S19: (e.g.) Figure 18 As shown, a gate barrier layer 1211 is formed within the sacrificial gap 123. For example, a thin-film deposition process can be used to form the gate barrier layer 1211 within the sacrificial gap 123.

[0174] Here, the material of the gate barrier layer 1211 may include one or more of titanium nitride, tantalum nitride, and tungsten carbide, or other suitable materials.

[0175] After forming the gate barrier layer 1211, step S19 can be performed, i.e., as follows: Figure 19 As shown, a gate layer 121 is formed within the sacrificial gap 123.

[0176] For example, a thin-film deposition process can be used to form the gate layer 121 within the sacrificial gap 123.

[0177] Here, the material of the gate layer 121 may include, for example, one or more combinations of tungsten, cobalt, copper, aluminum, doped silicon, and silicide. Furthermore, the materials of each gate layer 121 may be the same or different. In some embodiments, the materials of each gate layer 121 are the same, for example, all are tungsten.

[0178] Understandably, when the gate barrier layer 1211 is formed, the gate layer 121 can be separated from the channel structure 104 by the gate barrier layer 1211. The gate barrier layer 1211 is configured as a material barrier layer, which can serve as a barrier layer to reduce the diffusion of impurity atoms or gases into the gate dielectric layer 120 and the channel structure 104; the gate barrier layer 1211 can also be configured as an adhesive layer to enhance the adhesion between the gate layer 121 and the gate dielectric layer 120.

[0179] In some embodiments, the diameter of the dielectric core 111 at the first cover layer 102 is greater than or equal to the diameter of the dielectric core 111 at the stack structure 101.

[0180] In cases where the semiconductor structure 100 also includes a source layer SL, in some examples, after step S19, the fabrication method of the semiconductor structure 100 further includes:

[0181] S20, such as Figure 20 As shown, an array interconnect layer 204 is formed on the first cover layer 102.

[0182] Here, the array interconnect layer 204 can be electrically coupled to the memory cell string. The array interconnect layer 204 may include the drain terminal (i.e., bit line BL) of the memory cell string 105, which can be electrically coupled to the channel layer 110d of each transistor T in at least one memory cell string 105. In this way, the array interconnect layer 204 can realize the electrical coupling between the semiconductor structure 100 and the peripheral circuit.

[0183] For example, such as Figure 20 As shown, the array interconnect layer 204 may include one or more first interlayer insulating layers 205, and may also include a plurality of contacts that are insulated from each other by these first interlayer insulating layers 205, such as... Figure 4a As shown, the contacts include, for example, a bit line contact BL-CNT, which is electrically coupled to the bit line BL; and a drain select gate contact SGD-CNT, which is electrically coupled to the drain select gate SGD. The array interconnect layer 204 may also include one or more first interconnect conductor layers 206. The first interconnect conductor layer 206 may include multiple interconnect lines, such as the bit line BL, and a word line interconnect line WL-CL electrically coupled to the word line WL.

[0184] Here, the materials of the first interconnect conductor layer 206 and the contacts may include, for example, one or more combinations of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials.

[0185] Furthermore, the material of the first interlayer insulation layer 205 may include, for example, one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0186] In some examples, the array interconnect layer 204 is used for electrical coupling with peripheral circuits, so that the memory cell string 105 of the semiconductor structure 100 can be electrically coupled to the peripheral circuits to realize the transmission of electrical signals between the memory cell string 105 and the peripheral circuits. Based on this, in some examples, after step S20, the above-mentioned semiconductor structure fabrication method may further include: Figure 21 As shown, a peripheral interconnect layer 210 is formed on the side of the array interconnect layer 204 away from the stack structure 101, and the peripheral interconnect layer 210 is electrically coupled to the array interconnect layer 204.

[0187] like Figure 21 As shown, the peripheral interconnect layer 210 can be used to electrically couple the array interconnect layer 204 and the peripheral circuit 202 in the substrate 200, so that the semiconductor structure 100 and the peripheral circuit 202 can be electrically coupled. The peripheral circuit 202 may include a transistor 209. Specifically, the peripheral interconnect layer 210 can be electrically coupled to the transistor 209 of the peripheral circuit 202 to realize the transmission of electrical signals between the transistor 209 and the peripheral interconnect layer 210.

[0188] The peripheral interconnect layer 210 may include one or more second interlayer insulating layers 211, and may also include one or more second interconnect conductor layers 212. Different second interconnect conductor layers 212 may be electrically coupled to each other via contacts.

[0189] The material of the second interconnect conductor layer 212 and the contacts can be, for example, one or more combinations of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials. The material of the second interlayer insulating layer 211 is an insulating material, for example, one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0190] In some possible implementations, a layer such as the peripheral interconnect layer 210 and the array interconnect layer 204 can also be provided between them. Figure 21 The bonding interface 207 shown allows the peripheral interconnect layer 210 and the array interconnect layer 204 to be bonded to each other and electrically coupled.

[0191] S21, such as Figure 22 As shown, substrate 201 is removed.

[0192] Here, the base plate 201a in the substrate 201 can be removed using CMP process, and the first sacrificial layer 201b and the second sacrificial layer 201c in the substrate 201 can be removed using etching process.

[0193] S22, such as Figure 23As shown, the barrier layer 203a is etched, and the barrier layer 110a, charge storage layer 110b and tunneling layer 110c exposed in the functional layer 110 to expose the channel layer 110d.

[0194] S23, such as Figure 24 As shown, a source layer SL is formed on the side of the stacked structure 101 away from the first capping layer 102, and the source layer SL is electrically coupled to the channel layer 110d.

[0195] It should be noted that in some examples, during the fabrication of the semiconductor structure 100, the formation of the stacked structure 106 on the substrate 201 includes steps S11 and S12. In this case, the resulting semiconductor structure 100 is as follows: Figure 24 As shown, the stacked structure 101 includes a second capping layer 107, which is disposed on the side of the first capping layer 102 facing the substrate 201 and located on the side of the alternately stacked gate dielectric layer 120 and gate layer 121 away from the substrate 201. In some other examples, when forming the stacked structure 106 on the substrate 201, step S11 is included, but step S12 is not included. In this case, the resulting semiconductor structure 100 is as follows: Figure 25 As shown.

[0196] Understandably, as the number of gate dielectric layer 120 and gate sacrificial layer 122 in the stacked structure 106 increases, the process of etching the stacked structure 106 to form the channel hole 103 becomes increasingly difficult due to the increased aspect ratio of the channel hole 103. Specifically, when forming the channel hole 103 using dry and / or wet etching processes, the diameter at the top of the etched channel hole 103 is smaller than the diameter at other locations in the channel hole 103 due to the limitations of the etching process. That is, a narrowing occurs at the top of the channel hole 103. In subsequent processes, when the functional layer 110 and the dielectric core 111 are formed sequentially within the channel hole 103, pores easily form inside the dielectric core 111. As a result, when the conductive structure is formed above the channel hole 103 in subsequent processes, conductive material can easily enter the pores inside the dielectric core 111. This can affect the charge storage of the charge storage layer 110b in the functional layer 100, thereby affecting the storage performance of the three-dimensional memory.

[0197] To address the problem that the narrowing at the tip of the formed channel hole 103 leads to the formation of pores in the dielectric core 111 within the channel hole 103, allowing conductive material to easily enter these pores and thus affecting the storage performance of the three-dimensional memory, the first related technology proposes the following steps during the fabrication of the semiconductor structure: First, as... Figure 26As shown, the alternating gate dielectric layer 120 and gate sacrificial layer 122 are etched to form a channel via 103. Because the channel via 103 has a large depth-to-width ratio, a narrowing is formed at the top of the channel via 103; next, as... Figure 27 As shown, the top of the channel hole 103 is etched to widen the top of the channel hole 103, so that the diameter at the top of the channel hole 103 is greater than or equal to the diameter at other locations of the channel hole 103; next, as Figure 28 As shown, a barrier layer 110a, a charge storage layer 110b, a tunneling layer 110c, a channel layer 110d, and a dielectric core 111 are sequentially formed within the channel hole 103.

[0198] The second related technology proposes that the following steps can be used when fabricating semiconductor structures: First, as... Figure 26 As shown, the alternating gate dielectric layer 120 and gate sacrificial layer 122 are etched to form a channel via 103. Next, a functional layer is formed within the channel via 103, namely, a barrier layer 110a, a charge storage layer 110b, a tunneling layer 110c, and a channel layer 110d are sequentially formed within the channel via 103. The functional layer 110 located at the top of the channel via 103 is etched so that the diameter at the top of the channel via 103 is greater than or equal to the diameter at other locations of the channel via 103 before the dielectric core 111 is formed. This ensures that no pores appear inside the dielectric core 111 when the dielectric core 111 is filled into the channel via 103 in subsequent processes. Next, the dielectric core 111 is sequentially filled into the channel via 103.

[0199] The etching of the functional layer 110 located at the top of the channel hole 103 can include the following situations:

[0200] The first type, such as Figure 29 As shown, firstly, a barrier layer 110a is formed within the channel hole 103; next, as... Figure 30 As shown, the barrier layer 110a at the top of the channel hole 103 is etched. After etching the barrier layer 110a at the top of the channel hole 103, the diameter of the top of the channel hole 103 after the barrier layer 110a is formed is greater than or equal to the diameter at other locations of the channel hole 103 after the barrier layer 110a is formed; next, as Figure 31 As shown, a charge storage layer 110b, a tunneling layer 110c, and a channel layer 110d are sequentially formed on the barrier layer 110a.

[0201] The second method involves first forming a barrier layer 110a and a charge storage layer 110b sequentially within the channel hole 103; then, etching the charge storage layer 110b at the top of the channel hole 103. After etching the charge storage layer 110b at the top of the channel hole 103, the diameter of the top of the channel hole 103 after forming the barrier layer 110a and the charge storage layer 110b is greater than or equal to the diameter at other locations of the channel hole 103 after forming the barrier layer 110a and the charge storage layer 110b; next, forming a tunneling layer 110c and a channel layer 110d sequentially on the charge storage layer 110b.

[0202] The third method: First, a barrier layer 110a, a charge storage layer 110b, and a tunneling layer 110c are sequentially formed inside the channel hole 103; next, the tunneling layer 110c at the top of the channel hole 103 is etched. After etching the tunneling layer 110c at the top of the channel hole 103, the diameter of the top of the channel hole 103 after the barrier layer 110a, charge storage layer 110b, and tunneling layer 110c are formed is greater than or equal to the diameter at other locations of the channel hole 103 after the barrier layer 110a, charge storage layer 110b, and tunneling layer 110c are formed; next, a channel layer 110d is formed on the tunneling layer 110c.

[0203] The fourth method involves first forming a barrier layer 110a, a charge storage layer 110b, a tunneling layer 110c, and a channel layer 110d sequentially within the channel hole 103; then, etching is performed on the channel layer 110d at the top of the channel hole 103. After etching, the diameter of the top of the channel hole 103 after forming the barrier layer 110a, charge storage layer 110b, tunneling layer 110c, and channel layer 110d is greater than or equal to the diameter at other locations of the channel hole 103 after forming the barrier layer 110a, charge storage layer 110b, tunneling layer 110c, and channel layer 110d.

[0204] It should be understood that when the barrier layer 110a, charge storage layer 110b, tunneling layer 110c, or channel layer 110d at the top of the channel hole 103 are etched, they will not be completely etched away. Only a portion of the barrier layer 110a, charge storage layer 110b, tunneling layer 110c, or channel layer 110d will be etched, which is equivalent to thinning the barrier layer 110a, charge storage layer 110b, tunneling layer 110c, or channel layer 110d. Therefore, the barrier layer 110a, charge storage layer 110b, tunneling layer 110c, and channel layer 110d can still play their corresponding roles at the top of the channel hole 103.

[0205] It is understandable that when etching the functional layer 110 located at the top of the channel hole 103, it can be done as shown in the first, second, third and fourth methods above, by etching only one of the barrier layer 110a, charge storage layer 110b, tunneling layer 110c and channel layer 110d. Of course, it is also possible to etch multiple layers of the barrier layer 110a, charge storage layer 110b, tunneling layer 110c and channel layer 110d.

[0206] While the first and second related technologies described above involve re-etching the gate dielectric layer 120 and gate sacrificial layer 122 located at the top of the channel hole 103 before forming the dielectric core 111, or etching the functional layer 110 located at the top of the channel hole 103 to perform hole enlargement processing and remove the narrowing, thus avoiding the presence of voids when forming the dielectric core 111, this increases the number of process steps in fabricating the semiconductor structure, thereby complicating the fabrication process and increasing production costs. Furthermore, the re-etching of the top of the channel hole 103 or the functional layer 110 at the top of the channel hole 103 during the hole enlargement process in the first and second related technologies inevitably has an adverse effect on the structural stability of the semiconductor structure, and also tests the reliability of the etching operation, affecting product yield and undoubtedly increasing fabrication costs.

[0207] In the process of fabricating the semiconductor structure 100 in the embodiments of this application, since a first capping layer 102 is formed on one side of the stacked structure 106, and the acid corrosion resistance of the first capping layer 102 is less than that of the stacked structure 106, when the channel hole 103 is planarized using an etchant, the corrosion rate of the etchant on the first capping layer 102 is greater than that of the etchant on the stacked structure 106. Therefore, it can be ensured that after the channel hole 103 is planarized using an etchant, the diameter of the channel hole 103 in the first capping layer 102 is greater than or equal to the diameter of the channel hole 103 in the stacked structure 106. In this way, the top of the channel hole 103 can be enlarged, solving the problem of narrowing at the top of the channel hole 103 when etching to form the channel hole 103. By using an etching solution to planarize the channel hole 103, the diameter at the top of the channel hole 103 can be increased, making the diameter at the top of the channel hole 103 greater than or equal to the diameter at other locations of the channel hole 103. In this way, when the functional layer 110 and the dielectric core 111 are sequentially formed inside the channel hole 103 to form the channel structure 104, the formation of pores inside the dielectric core 111 is avoided. This prevents the conductive material from easily entering the pores inside the channel hole 103 when the conductive structure is formed above the channel hole 103 in subsequent processes, thus avoiding the problem of charge storage and consequently affecting the storage performance of the memory. This increases the product yield and ensures the storage performance of the three-dimensional memory.

[0208] Based on this, planarizing the channel hole 103 with an etching solution is an existing process step in the preparation of semiconductor structures. This application utilizes the existing process step to enlarge the narrowed opening at the top of the channel hole 103. That is, while planarizing the channel hole 103 with an etching solution, the top of the channel hole 103 is enlarged. Therefore, no additional operation steps are required, and no additional preparation cost is increased.

[0209] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A stacked structure is formed on a substrate, the stacked structure comprising a gate dielectric layer and a gate sacrificial layer that are stacked alternately in sequence; A first cover layer is formed on the stacked structure; The first capping layer and the stacked structure are etched to form a channel hole; the channel hole sequentially penetrates the first capping layer and the stacked structure; The sidewalls of the channel hole are etched using an etchant to flatten them; wherein the acid resistance of the first capping layer to the etchant is less than that of the gate dielectric layer and the gate sacrificial layer to the etchant, and the diameter of the etched channel hole in the first capping layer is greater than or equal to the diameter of the channel hole in the stacked structure. A functional layer and a dielectric core are sequentially formed within the channel hole to form a channel structure; wherein the functional layer is disposed on the outer wall of the dielectric core.

2. The preparation method according to claim 1, characterized in that, The formation of the stacked structure on the substrate includes: A gate dielectric layer and a gate sacrificial layer are formed on the substrate in alternating layers; A second capping layer is formed on the side of the stacked alternating gate dielectric layer and gate sacrificial layer away from the substrate; the stacked structure further includes the second capping layer.

3. The preparation method according to claim 2, characterized in that, The first cover layer is made of the same material as the second cover layer, and the density of the material in the first cover layer is less than the density of the material in the second cover layer.

4. The preparation method according to claim 2, characterized in that, The materials of the first cover layer and the second cover layer are different.

5. The preparation method according to any one of claims 1 to 4, characterized in that, After the functional layer and dielectric core are sequentially formed within the channel hole to form the channel structure, the fabrication method further includes: Remove the gate sacrificial layer to form a sacrificial gap; A gate layer is formed within the sacrificial gap to form a stacked structure comprising alternating layers of the gate dielectric layer and the gate layer.

6. The preparation method according to claim 1, characterized in that, Before forming the stacked structure on the substrate, the fabrication method further includes: An etching barrier layer is formed on the substrate.

7. A semiconductor structure, characterized in that, include: A stacked structure, comprising alternating layers of gate dielectric and gate layer; A first covering layer is disposed on one side of the stacked structure; A channel hole penetrates the first cover layer and the stacked structure; wherein the diameter of the channel hole at the first cover layer is greater than or equal to the diameter of the channel hole at the stacked structure, and the acid corrosion resistance of the first cover layer is less than that of the gate dielectric layer. A channel structure is disposed within the channel hole, the channel structure comprising a dielectric core and a functional layer; the functional layer is disposed on the outer wall of the dielectric core.

8. The semiconductor structure according to claim 7, characterized in that, The diameter of the dielectric core at the first cover layer is greater than or equal to the diameter of the dielectric core at the stacked structure.

9. The semiconductor structure according to claim 7, characterized in that, The stacked structure further includes a second cover layer, which is disposed on the side of the first cover layer facing the stacked alternating gate dielectric layer and gate layer, and is located on the side of the stacked alternating gate dielectric layer and gate layer facing the first cover layer; The acid corrosion resistance of the first coating layer is less than that of the second coating layer.

10. The semiconductor structure according to claim 9, characterized in that, The thickness of the first covering layer is greater than or equal to the thickness of the second covering layer.

11. The semiconductor structure according to claim 9 or 10, characterized in that, The first cover layer is made of the same material as the second cover layer, and the density of the material in the first cover layer is less than the density of the material in the second cover layer.

12. The semiconductor structure according to claim 9 or 10, characterized in that, The materials of the first cover layer and the second cover layer are different.

13. The semiconductor structure according to any one of claims 7-10, characterized in that, The thickness of the first covering layer ranges from 500 Å to 2000 Å.

14. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure further includes a source layer disposed on the side of the stacked structure away from the first capping layer and coupled to the functional layer in the channel structure.

15. A three-dimensional memory, characterized in that, Includes peripheral circuitry and a semiconductor structure as described in any one of claims 7 to 14; The peripheral circuit is electrically coupled to the semiconductor structure.

16. A storage system, characterized in that, Includes a controller and the three-dimensional memory as described in claim 15; The controller is electrically coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

17. An electronic device, characterized in that, It includes a printed circuit board and a storage system as described in claim 16, wherein the storage system is coupled to the printed circuit board.

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