Array substrate, preparation method of array substrate and display panel

Abstract

The application provides an array substrate, a preparation method of the array substrate and a display panel. The array substrate is applied to a display panel with a light-emitting pixel layer. The display panel comprises a light-transmitting display area. The array substrate is provided with a light-transmitting connecting line. The array substrate outside the light-transmitting display area is provided with a metal oxide thin film transistor. At least part of the connecting line is located in the light-transmitting display area. One end of the connecting line is electrically connected to the metal oxide thin film transistor. The other end of the connecting line is used for electrically connecting to the light-emitting pixel layer located in the light-transmitting display area. The active layer of the metal oxide thin film transistor is provided in the same layer as the connecting line, so that the preparation process can be simplified. Therefore, the array substrate, the preparation method of the array substrate and the display panel provided by the application are simple in preparation method and can simplify the preparation process of the array substrate and the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, and in particular to an array substrate, a preparation method of the array substrate, and a display panel. BACKGROUND

[0002] With the development of display technology, the market demand for display panels with high screen-to-body ratio is increasingly urgent, and display panels are developing towards full-screen.

[0003] In the related art, a display panel includes a light-transmitting display area, and a backlight surface of the display panel in the light-transmitting display area is integrated with an under-screen functional device. Light can pass through the display panel in the light-transmitting display area to reach the under-screen functional device, thereby realizing the function of the under-screen functional device. On the other hand, the display panel in the light-transmitting display area can also normally emit light to realize a display function, thereby ensuring that the display panel has a high screen-to-body ratio.

[0004] However, the preparation process of the display panel is relatively complex. SUMMARY

[0005] In view of at least one of the above technical problems, the embodiments of the present application provide an array substrate, a preparation method of the array substrate, and a display panel. The preparation method of the array substrate is relatively simple, and can simplify the preparation process of the array substrate and the display panel.

[0006] To achieve the above object, the embodiments of the present application provide the following technical solutions.

[0007] A first aspect of the embodiments of the present application provides an array substrate for a display panel having a light-emitting pixel layer. The display panel includes a light-transmitting display area.

[0008] The array substrate is provided with a light-transmitting connection line. The array substrate outside the light-transmitting display area is provided with a metal oxide thin film transistor. At least part of the connection line is located in the light-transmitting display area. One end of the connection line is electrically connected to the metal oxide thin film transistor, and the other end of the connection line is used for electrically connecting to the light-emitting pixel layer located in the light-transmitting display area.

[0009] The active layer of the metal oxide thin film transistor is provided in the same layer as the connection line.

[0010] The array substrate provided by the embodiment of the present application is applied to a display panel with a light-emitting pixel layer, and the display panel comprises a light-transmitting display area for setting a function device under screen. The array substrate is provided with a connection line. The light-emitting pixel layer and the array substrate can be electrically connected through the connection line. The array substrate located outside the light-transmitting display area is provided with a metal oxide thin film transistor, and at least part of the connection line is located in the light-transmitting display area. The light-emitting pixel layer located in the light-transmitting display area is electrically connected to the metal oxide thin film transistor through the connection line located in the light-transmitting display area, so that the metal oxide thin film transistor controls the light-emitting pixel layer located in the light-transmitting display area to emit light. The connection line is light-transmitting, so as to avoid the influence of the connection line on the light transmittance of the light-transmitting display area. The active layer of the metal oxide thin film transistor is provided in the same layer as the connection line, so that the active layer of the metal oxide thin film transistor and the connection line are prepared at the same time. An ITO layer does not need to be prepared separately between the metal oxide thin film transistor and the light-emitting pixel layer, so that the preparation method of the array substrate is relatively simple, the preparation process of the array substrate and the display panel is simplified, the production cost is reduced, and the production capacity is improved.

[0011] In a possible implementation, the connection line comprises a first connection line, and the first connection line is located in the light-transmitting display area.

[0012] One end of the first connection line is electrically connected to the light-emitting pixel layer located in the light-transmitting display area, and the other end of at least part of the first connection line extends to outside the light-transmitting display area and is electrically connected to the metal oxide thin film transistor.

[0013] In this way, the first connection line is provided in the same layer as the active layer of the metal oxide thin film transistor, so that the preparation method of the array substrate is relatively simple, and the preparation process of the array substrate and the display panel is simplified.

[0014] In a possible implementation, the array substrate further comprises a transition area adjacent to the light-transmitting display area, and the metal oxide thin film transistor is located in the transition area.

[0015] The connection line comprises a second connection line located in the transition area, one end of the second connection line is electrically connected to the metal oxide thin film transistor located in the transition area, and the other end of the second connection line is used for electrically connecting to the light-emitting pixel layer located in the transition area.

[0016] Alternatively, the array substrate further comprises an insulating layer located between the metal oxide thin film transistor and the light-emitting pixel layer, and the insulating layer located in the transition area is provided with a first via hole. The light-emitting pixel layer located in the transition area is electrically connected to the metal oxide thin film transistor located in the transition area through the first via hole.

[0017] It can be implemented that one end of at least part of the first connection line extends into the transition region and is electrically connected to the metal oxide thin film transistor located in the transition region.

[0018] In this way, the electrical connection mode of the light-emitting pixel layer in the transition region and the array substrate can be provided with multiple choices.

[0019] In a possible implementation, the display panel further includes a non-light-transmitting display region, the transition region is located between the light-transmitting display region and the non-light-transmitting display region, and the metal oxide thin film transistor is located in the non-light-transmitting display region.

[0020] The connection line includes a third connection line located in the non-light-transmitting display region, one end of the third connection line is electrically connected to the metal oxide thin film transistor located in the non-light-transmitting display region, and the other end of the third connection line is used for electrical connection to the light-emitting pixel layer located in the non-light-transmitting display region.

[0021] Alternatively, the array substrate includes an insulating layer located between the metal oxide thin film transistor and the light-emitting pixel layer, and the insulating layer located in the non-light-transmitting display region has a second via hole, and the light-emitting pixel layer located in the non-light-transmitting display region is electrically connected to the metal oxide thin film transistor located in the non-light-transmitting display region through the second via hole.

[0022] In this way, the electrical connection mode of the light-emitting pixel layer in the non-light-transmitting display region and the array substrate can be provided with multiple choices.

[0023] In a possible implementation, the connection line is connected to the active layer of the metal oxide thin film transistor, and part of the connection line forms a source electrode or a drain electrode of the metal oxide thin film transistor.

[0024] In this way, the source electrode or the drain electrode of the MO thin film transistor can be omitted, so that the preparation process of the array substrate and the display panel is simplified.

[0025] In a possible implementation, the connection line is arranged apart from the active layer of the metal oxide thin film transistor, the array substrate includes a low-temperature polycrystalline silicon thin film transistor, and the connection line is connected to a source electrode or a drain electrode of the low-temperature polycrystalline silicon thin film transistor.

[0026] In this way, the advantages of the MO thin film transistor and the LTPS (Low Temperature Polycrystalline) thin film transistor can be combined.

[0027] In a possible implementation, the thickness of the active layer of the metal oxide thin film transistor is less than or equal to the thickness of the connection line.

[0028] It can be implemented that the difference between the thickness of the active layer of the metal oxide thin film transistor and the thickness of the connection line is not greater than 50 angstroms.

[0029] In this way, the active layer of the MO thin film transistor is thin, and the flatness of the array substrate can be reduced. The thickness of the connection line is large, so that the resistance of the connection line is low, and the voltage drop can be reduced.

[0030] In a possible implementation, the material of the active layer of the metal oxide thin film transistor includes at least one of indium gallium zinc oxide, zinc aluminum oxide, zinc oxide, and indium zinc oxide.

[0031] In this way, more choices can be provided for the material of the active layer of the MO thin film transistor.

[0032] A second aspect of the embodiments of the present application provides a preparation method of an array substrate, the array substrate being applied to a display panel having a light-emitting pixel layer, the display panel including a light-transmitting display area, and the preparation method of the array substrate including:

[0033] providing a substrate;

[0034] forming a metal oxide semiconductor layer on the substrate;

[0035] processing part of the metal oxide semiconductor layer, and forming a connection line, and the remaining part of the metal oxide semiconductor layer forming an active layer of a metal oxide thin film transistor; the metal oxide thin film transistor is located outside the light-transmitting display area, and at least part of the connection line is located in the light-transmitting display area;

[0036] one end of the connection line is electrically connected to the metal oxide thin film transistor, and the other end of the connection line is used for electrical connection to the light-emitting pixel layer located in the light-transmitting display area.

[0037] The preparation method of the array substrate provided by the embodiments of the present application is applied to a display panel having a light-emitting pixel layer, the display panel including a light-transmitting display area, and the light-transmitting display area being used for setting a function device under the screen. The active layer of the metal oxide thin film transistor and the connection line are simultaneously prepared by using the metal oxide semiconductor layer on the substrate, at least part of the connection line is located in the light-transmitting display area, and the light-emitting pixel layer located in the light-transmitting display area is electrically connected to the metal oxide thin film transistor through the connection line located in the light-transmitting display area, so that the metal oxide thin film transistor controls the light-emitting pixel layer located in the light-transmitting display area to emit light. The connection line is light-transmitting, so as to avoid the influence of the connection line on the light transmittance of the light-transmitting display area. Since the active layer of the metal oxide thin film transistor and the connection line are simultaneously prepared, it is not necessary to separately prepare an ITO layer between the metal oxide thin film transistor and the light-emitting pixel layer, so that the preparation method of the array substrate is relatively simple, the preparation process of the array substrate and the display panel is simplified, the production cost is reduced, and the production capacity is improved.

[0038] The third aspect of the embodiment of the present application provides a display panel, comprising a light-emitting pixel layer and the array substrate in the first aspect.

[0039] The display panel provided by the embodiment of the present application comprises an array substrate, the array substrate is applied to a display panel with a light-emitting pixel layer, and the display panel comprises a light-transmitting display area used for arranging an under-screen functional device. The array substrate is provided with a connection line. The light-emitting pixel layer and the array substrate can be electrically connected through the connection line. The array substrate located outside the light-transmitting display area is provided with a metal oxide thin film transistor, at least part of the connection line is located in the light-transmitting display area, and the light-emitting pixel layer located in the light-transmitting display area is electrically connected to the metal oxide thin film transistor through the connection line located in the light-transmitting display area, so that the metal oxide thin film transistor controls the light-emitting pixel layer located in the light-transmitting display area to emit light. The connection line is light-transmitting, so as to avoid the influence of the connection line on the light transmittance of the light-transmitting display area. The active layer of the metal oxide thin film transistor is provided in the same layer as the connection line, so that the active layer of the metal oxide thin film transistor and the connection line are prepared at the same time. An ITO layer does not need to be prepared separately between the metal oxide thin film transistor and the light-emitting pixel layer, so that the preparation method of the array substrate is relatively simple, the preparation process of the array substrate and the display panel is simplified, the production cost is reduced, and the production capacity is improved.

[0040] The configuration of the present application and other inventive purposes and benefits will be more obvious and easy to understand through the description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0042] Figure 1 The display panel structure schematic diagram provided by the embodiment of the present application is shown in the figure;

[0043] Figure 2 Another structure schematic diagram of the display panel provided by the embodiment of the present application is shown in the figure;

[0044] Figure 3 The partial cross-sectional view of the display panel provided by the embodiment of the present application is shown in the figure;

[0045] Figure 4 Another partial cross-sectional view of the display panel provided by the embodiment of the present application is shown in the figure;

[0046] Figure 5Another partial sectional view of the display panel provided by the embodiment of the present application;

[0047] Figure 6 Flow chart of the preparation method of the array substrate provided by the embodiment of the present application;

[0048] Figure 7 Structural schematic diagram after step S100 is completed, provided by the embodiment of the present application;

[0049] Figure 8 Structural schematic diagram after step S200 is completed, provided by the embodiment of the present application;

[0050] Figure 9 Structural schematic diagram after step S300 is completed, provided by the embodiment of the present application.

[0051] Explanation of reference numerals:

[0052] 100: display panel; 100a: light-transmitting display area;

[0053] 100b: transition area; 100c: non-light-transmitting display area;

[0054] 101: MO thin film transistor; 102: LTPS thin film transistor;

[0055] 103: driving unit; 110: array substrate;

[0056] 111: first active layer; 112: second active layer;

[0057] 113: first gate layer; 114: second gate layer;

[0058] 115: first source-drain layer; 116: second source-drain layer;

[0059] 117: substrate; 118: MO semiconductor layer;

[0060] 121: first insulating layer; 122: second insulating layer;

[0061] 124: fourth insulating layer; 125: fifth insulating layer;

[0062] 126: planarization layer; 130: connecting line;

[0063] 131: first connecting line; 140: light-emitting pixel layer;

[0064] 141: pixel. DETAILED DESCRIPTION

[0065] In related technologies, a display panel may include an array substrate on which a light-emitting pixel layer is disposed. The display panel includes a light-transmitting display area for housing under-display functional devices. A thin-film transistor (TFT) is disposed in the array substrate, and an indium tin oxide (ITO) layer is disposed between the TFT and the light-emitting pixel layer. The TFT may be located outside the light-transmitting display area, while the ITO layer is at least partially located within the light-transmitting display area. The light-emitting pixel layer located in the light-transmitting display area is electrically connected to the TFT located outside the light-transmitting display area via the ITO layer.

[0066] However, in order to electrically connect the light-emitting pixel layer located in the light-transmitting display area to the thin-film transistor located outside the light-transmitting display area, an ITO layer needs to be set between the thin-film transistor and the light-emitting pixel layer. This makes the fabrication method of the array substrate more complicated, which in turn makes the manufacturing process of the display panel more complicated, increases costs, and reduces production capacity.

[0067] Based on at least one of the aforementioned technical problems, embodiments of this application provide an array substrate, a method for fabricating the array substrate, and a display panel. The array substrate is applied to a display panel having a light-emitting pixel layer. The display panel includes a light-transmitting display area for housing under-display functional devices. Connecting lines are disposed in the array substrate. The light-emitting pixel layer and the array substrate can be electrically connected via the connecting lines. A metal-oxide-slim transistor (MTT) is disposed in the array substrate outside the light-transmitting display area. At least a portion of the connecting lines are located within the light-transmitting display area. The light-emitting pixel layer located in the light-transmitting display area is electrically connected to the MTT via the connecting lines located in the light-transmitting display area, thereby enabling the MTT to control the light-emitting pixel layer in the light-transmitting display area to emit light. The connecting lines are light-transmitting to avoid affecting the transmittance of the light-transmitting display area. The active layer of the MTT is disposed in the same layer as the connecting lines, allowing the active layer of the MTT and the connecting lines to be fabricated simultaneously. There is no need to separately fabricate an ITO layer between the MTT and the light-emitting pixel layer, thus simplifying the fabrication method of the array substrate, reducing the fabrication process of the array substrate and the display panel, lowering production costs, and increasing production capacity.

[0068] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0069] The following will combine Figures 1-9The display device provided in the embodiments of this application will be described.

[0070] This embodiment provides a display device, which includes a display panel 100. The display device can be a mobile or fixed terminal with a display panel 100, such as an electronic paper device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart bracelet, smartwatch, supercomputer, or navigator.

[0071] The display panel 100 can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (Micro LED or μLED) display panel, or a liquid crystal display (LCD) display panel.

[0072] The display panel 100 provided in the embodiments of this application will be described below.

[0073] This embodiment provides a display panel 100, which can be applied to the display device in the above embodiment.

[0074] The display panel 100 may include a light-emitting surface and a backlight surface disposed opposite to each other. The light-emitting surface is used to display images, and the backlight surface is the surface opposite to the light-emitting surface along the thickness direction of the display panel 100.

[0075] like Figures 1-2 As shown, the display panel 100 may include a light-transmitting display area 100a. The backlight surface of the display panel 100 in the light-transmitting display area 100a may be provided with under-display functional devices. The under-display functional devices may include any one or more of the following: a camera, a fingerprint reader, an iris reader, and a proximity sensor.

[0076] This application describes an embodiment using an under-display camera as an example.

[0077] A camera is placed on the backlight side of the display panel 100 in the light-transmitting display area 100a. On the one hand, the display panel 100 in the light-transmitting display area 100a can display the image normally to ensure that the display panel 100 has a high screen ratio; on the other hand, the light-transmitting display area 100a has good light transmittance so that light can reach the camera.

[0078] In some examples, such as Figure 2As shown, the display panel 100 may further include a transition area 100b, which is adjacent to the light-transmitting display area 100a. The transition area 100b can display images normally. The light transmittance of the display panel 100 in the transition area 100b is less than that in the light-transmitting display area 100a. For example, the transition area 100b may be arranged around the outer side of the light-transmitting display area 100a.

[0079] In other examples, such as Figure 1 and Figure 2 As shown, the display panel 100 may further include a non-transparent display area 100c, which can display images normally. For example, the area other than the transparent display area 100a and the transition area 100b is the non-transparent display area 100c. The transparent display area 100a, the transition area 100b, and the non-transparent display area 100c can be arranged adjacent to each other in sequence, that is, the transition area 100b can be located between the transparent display area 100a and the non-transparent display area 100c. For example, the non-transparent display area 100c can be arranged around the outside of the transition area 100b. The light transmittance of the display panel 100 in the non-transparent display area 100c can be less than or equal to the light transmittance of the display panel 100 in the transition area 100b.

[0080] like Figure 3 As shown, the display panel 100 may include an array substrate 110 and a light-emitting pixel layer 140 located on the array substrate 110.

[0081] The light-emitting pixel layer 140 may include a plurality of pixels 141, each being a light-emitting unit within the layer. The plurality of pixels 141 may be arranged in an array. The plurality of pixels 141 may include, but is not limited to, red, green, and blue pixels. In other examples, the plurality of pixels 141 may also include white pixels. Each pixel 141 may include a pixel anode, a pixel cathode, and a light-emitting layer disposed between the pixel anode and the pixel cathode.

[0082] The pixel 141 in the light-transmitting display area 100a, the transition area 100b, and the non-light-transmitting display area 100c can have the same or different sizes. For example, ... Figure 2As shown, part A illustrates pixels 141 in the light-transmitting display area 100a, and part B illustrates pixels 141 in the opaque display area 100c. The size of pixels 141 in the light-transmitting display area 100a can be smaller than the size of pixels 141 in the opaque display area 100c. Smaller pixel sizes in the light-transmitting display area 100a reduce the impact of pixels 141 on the light transmittance of the light-transmitting display area 100a; larger pixel sizes in the opaque display area 100c result in higher luminous efficiency in the opaque display area 100c. The size of pixels 141 in the transition area 100b can be the same as or different from the size of pixels 141 in the light-transmitting display area 100a or the opaque display area 100c.

[0083] The array substrate 110 provided in the embodiments of this application will be described below.

[0084] This application provides an array substrate 110, such as Figure 2 and Figure 3 As shown, the array substrate 110 can be applied to the display panel 100 in the above embodiments. The array substrate 110 may contain a plurality of driving units 103, which can be arranged in an array. The driving units 103 are electrically connected to the light-emitting pixel layer 140 and provide driving current to the light-emitting pixel layer 140. The driving units 103 can be electrically connected to the light-emitting pixel layer 140 through pixel anodes. The driving units 103 may include thin-film transistors (TFTs).

[0085] It is understandable that the driving unit 103 may not be provided in the display panel 100 of the light-transmitting display area 100a (because the driving unit 103 has poor light transmittance), thereby avoiding the influence of the driving unit 103 on the light transmittance of the display panel 100 of the light-transmitting display area 100a. The driving unit 103 can be provided in the transition area 100b, so that the driving unit 103 located in the transition area 100b drives the light-emitting pixel layer 140 in the light-transmitting display area 100a to emit light. The driving unit 103 in the transition area 100b can also drive the light-emitting pixel layer 140 in the transition area 100b to emit light. Furthermore, the driving unit 103 can be provided in the display panel 100 of the light-blocking display area 100c, so that the driving unit 103 in the light-blocking display area 100c drives the light-emitting pixel layer 140 in the light-blocking display area 100c to emit light.

[0086] like Figure 2As shown, a connection line 130 may be provided in the array substrate 110. The connection line 130 is used for electrically connecting the light-emitting pixel layer 140 and the driving unit 103. In some examples, at least a portion of the connection line 130 is located in the light-transmitting display area 100a, and the connection line 130 located in the light-transmitting display area 100a is the first connection line 131 (…). Figure 3 In some other examples, a connecting line 130 may also be provided in the transition area 100b, and the connecting line 130 located in the transition area 100b is a second connecting line (not shown in the figure). In other examples, a connecting line 130 may also be provided in the non-transparent display area 100c, and the connecting line 130 located in the non-transparent display area 100c is a third connecting line (not shown in the figure).

[0087] The connecting line 130 may include only the first connecting line 131, or it may include both the first connecting line 131 and the second connecting line, or it may include both the first connecting line 131 and the third connecting line, or it may include the first connecting line 131, the second connecting line, and the third connecting line.

[0088] like Figure 3 and Figure 4 As shown, the thin-film transistor of the driving unit 103 may include a metal oxide (MO) thin-film transistor. The MO thin-film transistor 101 is a thin-film transistor with a light-transmitting oxide material as the active layer, which is the first active layer 111.

[0089] The first active layer 111 and the connecting lines 130 can be disposed on the same layer. Since the material forming the first active layer 111 is light-transmitting and can be conductive, the connecting lines 130 can be formed using the same material, resulting in light-transmitting and conductive connecting lines 130, thus avoiding any impact on the light transmittance of the display panel 100 in the light-transmitting display area 100a. Furthermore, since the first active layer 111 and the connecting lines 130 are fabricated simultaneously, there is no need to separately fabricate an ITO layer between the MO thin-film transistor 101 and the light-emitting pixel layer 140. This simplifies the fabrication method of the array substrate 110, reduces production costs, and increases production capacity.

[0090] It should be noted that "same-layer configuration" refers to forming a base film layer from the same raw material, and then patterning and / or other processing techniques on the base film layer to form multiple structural film layers. For example, a metal oxide semiconductor layer is first used to form a base film layer. After patterning and partially conductiveizing the base film layer, a first active layer 111 and a connecting line 130 are formed. The processing techniques used to form the first active layer 111 and the connecting line 130 can be the same or different. After processing, the chemical or physical properties of the first active layer 111 and the connecting line 130 can be the same or different. Furthermore, the first active layer 111 and the connecting line 130 can be located on the same horizontal plane or on different horizontal planes, and can also have the same thickness or different thicknesses.

[0091] For example, the materials of the first active layer 111 and the connection line 130 may include any one or more of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO).

[0092] In some embodiments, such as Figure 5 As shown, in the display panel 100, Low Temperature Polycrystalline Oxide (LTPO) technology can be used, while Low Temperature Polycrystalline Silicon (LTPS) thin-film transistors and MO thin-film transistors 101 are used as thin-film transistors in the driving unit 103. LTPS thin-film transistor 102 can be used as a driving thin-film transistor, which has high mobility, can reduce driving voltage, and can achieve high refresh rate and high resolution; MO thin-film transistor 101 can be used as a switching thin-film transistor, which has low leakage current, can enable the display panel 100 to maintain good display effect at low frame rate, and reduce the power consumption of the display panel 100. LTPO can combine the advantages of these two thin-film transistors.

[0093] It is understood that an MO thin-film transistor 101 can be disposed in the driving unit 103, and the MO thin-film transistor 101 is electrically connected to the light-emitting pixel layer 140. Alternatively, both the MO thin-film transistor 101 and an LTPS thin-film transistor 102 can be disposed simultaneously, with the LTPS thin-film transistor 102 electrically connected to the light-emitting pixel layer 140, and the MO thin-film transistor 101 electrically connected to the light-emitting pixel layer 140 through the LTPS thin-film transistor 102. Alternatively, the MO thin-film transistor 101 and other types of thin-film transistors can be disposed simultaneously; this embodiment of the application does not impose any limitations on this.

[0094] The array substrate 110 will be described in detail below.

[0095] like Figures 3-5 As shown, the array substrate 110 may include a substrate 117, with thin-film transistors located on the side of the substrate 117 facing the light-emitting pixel layer 140. The substrate 117 may provide support for the remaining structural layers subsequently formed.

[0096] For example, substrate 117 may be a rigid substrate, such as glass. In other examples, substrate 117 may be a flexible substrate, and the material of substrate 117 may include at least one of polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, and polyethersulfone.

[0097] For example, a buffer layer (not shown in the figure) may be provided between the substrate 117 and the thin-film transistor. The buffer layer can prevent water and oxygen from penetrating through the substrate 117 and entering the driving unit 103 to cause corrosion. The buffer layer can be a single-layer structure or a multi-layer stacked structure.

[0098] For example, a planarization layer 126 is provided on the side of the light-emitting pixel layer 140 facing the substrate 117. The planarization layer 126 provides good planar support for the subsequent formation of the light-emitting pixel layer 140. The material of the planarization layer 126 can be an inorganic material such as silicon oxide or silicon nitride, or an organic material such as polyimide (PI), polyacrylate, epoxy resin, polyethylene (PE), polypropylene, polystyrene, polyethylene terephthalate, polymethyl methacrylate (PMMA), polyethylene terephthalate, or polyimide, etc.

[0099] The connection method between the first connection line 131 and the thin-film transistor is described below.

[0100] like Figure 3 As shown, the light-emitting pixel layer 140 located in the light-transmitting display area 100a is electrically connected to the MO thin film transistor 101 through the first connection line 131, so that the MO thin film transistor 101 controls the light-emitting pixel layer 140 in the light-transmitting display area 100a to emit light.

[0101] For example, at least one end of the first connection line 131 located in the light-transmitting display area 100a extends into the transition area 100b and is electrically connected to the MO thin film transistor 101 located in the transition area 100b, and the other end of the first connection line 131 located in the light-transmitting display area 100a is electrically connected to the light-emitting pixel layer 140 located in the light-transmitting display area 100a.

[0102] In the first implementation, such as Figure 3 and Figure 4 As shown, the array substrate 110 includes an MO thin-film transistor 101, and the MO thin-film transistor 101 is electrically connected to the light-emitting pixel layer 140.

[0103] Specifically, the MO thin-film transistor 101 may include a first active layer 111 located on a substrate 117, a first gate layer 113 located on the side of the first active layer 111 facing away from the substrate 117, and a first source / drain layer 115 located on the side of the first gate layer 113 facing away from the substrate 117. A first insulating layer 121 is disposed between the first active layer 111 and the first gate layer 113, a second insulating layer 122 is disposed between the first gate layer 113 and the first source / drain layer 115, and a third insulating layer (not shown in the figure, such as a passivation layer) is disposed on the side of the first source / drain layer 115 facing away from the substrate 117.

[0104] like Figure 4 As shown, a first active layer 111 and a first connecting line 131 are disposed on the same layer. One end of the first connecting line 131 extends into the transition region 100b and connects to one end of the first active layer 111 in the transition region 100b. In this case, a portion of the first connecting line 131 can form the source or drain of the MO thin-film transistor 101, thus eliminating the need to separately fabricate the source or drain of the MO thin-film transistor 101. The other end of the first connecting line 131 is electrically connected to the light-emitting pixel layer 140 in the light-transmitting display area 100a through a via. This allows the MO thin-film transistor 101 in the transition region 100b to control the light-emitting pixel layer 140 in the light-transmitting display area 100a to emit light.

[0105] It should be noted that a "via" refers to a through-hole that penetrates the structural film layer, with one opening of the via facing the light-emitting side and the other opening facing the backlight side. "Electrical connection through via" means that the via can be filled with conductive material to form a conductive pillar, thereby allowing the structural film layers at both ends of the via to be electrically connected through the conductive pillar.

[0106] In other examples, such as Figure 3 As shown, the first connection line 131 is electrically connected to the source or drain of the first source / drain layer 115 of the MO thin film transistor 101 through a via. At this time, the first connection line 131 and the first active layer 111 can be arranged at intervals, so that the wiring pattern of the structural film layer where the first connection line 131 and the first active layer 111 are located is relatively simple.

[0107] In the second implementation method, such as Figure 5As shown, both an MO thin-film transistor 101 and an LTPS thin-film transistor 102 are provided, and the LTPS thin-film transistor 102 is electrically connected to the light-emitting pixel layer 140. The MO thin-film transistor 101 can be electrically connected to the LTPS thin-film transistor 102. The structure of the MO thin-film transistor 101 has been described in the first implementation and will not be repeated here.

[0108] like Figure 5 As shown, an active layer and a gate layer of an LTPS thin-film transistor 102 are disposed on the side of the first active layer 111 facing the substrate 117. The active layer and the gate layer are a second active layer 112 and a second gate layer 114. The second gate layer 114 is located on the side of the second active layer 112 facing away from the substrate 117, and a fourth insulating layer 124 is disposed between the second gate layer 114 and the second active layer 112. A fifth insulating layer 125 is disposed between the second gate layer 114 and the first active layer 111.

[0109] In the LTPS thin film transistor 102, the source and drain layer is the second source and drain layer 116. The second source and drain layer 116 and the first source and drain layer 115 can be disposed in the same layer, thereby simplifying the fabrication process.

[0110] It should be noted that the above-mentioned MO thin-film transistor 101 is a top-gate structure, that is, the first gate layer 113 is located on the side of the first active layer 111 facing away from the substrate 117. In other examples, the MO thin-film transistor 101 can also be a bottom-gate structure, that is, the first gate layer 113 is located on the side of the first active layer 111 facing the substrate 117, or the MO thin-film transistor 101 can also be a dual-gate structure, with the first gate layer 113 disposed on both opposite sides of the first active layer 111.

[0111] like Figure 5 As shown, a first active layer 111 and a first connecting line 131 are disposed on the same layer. One end of the first connecting line 131 extends into the transition region 100b and is electrically connected to the source or drain of the LTPS thin-film transistor 102 through a via. The other end of the first connecting line 131 is located in the light-transmitting display region 100a and is electrically connected to the light-emitting pixel layer 140 in the light-transmitting display region 100a through a via. At this time, the first connecting line 131 and the active layer of the LTPS thin-film transistor 101 are spaced apart.

[0112] It is understandable that when a second connection line is provided in the transition region 100b, the connection method between the second connection line and the thin-film transistor is similar to that of the first connection line 131. The second connection line can be connected to the first active layer 111 of the MO thin-film transistor 101 located in the transition region 100b, or the second connection line can be electrically connected to the source or drain of the LTPS thin-film transistor 102 located in the transition region 100b through a via. When a third connection line is provided in the opaque display region 100c, the third connection line can be connected to the first active layer 111 of the MO thin-film transistor 101 located in the opaque display region 100c, or the third connection line can be electrically connected to the source or drain of the LTPS thin-film transistor 102 located in the opaque display region 100c through a via. The connection method between the third connection line and the thin-film transistor is similar to that of the first connection line 131 and the second connection line, and will not be described again.

[0113] When no second connection line is provided in the transition region 100b, a via (which can be a first via) can be provided on the structural film layer between the array substrate 110 and the light-emitting pixel layer 140 in the transition region 100b. For example, a via can be provided in the third insulating layer and the planarization layer 126. The light-emitting pixel layer 140 in the transition region 100b is electrically connected to the thin-film transistor in the transition region 100b through the via. For example, it can be electrically connected to the source or drain of the MO thin-film transistor 101, or it can be electrically connected to the source or drain of the LTPS thin-film transistor 102.

[0114] In the opaque display area 100c, when no third connection line is provided, a via (which can be a second via) can be provided on the structural film layer between the array substrate 110 and the light-emitting pixel layer 140 in the opaque display area 100c. For example, a via can be provided in the third insulating layer and the planarization layer 126. The light-emitting pixel layer 140 in the opaque display area 100c is electrically connected to the thin-film transistor in the opaque display area 100c through the via. For example, it can be electrically connected to the source or drain of the MO thin-film transistor, or it can be electrically connected to the source or drain of the LTPS thin-film transistor 102.

[0115] In some embodiments, the thickness of the first active layer 111 may be less than or equal to the thickness of the connecting line 130. When the thickness of the first active layer 111 is equal to the thickness of the connecting line 130, the fabrication of the first active layer 111 and the connecting line 130 is less difficult.

[0116] When the thickness of the first active layer 111 is less than the thickness of the connecting line 130, the smaller thickness of the first active layer 111 can reduce its impact on the flatness of the array substrate 110. The larger thickness of the connecting line 130 results in a lower resistance, which can reduce voltage drop and is beneficial for signal transmission.

[0117] For example, the difference between the thickness of the first active layer 111 and the thickness of the connecting line 130 can be less than or equal to 50 angstroms. For instance, the difference between the thickness of the first active layer 111 and the thickness of the connecting line 130 can be 0 angstroms (equal thickness), 5 angstroms, 10 angstroms, 20 angstroms, 30 angstroms, 40 angstroms, 50 angstroms or any value less than or equal to 50 angstroms, thereby making the fabrication of the first active layer 111 and the connecting line 130 easier.

[0118] It should be noted that the first gate layer 113, the second gate layer 114, the first source / drain layer 115, the second source / drain layer 116, etc., can be made of metals such as silver, copper, aluminum, and molybdenum, or alloys, or conductive oxides (such as indium tin oxide (ITO) and indium zinc oxide (IZO)).

[0119] The buffer layer, the first insulating layer 121, the second insulating layer 122, the third insulating layer, the fourth insulating layer 124, and the fifth insulating layer 125 can be made of silicon nitride, silicon oxynitride, silicon oxide, or various new organic insulating materials, or metal oxides with high dielectric constants such as aluminum oxide, tantalum oxide, etc., any one or more of these materials.

[0120] The following describes the fabrication method of the array substrate 110 provided in the embodiments of this application.

[0121] The method for preparing the array substrate 110 provided in this application embodiment can be used to prepare the array substrate 110 in the above embodiment.

[0122] like Figure 6 As shown, the fabrication method of the array substrate 110 may include:

[0123] S100: Provides a substrate.

[0124] like Figure 7 As shown, a substrate 117 is first provided, which can provide support for other structural films prepared on the substrate 117.

[0125] S200: A metal oxide semiconductor layer is formed on the substrate.

[0126] like Figure 8 As shown, an MO semiconductor layer 118 is formed on the substrate 117. The material of the MO semiconductor layer 118 may include any one or more of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO).

[0127] S300: Process a portion of the metal oxide semiconductor layer and form interconnects; the remaining portion of the metal oxide semiconductor layer forms the active layer of the metal oxide thin film transistor.

[0128] like Figure 9 As shown, the MO semiconductor layer 118 is patterned. The patterned MO semiconductor layer 118 may include a first part and a second part. The first part can be used to form a first active layer 111, and the second part can be used to form a connecting line 130.

[0129] The second part is made conductive to form the connecting line 130. The distribution of the connecting line 130 on the substrate 117 has been described in the above embodiments and will not be repeated here.

[0130] For example, doping can be used to make the second part conductive. In addition, while doping the second part, a portion of the first part can be doped to form the source contact region and drain contact region of the first active layer 111, which are used to contact the source and drain in the first source-drain layer 115, respectively.

[0131] In some embodiments, the thickness of the first active layer 111 may be less than or equal to the thickness of the interconnect 130. For example, the MO semiconductor layer 118 in the region where the first active layer 111 is located may be etched. The MO semiconductor layer 118 may be partially etched before patterning, or the first portion may be etched after patterning to reduce the thickness of the MO semiconductor layer 118 in the region where the first active layer 111 is located. The etching method may include wet etching or dry etching.

[0132] like Figure 3 As shown, in the embodiment of fabricating MO thin film transistor 101, a first insulating layer 121, a first gate layer 113, a second insulating layer 122, a first source / drain layer 115, a third insulating layer, and a planarization layer 126 are sequentially formed on the side of the first active layer 111 and the interconnect 130 away from the substrate 117.

[0133] like Figure 5 As shown, in the embodiment where MO thin-film transistor 101 and LTPS thin-film transistor 102 are fabricated simultaneously, before forming the first active layer 111 and the interconnect 130, a second active layer 112, a fourth insulating layer 124, a second gate layer 114, and a fifth insulating layer 125 may be formed sequentially. The first active layer 111 and the interconnect 130 may be fabricated on the side of the fifth insulating layer 125 facing away from the substrate 117. The first source / drain layer 115 and the second source / drain layer 116 may be disposed in the same layer, thereby simplifying the fabrication process of the display panel 100.

[0134] Then, a light-emitting pixel layer can be formed on the side of the MO thin-film transistor 101 that is away from the substrate. For example... Figures 3-5As shown, a light-emitting pixel layer 140 is formed on the side of the planarization layer 126 opposite to the substrate 117. The connection method between the light-emitting pixel layer 140 and the thin-film transistor has been described in the above embodiments and will not be repeated here.

[0135] It should be noted that the numerical values ​​and ranges involved in the embodiments of this application are approximate values. Due to the influence of the manufacturing process, there may be a certain range of errors, which can be considered negligible by those skilled in the art.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, It is used in a display panel having a light-emitting pixel layer, the display panel including a light-transmitting display area; The array substrate is provided with light-transmitting connecting lines; a metal oxide thin-film transistor is provided in the array substrate located outside the light-transmitting display area, at least a portion of the connecting lines are located within the light-transmitting display area, one end of the connecting lines is electrically connected to the metal oxide thin-film transistor, and the other end of the connecting lines is used to electrically connect to the light-emitting pixel layer located in the light-transmitting display area. The active layer of the metal oxide thin film transistor is disposed on the same layer as the interconnect. The connecting line includes a first connecting line, which is located within the light-transmitting display area; One end of the first connecting line is electrically connected to the light-emitting pixel layer located in the light-transmitting display area, and at least a portion of the other end of the first connecting line extends outside the light-transmitting display area and is electrically connected to the metal oxide thin film transistor; It also includes a transition region adjacent to the light-transmitting display area, wherein the metal oxide thin-film transistor is located in the transition region; The connection line includes a second connection line located within the transition region. One end of the second connection line is electrically connected to the metal oxide thin film transistor located in the transition region, and the other end of the second connection line is electrically connected to the light-emitting pixel layer located in the transition region. Alternatively, the array substrate may further include an insulating layer located between the metal oxide thin-film transistor and the light-emitting pixel layer. A first via is provided in the insulating layer located in the transition region, and the light-emitting pixel layer located in the transition region is electrically connected to the metal oxide thin-film transistor located in the transition region through the first via. At least a portion of one end of the first connection line extends into the transition region and is electrically connected to the metal oxide thin-film transistor located in the transition region.

2. The array substrate according to claim 1, characterized in that, It also includes a non-transparent display area, the transition area being located between the transparent display area and the non-transparent display area, and the metal oxide thin film transistor being located in the non-transparent display area; The connection line includes a third connection line located in the non-transparent display area. One end of the third connection line is electrically connected to the metal oxide thin film transistor located in the non-transparent display area, and the other end of the third connection line is used to electrically connect to the light-emitting pixel layer located in the non-transparent display area. Alternatively, the array substrate includes an insulating layer located between the metal oxide thin-film transistor and the light-emitting pixel layer. The insulating layer located in the non-transparent display area has a second via, and the light-emitting pixel layer located in the non-transparent display area is electrically connected to the metal oxide thin-film transistor located in the non-transparent display area through the second via.

3. The array substrate according to any one of claims 1-2, characterized in that, The connecting lines are connected to the active layer of the metal oxide thin film transistor, and a portion of the connecting lines form the source or drain of the metal oxide thin film transistor.

4. The array substrate according to any one of claims 1-2, characterized in that, The connecting line is spaced apart from the active layer of the metal oxide thin film transistor, and the array substrate includes a low-temperature polycrystalline silicon thin film transistor. The connecting line is connected to the source or drain of the low-temperature polycrystalline silicon thin film transistor.

5. The array substrate according to any one of claims 1-2, characterized in that, The thickness of the active layer of the metal oxide thin-film transistor is less than or equal to the thickness of the connecting line.

6. The array substrate according to claim 5, characterized in that, The difference between the thickness of the active layer of the metal oxide thin-film transistor and the thickness of the interconnect is no greater than 50 angstroms.

7. The array substrate according to any one of claims 1-2, characterized in that, The active layer of the metal oxide thin-film transistor is made of at least one of indium gallium zinc oxide, aluminum zinc oxide, zinc oxide, and indium zinc oxide.

8. A method for fabricating an array substrate, characterized in that, The array substrate is applied to a display panel having a light-emitting pixel layer, the display panel including a light-transmitting display area, and the method for fabricating the array substrate includes: Provide substrate; A metal oxide semiconductor layer is formed on the substrate; A portion of the metal oxide semiconductor layer is processed to form interconnects, and the remaining portion of the metal oxide semiconductor layer forms the active layer of a metal oxide thin film transistor; the metal oxide thin film transistor is located outside the light-transmitting display area, and at least a portion of the interconnects is located within the light-transmitting display area; One end of the connecting line is electrically connected to the metal oxide thin film transistor, and the other end of the connecting line is electrically connected to the light-emitting pixel layer located in the light-transmitting display area; The connecting line includes a first connecting line, which is located within the light-transmitting display area; One end of the first connecting line is electrically connected to the light-emitting pixel layer located in the light-transmitting display area, and at least a portion of the other end of the first connecting line extends outside the light-transmitting display area and is electrically connected to the metal oxide thin film transistor; It also includes a transition region adjacent to the light-transmitting display area, wherein the metal oxide thin-film transistor is located in the transition region; The connection line includes a second connection line located within the transition region. One end of the second connection line is electrically connected to the metal oxide thin film transistor located in the transition region, and the other end of the second connection line is electrically connected to the light-emitting pixel layer located in the transition region. Alternatively, the array substrate may further include an insulating layer located between the metal oxide thin-film transistor and the light-emitting pixel layer. A first via is provided in the insulating layer located in the transition region, and the light-emitting pixel layer located in the transition region is electrically connected to the metal oxide thin-film transistor located in the transition region through the first via. At least a portion of one end of the first connection line extends into the transition region and is electrically connected to the metal oxide thin-film transistor located in the transition region.

9. A display panel, characterized in that, It includes a light-emitting pixel layer and an array substrate as described in any one of claims 1-7, wherein the light-emitting pixel layer is stacked on the array substrate.

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