Organic light emitting panel and organic light emitting display device including the same

Abstract

The present invention relates to an organic light emitting panel and an organic light emitting display device including the same. The present disclosure relates to an organic light emitting display panel and an organic light emitting display device including the same, the display panel including: a buffer layer disposed on a first conductive layer and including a first contact hole; an active layer disposed on the buffer layer and including an active pattern and a conductive pattern disposed on the active pattern; a first insulating film disposed on or over the active layer and the buffer layer and including a second contact hole overlapping the first contact hole; a second conductive layer disposed on the first insulating film and contacting the first conductive layer through the first contact hole and the second contact hole; and a plate disposed in the same layer as the second conductive layer and spaced apart from the second conductive layer. Each of the first conductive layer, the active layer, and the plate serves as an electrode of a storage capacitor. Accordingly, a display panel having a storage capacitor with high capacity can be implemented.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0180932, filed on December 22, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an organic light-emitting display panel and an organic light-emitting display device including the display panel. Background Technology

[0004] Organic light-emitting display devices include one or more thin-film transistors (TFTs), storage capacitors, and multiple lines.

[0005] One or more thin-film transistors, capacitors, and one or more lines are sometimes implemented as fine patterns on a substrate included in an organic light-emitting display device, and the display device can operate based on complex connections between one or more thin-film transistors, at least one capacitor, and one or more lines.

[0006] Recently, there has been a growing demand for organic light-emitting display devices with high brightness and high resolution, and in order to meet this demand, it is desirable to achieve an efficient spatial arrangement and connection structure among the components included in the organic light-emitting display device. Summary of the Invention

[0007] Embodiments of this disclosure relate to an organic light-emitting display panel that exhibits high brightness characteristics by increasing the area of ​​the light-emitting region without reducing the area of ​​the storage capacitor disposed in the non-light-emitting region, and an organic light-emitting display device including the display panel.

[0008] Furthermore, embodiments of the present invention relate to an organic light-emitting display panel that has high brightness and high resolution by increasing the capacity of the storage capacitor without reducing the area of ​​the light-emitting region, and an organic light-emitting display device including the display panel.

[0009] Furthermore, embodiments of the present invention relate to an organic light-emitting display panel with a simple process by reducing the number of masks required to form the buffer layer and the first insulating film, and an organic light-emitting display device including the display panel.

[0010] Furthermore, embodiments of the present invention relate to an organic light-emitting display panel for easily driving sub-pixels by enabling the active layer to include active patterns and conductive patterns, and an organic light-emitting display device including the display panel.

[0011] According to one aspect of this disclosure, an organic light-emitting display panel and an organic light-emitting display device including the display panel are disclosed. The display panel includes: a substrate; a first conductive layer disposed on the substrate; a buffer layer disposed on the first conductive layer and including a first contact hole; a first active layer disposed on the buffer layer; a first insulating film disposed on or above the active layer and the buffer layer, and including a second contact hole overlapping the first contact hole; a second conductive layer disposed on the first insulating film and contacting a portion of the first conductive layer and a portion of the first active layer through the first and second contact holes; a second insulating film disposed on the second conductive layer and including a third contact hole overlapping the first and second contact holes; and a third conductive layer disposed on the second insulating film and contacting a portion of the second conductive layer through the second contact hole. The first, second, and third contact holes overlap each other.

[0012] According to another aspect of this disclosure, an organic light-emitting display panel and an organic light-emitting display device including the display panel are disclosed. The display panel includes: a substrate; a first conductive layer disposed on the substrate; a buffer layer disposed on the first conductive layer and including a first contact hole; an active layer disposed on the buffer layer and including an active pattern and a conductive pattern disposed on the active pattern; a first insulating film disposed on or above the active layer and the buffer layer, and including a second contact hole overlapping the first contact hole; a second conductive layer disposed on the first insulating film and contacting the first conductive layer through the first contact hole and the second contact hole; and a plate disposed in the same layer as the second conductive layer and spaced apart from the second conductive layer. Two or more of the first conductive layer, the active layer, and the plate overlap each other to form a storage capacitor.

[0013] According to various aspects of this disclosure, since multiple contact holes are overlapped in the region where the second node of the driving transistor is located, the area of ​​the conductive layer overlapping with the multiple contact holes can be reduced. In other words, the area of ​​the non-light-emitting region can be reduced without reducing the area of ​​the storage capacitor. Therefore, by increasing the area of ​​the light-emitting region relative to the non-light-emitting region by the area of ​​the reduced non-light-emitting region, an organic light-emitting display panel with high brightness characteristics and an organic light-emitting display device including the display panel can be provided.

[0014] Furthermore, according to various aspects of this disclosure, since at least two of the multiple contact holes in the region where the second node of the driving transistor is located overlap, and therefore the area of ​​the conductive layer overlapping with the at least two contact holes can be reduced, the size or capacity of the storage capacitor can be increased without reducing the area of ​​the light-emitting region, and thus an organic light-emitting display panel with high brightness and high resolution, as well as an organic light-emitting display device including the display panel, can be provided.

[0015] Furthermore, according to various aspects of this disclosure, by forming contact holes in the buffer layer and the first insulating film through the same process, an organic light-emitting display panel that can be manufactured using a simplified process and a reduced number of masks, as well as an organic light-emitting display device including the display panel, can be provided.

[0016] Furthermore, according to various aspects of this disclosure, since the active layer includes an active pattern and a conductive pattern disposed on the active pattern, an organic light-emitting display panel in which sub-pixels can be easily driven, and an organic light-emitting display device including the display panel, can be provided. Attached Figure Description

[0017] Figure 1 The system configuration of an organic light-emitting display device according to various aspects of this disclosure is illustrated schematically.

[0018] Figure 2 The subpixel structure is shown when an organic light-emitting display panel including an organic light-emitting diode (OLED) is used in a display device according to various aspects of this disclosure.

[0019] Figure 3 This is a plan view showing a portion of a sub-pixel in the active region of an organic light-emitting display device disposed in accordance with various aspects of this disclosure.

[0020] Figure 4 In one embodiment based on various aspects of this disclosure, along Figure 3 The cross-sectional view taken from line AB.

[0021] Figure 5 This illustrates another embodiment along various aspects of this disclosure. Figure 3 A cross-sectional view of the region intercepted by line AB.

[0022] Figure 6 This illustrates yet another embodiment along various aspects of this disclosure. Figure 3 A cross-sectional view of the region intercepted by line AB.

[0023] Figures 7 to 9Various embodiments of the arrangement of the buffer layer, the first active layer, the first insulating film, and the second conductive layer in an organic light-emitting display device 100 according to various aspects of the present disclosure are shown.

[0024] Figure 10 The arrangement relationship between the first active layer and the first insulating film is shown in another embodiment according to various aspects of this disclosure.

[0025] Figure 11 Based on all aspects of this disclosure Figure 3 The cross-sectional view taken from line CD.

[0026] Figure 12 Based on all aspects of this disclosure Figure 3 The cross-sectional view taken from line EF.

[0027] Figure 13 It shows in Figure 2 The location and width of the contact hole formed in the region included in the second node of the driving transistor.

[0028] Figure 14 Based on all aspects of this disclosure Figure 3 The cross-sectional view of line GH. Detailed Implementation

[0029] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that can be implemented, and in which the same reference numerals and symbols may be used to denote the same or similar parts, even when shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and parts incorporated herein are omitted where it is determined that the description may make the subject matter of some embodiments of the invention considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional parts, unless these terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0030] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of the invention. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0031] When referring to a first element being "connected or coupled to" a second element, or "contacting or overlapping" a second element, it should be understood that the first element can not only be "directly connected or coupled to" or "directly contacting or overlapping" a second element, but also that a third element can be "inserted" between the first and second elements, or that the first and second elements can be "connected or coupled," "contacting or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "contacting or overlapping," etc., with each other.

[0032] When time-related terms such as “after,” “later,” “next,” “before,” etc., are used to describe the process or operation of an element or configuration, or the flow or steps in an operation, processing, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations, unless used with the terms “directly” or “immediately.”

[0033] Additionally, when referring to any size, relative size, etc., the numerical or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. Furthermore, the term "may" fully encompasses all the meanings of the term "may".

[0034] Figure 1 The system configuration of an organic light-emitting display device according to various aspects of this disclosure is illustrated schematically.

[0035] Organic light-emitting display devices according to various aspects of this disclosure may include organic light-emitting display device 100, illumination devices, light-emitting devices, etc. Hereinafter, for ease of description, organic light-emitting display devices according to various aspects of this disclosure will be described with respect to organic light-emitting display device 100. However, it should be understood that the embodiments described herein can be applied to various organic light-emitting display devices, such as illumination devices, light-emitting devices, etc., and organic light-emitting display device 100, as long as they include transistors.

[0036] An organic light-emitting display device 100 according to the embodiments described herein includes an organic light-emitting display panel PNL for displaying images or emitting light, and a driving circuit for driving the organic light-emitting display panel PNL.

[0037] The organic light-emitting display device 100 according to the embodiments described herein may be based on a bottom-emitting type, in which light is emitted from an organic light-emitting element toward a substrate on which the organic light-emitting element is disposed; however, the embodiments of this disclosure are not limited thereto. In some embodiments, the organic light-emitting display device 100 according to the embodiments described herein may be based on a top-emitting type, in which light is emitted from an organic light-emitting element toward a surface opposite to the substrate on which the organic light-emitting element is disposed, or based on a dual-sided emitting type, in which light is emitted from an organic light-emitting element toward both the substrate and the surface opposite to the substrate.

[0038] An organic light-emitting display panel (PNL) may include multiple data lines (DL) and multiple gate lines (GL), as well as multiple sub-pixels (SP) defined by the multiple data lines (DL) and multiple gate lines (GL) and arranged in a matrix pattern.

[0039] Multiple data lines (DL) and multiple gate lines (GL) can be arranged to intersect each other in an organic light-emitting display panel (PNL). For example, the multiple gate lines (GL) can be arranged in rows or columns, and the multiple data lines (DL) can be arranged in columns or rows. In the following text, for ease of description and understanding, it is assumed that the multiple gate lines (GL) are arranged in rows and the multiple data lines (DL) are arranged in columns.

[0040] In addition to multiple data lines (DL) and multiple gate lines (GL), one or more other types of signal lines can be arranged in the organic light-emitting display panel (PNL) according to the sub-pixel structure, etc. Driving voltage lines, reference voltage lines, or common voltage lines can also be provided.

[0041] The type of signal lines disposed on an organic light-emitting display panel (PNL) can vary depending on variations such as the sub-pixel structure. Furthermore, all or some of each type of signal line described herein may include all or at least some of the electrodes to which signals are applied.

[0042] An organic light-emitting display panel (PNL) may include: an active region A / A on which an image is displayed; and a non-active region N / A, which serves as the outer edge and on which no image is displayed. Here, the non-active region N / A is sometimes referred to as the border region.

[0043] Multiple subpixels SP used for image display are arranged in the active region A / A.

[0044] A pad portion, including one or more conductive pads, can be disposed in an active region N / A for electrical connection with a data driver DDR, and multiple data link lines can be disposed in the active region N / A for electrical connection between the pad portion and multiple data lines DL. Here, the multiple data link lines can be portions of multiple data lines DL extending into the active region N / A (e.g., from the active region A / A), or they can be separate patterns electrically connected to the multiple data lines DL.

[0045] Furthermore, gate drive-related lines can be arranged in the non-active region N / A to send the voltage (signal) required for gate driving to the gate driver GDR via the pads electrically connected to the data driver DDR. For example, gate drive-related lines may include: clock lines for carrying clock signals; gate voltage lines for transmitting gate voltages (VGH, VGL); and gate drive control signal lines for carrying various types of control signals required to generate scan signals. These gate drive-related lines can be arranged in the non-active region N / A, unlike the gate lines GL located in the active region A / A.

[0046] The driving circuit may include: a data driver DDR that drives multiple data lines DL; a gate driver GDR that drives multiple gate lines GL; and a controller CTR for controlling the data driver DDR and the gate driver GDR.

[0047] The data driver DDR can drive multiple data lines DL by applying data voltage to them.

[0048] The gate driver GDR can drive multiple gate lines GL by supplying scan signals to multiple gate lines GL.

[0049] The controller CTR can control the drive operation of the data driver DDR and the gate driver GDR by supplying various types of control signals (DCS, GCS) required for their operation. Furthermore, the controller CTR can supply image data DATA to the data driver DDR.

[0050] The controller CTR starts scanning pixels according to the timing processed in each frame, converts image data input from external sources (e.g., host system, other devices, or other image sources) into a data signal form suitable for use in the data driver DDR, and then outputs the converted image data DATA, thus enabling the data to be written to pixels at pre-configured times according to the scan.

[0051] To control the data driver DDR and gate driver GDR, the controller CTR can receive timing signals from external sources (e.g., the host system, other devices, or other image sources), such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the input data enable signal, and clock signals. The controller CTR can use the received signals to generate various types of control signals and supply these generated signals to the data driver DDR and the gate driver GDR.

[0052] For example, in order to control the gate driver GDR, the controller CTR can output various types of gate control signals GCS, including gate start pulse GSP, gate shift clock GSC, gate output enable signal GOE, etc.

[0053] In addition, in order to control the data driver DDR, the controller CTR can output various types of data control signals DCS, including source start pulse SSP, source sampling clock SSC, source output enable signal SOE, etc.

[0054] The controller CTR can be a timing controller used in typical display technologies, or it can be a control device / appliance capable of performing other control functions besides the typical functions of a timing controller.

[0055] The controller CTR can be implemented as a separate component from the data driver DDR, or it can be implemented as an integrated circuit that integrates the data driver DDR.

[0056] After receiving image data DATA from the controller CTR, the data driver DDR can drive multiple data lines DL by supplying data voltage to them. Here, the data driver DDR is sometimes referred to as a source drive circuit or source driver.

[0057] The data driver DDR can send various signals to the controller CTR or receive various signals from the controller CTR through various interfaces.

[0058] A gate driver (GDR) can sequentially drive multiple gate lines GL by sequentially supplying scan signals to them. Here, the gate driver (GDR) is sometimes referred to as a scan drive circuit or scan driver.

[0059] Under the control of the controller CTR, the gate driver GDR can sequentially supply scan signals representing the on-state or off-state voltages to multiple gate lines GL.

[0060] When a specific gate line is asserted by a scan signal from the gate driver GDR, the data driver DDR can convert the image data DATA received from the controller CTR into an analog data voltage and supply the obtained data voltage to multiple data lines DL.

[0061] Depending on the driving scheme, display panel design, etc., the data driver DDR may be located on only one side of the display panel PNL (e.g., the top or bottom side), or in some embodiments, it may be located on both sides of the display panel PNL (e.g., the top and bottom sides).

[0062] Depending on the driving scheme, display panel design, etc., the gate driver GDR may be located on only one side of the panel PNL (e.g., the left or right side), or in some embodiments, it may be located on both sides of the display panel PNL (e.g., the left and right sides).

[0063] Data drivers (DDR) can be implemented using SDICs that include one or more source driver integrated circuits.

[0064] Each source driver integrated circuit (SDIC) may include a shift register, latch circuitry, a digital-to-analog converter (DAC), an output buffer, etc. In some implementations, the data driver (DDR) may also include one or more analog-to-digital converters (ADCs).

[0065] Each source driver integrated circuit (SDIC) can be connected to the conductive pads of the organic light-emitting display panel (PNL) using either tape-on-brush (TAB) or chip-on-glass (COG) bonding, such as bonding pads, or it can be directly disposed on the display panel 110. In some embodiments, each source driver integrated circuit (SDIC) can be integrated into the organic light-emitting display panel (PNL). In some embodiments, each source driver integrated circuit (SDIC) can be implemented as a chip-on-film (COF) type. In this case, each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data line DL in the organic light-emitting display panel (PNL) through the circuit film.

[0066] A gate driver (GDR) may include multiple gate drive circuits (GDCs). Each GDC may correspond to a different gate line (GL).

[0067] Each gate drive circuit (GDC) may include shift registers, level shifters, etc.

[0068] Each gate drive circuit (GDC) can be connected to the conductive pads of the organic light-emitting display panel (PNL) using either tape-on-brush (TAB) or chip-on-glass (COG) bonding. In some embodiments, each GDC can be implemented as a chip-on-film (COF). In this case, each GDC can be mounted on a circuit film and electrically connected to the gate line GL in the PNL via the circuit film. Furthermore, each GDC can be implemented as a gate-in-panel (GIP) and can be embedded within the PNL. That is, each GDC can be directly formed within the PNL.

[0069] Figure 2 The subpixel SP structure is shown when an organic light-emitting display panel (PNL) including organic light-emitting elements such as organic light-emitting diodes (OLEDs) is used in a display device according to various aspects of this disclosure.

[0070] Reference Figure 2 Each sub-pixel SP in an organic light-emitting display panel PNL including organic light-emitting elements may include: a second transistor T2 that transmits a data voltage Vdata to a first node N1 corresponding to the gate node of a driving transistor T1; and a storage capacitor Cst for holding the data voltage Vdata or a voltage corresponding to the image signal voltage for one frame time.

[0071] An organic light-emitting element (OLED) may include a first electrode (anode electrode or cathode electrode), an organic layer including at least one emitting layer, and a second electrode (cathode electrode or anode electrode).

[0072] In one implementation, a base voltage EVSS, such as a low-level voltage, can be applied to the second electrode of the organic light-emitting element (OLED).

[0073] The driving transistor T1 can drive the organic light-emitting diode (OLED) by supplying driving current to the OLED.

[0074] The driving transistor T1 can have a first node N1, a second node N2, and a third node N3.

[0075] The "nodes" of the first to third nodes N1, N2 and N3 can represent points, one or more electrodes or one or more lines having the same electrical state.

[0076] Each of the first node N1, the second node N2, and the third node N3 can be composed of one or more electrodes.

[0077] The first node N1 of the driving transistor T1 can be the node corresponding to its gate node, and can be electrically connected to the source node or drain node of the second transistor T2.

[0078] The second node N2 of the driving transistor T1 can be electrically connected to the first electrode 301 of the organic light-emitting element OLED, and can be a source node or a drain node.

[0079] The third node N3 of the driving transistor T1 can be either the drain node or the source node, which serves as the node to which the driving voltage EVDD is applied, and can be electrically connected to the driving voltage line DVL used to transmit the driving voltage EVDD.

[0080] The driving transistor T1 and the second transistor T2 can be either n-type transistors or p-type transistors.

[0081] The second transistor T2 can be electrically connected between the data line DL and the first node N1 of the driving transistor T1, and can be controlled by the scan signal SCAN transmitted through the gate line and applied to the gate node of the driving transistor T1.

[0082] The second transistor T2 can be turned on by the scan signal SCAN, and the data voltage Vdata transmitted through the data line DL is applied to the first node N1 of the driving transistor T1.

[0083] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor T1.

[0084] The storage capacitor Cst is an external capacitor that is intentionally designed to be located outside the driving transistor T1, rather than being internally stored, such as a parasitic capacitor (e.g., Cgs, Cgd) existing between the first node N1 and the second node N2 of the driving transistor T1.

[0085] The third transistor T3 can be electrically connected between the second node N2 of the driving transistor T1 and the reference voltage line RVL. The turn-on and turn-off operation of the third transistor T3 can be controlled by the second scan signal SCAN2 applied to the gate node of the third transistor T3.

[0086] The drain or source node of the third transistor T3 can be electrically connected to the reference voltage line RVL, and the source or drain node of the third transistor T3 can be electrically connected to the second node N2 of the driving transistor T1.

[0087] For example, the third transistor T3 can be turned on during the period of performing display driving and during the period of performing sensing driving to sense the characteristic value of driving transistor T1 or the characteristic value of organic light-emitting diode (OLED).

[0088] The third transistor T3 can be turned on by the second scan signal SCAN2, and the reference voltage Vref applied to the reference voltage line RVL is passed to the second node N2 of the driving transistor T1 according to the corresponding drive timing (e.g., display drive timing or initial timing within the time period used for sensing drive).

[0089] The third transistor T3 can be turned on by the second scan signal SCAN2, and the voltage at the second node N2 of the driving transistor T1 is transferred to the reference voltage line RVL according to the corresponding drive timing (e.g., sampling timing during the time period used for sensing drive).

[0090] In other words, the third transistor T3 can control the voltage state at the second node N2 of the driving transistor T1, or transfer the voltage at the second node N2 of the driving transistor T1 to the reference voltage line RVL.

[0091] The reference voltage line RVL can be electrically connected to an analog-to-digital converter that senses the voltage of the reference voltage line RVL, converts the sensed voltage into a digital value, and then outputs sensed data including that digital value.

[0092] The analog-to-digital converter can be included in the source driver integrated circuit SDIC that implements the data driver DDR.

[0093] The sensing data output from the analog-to-digital converter can be used to sense characteristic values ​​of the driving transistor T1 (e.g., threshold voltage, mobility, etc.) or characteristic values ​​of the organic light-emitting diode (OLED) (e.g., threshold voltage, etc.).

[0094] Each of the driving transistor T1, the second transistor T2, and the third transistor T3 can be an n-type transistor or a p-type transistor.

[0095] Meanwhile, the first scan signal SCAN1 and the second scan signal SCAN2 can be separate gate signals. In this case, the first scan signal SCAN1 and the second scan signal SCAN2 can be applied to the gate node of the second transistor T2 and the gate node of the third transistor T3 respectively through different gate lines.

[0096] In some implementations, the first scan signal SCAN1 and the second scan signal SCAN2 can be the same gate signal. In this case, the first scan signal SCAN1 and the second scan signal SCAN2 can be applied together to the gate node of the second transistor T2 and the gate node of the third transistor T3 through the same gate line.

[0097] It should be understood that, for the sake of discussion, Figure 2The subpixel structure shown with three transistors (3T) and one capacitor (1C) is merely one example of possible subpixel structures, and embodiments of this disclosure can be implemented in any of a variety of structures as needed. For example, a subpixel may also include at least one transistor and / or at least one capacitor.

[0098] In some implementations, each of the multiple sub-pixels may have the same structure, or some of the multiple sub-pixels may have different structures.

[0099] Figure 3 This is a plan view showing a portion of a sub-pixel in the active region of an organic light-emitting display device disposed in accordance with various aspects of this disclosure.

[0100] Reference Figure 3 The first conductive layer 310, the first active layer 320, the second conductive layer 330, and the plate 340 may be disposed in at least one sub-pixel of an organic light-emitting display device 100 including embodiments described herein.

[0101] Furthermore, a second active layer 325 disposed in the same layer as the first active layer 320 may be disposed in at least one sub-pixel, and a third conductive layer 360, which serves as the anode electrode (or cathode electrode) of the organic light-emitting element disposed on or above the second conductive layer 330 and the plate 340, may also be disposed in at least one sub-pixel.

[0102] Specifically, the first conductive layer 310 may be disposed on the substrate 300.

[0103] The first active layer 320 can be disposed on or above the first conductive layer 310.

[0104] Here, a portion of the first active layer 320 may overlap with a portion of the first conductive layer 310.

[0105] Furthermore, a second active layer 325 disposed in the same layer as the first active layer 320 and spaced apart from the first active layer 320 may be disposed on or above the substrate 300.

[0106] The second conductive layer 330 and the plate 340 can be disposed on or above the first active region 320. The second conductive layer 330 and the plate 340 can be spaced apart from each other and disposed in the same layer.

[0107] Despite Figure 3 The buffer layer may be disposed between the first conductive layer 310 and the first active layer 320, and the first insulating film may be disposed between the first active layer 320 and the second conductive layer 330.

[0108] The buffer layer may include a first contact hole CH1 in a region corresponding to a portion of the region where the second conductive layer 330 is disposed, and the first insulating film may also include a second contact hole CH2 in a region corresponding to a portion of the region where the second conductive layer 330 is disposed. The first contact hole CH1 may overlap with the second contact hole CH2. The first contact hole CH1 may expose a portion of the top surface of the first conductive layer 310, and the second contact hole CH2 may expose a portion of the top surface of the first conductive layer 310 and a portion of the upper surface of the first active layer 320.

[0109] The second conductive layer 330 can contact the first conductive layer 310 through the first contact hole CH1 and the second contact hole CH2. The second conductive layer 330 can contact the first active layer 320 through the second contact hole CH2.

[0110] Although not shown, the first active layer 320 can be electrically connected to Figure 2 The reference voltage line shown.

[0111] The plate 340 disposed on the first active layer 320 may be spaced apart from the second conductive layer 330.

[0112] A portion of plate 340 may overlap with a portion of the first active layer 320 and a portion of the first conductive layer 310.

[0113] Each of the first conductive layer 310, the first active layer 320, and the plate 340 can be used as an electrode of the storage capacitor Cst. The portion of the first active layer 320 that overlaps with the plate 340 and the first conductive layer 310 can be a conductive region or a region in which a conductive pattern is formed.

[0114] The plate 340 may include at least one extension 345 projecting from one side of the plate 340.

[0115] A portion of the extension 345 may overlap with a portion of the first active layer 320. The extension 345 may be... Figure 2 The gate electrode (first gate electrode) of the driving transistor T1 shown. The first active layer 320 can be used as the active layer of the driving transistor T1.

[0116] The second gate electrode 350 may be disposed on the substrate 300. The second gate electrode 350 may be disposed in the same layer as the second conductive layer 330 and the plate 340, and may be spaced apart from the second conductive layer 330 and the plate 340.

[0117] The second gate electrode 350 can be Figure 2 The gate electrode of the second transistor T2. The second active layer 325 can be the active layer of the second transistor T2.

[0118] Although not shown, the second gate electrode 350 can be electrically connected to a data line disposed above the substrate 300. Multiple data lines can be disposed on or above the substrate 300 in a first direction, and multiple gate lines (or scan lines) can be disposed in a second direction intersecting the first direction; however, embodiments of this disclosure are not limited thereto. Multiple signal lines can be arranged in various directions.

[0119] A portion of the second active layer 325 can be electrically connected to a portion of the board 340 via contact hole 341.

[0120] The point where the second active layer 325 and the board 340 are electrically connected can correspond to Figure 2 The first node.

[0121] exist Figure 3 In this embodiment, a contact hole 341 electrically connecting the second active layer 325 and the plate 340 is disposed in the region between the second conductive layer 330 and the extension 345; however, the embodiments of this disclosure are not limited thereto.

[0122] For example, the contact hole 341 that electrically connects the second active layer 325 and the plate 340 can be disposed between the second conductive layer 330 and the second gate electrode 350. In one embodiment, the contact hole 341 that electrically connects the second active layer 325 and the plate 340 can be disposed parallel to the second conductive layer 330 and the second gate electrode 350.

[0123] The third conductive layer 360 may be disposed on or above the second conductive layer 330, the plate 340, and the second gate electrode 350.

[0124] The third conductive layer 360 can be the anode or cathode electrode of the organic light-emitting element.

[0125] The third conductive layer 360 can contact a portion of the top surface of the second conductive layer 330 through a contact hole 342, which is formed in at least one insulating film disposed between the second conductive layer 330 and the third conductive layer 360.

[0126] In other words, the first conductive layer 310, the first active layer 320, the second conductive layer 330, and the third conductive layer 360 can be electrically connected to each other, and the connection points of the first conductive layer 310, the first active layer 320, the second conductive layer 330, and the third conductive layer 360 can correspond to... Figure 2 The second node N2.

[0127] As described above, the first contact hole CH1 for electrically connecting the first conductive layer 310 and the second conductive layer 330, the second contact hole CH2 for electrically connecting the first active layer 320 and the second conductive layer 330, and the contact hole 342 for electrically connecting the second conductive layer 330 and the third conductive layer 360 can overlap each other.

[0128] Specifically, the entire first contact hole CH1 may overlap with a portion of the second contact hole CH2, and the entire second contact hole CH2 may overlap with a portion of the contact hole 342.

[0129] Each of the first contact hole CH1, the second contact hole CH2, and the contact hole 342 can be disposed in the region between the first active layer 320 and the second active layer 325. In other words, each of the first contact hole CH1, the second contact hole CH2, and the contact hole 342 can include a region that does not overlap with the first active layer 320 and the second active layer 325.

[0130] When the first contact hole CH1, the second contact hole CH2, and the contact hole 342 do not overlap, the corresponding sub-pixel may need to include the area occupied by the first contact hole CH1, the area occupied by the contact hole CH2, and the area occupied by the contact hole 342.

[0131] In contrast, in the organic light-emitting display device 100 according to the embodiments described herein, since two or more of the first contact holes CH1, second contact holes CH2, and contact holes 342 of at least one insulating layer disposed between the second conductive layer 330 and the third conductive layer 360 overlap with or are adjacent to each other, the impact of contact holes on the display device can be reduced. Figure 2 The area occupied by the point corresponding to the second node N2.

[0132] In this way, due to the reduction of the relationship with Figure 2 The area of ​​the point corresponding to the second node N2 of the driving transistor T1 can be reduced, thus the size of the corresponding non-light-emitting region within the sub-pixel can be reduced, and the size of the corresponding light-emitting region can be increased. Furthermore, due to the reduction in the area of ​​the point corresponding to the second node N2 of the driving transistor T1... Figure 2 The area of ​​the point corresponding to the second node N2 of the driving transistor T1 can be increased, thus increasing the area of ​​the electrode of the associated storage capacitor Cst without reducing the area of ​​the light-emitting region of the organic light-emitting display device 100, and thereby increasing the capacity of the storage capacitor Cst.

[0133] For example, when a high brightness is required in the organic light-emitting display device 100 according to the embodiments described herein, it is necessary to increase the area of ​​the corresponding light-emitting region. As the size of the conductive layer 330 decreases, the area of ​​the non-light-emitting region can be reduced, and the area of ​​the light-emitting region relative to the non-light-emitting region can be designed to increase by reducing the area of ​​the non-light-emitting region. Therefore, a high-brightness organic light-emitting display device 100 can be realized.

[0134] Specifically, if the size of the second conductive layer 330 disposed in the non-light-emitting area is reduced, while maintaining the distance between the second conductive layer 330 and the plate 340 and the capacitance of the storage capacitor Cst, the position of the plate 340 can be arranged away from the light-emitting area (closer to the second conductive layer 330). Therefore, the area of ​​the non-light-emitting area can be reduced, and the area of ​​the light-emitting area can be increased by reducing the area of ​​the non-light-emitting area.

[0135] Furthermore, when the organic light-emitting display device 100 requires high resolution, a high-capacity storage capacitor Cst is needed, and in order to achieve such a high-capacity storage capacitor Cst, it is necessary to increase the area of ​​the electrodes of the storage capacitor Cst disposed in the sub-pixel.

[0136] The area of ​​each subpixel is finite, and if the area of ​​the electrodes of the storage capacitor (Cst) increases, the area of ​​the corresponding light-emitting region included in the subpixel may decrease. This can lead to reduced brightness of the subpixel and afterimages when driving the associated panel.

[0137] In the organic light-emitting display device 100 according to the embodiments described herein, since two or more of the first contact hole CH1, the second contact hole CH2, and the contact hole 342 overlap each other or mutually, the area of ​​the electrodes of the storage capacitor Cst can be increased to correspond to a decrease in the area occupied by the point corresponding to the second node N2 of the driving transistor T1. In other words, since the area of ​​the electrodes of the storage capacitor Cst can be increased without reducing the area of ​​the light-emitting region, the capacitance of the storage capacitor Cst can be increased, and thus an organic light-emitting display device 100 with high brightness and high resolution characteristics and prevention of afterimages can be realized.

[0138] Next, the structure of the region included in the second node N2 of the driving transistor T1 in at least one sub-pixel of the organic light-emitting display device 100 according to the embodiments described herein will be described with reference to the accompanying drawings.

[0139] Figure 4 In one embodiment based on various aspects of this disclosure, along Figure 3 The cross-sectional view taken from line AB.

[0140] As mentioned above, Figure 4 The area shown may include, with Figure 2 The region corresponding to the second node N2 of the driving transistor T1.

[0141] Reference Figure 4 The first conductive layer 310 can be disposed on the substrate 300.

[0142] The first conductive layer 310 may include a conductive material capable of absorbing or reflecting light. For example, the first conductive layer 310 may include any one of metals or alloys thereof, such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), etc.; however, embodiments of this disclosure are not limited thereto.

[0143] The first conductive layer 310 may be disposed below the first active layer 320 and used to protect the first active layer 320 from external factors (e.g., light) or to serve as an electrode for the storage capacitor Cst.

[0144] exist Figure 4 In the illustration, the first conductive layer 310 is shown as a single-layer structure; however, embodiments of the present disclosure are not limited thereto. For example, the first conductive layer 310 may have a multi-layer structure.

[0145] The buffer layer 411 can be disposed above the substrate on which the first conductive layer 310 is disposed.

[0146] The buffer layer 411 may include an inorganic insulating material, such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON); however, embodiments of this disclosure are not limited thereto.

[0147] exist Figure 4 In this embodiment, buffer layer 411 is represented as a single-layer structure; however, the implementation of this disclosure is not limited thereto. For example, buffer layer 411 may have a multi-layer structure.

[0148] The buffer layer 411 may include a first contact hole CH1 that exposes a portion of the top surface of the first conductive layer 310.

[0149] The first active layer 320 may be disposed on a portion of the top surface of the buffer layer 411.

[0150] like Figure 4 As shown, the first active layer 320 disposed in the sub-pixels of the organic light-emitting display device 100 according to the embodiments described herein may have a single layer.

[0151] The first active layer 320 can be any type of semiconductor layer.

[0152] The first active layer 320 may be formed of an oxide semiconductor. The material included in the first active layer 320 may be a metal oxide semiconductor and may be formed of: i) oxides of metals such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or ii) combinations of metals such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and oxides of molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti).

[0153] For example, the first active layer 320 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO); however, the embodiments of this disclosure are not limited thereto.

[0154] The first active layer 320 may include conductive and non-conductive regions. Furthermore, the first insulating film 412 may be disposed on the non-conductive region of the first active layer 320, and the conductive region of the first active layer 320 may be a region that does not overlap with the first insulating film 412.

[0155] The first insulating film 412 can be disposed on the first active layer 320.

[0156] The first insulating film 412 may include an inorganic insulating material, such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON); however, the embodiments of this disclosure are not limited thereto.

[0157] The first insulating film 412 may include a second contact hole CH2 that overlaps with the first contact hole CH1 disposed in the buffer layer 411.

[0158] Therefore, the first insulating film 412 can also expose a portion of the top surface of the first conductive layer 310 through the second contact hole CH2.

[0159] The width W1 of the first contact hole CH1 can be smaller than the width W2 of the second contact hole CH2. Here, the width W1 of the first contact hole CH1 and the width W2 of the second contact hole CH2 can be along... Figure 3 The maximum length of each contact hole along the cutting direction of line AB shown. Figure 3 The cutting direction of line AB shown can be Figure 3 The second direction (e.g., Figure 1 (The direction of travel of the gate line GL shown).

[0160] The first contact hole CH1 of the buffer layer 411 and the second contact hole CH2 of the first insulating film 412 can be formed by the same process. This provides the advantage of reducing the number of masks required to form the buffer layer 411 and the first insulating film 412.

[0161] Specifically, the material of the buffer layer 411 can be deposited on the substrate 300, and the material of the first active layer 320 can be deposited on the buffer layer 411. After patterning the material of the first active layer 320, the material of the first insulating film 412 can be deposited on the substrate 300.

[0162] Subsequently, a process for forming contact holes in each of the first insulating film 412 and the buffer layer 411 can be performed using a dry etching process. In this case, in the regions where the material of the first active layer 320 on the buffer layer 411 is present, the contact holes of the buffer layer 411 may not be formed in the corresponding regions because the material of the first active layer 320 acts as a mask.

[0163] In other words, such as Figure 4 As shown, even when the respective contact holes are formed in the first insulating film 412 and the buffer layer 411 by the same process, since the first contact hole of the buffer layer 411 is not formed in the region where the first active layer 320 is present, and the material of the first active layer 320 used as a mask is not present on the insulating film 412, the width W1 of the first contact hole CH1 of the buffer layer 411 can be smaller than the width W1 of the second contact hole CH2 of the first insulating film 412.

[0164] The first insulating film 412 can expose a portion of the top surface of the first active layer 320 disposed on the buffer layer 411 through the second contact hole CH2. The area of ​​the first active layer 320 that does not overlap with the first insulating film 412 can be a conductive area.

[0165] As described above, the material of the first insulating film 412 can be patterned using a dry etching process with plasma to form a first insulating film 412 having a second contact hole CH2. Furthermore, the first active layer 320 disposed in the region corresponding to the region where the material of the first insulating film 412 is removed by dry etching may become conductive due to the plasma (i.e., modified to act as a conductor).

[0166] However, the implementation of this disclosure is not limited thereto, and depending on the dry etching process conditions, a portion of the conductive region of the first active layer 320 may overlap with a portion of the first insulating film 412.

[0167] A second conductive layer 330 may be disposed above the substrate 300 on which the first insulating film 412 is disposed.

[0168] The second conductive layer 330 may include any one of metals such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), or alloys thereof; however, the embodiments of this disclosure are not limited thereto.

[0169] The second conductive layer 330 can contact the top surface of the first conductive layer 310 exposed through the first contact hole CH1 of the buffer layer 411 and the second contact hole CH2 of the first insulating film 412.

[0170] In addition, the second conductive layer 330 may be disposed above the buffer layer 411 and contact the conductive area of ​​the first active layer 320 disposed around the first contact hole CH1 of the buffer layer 411.

[0171] In other words, the second conductive layer 330 can be electrically connected to the first conductive layer 310, and can also be electrically connected to the first active layer 320.

[0172] The second insulating film 413 can be disposed on the second conductive layer 330.

[0173] The second insulating film 413 may include an inorganic insulating material, such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON); however, embodiments of this disclosure are not limited thereto.

[0174] The second insulating film 413 may include a third contact hole CH3 that exposes a portion of the top surface of the second conductive layer 330. The third contact hole CH3 of the second insulating film 413 may overlap with at least a portion of the first contact hole CH1 formed in the buffer layer 411 and with at least a portion of the second contact hole CH2 formed in the first insulating film 412.

[0175] The third insulating film 414 can be disposed on the second insulating film 413.

[0176] The third insulating film 414 may include organic insulating materials; however, embodiments of the present disclosure are not limited thereto.

[0177] The third insulating film 414 may include a fourth contact hole CH4 that overlaps with the third contact hole CH3 of the second insulating film 413.

[0178] Therefore, the third insulating film 414 can expose a portion of the top surface of the second conductive layer 330 through the fourth contact hole CH4.

[0179] The third conductive layer 360 can be disposed on the third insulating film 414.

[0180] The third conductive layer 360 may include a transparent conductive material, such as at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO); however, embodiments of this disclosure are not limited thereto.

[0181] The third conductive layer 360 can contact the second conductive layer 330 through the third contact hole CH3 of the second insulating film 413 and the fourth contact hole CH4 of the third insulating film 414.

[0182] Therefore, the third conductive layer 360 can be electrically connected to the second conductive layer 330, which is electrically connected to the first conductive layer 310 and the first active layer 320.

[0183] Meanwhile, the width W3 of the third contact hole CH3 of the second insulating film 413 can be substantially the same as the width W4 of the fourth contact hole CH4 of the third insulating film 414. The width W3 of the third contact hole CH3 of the second insulating film 413 and the width W4 of the fourth contact hole CH4 of the third insulating film 414 can be... Figure 3 The maximum length of each contact hole in the cutting direction of line AB shown.

[0184] However, the implementation of this disclosure is not limited thereto. For example, in Figure 3 In the cutting direction of line AB shown, the width W3 of the third contact hole CH3 of the second insulating film 413 can be smaller than the width W4 of the fourth contact hole CH4 of the third insulating film 414.

[0185] As described above, in the region included in the second node N2 of the driving transistor T1 of the organic light-emitting display device 100 according to the embodiments described herein, the first contact hole CH1 of the buffer layer 411, the second contact hole CH2 of the first insulating film 412, the third contact hole CH3 of the second insulating film 413, and the fourth contact hole CH4 of the third insulating film 414 may overlap each other.

[0186] Furthermore, the first conductive layer 310, the first active layer 320, the second conductive layer 330, and the third conductive layer 340 are electrically connected to each other through various contact holes (CH1, CH2, CH3, and CH4).

[0187] although Figure 4 The first active layer 320 is shown to have a single-layer structure; however, embodiments of the present disclosure are not limited thereto.

[0188] For example, the first active layer 320 can have a multilayer structure with two or more layers. (See reference...) Figure 5 Let's discuss this configuration in detail.

[0189] Figure 5This illustrates another embodiment along various aspects of this disclosure. Figure 3 A cross-sectional view of the region intercepted by line AB.

[0190] In the following description, for ease of description, some configurations, effects, etc. of the embodiments or examples discussed above may not be repeated. Furthermore, in the following description, the same reference numerals will be used for the same configurations or elements as those in the embodiments or examples described above.

[0191] like Figure 5 As shown, the organic light-emitting display device 100 according to the embodiments described herein includes a first conductive layer 310, a buffer layer 411 including a first contact hole CH1 and an active layer 520, a first insulating film 412 including a second contact hole CH2, a second conductive layer 330, a second insulating film 413 including a third contact hole CH3 and a third insulating film 414 including a fourth contact hole CH4, and a third conductive layer 360.

[0192] The first active layer 520 disposed on the buffer layer 411 may include an active pattern 521 and at least one conductive pattern 522 disposed on the active pattern 521. The conductive pattern 522 may be configured to expose a portion of the top surface and at least one side of the active pattern 521; however, the structure of the first active layer 520 according to the embodiments described herein is not limited thereto.

[0193] The active pattern 521 can be formed of an oxide semiconductor. The material included in the first active layer 520 can be a metal oxide semiconductor and can be formed from: i) oxides of metals such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or ii) combinations of metals such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and oxides of molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti).

[0194] For example, the active pattern 521 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO); however, the embodiments of this disclosure are not limited thereto.

[0195] The conductive pattern 522 may include any metal such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), or alloys thereof; however, embodiments of this disclosure are not limited thereto. For example, the conductive pattern 622 may include an alloy of molybdenum (Mo) and titanium (Ti); however, embodiments of this disclosure are not limited thereto.

[0196] The conductive pattern 522 can be disposed on the active pattern 521 to facilitate electrical connection with other components. Furthermore, the conductive pattern 522 can be used as a mask in the conductive process of the active pattern 521, thereby facilitating the conductive process of the active pattern 521 without requiring an additional mask.

[0197] The first insulating film 412 may be configured to expose a portion of the top surface of the active pattern 521 and at least one side surface. The first insulating film 412 may be configured to expose a portion of the top surface of the conductive pattern 522 and at least one side surface.

[0198] The active pattern 521 may include a conductive region 521a and a non-conductive region 521b.

[0199] The conductive region 521a of the active pattern 521 may not overlap with the first insulating film 412, and includes a region that does not overlap with the conductive pattern 522. In this embodiment, the non-conductive region 521b of the active pattern 521 may be a region that overlaps with the conductive pattern 522.

[0200] In another embodiment, the conductive region 521a of the active pattern 521 may not overlap with the first insulating film 412, and includes a portion of the region overlapping with the conductive pattern 522. In this embodiment, the non-conductive region 521b of the active pattern 521 may overlap with the first insulating film 412, and corresponds to the region overlapping with a portion of the conductive pattern 522.

[0201] In another embodiment, a portion of the conductive region 521a of the active pattern 521 may overlap with the first insulating film 412 and the conductive pattern 522. In this embodiment, a portion of the non-conductive region 521b of the active pattern 521 may overlap with a portion of the first insulating film 412.

[0202] The conductive region 521a of the active pattern 521 can be formed by a dry etching process of the first insulating film 412. In this case, the conductive pattern 522 disposed on the active pattern 521 is used as a mask, so the region of the active pattern 521 that does not overlap with the conductive pattern 522 can be made conductive by plasma (i.e., modified to act as a conductor).

[0203] Furthermore, depending on the dry etching process conditions, the conductive region 521a of the active pattern 521 may extend to a portion of the region overlapping with the conductive pattern 522.

[0204] An extension of the conductive region 521a of the active pattern 521 can contact the conductive pattern 522. For example, as Figure 5 As shown, when one end of the conductive pattern 522 is located at the boundary between the conductive region 521a and the non-conductive region 521b of the active pattern 521, the conductive pattern 522 can contact at least a portion of the conductive region 521a of the active pattern 521 at the boundary between the conductive region 521a and the non-conductive region 521b of the active pattern 521.

[0205] Furthermore, when a portion of the conductive region 521a of the active pattern 521 overlaps with a portion of the conductive pattern 522, the conductive pattern 522 can contact a portion of the top surface of the conductive region 521a of the active pattern 521.

[0206] The second conductive layer 330 can be disposed above the substrate 300 on which the first insulating film 412 is disposed.

[0207] Along Figure 3 In the region obtained by cutting line AB, a portion of the second conductive layer 330 may overlap with a portion of the first active layer 520, and the remaining portion of the second conductive layer 330 may not overlap with the first active layer 520.

[0208] The second conductive layer 330 can contact a portion of the active pattern 521 and a portion of the conductive pattern 522 of the first active layer 520 through the second contact hole CH2 formed in the first insulating film 412. Specifically, the second conductive layer 330 can contact a portion of the top surface and at least one side surface of the conductive pattern 522 that does not overlap with the first insulating film 412. In addition, the second conductive layer 330 can contact a portion of the top surface and at least one side surface (i.e., the conductive region 521a of the active pattern 521) that does not overlap with the conductive pattern 522.

[0209] The second conductive layer 330 can contact the first conductive layer 310 through the second contact hole CH2 formed in the first insulating film 412 and the first contact hole CH1 formed in the buffer layer 411.

[0210] Therefore, the second conductive layer 330 can be electrically connected to the active pattern 521 and conductive pattern 522 of the first conductive layer 310 and the first active layer 520.

[0211] According to the embodiments described herein, the resistance of the conductive pattern 522 can be lower than that of the active pattern 521. In this way, since the conductive pattern 522 is disposed on the active pattern 521 and the second conductive layer 330 is electrically connected to the conductive pattern 522 of the first active layer 520, the advantage of reduced contact resistance is provided.

[0212] The second insulating film 413 having the third contact hole CH3 and the third insulating film 414 having the fourth contact hole CH4 can be disposed on or above the second conductive layer 330.

[0213] exist Figure 3 In the cutting direction of line AB shown, the width W3 of the third contact hole CH3 of the second insulating film 413 can be smaller than the width W4 of the fourth contact hole CH4 of the third insulating film 414.

[0214] Furthermore, the third conductive layer 360 can be disposed above a substrate on which the third insulating film 414 is disposed. The third conductive layer 360 can be electrically connected to the second conductive layer 330 through the third contact hole CH3 and the fourth contact hole CH4.

[0215] Figure 4 and Figure 5 The diagram shows a structure in which one edge of the active layer (320, 520) overlaps with one edge of the buffer layer 411, but the structure of the organic light-emitting display device 100 according to the embodiments described herein is not limited thereto.

[0216] In the following sections, a detailed discussion will be given of other structures of the organic light-emitting display device 100 according to embodiments of the present disclosure.

[0217] Figure 6 This illustrates yet another embodiment along various aspects of this disclosure. Figure 3 A cross-sectional view of the region intercepted by line AB.

[0218] In the following description, for ease of description, some configurations, effects, etc. of the embodiments or examples discussed above will not be repeated. Furthermore, in the following description, the same reference numerals will be used for the same configurations or elements as those in the embodiments or examples described above.

[0219] Reference Figure 6 The first active layer 620 may be disposed on a portion of the top surface of the buffer layer 411.

[0220] Specifically, the active pattern 621 of the first active layer 620 may be disposed on a portion of the top surface of the buffer layer 411, and the conductive pattern 622 of the first active layer 620 may be disposed on the active pattern 621. The active pattern 621 may include a conductive region 621a and a non-conductive region 621b.

[0221] The active pattern 621 and the conductive pattern 622 may be configured to expose a portion of the top surface of the buffer layer 411. The conductive pattern 622 may be configured to expose a portion of the top surface of the active pattern 621 and at least one side surface.

[0222] The buffer layer 411 may include a first contact hole CH1 that exposes a portion of the top surface of the first conductive layer 310. A portion of the top surface of an extension of the buffer layer 411 formed from a side surface 611 of the buffer layer 411 may not overlap with the active pattern 621 and conductive pattern 622 of the first active layer 620, and may also not overlap with the first insulating film 412 disposed on the first active layer 620.

[0223] Multiple protrusions 670 may be disposed in at least a portion of the top surface of an extension that does not overlap with the first active layer 620 and the first insulating film 412 and extends from a side surface 611 of the buffer layer 411 formed by the first contact hole CH1.

[0224] The shapes of the multiple protrusions 670 may be irregular; however, the embodiments of this disclosure are not limited thereto.

[0225] Multiple protrusions 670 can be formed by a dry etching process for forming the second contact hole CH2 of the first insulating film 412.

[0226] Specifically, before the first insulating film 412 is formed, the materials of the active pattern 621 and the conductive pattern 622 can be sequentially deposited on the material of the buffer layer 411 before the first contact hole CH1 is formed.

[0227] Furthermore, after patterning the conductive pattern 622 using wet etching, a first active layer 620 including the active pattern 621 remaining in a non-conductive state can be formed by patterning the material of the active pattern 621 using wet etching.

[0228] In this configuration, since the conductive pattern 622 is disposed on the active pattern 621, it serves to prevent the active pattern 621 from being completely removed by the etching solution during the patterning process of the material forming the active pattern 621, and to allow the material forming the active pattern 621 to be patterned, thereby enabling the active pattern 621 to be formed below the conductive pattern 622. In other words, the conductive pattern 622 can improve the process stability of the first active layer 620.

[0229] As described above, when the active pattern 621 is patterned using wet etching, the outer edge of the active pattern 621 may have a very thin thickness due to the effect of the etching solution.

[0230] Subsequently, after depositing the material of the first insulating film 412 on the first active layer 620, which includes the active pattern 621 and the conductive pattern 622 that are kept in a non-conductive state, the first contact hole CH1 and the second contact hole CH2 can be formed substantially simultaneously by performing dry etching on the material of the first insulating film 412 and the material of the buffer layer 411.

[0231] The first contact hole CH1 of the buffer layer 411 can be formed to remove the material of the buffer layer 411 in the region corresponding to the region in which the active pattern 621 is not provided during a dry etching process for removing the material of the first insulating film 412.

[0232] Alternatively, the outer edge (with a thin thickness) of the active pattern 621 can be removed by plasma to expose a portion of the top surface of the buffer layer 411. Thus, a plurality of protrusions 670 can be formed by plasma on at least a portion of the top surface of the buffer layer 411 adjacent to the first contact hole CH1.

[0233] As described above, in the process of forming the second contact hole CH2 in the material of the first insulating film 412 and the first contact hole CH1 in the material of the buffer layer 411, the region of the active pattern 621 with a thin thickness (the outer edge of the active pattern) can be removed, and the region that is not removed by plasma and exposed can become conductive (i.e., modified to act as a conductor), and thus become the conductive region 621a of the active pattern 621.

[0234] However, the implementation of this disclosure is not limited thereto. Depending on the process conditions, a portion of the conductive region 621a of the active pattern 621 may overlap with a portion of the conductive pattern 622 and may overlap with a portion of the first insulating film 412.

[0235] The conductive region 621a of the active pattern 621 can be electrically connected to a portion of the conductive pattern 622.

[0236] The second conductive layer 330 may be disposed on or above the buffer layer 411, the first active layer 620 and the first insulating film 412.

[0237] The second conductive layer 330 can contact a portion of the top surface and at least one side surface of the conductive pattern 622 of the first active layer 620 through the second contact hole CH2 formed in the first insulating film 412. The second conductive layer 330 can contact a portion of the top surface and at least one side surface of the conductive pattern 621a of the active pattern 621 of the first active layer 620 through the second contact hole CH2 provided in the first insulating film 412.

[0238] The second conductive layer 330 can contact all or some of the surfaces of the plurality of protrusions 670 disposed on at least a portion of the top surface of the buffer layer 411.

[0239] The second insulating film 413 having the third contact hole CH3 and the third insulating film 414 having the fourth contact hole CH4 can be disposed on or above the second conductive layer 330.

[0240] The third contact hole CH3 and the fourth contact hole CH4 can be configured to overlap with the multiple protrusions 670 of the buffer layer 411.

[0241] Furthermore, the third conductive layer 360 can be disposed above the substrate on which the third insulating film 414 is disposed. The third conductive layer 360 can be electrically connected to the second conductive layer 330 through the third contact hole CH3 and the fourth contact hole CH4. Even if the plurality of protrusions 670 are disposed in at least a portion of the top surface of the buffer layer 411, the third conductive layer 360 can contact the second conductive layer 330.

[0242] At the same time, in relation to Figure 2 The region corresponding to the second node N2 of the driving transistor T1 contains, but is not limited to, the structure of the organic light-emitting display device 100 according to the embodiments described herein, comprising a buffer layer 411, a first active layer (320, 520, or 620), a first insulating film 412, and a second conductive layer 330, which is provided in the region corresponding to the second node N2 of the driving transistor T1. Figures 4 to 6 The structure shown can therefore form different structures.

[0243] In the following text, refer to Figure 7 and Figure 9 Further discussion will be given regarding other structures of organic light-emitting display devices based on various aspects of this disclosure.

[0244] Figures 7 to 9 Various embodiments of the arrangement of the buffer layer, the first active layer, the first insulating film, and the second conductive layer of an organic light-emitting display device according to the embodiments described herein are shown.

[0245] In the following description, for ease of description, some configurations, effects, etc. of the embodiments or examples discussed above may not be repeated. Furthermore, in the following description, the same reference numerals will be used for the same configurations or elements as those in the embodiments or examples described above.

[0246] Reference Figure 7 The active pattern 721 of the first active layer 720 can be disposed on a portion of the top surface of the buffer layer 411, and the conductive pattern 722 of the first active layer 720 can be disposed on the active pattern 721.

[0247] The active pattern 721 may include a conductive region 721a and a non-conductive region 721b. A portion of the conductive pattern 722 may contact a portion of the conductive region 721a of the active pattern 721.

[0248] The active pattern 721 and the conductive pattern 722 may be configured to expose a portion of the top surface of the buffer layer 411. The conductive pattern 722 may be configured to expose a portion of the top surface of the active pattern 721 and at least one side surface.

[0249] The buffer layer 411 may include a first contact hole CH1 that exposes a portion of the top surface of the first conductive layer 310. A portion of the top surface of an extension extending from a side surface 611 of the buffer layer 411 formed by the first contact hole CH1 may not overlap with the active pattern 721 and conductive pattern 722 of the first active layer 720, and may also not overlap with the first insulating film 412 disposed on the first active layer 720.

[0250] The second conductive layer 330 can contact the surfaces of the first active layer 720 and the buffer layer 411 that do not overlap with the first insulating film 412.

[0251] The second conductive layer 330 can contact a portion of the conductive region 721a and a portion of the conductive pattern 722 of the first active layer 720 through the second contact hole CH2 of the first insulating film 412.

[0252] form Figure 7 The processes for the first contact hole CH1 of the buffer layer 411 and the second contact hole CH2 of the first insulating film 412 shown can be equivalent to those described in reference. Figure 6 The described process.

[0253] and Figure 6 Compared to the structure, in Figure 7In the structure, depending on the process conditions for forming the first contact hole CH1 of the buffer layer 411 and the second contact hole CH2 of the first insulating film 412, a protrusion may not be formed in a portion of the top surface of the extension that does not overlap with the first active layer 720 and the first insulating film 412 and extends from a side surface 611 of the buffer layer 411.

[0254] Furthermore, depending on the process conditions, the conductive region 621a of the active pattern 621 may not overlap with the conductive pattern 622 and the first insulating film 412, and a portion of the non-conductive region 621b of the active pattern 621 may overlap not only with a portion of the conductive pattern 622, but also with a portion of the first insulating film 412.

[0255] A second insulating film 413 including a third contact hole CH3 and a third insulating film 414 including a fourth contact hole CH4 may be disposed on or above the second conductive layer 330. Each of the third contact hole CH3 and the fourth contact hole CH4 may overlap with the first contact hole CH1 and the second contact hole CH2.

[0256] The third conductive layer 360 can be disposed on the third insulating film 414.

[0257] The third conductive layer 360 can be electrically connected to the second conductive layer 330 through the third contact hole CH3 and the fourth contact hole CH4.

[0258] At the same time, despite Figures 5 to 7 A structure is shown in which a portion of the top surface of the active pattern (521, 621, or 721) of the first active layer (520, 620, or 720) does not overlap with the conductive pattern (522, 622, or 722); however, embodiments of the present disclosure are not limited thereto.

[0259] Reference Figure 8 At least one outer edge of the active pattern 821 of the first active layer 820 may overlap with the outer edge of the conductive pattern 822 of the first active layer 820.

[0260] In this embodiment, after depositing the material of the active pattern 821 on the material of the buffer layer 411 and depositing the material of the conductive pattern 822 on the material of the active pattern 821, the material of the conductive pattern 822 can then be patterned by wet etching using photoresist.

[0261] After that, as Figure 8As shown, the active pattern 821 and conductive pattern 822 of the first active layer 820 can be formed by patterning the material of the active pattern 821 using photoresist and conductive pattern 822 through wet etching. Specifically, one outer edge of the photoresist pattern can overlap with one outer edge of the conductive pattern 822, and when wet etching of the material of the active pattern 821 is performed using the photoresist pattern and conductive pattern 822 as a mask, the outer edges of the conductive pattern 822 and the outer edges of the active pattern 821 can overlap, as shown. Figure 8 As shown in the image.

[0262] Furthermore, the top surface of the active pattern 821, which remains in a non-conductive state, can be covered by the conductive pattern 822, and the side surface of the active pattern 821 can be left uncovered by the conductive pattern 822 and can exist in an exposed state.

[0263] Subsequently, the material for forming the first insulating film 412 can be formed by removing the photoresist pattern set on the conductive pattern 822.

[0264] The second contact hole CH2 can be formed in the first insulating film 412 by a dry etching process, and the first contact hole CH1 can be formed in the buffer layer 411. In this process, the side surface of the active pattern 821 that is not covered by the conductive pattern 822 can become conductive by plasma.

[0265] By changing conditions such as the dry etching process time and the amount or intensity of plasma energy, the interior (e.g., the outer edge of the side) of the active pattern 821 and the surface of the side surface forming the active pattern 821 can become conductive (i.e., modified to act as a conductor).

[0266] The active pattern 821 may include a conductive region 821a and a non-conductive region 821b.

[0267] The conductive pattern 822 may overlap with at least a portion of the conductive region 821a of the active pattern 821. Therefore, the conductive region 821a of the active pattern 821 may be electrically connected to a portion of the conductive pattern 822.

[0268] The first insulating film 412 can be disposed on the first active layer 820, and the second conductive layer 330 can be disposed on the first insulating film 412.

[0269] The second conductive layer 330 can contact a portion of the top surface and at least one side surface of the conductive pattern 822 of the first active layer 820 through the second contact hole CH2 formed in the first insulating film 412.

[0270] The second conductive layer 330 can contact the conductive region 821a of the active pattern 821 of the first active layer 820 through the second contact hole CH2 formed in the first insulating film 412.

[0271] A second insulating film 413 including a third contact hole CH3 and a third insulating film 414 including a fourth contact hole CH4 can be disposed on the second conductive layer 330.

[0272] The third conductive layer 360 can be disposed on the third insulating film 414.

[0273] The third conductive layer 360 can be electrically connected to the second conductive layer 330 through the third contact hole CH3 and the fourth contact hole CH4.

[0274] However, the shape of the first active layer according to the embodiments described herein is not limited thereto.

[0275] For example, such as Figure 9 As shown, the active pattern 921 may have a structure that exposes a portion of the rear surface of the conductive pattern 922.

[0276] It can be done Figure 8 The process described herein forms a first active layer 920 having a structure in which an active pattern 921 exposes a portion of the rear surface of a conductive pattern 922.

[0277] and Figure 8 Compared to the structure, in Figure 9 In the structure, since the material of the active pattern 921 may be over-etched by the etching solution during the wet etching process of the material of the active pattern 921 using photoresist pattern and conductive pattern 922, a structure is provided in view of this situation, in which the active pattern 921 is allowed to expose a portion of the back surface of the conductive pattern 922.

[0278] In the dry etching process in which the second contact hole CH2 is formed in the first insulating layer 412 and the first contact hole CH1 is formed in the buffer layer 411, the outer edge of the active pattern 921 that is not covered by the conductive pattern 922 can become conductive by plasma (i.e., modified to act as a conductor).

[0279] In this case, the top surface of the active pattern 921, which remains in a non-conductive state, can be covered by the conductive pattern 922, and the side surface of the active pattern 921 may not be covered by the conductive pattern 922 and may exist in an exposed state.

[0280] Therefore, the active pattern 921 may include a conductive region 921a and a non-conductive region 921b. The conductive region 921a of the active pattern 921 may be the region corresponding to the outer edge of the active pattern 921, and the remaining regions may be non-conductive regions 921b.

[0281] Simultaneously, the boundary region between the outer edge of the active pattern 921 and the top surface can also become conductive, and the rear surface of the conductive pattern 922 can contact the boundary region between the outer edge of the active pattern 921 and the top surface.

[0282] The first insulating film 412 can be disposed on the first active layer 920, and the second conductive layer 330 can be disposed on the first insulating film 412.

[0283] The second conductive layer 330 can contact a portion of the top surface and at least one side surface of the conductive pattern 922 of the first active layer 920 through the second contact hole CH2 formed in the first insulating film 412. Furthermore, the second conductive layer 330 can also contact at least a portion of the rear surface of the conductive pattern 922.

[0284] The second conductive layer 330 can contact the outer edge of the active pattern 921 of the active pattern 921 of the active pattern 921 of the first active layer 920 through the second contact hole CH2 formed in the first insulating film 412.

[0285] In other words, even when the active pattern 921 is over-etched to expose a portion of the rear surface of the conductive pattern 922 by forming an element disposed above the substrate 300, this structure can facilitate easy driving of the associated sub-pixels because the conductive pattern 922 can contact the outer side edge of the active pattern 921, i.e., the conductive region 921a of the active pattern 921, and the second conductive layer 330 can contact the first active layer 920.

[0286] At the same time, Figure 9 Although it has been described that the outer edge of the active pattern 921 can become conductive and the outer edge of the active pattern 921 can correspond to the structure of the conductive region 921a, the embodiments of the present disclosure are not limited thereto.

[0287] For example, in relation to along Figure 3 In the region corresponding to the area cut by line AB, according to the conditions of the process (dry etching process) that is modified to act as a conductor of active pattern 921, the outer edge or one side surface of active pattern 921 may not become conductive (i.e., not modified to act as a conductor).

[0288] However, the active pattern 921 can be used in addition to the pattern along the edge. Figure 3The area outside the area corresponding to the area cut by line AB becomes conductive, and the corresponding conductive area can be electrically connected to the conductive pattern 922 by contact.

[0289] In addition, Figures 3 to 9 Although a structure in which a portion of the top surface of the first active layer (320, 520, 620, 720, 820 or 920) is exposed through the second contact hole CH2 has been discussed, embodiments of the present disclosure are not limited thereto.

[0290] The arrangement relationship between the first active layer and the first insulating film in another embodiment of various aspects of this disclosure will be discussed.

[0291] Figure 10 The arrangement of the first active layer and the first insulating film is shown in another embodiment according to various aspects of this disclosure. Apart from the arrangement of the first active layer and the first insulating film, the structure of the remaining components can be the same as... Figure 5 The components have basically the same structure.

[0292] In the following description, for ease of description, some configurations, effects, etc. of the embodiments or examples discussed above may not be repeated. Furthermore, in the following description, the same reference numerals will be used for the same configurations or elements as those in the embodiments or examples described above.

[0293] Reference Figure 10 The first insulating film 1012 can cover the entire upper surface of the conductive pattern 522 of the first active layer 520, and expose one side surface of the conductive pattern 522 through the second contact hole CH2.

[0294] The first insulating film 1012 may be configured to expose a portion of the top surface and a side surface of the active pattern 521 of the first active layer 520.

[0295] In this configuration, the second conductive layer 330 can contact the side surface of the conductive pattern 522 through the second contact hole CH2 of the first insulating film 1012 and can be electrically connected to the conductive pattern 522. Furthermore, the second conductive layer 330 can contact a portion of the upper surface and a side surface of the active pattern 521 through the second contact hole CH2 of the first insulating film 1012 and can be electrically connected to the active pattern.

[0296] At the same time, Figures 5 to 10Although the structure of the first active layer (520, 620, 720, 820, or 920) comprising an active pattern (521, 621, 721, 821, or 921) and a conductive pattern (522, 622, 722, 822, or 922) has been described, however, Figure 3 The active layer 325 shown may also include active patterns and conductive patterns.

[0297] Next, we will refer to Figure 11 Another structure is described for the region included in the second node N2 of the driving transistor T1 in the sub-pixel of the organic light-emitting display device 100 according to the embodiments described herein.

[0298] Figure 11 Based on all aspects of this disclosure Figure 3 The cross-sectional view taken from line CD.

[0299] In the following description, for ease of description, some configurations, effects, etc. of the embodiments or examples discussed above may not be repeated. Furthermore, in the following description, the same reference numerals will be used for the same configurations or elements as those in the embodiments or examples described above.

[0300] In the following description, the application will be used as a basis. Figure 5 The structure of the first active layer 520 shown in the figure is used to describe the first active layer.

[0301] Reference Figure 11 The first conductive layer 310 can be disposed on the substrate 300.

[0302] The buffer layer 411 can be disposed on the first conductive layer 310.

[0303] The first active layer 520 may be disposed on the buffer layer 411. The first active layer 520 may include an active pattern 521 disposed on the buffer layer 411 and at least one conductive pattern 522 disposed on the active pattern 521.

[0304] The first insulating film 412 can be disposed on the first active layer 520.

[0305] The first insulating film 412 may be configured to expose a portion of the top surface of the active pattern 521 and at least one side surface. The first insulating film 412 may be configured to expose a portion of the top surface of the conductive pattern 522 and at least one side surface.

[0306] The active pattern 521 may include a conductive region 521a and a non-conductive region 521b.

[0307] Specifically, such as Figure 11As shown, the conductive region 521a of the active pattern 521 may not overlap with the first insulating film 412, and may be or include a region that does not overlap with the conductive pattern 522.

[0308] In another embodiment, the conductive region 521a of the active pattern 521 may not overlap with the first insulating film 412, and may include a portion of the region that overlaps with the conductive pattern 522. In another embodiment, a portion of the conductive region 521a of the active pattern 521 may overlap with both the first insulating film 412 and the conductive pattern 522.

[0309] The conductive region 521a of the active pattern 521 can be formed in the process of forming the first contact hole CH1 in the buffer layer 411 and / or forming the second contact hole CH2 in the first insulating film 412. The size of the conductive region 521a can vary depending on the process conditions.

[0310] The non-conductive region 521b of the active pattern 521 can be any region of the active pattern 521 other than the conductive region 521a.

[0311] The conductive pattern 522 of the first active layer 520 can contact a portion of the conductive region 521a of the active pattern 521.

[0312] The first insulating film 412 may be configured to expose a portion of the top surface of the active pattern 521 and at least one side surface. The first insulating film 412 may be configured to expose a portion of the top surface of the conductive pattern 522 and at least one side surface.

[0313] The second conductive layer 330 can be disposed above the substrate 300 on which the first insulating film 412 is disposed.

[0314] Along Figure 3 In the area where the line CD is cut, the entire second conductive layer 330 can overlap with the first active layer 520.

[0315] The second conductive layer 330 can contact a portion of the active pattern 521 and a portion of the conductive pattern 522 of the first active layer 520 through the second contact hole CH2 formed in the first insulating film 412. Therefore, the second conductive layer 330 can be electrically connected to the active pattern 521 and the conductive pattern 522 of the first active layer 520.

[0316] Along Figure 3 In the area where the CD is cut, the buffer layer 411 may not have the first contact hole CH1.

[0317] The first contact hole CH1 of the buffer layer 411 can be formed in the same process as the second contact hole CH2 formed in the first insulating film 412 by dry etching. Since the first active layer 520 acts as a mask in the area where it is disposed on the buffer layer 411, the first active layer 520 can thus prevent the formation of contact holes in the buffer layer 411. Therefore, as... Figure 11 As shown, the first contact hole CH1 of the buffer layer 411 may not be formed in the region on the top surface of the first active layer 520 in which the buffer layer 411 is disposed.

[0318] The second insulating film 413 having the third contact hole CH3 and the third insulating film 414 having the fourth contact hole CH4 can be disposed on or above the second conductive layer 330.

[0319] The third contact hole CH3 and the fourth contact hole CH4 can be contact holes that expose a portion of the top surface of the second conductive layer 330.

[0320] The third conductive layer 360 can be disposed above the substrate 300 on which the third insulating film 414 is disposed.

[0321] The third conductive layer 360 can contact the second conductive layer 330 through the third contact hole CH3 and the fourth contact hole CH4. Therefore, the third conductive layer 360 can be electrically connected to the second conductive layer 330.

[0322] Next, we will refer to Figure 12 Another structure is described for the region included in the second node N2 of the driving transistor T1 in the sub-pixel of the organic light-emitting display device 100 according to the embodiments described herein.

[0323] Figure 12 Based on all aspects of this disclosure Figure 3 The cross-sectional view taken from line EF.

[0324] In the following description, for ease of description, some configurations, effects, etc. of the embodiments or examples discussed above may not be repeated. Furthermore, in the following description, the same reference numerals will be used for the same configurations or elements as those in the embodiments or examples described above.

[0325] In the following description, the application will be used as a basis. Figure 5 The structure of the first active layer 520 shown in the figure is used to describe the first active layer.

[0326] Reference Figure 12 The first conductive layer 310 can be disposed on the substrate 300.

[0327] A buffer layer 411, including the first contact hole CH1, can be disposed on the first conductive layer 310. The buffer layer 411 can expose a portion of the top surface of the first conductive layer 310 through the first contact hole CH1.

[0328] A first insulating film 412, including a second contact hole CH2, may be disposed on a buffer layer 411. The second contact hole CH2 of the first insulating film 412 may overlap with the first contact hole CH1 of the buffer layer 411, and a portion of the top surface of the first conductive layer 310 may be exposed at the same location as the first contact hole CH1.

[0329] The second conductive layer 330 can be disposed above the substrate 300 on which the first insulating film 412 is disposed.

[0330] The second insulating film 413 having the third contact hole CH3 and the third insulating film 414 having the fourth contact hole CH4 can be disposed on or above the second conductive layer 330.

[0331] The third contact hole CH3 and the fourth contact hole CH4 can be contact holes that expose a portion of the top surface of the second conductive layer 330.

[0332] The third conductive layer 360 can be disposed above the substrate 300 on which the third insulating film 414 is disposed.

[0333] The third conductive layer 360 can contact the second conductive layer 330 through the third contact hole CH3 and the fourth contact hole CH4. Therefore, the third conductive layer 360 can be electrically connected to the second conductive layer 330.

[0334] Along Figure 3 In the region cut by line EF, the second conductive layer 330 may not overlap with the first active layer 520.

[0335] The widths L of the first contact hole CH1 and the second contact hole CH2 can correspond to each other. Here, the width L of the first contact hole CH1 and the second contact hole CH2 can be the width of each contact hole in... Figure 3 The maximum length in the first direction (e.g., the direction in which the data line travels).

[0336] As described above, the first contact hole CH1 of the buffer layer 411 and the second contact hole CH2 of the first insulating film 412 can be formed by the same process.

[0337] Due to along Figure 3 The area cut by line EF shown corresponds to the area where the first active layer 520 is not provided on the buffer layer 411, so the second contact hole CH2 of the insulating film 412 and the first contact hole CH1 of the buffer layer 411 can be formed when the dry etching process is performed.

[0338] In other words, the position of the first contact hole CH1 of the buffer layer 411 can depend on the position corresponding to the location of the first contact hole CH1 of the buffer layer 411. Figure 2 The arrangement relationship between the buffer layer 411 and the first active layer 350 in the region of the second node N2 is determined. Therefore, even when the first contact hole CH1 of the buffer layer 411 and the second contact hole CH2 of the first insulating film 412 are formed by the same process, the respective widths of the first contact hole CH1 and the second contact hole CH2 can become partially different.

[0339] Reference Figure 13 This will be discussed in detail.

[0340] Figure 13 It shows in Figure 2 The location and width of the contact hole formed in the region included in the second node of the driving transistor.

[0341] The first contact hole CH1 can overlap with the second contact hole CH2.

[0342] The widths L of the first contact hole CH1 and the second contact hole CH2 in the first direction can correspond to each other.

[0343] The width W1 of the first contact hole CH1 and the width W2 of the second contact hole CH2 can be different from each other in the second direction.

[0344] In the planar view, the area of ​​the second contact hole CH2 can be larger than the area of ​​the first contact hole CH1. This is because the first contact hole CH1 may not be formed in the region where the buffer layer overlaps with the first active layer.

[0345] In other words, the area where the second contact hole CH2 does not overlap with the first contact hole CH1 can be the area where the second contact hole CH2 overlaps with the first active layer.

[0346] In addition, a contact hole 342 may be provided around the first contact hole CH1 and the second contact hole CH2. The contact hole 342 may include a third contact hole CH3 and a fourth contact hole CH4 of the second insulating film, and the widths of the third contact hole CH3 and the fourth contact hole CH4 may be substantially equal in both the first direction and the second direction, or may be different in at least one of the first direction and the second direction.

[0347] When the widths of the third contact hole CH3 and the fourth contact hole CH4 are substantially equal in both the first and second directions, such as Figure 13 As shown in the diagram, in the plan view, the areas of the third contact hole CH3 and the fourth contact hole CH4 can be substantially equal.

[0348] When the widths of the third contact hole CH3 and the fourth contact hole CH4 are different in at least one of the first and second directions, the areas of the third contact hole CH3 and the fourth contact hole CH4 may be different in the plan view.

[0349] In this way, due to the overlap of at least two of the first to fourth contact holes, the impact can be reduced. Figure 2 The area occupied by the contact hole in the region included in the second node N2 of the driving transistor T1.

[0350] As mentioned above, the size of the storage capacitor located in the sub-pixel can be increased by reducing the area occupied by the contact hole.

[0351] The storage capacitor of the organic light-emitting display device 100 according to the embodiments described herein may include multiple layers of electrodes, thereby enabling the realization of a storage capacitor with high capacitance characteristics.

[0352] Reference Figure 14 The structure of the storage capacitor according to the embodiments described herein is discussed.

[0353] Figure 14 Based on all aspects of this disclosure Figure 3 The cross-sectional view of line GH.

[0354] In the following description, for ease of description, some configurations, effects, etc. of the embodiments or examples discussed above may not be repeated. Furthermore, in the following description, the same reference numerals will be used for the same configurations or elements as those in the embodiments or examples described above.

[0355] In the following description, the application will be used as a basis. Figure 5 The structure of the first active layer 520 shown in the figure is used to describe the first active layer.

[0356] Reference Figure 14 The first conductive layer 310, buffer layer 411, active pattern 521 and conductive pattern 522 of the first active layer 520, first insulating film 412, plate 340, second insulating film 413, third insulating film 414 and third conductive layer 360 can be sequentially disposed above the substrate 300.

[0357] As described above, plate 340 can be disposed in the same layer as the second conductive layer 330.

[0358] When one or more layers of inorganic insulating material are disposed between the first conductive layer 310, the active pattern 521 of the first active layer 520 and the plate 340, each of the first conductive layer 310, the active pattern 521 of the first active layer 520 and the plate 340 is configured to overlap each other, thereby acting as an electrode of the storage capacitor.

[0359] According to the embodiments described herein, since the first active layer 520 includes a conductive pattern 522, and a large portion of the area where the plate 340, the first active layer 520, and the first conductive layer 310 overlap is used as a storage capacitor Cst, an organic light-emitting display device 100 with high resolution can be realized.

[0360] although Figure 14 The structure in which the first active layer 520 includes a conductive pattern 522 is shown; however, as Figure 4 As shown, the first active layer 520 may have a structure comprising only active patterns. In this case, the region in which the active patterns are disposed of, where the storage capacitor is located, may be a conductive region.

[0361] Since the storage capacitor of the organic light-emitting display device 100 according to the embodiments described herein has a multilayer structure, a storage capacitor with high capacitance characteristics can be realized.

[0362] According to the embodiments described herein, since at least two contact holes in the contact holes provided in the region corresponding to the second node of the driving transistor overlap, the size or capacity of the storage capacitor can be increased without reducing the area of ​​the light-emitting region, and thus, an organic light-emitting display panel with high brightness and high resolution and an organic light-emitting display device including the display panel can be provided.

[0363] Furthermore, according to the embodiments described herein, by forming contact holes in the buffer layer and the first insulating film through the same process, an organic light-emitting display panel, and an organic light-emitting display device including the display panel, can be provided that can be manufactured using a reduced number of masks and a simplified process.

[0364] Furthermore, according to the embodiments described herein, since the active layer includes an active pattern and a conductive pattern disposed on the active pattern, an organic light-emitting display panel that can easily drive sub-pixels and an organic light-emitting display device including the display panel can be provided.

[0365] The above description is presented to enable those skilled in the art to implement and use the technical concepts of the invention, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the illustrated embodiments, but is consistent with the widest scope consistent with the claims. The scope of protection of the invention should be understood based on the appended claims, and all technical ideas within their equivalents should be understood to be included within the scope of the invention.

Claims

1. An organic light-emitting display device, comprising: substrate; A first conductive layer is disposed on the substrate; A buffer layer is disposed on the first conductive layer and includes a first contact hole overlapping a portion of the first conductive layer; A first active layer is disposed on a portion of the top surface of the buffer layer; A first insulating film is disposed above the first active layer and the buffer layer, and includes a second contact hole overlapping the first contact hole; A second conductive layer is disposed on the first insulating film and contacts a portion of the first conductive layer and a portion of the first active layer through the first contact hole and the second contact hole; A second insulating film is disposed on the second conductive layer and includes a third contact hole that overlaps with the first contact hole and the second contact hole; as well as A third conductive layer is disposed on the second insulating film and contacts a portion of the second conductive layer through the second contact hole. Wherein, the first contact hole, the second contact hole, and the third contact hole overlap each other, and The first active layer serves as the electrode of the storage capacitor.

2. The organic light-emitting display device according to claim 1, wherein, The first active layer includes at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO), and The area where the first active layer overlaps with the second contact hole is a conductive area.

3. The organic light-emitting display device according to claim 1, wherein, The first active layer includes an active pattern disposed on the buffer layer and at least one conductive pattern disposed on the active pattern, and The active pattern includes at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO), and the conductive pattern includes any one of a metal or alloy, wherein the metal includes aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti), and the alloy includes two or more of aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti).

4. The organic light-emitting display device according to claim 3, wherein, The active pattern includes conductive and non-conductive regions, and the conductive pattern contacts the conductive region of the active pattern.

5. The organic light-emitting display device according to claim 3, wherein, The conductive pattern exposes a portion of the top surface and at least one side surface of the active pattern.

6. The organic light-emitting display device according to claim 3, wherein, At least one outer edge of the conductive pattern overlaps with the outer edge of the active pattern.

7. The organic light-emitting display device according to claim 3, wherein, The active pattern exposes a portion of the rear surface of the conductive pattern.

8. The organic light-emitting display device according to claim 3, wherein, The second conductive layer contacts a portion of the conductive pattern and a portion of the active pattern through the third contact hole.

9. The organic light-emitting display device according to claim 1, wherein, The first active layer exposes a portion of the top surface of the buffer layer, and the portion of the top surface of the buffer layer exposed by the first active layer includes a plurality of protrusions.

10. The organic light-emitting display device according to claim 1, wherein, The width of the first contact hole in the first direction corresponds to the width of the second contact hole in the first direction, and the width of the first contact hole in the second direction intersecting the first direction is less than the width of the second contact hole in the second direction.

11. The organic light-emitting display device according to claim 1, wherein, The third conductive layer is the anode or cathode electrode of the organic light-emitting element.

12. The organic light-emitting display device according to claim 1, further comprising a plate disposed in the same layer as the second conductive layer and spaced apart from the second conductive layer. in, The plate forms the storage capacitor by overlapping with a portion of the first conductive layer and a portion of the first active layer.

13. The organic light-emitting display device according to claim 12, wherein, The plate includes an extension that overlaps with a portion of the active layer, and the extension is a first gate electrode of a driving transistor.

14. The organic light-emitting display device according to claim 13, wherein, The region containing the first contact hole, the second contact hole, and the third contact hole is the region including the node to which the reference voltage is applied to the driving transistor.

15. The organic light-emitting display device according to claim 1, further comprising: The second active layer is disposed in the same layer as the first active layer and is spaced apart from the first active layer; as well as A second gate electrode is disposed above the second active layer and overlaps with a portion of the second active layer.

16. The organic light-emitting display device according to claim 15, wherein, The second gate electrode is electrically connected to the data line.

17. The organic light-emitting display device according to claim 15, wherein, The region between the first active layer and the second active layer overlaps with one or more of a portion of the first contact hole, a portion of the second contact hole, and a portion of the third contact hole.

18. An organic light-emitting display panel, comprising: substrate; A first conductive layer is disposed on the substrate; A buffer layer is disposed on the first conductive layer and includes a first contact hole overlapping a portion of the first conductive layer; An active layer includes an active pattern disposed on the buffer layer and a conductive pattern disposed on the active pattern; A first insulating film is disposed above the active layer and the buffer layer, and includes a second contact hole overlapping the first contact hole; A second conductive layer is disposed on the first insulating film and contacts the first conductive layer through the first contact hole and the second contact hole; as well as A plate, which is disposed in the same layer as the second conductive layer and spaced apart from the second conductive layer, Wherein, the first conductive layer, the active layer, and the plate overlap each other, such that two or more of the first conductive layer, the active layer, and the plate form storage capacitors, and The active layer serves as the electrode of the storage capacitor.

19. The organic light-emitting display panel according to claim 18, further comprising: A second insulating film is disposed on the second conductive layer and includes a third contact hole that overlaps with the first contact hole and the second contact hole; A third insulating film is disposed on the second insulating film and includes a fourth contact hole overlapping the third contact hole; as well as A third conductive layer is disposed on the third insulating film and contacts a portion of the second conductive layer through the second contact hole and the third contact hole.

20. The organic light-emitting display panel according to claim 19, wherein, The first contact hole, the second contact hole, and the third contact hole overlap each other.

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