Organic light emitting diode display panel and manufacturing method thereof

Abstract

The present application provides an organic light emitting diode display panel and a manufacturing method thereof. The organic light emitting diode display panel includes a substrate, a thin film transistor layer, a passivation layer and a cathode. The thin film transistor layer is arranged on the substrate, including a source electrode, a drain electrode and an auxiliary cathode, and the auxiliary cathode is arranged in the same layer as the source electrode and the drain electrode. The passivation layer covers the side of the thin film transistor layer away from the substrate. The cathode is arranged on the side of the passivation layer away from the thin film transistor layer. Among them, the passivation layer includes a first passivation layer and a second passivation layer, and an undercut structure is formed between the first passivation layer and the second passivation layer. The undercut structure exposes the auxiliary cathode, and the cathode extends into the undercut structure and is connected to the auxiliary cathode. The organic light emitting diode display panel of the present application uses a passivation layer to form an undercut structure, which can improve the connection performance of the cathode and the auxiliary cathode and reduce the voltage drop.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an organic light emitting diode display panel and a method for manufacturing the same. Background Art

[0002] Organic light-emitting diode display panels can be divided into top-emitting and bottom-emitting types according to the direction of light emission. In existing top-emitting organic light-emitting diode display panels, since the cathode is a whole-surface electrode, in order to increase the transmittance of light, the cathode needs to be as thin as possible. However, the thinner the cathode layer thickness, the greater the resistance. When an electrical signal is provided from the edge of the display panel to the cathode, the voltage drop (IR Drop) gradually increases from the edge of the display panel to the center of the display panel. After the display panel is lit, the edge will be bright and the middle will be dark. This situation is more serious in large-size display panels, and has become one of the difficulties that large-size organic light-emitting diode display panels currently need to overcome.

[0003] The problem of voltage drop can be solved by providing an auxiliary cathode on the array substrate, and the cathode and the auxiliary cathode are connected through a via hole. However, during the evaporation process of the electron transport layer and / or the electron injection layer, the electron transport layer and / or the electron injection layer will enter the via hole and occupy the via hole, thereby preventing the cathode from connecting with the auxiliary cathode in the via hole. Summary of the invention

[0004] In view of this, the present application provides an organic light emitting diode display panel capable of improving the connection performance between a cathode and an auxiliary cathode and a method for manufacturing the same.

[0005] The present application provides an organic light emitting diode display panel, which includes:

[0006] substrate;

[0007] A thin film transistor layer, disposed on the substrate, the thin film transistor layer comprising a source electrode, a drain electrode and an auxiliary cathode, the auxiliary cathode being disposed in the same layer as the source electrode and the drain electrode;

[0008] a passivation layer covering a side of the thin film transistor layer away from the substrate; and

[0009] A cathode, disposed on a side of the passivation layer away from the thin film transistor layer;

[0010] Wherein, the passivation layer includes a first passivation layer and a second passivation layer, the second passivation layer is located on the side of the first passivation layer away from the thin film transistor layer, a first through hole is opened in the first passivation layer, a second through hole is opened in the second passivation layer, the first through hole is connected to the second through hole, the first through hole and the second through hole constitute an undercut structure, the undercut structure exposes the auxiliary cathode, and the cathode extends into the undercut structure and is connected to the auxiliary cathode.

[0011] Optionally, in one implementation, the material of the first passivation layer includes silicon oxide, and the material of the second passivation layer includes silicon nitride.

[0012] Optionally, in one embodiment, the cathode is located on a side wall of the undercut structure and is connected to the auxiliary cathode.

[0013] Optionally, in one embodiment, the organic light emitting diode display panel further includes an electronic functional layer, wherein the electronic functional layer is disposed on a side of the cathode close to the passivation layer, a portion of the electronic functional layer is located on the auxiliary cathode in the undercut structure, and the cathode is located between a portion of the electronic functional layer and a side wall of the undercut structure.

[0014] Optionally, in one embodiment, the auxiliary cathode includes a conductive metal layer and a protective metal layer which are stacked, the conductive metal layer is disposed between the protective metal layer and the substrate, and the material of the protective metal layer is resistant to hydrofluoric acid corrosion.

[0015] Optionally, in one embodiment, the organic light emitting diode display panel further includes a planar layer, wherein the planar layer is disposed on a side of the passivation layer away from the thin film transistor layer, and a third through hole is opened in the planar layer, wherein the third through hole is connected to the second through hole, and the cathode extends from the third through hole into the undercut structure.

[0016] The present application also provides a method for manufacturing an organic light emitting diode display panel, which comprises the following steps:

[0017] providing a substrate;

[0018] forming a thin film transistor layer on the substrate, wherein the thin film transistor layer comprises a source electrode, a drain electrode and an auxiliary cathode, and the auxiliary cathode is arranged in the same layer as the source electrode and the drain electrode;

[0019] forming a passivation layer on the thin film transistor layer, wherein the passivation layer comprises a first passivation layer and a second passivation layer, wherein the second passivation layer is located on a side of the first passivation layer away from the thin film transistor layer;

[0020] Etching the first passivation layer and the second passivation layer with an etching solution to form an undercut structure, wherein the etching speed of the etching solution on the first passivation layer is greater than the etching speed of the second passivation layer, and the undercut structure exposes the auxiliary cathode; and

[0021] A cathode is formed on the passivation layer, and the cathode extends into the undercut structure and is connected to the auxiliary cathode.

[0022] Optionally, in one implementation, after forming a passivation layer on the thin film transistor layer, before etching the first passivation layer and the second passivation layer with an etching solution, the method further includes:

[0023] Using an etching gas to simultaneously etch the first passivation layer and the second passivation layer to form a prefabricated hole in the first passivation layer, the prefabricated hole penetrates the first passivation layer and the second passivation layer, and forms a contact hole above the thin film transistor layer to expose the source electrode of the thin film transistor layer;

[0024] The etching of the first passivation layer and the second passivation layer by using an etching solution comprises:

[0025] The first passivation layer and the second passivation layer are etched at the prefabricated hole using an etching solution.

[0026] Optionally, in one implementation, after forming a passivation layer on the thin film transistor layer, before etching the first passivation layer and the second passivation layer with an etching solution, the method further includes:

[0027] forming a planarization layer on the passivation layer; and

[0028] patterning the planar layer using a half-tone mask to form a third through hole and a first blind hole in the planar layer;

[0029] The etching of the first passivation layer and the second passivation layer by using an etching solution comprises:

[0030] etching the first passivation layer and the second passivation layer at the third through hole;

[0031] After etching the first passivation layer and the second passivation layer with an etching solution, the method further comprises:

[0032] Perform dry etching on the first blind hole to form a through hole;

[0033] The first passivation layer and the second passivation layer are etched at the through hole to form a contact hole to expose the source electrode of the thin film transistor layer.

[0034] Optionally, in one embodiment, the first passivation layer includes silicon oxide, the second passivation layer includes silicon nitride, the etching solution is hydrofluoric acid, and the etching rate ratio of the etching solution to silicon oxide and silicon nitride is greater than or equal to 10.

[0035] The organic light emitting diode display panel of the present application utilizes a passivation layer to form an undercut structure, which can improve the connection performance of the cathode and the auxiliary cathode and reduce the voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solution in the present application, the drawings required for use in the description of the implementation methods will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 Schematic diagram of the structure of a display panel according to an embodiment of the present application.

[0038] Figure 2 for Figure 1 A schematic top view of a sub-pixel and an auxiliary cathode connection hole of a display panel.

[0039] Figure 3(a) to Figure 3(l) FIG. 1 is a schematic diagram of steps of a first embodiment of a method for manufacturing a display panel of the present application.

[0040] Figure 4(a) to Figure 4(m) FIG. 1 is a schematic diagram of steps of a second embodiment of a method for manufacturing a display panel of the present application. DETAILED DESCRIPTION

[0041] The technical solution in this application will be described clearly and completely below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0042] In the present application, unless otherwise expressly specified and limited, the first feature "above" or "below" the second feature may include the first and second features directly, or may include the first and second features not being directly connected but being in contact through another feature between them. Moreover, the first feature "above", "above" and "above" the second feature include the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. The first feature "below", "below" and "below" the second feature include the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features.

[0043] The organic light emitting diode display panel in the embodiment of the present application can be used in mobile phones, tablet computers, e-readers, electronic display screens, laptop computers, mobile phones, augmented reality (AR) and virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc. Specifically, the organic light emitting diode display panel can be an active matrix organic light emitting diode (AMOLED) display panel or a passive matrix organic light emitting diode (PMOLED) display panel.

[0044] Please refer to Figure 1 The organic light emitting diode display panel 100 of the embodiment of the present application includes a substrate 10, a light shielding layer LS, a buffer layer BL, a thin film transistor layer 20, a passivation layer 30, a planarization layer 40 and an organic light emitting layer 50. The thin film transistor layer 20, the passivation layer 30, the planarization layer 40 and the organic light emitting layer 50 are sequentially stacked on the substrate 10.

[0045] The substrate 10 may be glass, plastic or a flexible substrate. The flexible substrate may be composed of a single flexible organic layer or two or more flexible organic layers. Optionally, the substrate 10 includes two flexible organic layers stacked in sequence and a barrier layer disposed between the two flexible organic layers. The materials of the two flexible organic layers are independently selected from one of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate (PAR), polycarbonate (PC), polyetherimide (PEI) and polyether sulfone (PES). The barrier layer is selected from inorganic materials such as silicon dioxide and silicon nitride.

[0046] The light shielding layer LS is disposed on the substrate 10. The light shielding layer LS is used to prevent the active layer CL of the thin film transistor in the thin film transistor layer 20 from being affected by light. Optionally, the material of the light shielding layer LS is selected from copper (CU), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), copper-niobium (CuNb) alloy, copper (Cu) and molybdenum (Mo) stacking, copper (Cu) and molybdenum-titanium (MoTi) alloy stacking, copper (Cu) and titanium (Ti) stacking, aluminum (Al) and molybdenum (Mo) stacking, molybdenum (Mo) and tantalum (Ta) stacking, molybdenum (Mo) and tungsten (W) stacking, molybdenum (Mo)-aluminum (Al)-molybdenum (Mo) stacking. Optionally, the light shielding layer LS may include a light shielding metal layer, a diffusion barrier layer, and an etching barrier layer that are stacked. The material of the light shielding metal layer may be a Mo / Cu stacking. The material of the diffusion barrier layer may be a material such as MoTi, Mo, Ta, etc., whose work function is similar to that of Cu. The material of the etching stop layer can be metal oxides such as ITO and IGZO.

[0047] The buffer layer BL is used to prevent the metal of the light shielding layer LS from entering the active layer CL of the thin film transistor T in the thin film transistor layer 20. Optionally, the material of the buffer layer BL is selected from one of silicon oxide, nitride oxide, silicon oxynitride and a stack of silicon oxide, nitride oxide and silicon oxynitride.

[0048] The thin film transistor layer 20 is disposed on the substrate 10. The thin film transistor layer 20 includes a pixel driving circuit that drives the sub-pixels of the organic light emitting diode display panel 100 to emit light. The pixel driving circuit can be a 2T1C, 3T1C, 5T1C or 7T1C pixel driving circuit commonly used in the art. Specifically, the thin film transistor layer 20 includes a plurality of thin film transistors T. The plurality of thin film transistors T can be divided into a driving transistor, a switching transistor, etc. according to their functions in the pixel circuit. It should be noted that in Figure 1 Only the complete structure of a thin film transistor T of the pixel circuit is shown, and some parts of the pixel circuit are omitted.

[0049] The thin film transistor T is located in the display area AA. The thin film transistor T includes an active layer CL, a gate insulating layer GI, a gate GE, an interlayer insulating layer IL, and a source electrode SE and a drain electrode DE which are sequentially stacked on the buffer layer BL. Specifically, the active layer CL is located on the surface of the buffer layer BL away from the substrate 10. The active layer CL includes a channel region and a source region and a drain region located on both sides of the channel region. The gate insulating layer GI is disposed on the channel region. The gate GE is disposed on the gate insulating layer GI. The interlayer insulating layer IL covers the gate GE and the active layer CL. The source electrode SE and the drain electrode DE are located on the interlayer insulating layer IL. The source electrode SE and the drain electrode DE are respectively disposed corresponding to the source region and the drain region of the active layer CL, and are respectively connected to the source region and the drain region of the active layer CL via vias provided in the interlayer insulating layer IL.

[0050] The thin film transistor layer 20 also includes an auxiliary cathode 21. The auxiliary cathode 21 is arranged in the same layer as the source SE and drain DE of the thin film transistor. It can be understood that the source SE, the drain DE and the auxiliary cathode 21 can be manufactured using the same material in the same process. Optionally, the auxiliary cathode 21 includes a conductive metal layer and a protective metal layer that are stacked. The conductive metal layer is arranged between the protective metal layer and the substrate 10. The material of the protective metal layer is resistant to hydrofluoric acid corrosion and is used to protect the auxiliary cathode 21 from being corroded by the etching solution used in the hole opening process. In a specific embodiment, the material of the auxiliary cathode 21 is a laminated metal of MoTi / Cu / MoTi. The MoTi located at the top is a protective metal layer, the Cu located in the middle is a conductive metal layer, and the MoTi located at the bottom plays a blocking role. The thin film transistor layer 20 also includes a peripheral circuit terminal 22. The peripheral circuit terminal 22 is arranged in the same layer as the source SE and drain DE of the thin film transistor, but is located in the non-display area AA.

[0051] The passivation layer 30 covers the side of the thin film transistor layer 20 away from the substrate 10, and plays a role in protecting the thin film transistor layer 20. The passivation layer 30 includes a first passivation layer 31 and a second passivation layer 32, and the second passivation layer 32 is located on the side of the first passivation layer 31 away from the thin film transistor layer 20. A first through hole 31a is opened in the first passivation layer 31, and a second through hole 32a is opened in the second passivation layer 32. The first through hole 31a is connected to the second through hole 32a, and the first through hole 31a and the second through hole 32a constitute an undercut structure 30a. The depth of the undercut structure 30a is more than 0.2μm. The undercut structure 30a exposes the auxiliary cathode 21.

[0052] In order to form the undercut structure 30a in the passivation layer 30, when the first passivation layer 31 and the second passivation layer 32 are simultaneously etched using the same etching solution or etching gas, the etching speed of the first passivation layer 31 by the etching solution or etching gas is greater than the etching speed of the second passivation layer 32. Optionally, the material of the first passivation layer 31 includes silicon oxide, and the material of the second passivation layer 32 includes silicon nitride. The etching solution contains hydrofluoric acid. In a more specific embodiment, the first passivation layer 31 is composed of silicon oxide, and the second passivation layer 32 is composed of silicon nitride. The etching solution is hydrofluoric acid.

[0053] The flat layer 40 is disposed on the side of the passivation layer 30 away from the thin film transistor layer 20. The flat layer 40 is used to form a flat terrain, which is convenient for the subsequent formation of an organic light-emitting diode device above the thin film transistor layer 20. A third through hole 40a is provided in the flat layer 40, and the third through hole 40a is connected to the second through hole 32a. The first through hole 31a, the second through hole 32a and the third through hole 40a together constitute an auxiliary cathode connection hole VA. Optionally, the material of the flat layer 40 is an organic material, which can be specifically selected from one of acrylic resin, epoxy resin and perfluoroalkoxy resin (PFA).

[0054] The organic light-emitting layer 50 is arranged on the flat layer 40. The organic light-emitting layer 50 includes a plurality of organic light-emitting devices. Optionally, the plurality of organic light-emitting devices are arranged in a matrix. The organic light-emitting layer 50 includes an anode (Anode) 51, a pixel definition layer (Pixel Define Layer, PDL) 52, a hole injection layer (Hole Inject Layer, HIL) 53, a hole transfer layer (Hole Transfer Layer, HTL) 54, an emitting layer (Emitting Layer, EML) 55, an electron transfer layer (Electron Transfer Layer, ETL) 56, an electron injection layer (Electron Inject Layer, EIL) 57 and a cathode (Cathode) 58, which are stacked in sequence. Among them, the anode 51, the hole injection layer 53, the hole transfer layer 54, the emitting layer 55, the electron transfer layer 56, the electron injection layer 57 and the cathode 58 constitute an organic light-emitting device.

[0055] Please refer to Figure 2 From a top view, the organic light emitting diode display panel 100 includes a plurality of sub-pixels PX arranged in an array. Figure 2, a red sub-pixel PX1, a green sub-pixel PX2, and a blue sub-pixel PX3 are shown. The red sub-pixel PX1, the green sub-pixel PX2, and the blue sub-pixel PX3 are arranged along a first direction D1, and the red sub-pixel PX1, the green sub-pixel PX2, and the blue sub-pixel PX3 extend along a second direction D2 intersecting the first direction D1, respectively. Optionally, the first direction D1 is perpendicular to the second direction D2. Each sub-pixel PX can be divided into a light-emitting area LD and a non-light-emitting area NLD. The light-emitting area LD refers to an area where an organic light-emitting device is provided, and the non-light-emitting area NLD is an area other than the light-emitting area LD. The light-emitting area LD and the non-light-emitting area NLD are arranged in the second direction D2. The auxiliary cathode connection hole VA is provided in the non-light-emitting area NLD, or it can be said that the auxiliary cathode connection hole VA is located on one side of the organic light-emitting device in the second direction D2.

[0056] The organic light-emitting layer 50 includes a plurality of anodes 51 disposed on the planar layer 40. The plurality of anodes 51 are insulated and spaced apart from each other and disposed on the planar layer 40. Each anode 51 is connected to the drain electrode DE of a thin film transistor T through a first contact hole CH1 provided in the planar layer 40 and the passivation layer 30. The material of the anode 51 may include one or more of ITO (indium tin oxide), IZO (indium zinc oxide), Ag (silver), Pd (palladium), Cu (copper), Al (aluminum), Ni (nickel) and La (lanthanum). The anode 51 may be a single-layer structure, a double-layer structure or a three-layer structure. Optionally, the anode 51 is a stacked structure of ITO / Ag / ITO. In addition, the organic light-emitting diode display panel 100 also includes a terminal portion PAD. The terminal portion PAD is provided in the same layer as the anode 51, and is connected to the peripheral circuit terminal 22 through a second contact hole CH2 provided in the passivation layer 30.

[0057] The pixel definition layer 52 covers the plurality of anodes 51 and the planar layer 40. A plurality of openings 52a are provided in the pixel definition layer 52. The hole injection layer 53, the hole transport layer 54 and the light emitting layer 55 are sequentially stacked in each opening 52a. The electron transport layer 56, the electron injection layer 57 and the cathode 58 sequentially cover the light emitting layer 55 and the pixel definition layer 52.

[0058] The electron transport layer 56 and the electron injection layer 57 can both be referred to as electronic functional layers. Due to process reasons, when the electron transport layer 56 and the electron injection layer 57 are evaporated, the electron transport layer 56 and the electron injection layer 57 will enter the first through hole 31a and connect to the auxiliary cathode 21. However, the electron transport layer 56 and the electron injection layer 57 are not conductive, which will hinder the conduction between the cathode 58 and the auxiliary cathode 21. The present application forms a protruding structure by using the second passivation layer 32. During evaporation, the materials of the electron transport layer 56 and the electron injection layer 57 are shielded, thereby reserving a circle of space around the electron transport layer 56 and / or the electron injection layer 57 formed in the undercut structure 30a. When the cathode 58 is subsequently evaporated, due to the material properties of the cathode 58, it will extend along the side walls of the third through hole 40a, the second through hole 32a and the first through hole 31a, occupying the space reserved around the electron transport layer 56 and the electron injection layer 57 in the undercut structure 30a, thereby connecting to the auxiliary cathode 21. In other words, the electronic functional layer includes a first portion P1 and a second portion P2, the first portion P1 is located in the light emitting area LD, and the second portion P2 is located in the non-light emitting area NLD. Further, the first portion P1 is located on the side of the cathode 58 away from the passivation layer 30, and the second portion P2 is located on the auxiliary cathode 21 in the undercut structure 30a. Specifically, the cathode 58 is located between the second portion P2 and the sidewall of the undercut structure 30a, and is connected to the auxiliary cathode 21. In other words, the cathode 58 extends along the sidewall of the auxiliary cathode connection hole VA, occupies the space reserved around the electronic functional layer in the undercut structure 30a, and is connected to the auxiliary cathode 21. Optionally, the material of the cathode 58 can be selected from aluminum (Al), gold (Au), silver (Ag), etc.

[0059] The embodiment of the present application forms an undercut structure 30a in the passivation layer 30, thereby preventing the electronic functional layer from hindering the connection between the cathode 58 and the auxiliary cathode 21, improving the connection performance between the cathode 58 and the auxiliary cathode 21, reducing the voltage drop, and improving the display quality. In addition, in the present application, no additional film layer is required to make the undercut structure 30a, and the process is simple and the cost is low.

[0060] The present application also provides a method for manufacturing an organic light emitting diode display panel, which is used to manufacture the above-mentioned organic light emitting diode display panel. The method for manufacturing an organic light emitting diode display panel comprises the following steps:

[0061] providing a substrate;

[0062] A thin film transistor layer is formed on the substrate, wherein the thin film transistor layer includes a source electrode, a drain electrode and an auxiliary cathode, and the auxiliary cathode is arranged in the same layer as the source electrode and the drain electrode;

[0063] forming a passivation layer on the thin film transistor layer, wherein the passivation layer comprises a first passivation layer and a second passivation layer, wherein the second passivation layer is located on a side of the first passivation layer away from the thin film transistor layer;

[0064] Etching the first passivation layer and the second passivation layer with an etching solution to form an undercut structure, wherein the etching speed of the etching solution on the first passivation layer is greater than the etching speed of the second passivation layer, and the undercut structure exposes the auxiliary cathode; and

[0065] A cathode is formed on the passivation layer, and the cathode extends into the undercut structure and is connected to the auxiliary cathode.

[0066] The embodiments of the present application use two different materials to form a passivation layer, and then use etching solutions with different etching speeds for the two different materials to form an undercut structure in the passivation layer, which can prevent the electronic functional layer from hindering the connection between the cathode and the auxiliary cathode, improve the connection performance between the cathode and the auxiliary cathode, reduce the voltage drop, and improve the display quality. In addition, in the present application, there is no need to add an additional film layer to make the undercut structure, the process is simple, and the cost is low. Below, the manufacturing method of the organic light emitting diode display panel of the present application is described through two specific embodiments.

[0067] Referring to FIG. 3( a) to FIG. 3( k), a first embodiment of a method for manufacturing an organic light emitting diode display panel of the present application includes the following steps:

[0068] 101 : Please refer to FIG. 3( a ), a substrate 10 is provided, and a light shielding layer LS is formed on the substrate 10 .

[0069] Step 101 specifically includes: depositing a MiTi / Cu metal layer on the glass substrate 10 by physical vapor sputtering, and etching with H 2 O 2 to form a patterned light shielding layer LS.

[0070] 102: Please refer to FIG. 3(b) , a buffer layer BL is formed on the light shielding layer LS.

[0071] Step 102 specifically includes: depositing a buffer layer BL on the light shielding layer LS by chemical vapor deposition. The material of the buffer layer BL may be silicon oxide or silicon nitride.

[0072] 103: Please refer to Figure 3(b) to Figure 3(e) , a thin film transistor layer 20 is formed on the buffer layer BL.

[0073] Step 103 specifically includes:

[0074] 1031 : An active layer CL is formed on the buffer layer BL.

[0075] In step 1031, a semiconductor material layer is formed on the buffer layer BL by physical vapor sputtering deposition. The active layer CL pattern is formed by photolithography. The semiconductor material can be a metal oxide semiconductor such as ITO or IGZO or a silicon-based semiconductor. Optionally, the semiconductor material is IGZO, and the etchant can use an oxalic acid solution.

[0076] 1032 : Form a gate insulating layer GI and a gate GE on the active layer CL.

[0077] In step 1032, a gate insulating material layer and a first metal layer are deposited by chemical vapor deposition, and a gate insulating layer GI and a gate GE are formed by photolithography. After the photoresist is stripped, the IGZO is made conductive by plasma treatment with the gate GE as a shield.

[0078] 1033 : An interlayer insulating layer IL is formed on the gate electrode GE and the active layer CL.

[0079] In step 1033, an interlayer insulating layer IL is deposited by chemical vapor deposition, and holes are dug in the interlayer insulating layer IL and the buffer layer BL by two photolithography processes to form contact holes between the source electrode SE and the drain electrode DE and the active layer CL, and a contact hole between the drain electrode DE and the light shielding layer LS. The hole digging process can be performed by dry etching with an oxidizing gas such as F series.

[0080] 1034 : A source electrode SE, a drain electrode DE, an auxiliary cathode electrode 21 and a peripheral circuit terminal 22 are formed on the interlayer insulating layer IL.

[0081] In step 1034, a second metal layer may be deposited, and then patterned to form a source electrode SE, a drain electrode DE, and an auxiliary cathode 21. The auxiliary cathode 21 includes a stacked conductive metal layer and a protective metal layer, the conductive metal layer is disposed between the protective metal layer and the substrate 10, and the material of the protective metal layer is resistant to hydrofluoric acid corrosion.

[0082] In step 1034, a MoTi / Cu / MoTi metal layer is deposited by physical vapor deposition, and a source electrode SE, a drain electrode DE, an auxiliary cathode 21 and a peripheral circuit terminal 22 are formed by photolithography. The etching liquid used in the photolithography is a H2O2-based etching liquid.

[0083] 104: Please refer to Figure 3(e) to Figure 3(f) , forming a passivation layer 30 on the thin film transistor layer 20, wherein the passivation layer 30 includes a first passivation layer 31 and a second passivation layer 32, wherein the second passivation layer 32 is located on a side of the first passivation layer 31 away from the thin film transistor layer 20;

[0084] The first passivation layer 31 and the second passivation layer 32 are simultaneously etched by etching gas to form a first prefabricated hole PVA1 in the first passivation layer 31, the first prefabricated hole PVA1 penetrates the first passivation layer 31 and the second passivation layer 32 and exposes the auxiliary cathode 21, and forms a second prefabricated hole PVA2 above the thin film transistor layer 20 to expose the drain DE of the thin film transistor layer 20, and at the same time, forms a third prefabricated hole PVA3 above the peripheral circuit terminal 22 to expose the peripheral circuit terminal 22.

[0085] In step 104, a layer of silicon oxide and a layer of silicon nitride are deposited on the interlayer insulating layer IL, the source SE, the drain DE, the auxiliary cathode 21 and the peripheral circuit terminal 22 by chemical vapor deposition, a pattern of a passivation protection layer is formed by a photolithography process, and an oxidizing gas such as F series gas is used as a dry etchant; the preliminary etching is completed to obtain the first prefabricated hole PVA1.

[0086] 105: Please refer to Figure 3(f) to Figure 3(h) The first passivation layer 31 and the second passivation layer 32 are etched at the first prefabricated hole PVA1 using an etching solution to form an undercut structure 30 a . The etching speed of the etching solution on the first passivation layer 31 is greater than the etching speed of the second passivation layer 32 .

[0087] Optionally, the first passivation layer 31 includes silicon oxide, the second passivation layer 32 includes silicon nitride, the etching liquid is hydrofluoric acid, and the etching rate ratio of the etching liquid to silicon oxide and silicon nitride is greater than or equal to 10. Optionally, the first passivation layer 31 is silicon oxide, the second passivation layer 32 is silicon nitride, the etching liquid is hydrofluoric acid, and the etching rate ratio of the etching liquid to silicon oxide and silicon nitride is greater than or equal to 10. Since the auxiliary cathode 21 has a protective metal layer resistant to hydrofluoric acid corrosion, the auxiliary cathode 21 will not be damaged when etching the undercut structure 30a.

[0088] It can be understood that the passivation layer 30 can also be a stacked layer of SiN / SiO 2 / SiN, and the SiO 2 and the SiN thereon form an undercut structure 30 a.

[0089] On the basis of the first prefabricated hole PVA1, photolithography is performed to open the hole, and HF wet etching solution is used to etch the hole to complete the production of the undercut structure 30a. The PV film SiO2 / SiN etching rate ratio can be adjusted to more than 10.

[0090] 106: Referring to FIG. 3(g) and FIG. 3(h), a planar layer 40 is formed on the passivation layer 30, and the organic planar layer 40 in the non-display area NA is removed. A third through hole 40a is opened in the planar layer 40, and the third through hole 40a is connected to the second through hole 32a. The first through hole 31a, the second through hole 32a and the third through hole 40a together constitute the auxiliary cathode connection hole VA. At the same time, through holes are formed in the planar layer 40 above the second preformed hole PVA2 and the third preformed hole PVA3, respectively, to form the first contact hole CH1 and the second contact hole CH2.

[0091] 107 : Please refer to FIG. 3( h ) and FIG. 3( i ) , an anode 51 and a terminal portion PAD are formed on the planar layer 40 .

[0092] The anode 51 and the terminal portion PAD are formed by physical vapor deposition, exposure, development and wet etching. The anode 51 is connected to the drain electrode DE through the first contact hole CH1. The terminal portion PAD is connected to the peripheral circuit terminal 22 through the second contact hole CH2.

[0093] 108 : Please refer to FIG. 3 ( i ) and FIG. 3 ( j ), a pixel definition layer 52 is formed on the anode 51 , and a plurality of openings 52 a are formed in the pixel definition layer 52 .

[0094] 109: Please refer to Figure 3(j) and Figure 3(k). A hole injection layer 53, a hole transport layer 54, and a light-emitting layer 55 are formed in the opening 52a of the pixel definition layer 52, and an electron transport layer 56 and an electron injection layer 57 are formed by vapor deposition on the pixel definition layer 52 and the light-emitting layer 55.

[0095] In step 109, the first portion P1 of the electron transport layer 56 and the electron injection layer 57 is located on the side of the anode 51 away from the passivation layer 30 and above the thin film transistor T, and the second portion P2 is located on the auxiliary cathode 21 in the undercut structure 30a. Since a protruding structure is formed by the second passivation layer 32, the materials of the electron transport layer 56 and the electron injection layer 57 are shielded during evaporation, thereby reserving a circle of space around the electron transport layer 56 and / or the electron injection layer 57 formed in the undercut structure 30a.

[0096] 110 : Please refer to FIG. 3 ( l ), ​​a cathode 58 is formed on the electron injection layer 57 , and the cathode 58 extends into the undercut structure 30 a and is connected to the auxiliary cathode 21 .

[0097] In step 110, the cathode 58 is formed by sputtering deposition. When the cathode 58 is evaporated, due to the material properties of the cathode 58, it will extend along the side walls of the third through hole 40a, the second through hole 32a and the first through hole 31a, occupying the space reserved around the electron transport layer 56 and the electron injection layer 57 in the bottom cut structure 30a, thereby connecting with the auxiliary cathode 21.

[0098] In this embodiment, an undercut structure 30 a is formed in the passivation layer 30 by using etching solutions with different etching speeds for two different materials, and then a flat layer 40 is formed, and the process is simple.

[0099] Referring to FIG. 4( a) to FIG. 4( m), a second embodiment of a method for manufacturing an organic light emitting diode display panel of the present application includes the following steps:

[0100] 201 : Please refer to FIG. 4( a ), a substrate 10 is provided, and a light shielding layer LS is formed on the substrate 10 .

[0101] Step 201 specifically includes: depositing a light-shielding metal layer on the glass substrate 10 by physical vapor sputtering, and then depositing a diffusion barrier layer and an etching barrier layer on the light-shielding metal layer by PVD, and forming a patterned light-shielding layer LS by photolithography. The material of the light-shielding metal layer can be a stack of Mo / Cu. The material of the diffusion barrier layer can be a material with a work function similar to that of Cu, such as MoTi, Mo, and Ta. The material of the etching barrier layer can be a metal oxide such as ITO and IGZO. The light-shielding metal layer and the diffusion barrier layer can use H2O2-based solution as an etchant, and the etching barrier layer can use oxalic acid-based solution as an etchant.

[0102] 202: Please refer to Figure 4(a) to Figure 4(b) , a buffer layer BL is formed on the light shielding layer LS.

[0103] Step 202 specifically includes: depositing a buffer layer BL on the light shielding layer LS by chemical vapor deposition. The buffer layer BL can be silicon oxide or silicon nitride. When the etching stop layer is IGZO, plasma treatment is also required to conduct the etching stop layer to ensure that the subsequent charge transfer between the source and the light shielding layer LS is mutual and the threshold voltage Vth is compensated.

[0104] 203: Please refer to Figure 4(b) to Figure 4(e) , a thin film transistor layer 20 is formed on the buffer layer BL.

[0105] Step 203 specifically includes:

[0106] 2031 : An active layer CL is formed on the buffer layer BL.

[0107] In step 2031, a semiconductor material layer is formed on the buffer layer BL by physical vapor sputtering deposition. The active layer CL pattern is formed by photolithography. The semiconductor material can be a metal oxide semiconductor such as ITO or IGZO or a silicon-based semiconductor. Optionally, the semiconductor material is IGZO, and the etchant can use an oxalic acid solution.

[0108] 2032: Form a gate insulating layer GI and a gate GE on the active layer CL.

[0109] In step 2032, a gate insulating material layer and a first metal layer are deposited by chemical vapor deposition, and a gate insulating layer GI and a gate GE are formed by photolithography. After the photoresist is stripped, the IGZO is made conductive by plasma treatment with the gate as a shield.

[0110] 2033: An interlayer insulating layer IL is formed on the gate electrode and the active layer CL.

[0111] In step 2033, the interlayer insulating layer IL is deposited by chemical vapor deposition, and holes are dug in the interlayer insulating layer IL and the buffer layer BL by two photolithography processes to form contact holes between the source electrode SE and the drain electrode DE and the active layer CL, and a contact hole between the drain electrode DE and the light shielding layer LS. The hole digging process can be performed by dry etching with an oxidizing gas such as F series.

[0112] 2034: A source electrode SE, a drain electrode DE, an auxiliary cathode electrode 21 and a peripheral circuit terminal 22 are formed on the interlayer insulating layer IL.

[0113] In step 2034, a second metal layer may be deposited, and then patterned to form a source electrode SE, a drain electrode DE, an auxiliary cathode 21, and a peripheral circuit terminal 22. The auxiliary cathode 21 includes a stacked conductive metal layer and a protective metal layer, the conductive metal layer is disposed between the protective metal layer and the substrate 10, and the material of the protective metal layer is resistant to hydrofluoric acid corrosion.

[0114] In step 2034, a MoTi / Cu / MoTi metal layer is deposited by physical vapor deposition, and a SE, a drain DE, an auxiliary cathode 21 and a peripheral circuit terminal 22 are formed by photolithography. The etching solution used in the photolithography is a H2O2-based etching solution.

[0115] 204: Please refer to Figure 4(e) and Figure 4(f), a passivation layer 30 is formed on the thin film transistor layer 20, the passivation layer 30 includes a first passivation layer 31 and a second passivation layer 32, and the second passivation layer 32 is located on the side of the first passivation layer 31 away from the thin film transistor layer 20.

[0116] 205 : forming a planarization layer 40 on the passivation layer 30 .

[0117] 206: The planar layer 40 is patterned using a half-tone mask, the organic planar layer 40 in the non-display area is removed, and a third through hole 40a, a first blind hole BH1 (semi-open hole) and a second blind hole BH2 (semi-open hole) are formed in the planar layer 40. The third through hole 40a corresponds to the auxiliary electrode, and the first blind hole BH1 corresponds to the drain DE of the thin film transistor T. The second blind hole BH2 corresponds to the peripheral circuit terminal 22. 0.2 μm to 1 μm of organic photoresist is retained in the first blind hole BH1 and the second blind hole BH2 to prevent the source electrode from being etched when the undercut structure 30a is subsequently etched.

[0118] 207: Referring to FIG. 4(f) and FIG. 4(g), the first passivation layer 31 and the second passivation layer 32 are etched at the third through hole 40a using an etching solution to form a first through hole 31a in the first passivation layer 31 and a second through hole 32a in the second passivation layer 32. The first through hole 31a is connected to the second through hole 32a to form an undercut structure 30a. The etching speed of the etching solution on the first passivation layer 31 is greater than the etching speed of the second passivation layer 32.

[0119] Optionally, the first passivation layer 31 includes silicon oxide, the second passivation layer 32 includes silicon nitride, the etching liquid is hydrofluoric acid, and the etching rate ratio of the etching liquid to silicon oxide and silicon nitride is greater than or equal to 10. Optionally, the first passivation layer 31 is silicon oxide, the second passivation layer 32 is silicon nitride, the etching liquid is hydrofluoric acid, and the etching rate ratio of the etching liquid to silicon oxide and silicon nitride is greater than or equal to 10. Since the auxiliary cathode 21 has a protective metal layer resistant to hydrofluoric acid corrosion, the auxiliary cathode 21 will not be damaged when etching the undercut structure 30a.

[0120] 208: Please refer to FIG. 4(g) and FIG. 4(h), dry etching is performed on the first blind hole BH1, so that the first blind hole BH1 forms the fourth through hole TH1, and the second blind hole BH2 forms the fifth through hole TH2.

[0121] In step 208 , the first blind hole BH1 and the second blind hole BH2 are completely opened by using O 2 through a dry etching process, thereby completing the opening of the planar layer 40 on the passivation layer 30 .

[0122] 209 : Referring to FIG. 4( h ) and FIG. 4( i ), the first passivation layer 31 and the second passivation layer 32 are etched at the fourth through hole TH1 and the fifth through hole TH2 to form a first contact hole CH1 and a second contact hole CH2 , respectively.

[0123] In step 209 , a dry etching process is used to open holes in the passivation layer 30 .

[0124] 210 : Referring to FIG. 4( i ) and FIG. 4( j ), an anode 51 and a terminal portion PAD are formed on the planar layer 40 .

[0125] The anode 51 and the terminal portion PAD are formed by physical vapor deposition, exposure, development and wet etching. The anode 51 is connected to the drain electrode DE through the first contact hole CH1. The terminal portion PAD is connected to the peripheral circuit terminal 22 through the second contact hole CH2.

[0126] 211 : Please refer to FIG. 4( j ) and FIG. 4( k ), a pixel definition layer 52 is formed on the anode 51 , and a plurality of openings 52 a are formed in the pixel definition layer 52 .

[0127] 212: Please refer to Figure 4(k) and Figure 4(l), a hole injection layer 53, a hole transport layer 54, and a light-emitting layer 55 are formed in the opening 52a of the pixel definition layer 52, and an electron transport layer 56 and an electron injection layer 57 are evaporated on the pixel definition layer 52 and the light-emitting layer 55.

[0128] In step 212, the first portion P1 of the electron transport layer 56 and the electron injection layer 57 is located on the side of the anode 51 away from the passivation layer 30 and above the thin film transistor T, and the second portion P2 is located on the auxiliary cathode 21 in the undercut structure 30a. Since a protruding structure is formed by the second passivation layer 32, the materials of the electron transport layer 56 and the electron injection layer 57 are shielded during evaporation, thereby reserving a circle of space around the electron transport layer 56 and / or the electron injection layer 57 formed in the undercut structure 30a.

[0129] 213 : Please refer to FIG. 4 ( l ) and FIG. 4 ( m ), a cathode 58 is formed on the electron injection layer 57 , and the cathode 58 extends into the undercut structure 30 a and is connected to the auxiliary cathode 21 .

[0130] In step 213, the cathode 58 is formed by sputtering deposition. When the cathode is evaporated, due to the material properties of the cathode 58, it will extend along the side walls of the third through hole 40a, the second through hole 32a and the first through hole 31a, occupying the space reserved around the electron transport layer 56 and the electron injection layer 57 in the bottom cut structure 30a, thereby connecting with the auxiliary cathode 21.

[0131] In this embodiment, a through hole is formed in the planar layer 40 using a half-tone mask, and then the passivation layer 30 is etched to form an undercut structure 30 a. The half-tone mask has high precision, and the depth and width of the formed undercut structure 30 a are easier to control.

[0132] The above provides a detailed introduction to the implementation methods of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The above description of the implementation methods is only used to help understand the present application. At the same time, for those skilled in the art, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A method for manufacturing an organic light emitting diode display panel, characterized in that: The following steps are involved: providing a substrate; forming a thin film transistor layer on the substrate, wherein the thin film transistor layer comprises a source electrode, a drain electrode and an auxiliary cathode, and the auxiliary cathode is arranged in the same layer as the source electrode and the drain electrode; forming a passivation layer on the thin film transistor layer, wherein the passivation layer comprises a first passivation layer and a second passivation layer, wherein the second passivation layer is located on a side of the first passivation layer away from the thin film transistor layer; Using an etching solution to etch the first passivation layer and the second passivation layer to form an undercut structure, wherein the etching speed of the etching solution on the first passivation layer is greater than the etching speed of the second passivation layer, and the undercut structure exposes the auxiliary cathode; as well as forming a cathode on the passivation layer, wherein the cathode extends into the undercut structure and is connected to the auxiliary cathode; Among them, after forming the passivation layer on the thin film transistor layer, before etching the first passivation layer and the second passivation layer with the etching liquid, it also includes: forming a flat layer on the passivation layer; and patterning the flat layer with a half-tone mask to form a third through hole and a first blind hole in the flat layer; etching the first passivation layer and the second passivation layer with the etching liquid includes: etching the first passivation layer and the second passivation layer at the third through hole; after etching the first passivation layer and the second passivation layer with the etching liquid, it also includes: performing dry etching at the first blind hole to form a through hole through the first blind hole; etching the first passivation layer and the second passivation layer at the through hole to form a contact hole to expose the source of the thin film transistor layer.

2. The method for manufacturing an organic light emitting diode display panel according to claim 1, wherein: The first passivation layer includes silicon oxide, the second passivation layer includes silicon nitride, the etching solution is hydrofluoric acid, and the etching rate ratio of the etching solution to silicon oxide and silicon nitride is greater than or equal to 10.

3. An organic light emitting diode display panel, characterized in that: The organic light emitting diode display panel is prepared by the manufacturing method of any one of claims 1 to 2, wherein the organic light emitting diode display panel comprises: substrate; A thin film transistor layer, disposed on the substrate, the thin film transistor layer comprising a source electrode, a drain electrode and an auxiliary cathode, the auxiliary cathode being disposed in the same layer as the source electrode and the drain electrode; a passivation layer covering a side of the thin film transistor layer away from the substrate; and A cathode, disposed on a side of the passivation layer away from the thin film transistor layer; Wherein, the passivation layer includes a first passivation layer and a second passivation layer, the second passivation layer is located on the side of the first passivation layer away from the thin film transistor layer, a first through hole is opened in the first passivation layer, a second through hole is opened in the second passivation layer, the first through hole is connected to the second through hole, the first through hole and the second through hole constitute an undercut structure, the undercut structure exposes the auxiliary cathode, and the cathode extends into the undercut structure and is connected to the auxiliary cathode.

4. The organic light emitting diode display panel according to claim 3, wherein: The material of the first passivation layer includes silicon oxide, and the material of the second passivation layer includes silicon nitride.

5. The organic light emitting diode display panel according to claim 3, wherein: The cathode is located on the sidewall of the undercut structure and is connected to the auxiliary cathode.

6. The organic light emitting diode display panel according to claim 5, wherein: The organic light emitting diode display panel also includes an electronic functional layer, which is arranged on a side of the cathode close to the passivation layer, a portion of the electronic functional layer is located on the auxiliary cathode in the undercut structure, and the cathode is located between a portion of the electronic functional layer and a side wall of the undercut structure.

7. The organic light emitting diode display panel according to claim 3, wherein: The auxiliary cathode comprises a conductive metal layer and a protective metal layer which are stacked, wherein the conductive metal layer is arranged between the protective metal layer and the substrate, and the material of the protective metal layer is resistant to hydrofluoric acid corrosion.

8. The organic light emitting diode display panel according to claim 3, wherein: The organic light emitting diode display panel also includes a planar layer, which is arranged on a side of the passivation layer away from the thin film transistor layer. A third through hole is opened in the planar layer, and the third through hole is connected to the second through hole. The cathode extends from the third through hole into the undercut structure.

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