A digital output non-cooled infrared readout device based on phase-locked loop

Abstract

The application provides a non-cooled infrared readout device based on a phase-locked loop, comprising: a phase-locked loop and a timing module, which divides and multiplies an input clock, and generates driving timing signals required by each module; a front-end module of a mirror image detector, which is used for generating a sensing current based on the photosensitive pixels and reference pixels; a column-level transimpedance amplifier module; a sample-and-hold module; a voltage comparison module, which comprises a slope signal generation module and a comparator module; a counter module, which synchronously counts when the slope signal linearly changes; an in-column storage module, which, when the step voltage flips, latches the count of the counter module at the time and then outputs to a data bus. By embedding an analog-to-digital converter in the readout circuit, the difficulty and cost of use of the user and the volume of the product are reduced, and at the same time, the working frequency of the input and output ports of the detector based on the phase-locked loop timing circuit can also be reduced, further reducing the power consumption and difficulty of use of the product.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of infrared imaging, in particular to a digital output non-cooled infrared readout device based on a phase-locked loop. BACKGROUND

[0002] At present, non-cooled infrared imaging technology has important applications in the fields of military, industry and agriculture, medicine, astronomy, etc. As the core of non-cooled infrared imaging technology, infrared focal plane array includes two parts: infrared detector array and readout circuit. Among them, microbolometer focal plane array (FPA) has higher sensitivity and is the most widely used non-cooled infrared focal plane array. Its working principle is that the thermal sensitive material changes its temperature after absorbing the incident infrared radiation, thereby causing the change of its own resistance value, and the size of the infrared radiation signal is detected by measuring the change of its resistance value.

[0003] Microbolometer generally adopts a cantilever beam micro-bridge structure made by micro-machining technology. The bridge surface is deposited with a layer of thermal sensitive material with high temperature coefficient of resistance (TCR), and the bridge surface is supported by two bridge legs with good mechanical properties and plated with conductive material. The contact point of the bridge leg and the substrate is the bridge pier, which is electrically connected to the silicon readout circuit (ROIC) below the microbolometer. Through the bridge leg and the bridge pier, the thermal sensitive material is connected to the electrical channel of the readout circuit, forming a pixel unit sensitive to temperature and connected to the readout circuit, which is simply called pixel. The sensitive pixel is also called sensitive microbolometer, and there are two kinds of blind pixels corresponding to it. One kind of bridge surface is in thermal short circuit with the substrate, and the temperature is constant equal to the substrate temperature, which is called thermal short circuit pixel. The other kind is the same structure as the sensitive microbolometer, but is blocked, so it cannot sense the target radiation, which is called blocked pixel. The use of these two kinds of blind micro-pixels can effectively offset the output voltage fluctuation of the sensitive pixel resistance with the change of the substrate temperature, realizing the function of TEC (thermoelectric cooler) free.

[0004] The function of the readout circuit is to process (such as filtering and amplifying) and read out the response signal of the sensitive pixel, and to correct the non-uniformity of the pixel resistance. The quality of signal processing, the quality of non-uniformity correction and the noise of the readout circuit itself will have a significant impact on the performance of the infrared imaging system. The traditional readout circuit adopts analog output. Because the infrared signal is very weak and the video data volume is very large, users need to use high-speed and high-precision analog-to-digital converter (ADC) and its driving circuit on hardware. ADC generally requires bit number not less than 14, clock frequency up to 300MHz, and sampling rate up to 20M samples per second. This not only increases the noise and power consumption, making it difficult for users to use, but also seriously increases the volume and cost of the product. Therefore, non-cooled infrared readout circuit with digital output has gradually become the mainstream. SUMMARY

[0005] The following presents a simplified summary of the application in order to provide a basic understanding of some aspects of the application. This summary is not an extensive overview of the application. It is not intended to identify key or critical elements of the application or to delineate the scope of the application. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

[0006] The technical problem solved by the present application is to provide a readout device of a non-cooled infrared detector based on a phase-locked loop (PLL), which embeds an analog-to-digital converter in a readout circuit, reduces the use difficulty and use cost of a user, and reduces the volume of a product. Meanwhile, the timing circuit based on the phase-locked loop can also reduce the working frequency of an input and output port of the detector, and further reduce the power consumption and use difficulty of the product.

[0007] The present application provides a readout device of a non-cooled infrared detector based on a phase-locked loop, comprising: a phase-locked loop and timing module, which receives a clock input, divides and multiplies the input clock, and generates driving timing signals required by each module; a mirror detector front-end module, which is divided into two columns, one column is a row-by-row selected photosensitive pixel, and the other column is a row-by-row selected reference pixel, both of which have the same circuit architecture and working timing, wherein the mirror detector front-end module is used to generate a sensing current based on the photosensitive pixel and the reference pixel; a column-level transimpedance amplifier module, which amplifies and filters the sensing current and converts it into a sensing voltage; a sample and hold module, which holds the sensing voltage as a holding voltage; a voltage comparison module, which comprises a slope signal generation module and a comparator module, wherein the slope signal generation module is used to generate a slope signal, the comparator module is used to compare the size of the slope signal and the holding voltage, and output a step voltage; a counter module, which synchronously counts when the slope signal linearly changes; an in-column storage module, which latches the count of the counter module at the time when the step voltage flips and then outputs to a data bus.

[0008] In one embodiment, the device further comprises: an output driver module, which is used to convert the parallel data bus into serial data through a tri-state gate and output to outside the chip.

[0009] In another embodiment, the phase-locked loop and timing module comprises: a first divider module for generating a D1 divided clock of the input clock based on the input clock; a second divider module having an input connected to the output clock and outputting a D2 divided clock to a phase difference conversion module; the phase difference conversion module comprising a phase-frequency detector module and a charge pump module for receiving the D1 divided clock and the D2 divided clock and generating a current related to a phase difference between the two clocks based on the D1 divided clock and the D2 divided clock; a loop low-pass filter module for generating a voltage related to the phase difference between the two clocks based on the current related to the phase difference between the two clocks and controlling a voltage-controlled oscillator module to generate the output clock.

[0010] In yet another embodiment, the mirror-like detector front-end module comprises a common mirror channel and a readout channel and a digital-to-analog converter module; the readout channel and the mirror channel each comprise M photosensitive pixels, a thermal shorting pixel, a first saturable tube and a second saturable tube, or a combination thereof; the common end of the thermal shorting pixel in the readout channel and the mirror channel is a voltage V s1 , and the common end of the photosensitive pixels is a voltage V s2 ; each photosensitive pixel in the readout channel is connected to the source end of the first saturable tube through a selection switch, the gate end of the saturable tube is driven by the gate voltage of the first saturable tube of the mirror channel through a buffer, the drain end is the output end, and is connected to the source end of the second saturable tube of the readout channel, and the drain end of the second saturable tube of the readout channel is connected to the thermal shorting pixel of the readout channel; each photosensitive pixel in the mirror channel is connected to the source end of the first saturable tube through a selection switch, the gate end of the saturable tube is driven by the gate end of the first saturable tube of the readout channel based on the gate voltage through a buffer, the drain end is the output end, and is connected to the source end of the second saturable tube of the mirror channel, and the drain end of the second saturable tube of the mirror channel is connected to the thermal shorting pixel of the mirror channel; the digital-to-analog converter module is used to generate voltages V gch1 and V gm1 based on the current difference between the first saturable tube and the second saturable tube of the readout channel, respectively, for controlling the gate end of the second saturable tube of the readout channel and the gate end of the second saturable tube of the mirror channel.

[0011] In still another embodiment, the volume of the first saturable tube and the second saturable tube in the mirror channel is K times the volume of the first saturable tube and the second saturable tube in the readout channel.

[0012] In still another embodiment, the thermal shorting pixel comprises one or a combination of a plurality of series resistors, a plurality of parallel resistors or a plurality of series-parallel resistors.

[0013] In another embodiment, the thermal short-circuiting pixel in the mirror channel further comprises L saturated tubes, L resistors and L switches, wherein one end of each resistor is connected to the source terminal of one saturated tube, the other end of each resistor is connected to a common terminal with voltage V s1 , the drain terminal of each saturated tube is connected to one switch and to the gate terminal of the first saturated tube in the mirror channel, and the gate terminal of each saturated tube is connected to a common terminal with voltage V gm1 .

[0014] In another embodiment, the voltage comparison module further comprises an in-column buffer module, which is configured to receive the hold voltage and the ramp signal respectively, and input the hold voltage and the ramp signal into the comparator.

[0015] The technical solution provided in the present application reduces the use difficulty and cost of users and the volume of products by embedding an analog-to-digital converter in a readout circuit. Meanwhile, the phase-locked loop-based timing circuit can also reduce the working frequency of the input and output ports of the detector, further reducing the power consumption and use difficulty of the product. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to further illustrate the above and other advantages and features of the present application, specific embodiments thereof are set forth with reference to the attached drawings. These drawings show by way of illustration, not of limitation, certain embodiments of the present application. Like reference numbers in the various drawings indicate like elements. It should be noted that the figures are not necessarily drawn to scale. It should be understood that these drawings are merely schematic and are not drawn to scale. It should be understood that the present application is not limited to the embodiments illustrated in the figures.

[0017] Figure 1 A block diagram of a phase-locked loop-based digital output readout circuit according to an embodiment of the present application is schematically shown;

[0018] Figure 2 A timing diagram of a 14-bit single-ramp analog-to-digital converter according to an embodiment of the present application is schematically shown;

[0019] Figure 3 A circuit diagram of an example phase-locked loop according to an embodiment of the present application is schematically shown;

[0020] Figure 4 Circuit diagrams of two example mirror-type detector front-end circuits according to an embodiment of the present application are schematically shown;

[0021] Figure 5 Circuit diagrams of four example circuits for reducing pixel resistance noise according to an embodiment of the present application are schematically shown;

[0022] Figure 6A circuit diagram of a redundant selection scheme of two hot shorting pixels according to an embodiment of the present application is shown schematically;

[0023] Figure 7 An example circuit diagram of four in-column buffers according to an embodiment of the present application is shown schematically;

[0024] Figure 8 An example circuit diagram of six in-column comparators according to an embodiment of the present application is shown schematically;

[0025] Figure 9 An example circuit diagram of an output driver according to an embodiment of the present application is shown schematically. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present application will be described hereinafter with reference to the accompanying drawings. In the description, specific

[0027] As described in the foregoing section of background art, the present application provides a readout device for a non-cooled infrared detector based on a phase-locked loop, which embeds an analog-to-digital converter in the readout circuit, thereby reducing the difficulty and cost of use for the user and the volume of the product. At the same time, the timing circuit based on the phase-locked loop can also reduce the working frequency of the input and output ports of the detector, further reducing the power consumption and difficulty of use of the product.

[0028] The present application will be described in detail below with reference to the accompanying drawings. Figures 1-9 The embodiments of the present application will be described in detail.

[0029] Figure 1 is a block diagram of a digital output readout circuit based on a phase-locked loop. Figure 1The readout circuit mainly includes eight parts, namely, a phase-locked loop (PLL) and timing module 101, a mirror detector front-end module 102 (hereinafter referred to as a mirror module), a column-level trans-impedance amplifier module 103, a sample-and-hold module 104, a voltage comparison module 105, a counter module 106, a column memory module 107, and an output driver module 108. The input signals of the phase-locked loop are a clock CLK, a frame synchronization signal FS, and a reset signal RST, and the output signals generated are a same-frequency and same-phase signal CLKbuf of CLK, a divided frequency signal CLK1 of CLK, and a multiplied frequency signal CLKout of CLK. The CLKbuf, CLK1, and CLKout control the working timing of the entire readout circuit through a control timing circuit, ensuring the synchronization between the signals of each module. The input voltage signals of the mirror module 102 are Vs1, Vs2, and Vg1, which provide a bias voltage for the light-sensing pixels and generate a sensing current Ipix. The column-level trans-impedance amplifier module 103 (ColAmp) amplifies and filters the sensing current Ipix and converts it into a sensing voltage Vint. The sample-and-hold module 104 (Sample / Hold) samples and saves the received sensing voltage Vint to a holding capacitor to become a holding voltage Vsh, which can effectively ensure that the sensing voltage is kept at a constant value during the readout circuit process, and will not fluctuate to affect the output result of the readout circuit. The voltage comparison module 105 includes a ramp signal generation module 1051 (RampGen), a column buffer module 1052 (ColBuf), and a comparator module 1053 (COMP). The voltage comparison circuit compares the holding voltage Vsh and the ramp signal Ramp, and outputs a step voltage Vstep used to control the writing of the column memory (ColMemory), wherein the ramp signal Ramp is used as the reference voltage of the holding voltage Vsh to determine the value of the holding voltage Vsh. When the output step voltage Vstep flips, the memory module 107 saves the encoding of the n-bit counter module 106 (counter) at that time and outputs to the data bus Vbus[n-1:0]. For a non-cooled infrared readout circuit, the number of counter bits n is greater than or equal to 14. The input clock of the counter module 106 is the output CLKout of the phase-locked loop, and the reset signal rstRamp is the same as the timing of the ramp generation circuit. The output driver module 108 (OutputDriver) converts the parallel data bus Vbus[n-1:0] into serial data Dout[p-1:0] through a tri-state gate and outputs to the outside of the chip.

[0030] In combination Figure 2For example, the 14-bit ADC is taken as an example, the single slope ADC timing diagram is used to explain the working principle of the single slope ADC. The clock of the ADC is CLKout, when the reset signal rstRamp is valid, the counter is reset to 0, and the ramp signal is reset to the reset voltage Vrst. After the reset, the counter starts counting, and at the same time, the ramp signal Ramp starts to change linearly (monotonically increases in the figure). The output Vstep of the comparator is high. When Ramp is higher than the hold voltage Vsh, Vstep flips to low. Assuming that the comparator output is encoded as i at this time, the memory Latch will latch the encoding i. The higher the hold voltage Vsh, the larger the latched counter encoding i, and the quantization process is realized. Specifically, the 384x288 array infrared focal plane array readout circuit is taken as an example to specifically describe the present application, but not to limit the scope of the present application. As in the timing diagram of Figure 2 For the 384x288 array detector, 50Hz working, one line time can be set to 68us, and the quantization time (the time when the counter and RAMP work) is set to 64us, then the period of the 14-bit ADC clock CLKout is 3.9ns, and the frequency is 256MHz. Assuming that the range of the ramp signal Ramp is 0.5V to 4.596V, then the step size VLSB of the ADC is 0.25mV. Therefore, if the hold voltage Vsh is 0.5V, the comparator output Vstep flips just after the reset, and the corresponding encoding is 0. If the hold voltage Vsh is 2.548V, then the corresponding encoding is 8192, and the comparator flips at 32us after the reset. If the hold voltage Vsh is 3V, then the corresponding encoding is 10000. That is, the larger Vsh, the larger the output encoding.

[0031] Figure 3is an example of a phase-locked loop. The input clock CLK is buffered to get CLKbuf. The input clock CLK, frame sync FS and reset signal RST are input to a first divider module 301 (Divl) to generate a Dl divided clock CLKl of CLK. CLKl and the output CLKfb of a second divider module 302 (Div2) are input to a phase difference conversion module 303, which includes a phase frequency detector (PFD) and a charge pump (CP) to generate a current Icp related to the phase difference of the two clocks. The current Icp is input to a loop low pass filter module 304 (LPF) to generate a voltage Vctrl, which controls a voltage controlled oscillator VCO to generate an output clock CLKout. The second divider module 302 (Div2) divides CLKout to generate CLKfb. Thus, the frequency of CLKout is D2 / Dl times of CLK. Through the phase-locked loop, the readout circuit generates three clocks CLKout, CLKbuf and CLKl synchronized with the input signals CLK, FS and RST. The working state of each module is controlled by a timing circuit. Since the frequency of CLKout is as high as 256MHz, it is difficult for users to use. The input clock CLK is first divided by 8 to get CLKl, and CLKl is then multiplied by 64 to get CLKout. Thus, the frequency of the input clock CLK is only 32MHz, which reduces the noise caused by the clock and improves the usability and stability of the product.

[0032] Figure 4 are example circuit diagrams of two kinds of mirror modules. Suppose the circuit contains M rows and N columns of light sensing pixels. The mirror circuit includes two columns, one of which is a mirror column shared by the whole circuit, and the other of which is a readout channel. Each readout channel contains M light sensing pixels Rs[M-1:0], one hot short pixel Rd, and one saturable tube Ml and M2. The common terminal of the hot short pixel is Vs1, and the common terminal of the light sensing pixels is voltage Vs2. As shown in Figure 4(a) As shown in the first example, each row of pixels Rs[i] is connected to the source terminal of saturable tube Ml through selection switch sw[i]. The gate terminal of Ml is driven by the gate voltage of saturable tube Mm1 through buffer buf1, and the drain terminal is the output terminal, which is connected to the drain terminal of saturable tube M2. The current of Ml and M2 is subtracted to obtain the induced current Ipix. The external voltage Vgl is converted into voltage Vgch1 and Vgm1 by digital-to-analog converter module 401 (DAC) to control the gate terminal of saturable tube M2 and the gate terminal of mirror column saturable tube Mm2, respectively. The drain terminal of saturable tube M2 is connected to thermal shorting pixel Rd, and the other end of Rd is connected to common terminal Vs1. The main feature of the mirror circuit provided by the present application is that the mirror column and the readout channel are completely matched, and the working timing is completely the same. Therefore, the mirror column contains M blocked pixels Rsm[M-1:0], and the common terminal is also Vs2. Each row of Rsm[i] is connected to the source terminal of saturable tube Mm1 through selection switch sw[i]. The gate terminal of saturable tube Mm1 is shorted with the drain terminal and connected to the drain terminal of saturable tube Mm2. The source terminal of saturable tube Mm2 is connected to thermal shorting pixel Rdm, and the other end of Rdm is connected to common terminal Vs1. The size ratio of the mirror column to the readout channel is K:1, that is, the volume of Rsm[i] is K times that of Rs[i], the volume of Rdm is K times that of Rd, and the volume of Mm1 and Mm2 is K times that of Ml and M2. The value of K is generally 1 to 80. The larger K is, the lower the noise contributed by the mirror column is. In order to simplify the manufacturing process, Rsm can also be a thermal shorting pixel. As shown in Figure 4 (b) As shown in the second example, the mirror column and the readout channel are still completely matched, and the working timing is also completely the same. However, the photosensitive pixel Rs and the mirror column pixel Rsm both adopt the "shared pier" connection mode of first and last connection. For this purpose, both of them are increased with switches en[M-1:0]. It should be noted that the pixel can also adopt other connection modes, as long as the mirror column and the readout channel are completely matched, and the working timing is completely the same, then the mirror circuit architecture belongs to the scope of the present patent.

[0033] Figure 5 (a) - (d) shown are four circuit examples for reducing the resistance noise of the pixel, including but not limited to being applied to Rd resistance and Rdm resistance. The pixel resistance mainly includes thermal noise and flicker noise. In order to reduce the resistance noise of the pixel, but without affecting the normal operation of the circuit, it is necessary to increase the resistance volume and keep the resistance unchanged. The solution is to connect multiple resistances in series and parallel, such as two in parallel and two in series, three in parallel and three in series, four in parallel and four in series. Figure 5 As shown, m 2 resistances can be used for m parallel and m series, such as two in parallel and two in series, three in parallel and three in series, four in parallel and four in series. 2 In addition, j resistances can be selected from m 2 resistances for k parallel and k series, so there are m 2 -j+j*k m2u resistances, such as(d) shown. It is to be noted that the resistors can be connected in other ways, as long as they are arranged in the above-mentioned combination, and they all belong to the scope of the present patent.

[0034] Figure 6 is an example circuit diagram of the redundant selection scheme of two Rdm, which is also applicable to other pixel resistors. The volume of the saturation tube Mm2 and the thermal short resistor Rdm is K times that of the saturation tube M2 and the thermal short resistor Rd in the readout channel. In the redundant selection scheme of two Rdm, the circuit contains L (L≥K) saturation tubes M m2u [L-1:0] and L resistors R dmu [L-1:0]. Each M m2u and R dmu has the same volume as M2 and Rd or several times the volume of M2 and Rd. As shown in Figure 6 (a), in the first scheme, each saturation tube M m2u [j] and R dmu [j] is connected to the gate of the saturation tube Mm1 through the switch S1[j], and the control signals of the switches S1[L-1:1] are generated by the decoder module 601 (DEC). As shown in Figure 6 (b), in the second scheme, each saturation tube M m2u [j] and R dmu [j] is still connected to the gate of the saturation tube Mm1 through the switch S1[j]. However, at the same time, M m2u [j] and R dmu [j] are also connected to the voltage Vs5 through the switch controlled by the inverse signal SN1[j] of S1[j], and the control signals of the switches S1[L-1:0] and SN1[L-1:0] are generated by the decoder (DEC). Therefore, when a failure occurs in an individual circuit, the remaining circuits with no failure can be selected by the encoder module 601, without the need to re-adjust the circuit, thus avoiding the waste of time and effectively improving the efficiency.

[0035] Figure 7 is an example circuit diagram of four column buffers (ColBuf), which is applicable to Figure 1 , the hold voltage Vsh and the ramp signal Ramp pass through the same column buffer, and then are input into the comparator for comparison. As shown in Figure 7 (a)-7(d), the column buffer can be implemented in various structures, such as the folded cascode operational amplifier, two five-tube operational amplifiers in parallel, the source follower, the Class AB operational amplifier, etc. As long as the hold voltage Vsh and the ramp signal Ramp pass through the same column buffer, and then are input into the comparator for comparison, no matter which structure is adopted for the column buffer, it all belongs to the scope of the present patent.

[0036] Figure 8is an example circuit diagram of the six in-column comparator modules (COMP). The comparator compares the magnitude of the positive input Vinp and the negative input Vinn and outputs the comparison result Vstep. As shown in Figure 8 (a), in the first example, MOS transistors M0 to M6 constitute a preamplifier stage, MOS transistors M7 to M10 constitute a differential-to-single-ended stage, or the OR gate is a digital output stage. The positive and negative inputs Vinp and Vinn are connected to the gates of MOS transistors M1 and M2, respectively, the sources of M1 and M2 are shorted together and connected to the drain of current source M0. The source of M0 is connected to voltage Vs3 and the gate is connected to control voltage Vbias. The drain Von1 of M1 is connected to the drain and gate of diode-connected MOS transistor M3, and the source of M3 is connected to voltage Vs1. Current source M5 is connected in parallel with M3, with the drain connected to the drain of M3, the source connected to the source of M3, and the gate connected to control voltage Vnb. The drain Vop1 of M2 is connected to the drain and gate of diode-connected MOS transistor M4, and the source of M4 is connected to voltage Vs1. Current source M6 is connected in parallel with M4, with the drain connected to the drain of M4, the source connected to the source of M4, and the gate also connected to control voltage Vnb. Vop1 and Von1 control the gates of differential-to-single-ended stage MOS transistors M7 and M8, respectively, and the sources of M7 and M8 are connected to voltage Vs1. The drain of M8 is connected to Vout, and the drain of M7 is connected to the drain and gate of diode-connected MOS transistor M9, and the source of M9 is connected to voltage Vs4. The gate of MOS transistor M10 is shorted to the gate of M9, the source is also connected to Vs4, and the drain is connected to Vout. Vout is logically ORed with the Set signal to obtain the output Vstep. Current sources M5 and M6 are optional.

[0037] As shown in Figure 8 (b), in the second example, the preamplifier, digital output stage, and the first example are the same, and the differential-to-single-ended stage is modified to a five-transistor open-loop amplifier, which is composed of MOS transistors M7 to M11. Vop1 and Von1 control the gates of M7 and M8, respectively, and the sources of M7 and M8 are shorted together to the drain of current source M11, the source of M11 is connected to voltage Vs2, and the gate is connected to control voltage Vbias1. The drain of M8 is connected to Vout, and the drain of M7 is connected to the drain and gate of diode-connected MOS transistor M9, and the source of M9 is connected to voltage Vs4. The gate of MOS transistor M10 is shorted to the gate of M9, the source is also connected to Vs4, and the drain is connected to Vout.

[0038] As shown in Figure 8(c) The third example is similar to the first example, but a positive feedback stage is inserted between the preamplifier and the differential-to-single-ended stage. Vop1 and Von1 control the gates of input transistors M13 and M14, respectively. The sources of M13 and M14 are connected to the drain of current source M12, the source of M12 is connected to voltage Vs4, and the gate of M12 is connected to control voltage Vbias2. The drains of M13 and M14 are the outputs of the positive feedback stage, Von2 and Vop2, respectively. Diode-connected M15 has its gate and drain connected to Von2, and its source connected to voltage Vs2. Diode-connected M16 has its gate and drain connected to Vop2, and its source also connected to voltage Vs2. Positive feedback transistor M17 has its drain connected to Von2, its source connected to voltage Vs2, and its gate controlled by Vop2. Positive feedback transistor M18 has its drain connected to Vop2, its source connected to voltage Vs2, and its gate controlled by Von2. Vop2 and Von2 are the inputs to the differential-to-single-ended stage.

[0039] As shown in Figure 8 (d) The fourth example is a simplified version of the third example, in which the preamplifier stage is removed, and the input is directly connected to the positive feedback stage. As shown in Figure 8 (e) The fifth example is similar to the third example, in which the preamplifier, the positive feedback stage, and the OR gate are the same, but the differential-to-single-ended stage is replaced by a five-transistor open-loop amplifier. As shown in Figure 8 (f) The sixth example is a simplified version of the fifth example, in which the preamplifier stage is removed, and the input is directly connected to the positive feedback stage.

[0040] Figure 9 A circuit diagram of an output driver module example is shown in FIG. 1. The parallel output signals of an n-bit ADC are converted into serial signals by n tri-state gates with shorted outputs, and then output to the outside of the chip. The tri-state gate is realized by a digital buffer and an enable switch. When the switch control signal en is valid, the tri-state gate is a digital buffer; when the switch control signal en is invalid, the output of the tri-state gate is in a high-impedance state. The switch control signal en is generated by a decoder controlled by CLKbuf and CLK1, which ensures that each switch is turned on in turn, realizing the parallel-to-serial conversion. For example, the number of memory columns corresponding to a 14-bit ADC is also 14, and the memory data is output to the driver through 14 data buses. The driver performs parallel-to-serial conversion on the 14 buses, and finally only one digital output pin is needed at the probe port.

[0041] The application has been described in detail by specific embodiments, but the application is not limited to these specific embodiments. Those skilled in the art should understand that various modifications, equivalent replacements, changes, etc. can be made to the application, and as long as the modifications, equivalent replacements, changes, etc. do not deviate from the spirit of the application, they should be within the protection scope of the application. In the structure of the application, the components can be decomposed and / or recombined, and these decompositions and / or recombinations should be regarded as equivalent solutions of the application.

Claims

1. A lock-in- phase loop based uncooled infrared readout device, characterized in that The application relates to an infrared readout device, which comprises: a phase-locked loop and timing module which receives a clock input and generates three phase-synchronous clock signals by frequency multiplication, frequency division and copying of the input clock (CLK), namely a first clock (CLKout), a second clock (CLK1) and a third clock (CLKbuf), the first clock, the second clock and the third clock control the working timing of the infrared readout device through a control timing circuit, and the synchronization between signals of various modules is ensured; a mirror probe front-end module which is divided into two columns, one column is a row-by-row selection photosensitive pixel, and the other column is a row-by-row selection reference pixel, the two columns have the same circuit architecture and working timing, and the mirror probe front-end module is used for generating a sensing current based on the photosensitive pixel and the reference pixel; a column-level trans-impedance amplifier module which is connected to an output node of the mirror probe front-end module, amplifies and filters the sensing current and then converts the sensing current into a sensing voltage; a sample-and-hold module which is connected to an output node of the column-level trans-impedance amplifier module and holds the sensing voltage as a holding voltage; a voltage comparison module which comprises a slope signal generation module and a comparator module, wherein the slope signal generation module is used for generating a slope signal under the control of the first clock, the comparator module is used for comparing the size of the slope signal and the holding voltage and outputting a step voltage; a counter module which is synchronously counted with the slope signal under the control of the first clock; an in-column storage module which is used for latching a current count value when the step voltage is reversed and outputting the current count value to a data bus; an output driver module which is used for converting the parallel data bus into serial data through a tri-state gate under the control of the second clock and the third clock and outputting the serial data to an off-chip.

2. The lock-in pyroelectric infrared readout device of claim 1, wherein, The phase-locked loop and timing module comprises: a first divider module which is used for performing D1 frequency division on the input clock (CLK) to generate the second clock (CLK1); a second divider module which is connected to an output of the phase-locked loop and timing module, performs D2 frequency division on the output to obtain a fourth clock (CLKfb) and provides the fourth clock (CLKfb) to a phase difference conversion module; a phase difference conversion module comprising a frequency and phase discriminator module and a charge pump module for receiving said second clock (CLK1) and said fourth clock (CLKfb) and for generating a current related to the phase difference between said second clock (CLK1) and said fourth clock (CLKfb) based on said second clock (CLK1) and said fourth clock (CLKfb) a current related to the phase difference between two of said clocks; a loop low-pass filter module which is used for generating a voltage related to the phase difference between the two clocks based on a current related to the phase difference between the two clocks and controlling a voltage-controlled oscillator module to generate the first clock (CLKout), the frequency of the first clock (CLKout) is D2 / D1 times of the input clock.

3. The lock-in pyroelectric infrared readout device of claim 1, wherein, The mirror probe front-end module comprises a common mirror channel and a readout channel and a digital-to-analog converter module; the reference pixel comprises a thermal short-circuit pixel and / or a thermal short-circuit pixel; the readout channel and the mirror channel respectively comprise one or a combination of M photosensitive pixels, a thermal short-circuit pixel, a first saturable tube and a second saturable tube; the common end of the thermal short-circuit pixel in the readout channel and the mirror channel is a voltage Vs1, and the common end of the photosensitive pixel is a voltage Vs2. Each photosensitive pixel in the readout channel is connected to the source terminal of a first saturation tube through a selection switch, the gate terminal of the saturation tube is driven by the gate voltage of the first saturation tube of the mirror channel through a buffer, the drain terminal is an output terminal, and is connected to the source terminal of the second saturation tube of the readout channel. The drain terminal of the second saturation tube of the readout channel is connected to the thermal shorting pixel of the readout channel; Each photosensitive pixel in the mirror channel is connected to the source terminal of a first saturation tube through a selection switch, the gate terminal of the saturation tube is driven by the gate terminal of the first saturation tube of the readout channel through a buffer based on the gate voltage, the drain terminal is an output terminal, and is connected to the source terminal of the second saturation tube of the mirror channel. The drain terminal of the second saturation tube of the mirror channel is connected to the thermal shorting pixel of the mirror channel. The digital-to-analog converter module is configured to generate voltages Vgch1 and Vgm1 based on the current difference between the first saturation tube and the second saturation tube of the readout channel, for controlling the gate terminal of the second saturation tube of the readout channel and the gate terminal of the second saturation tube of the mirror channel, respectively.

4. The lock-in pyroelectric infrared readout device of claim 3, wherein the first and second phase-locked loops are configured to operate at a frequency of 10 kHz to 100 kHz. The volume of the first saturation tube and the second saturation tube in the mirror channel is K times the volume of the first saturation tube and the second saturation tube in the readout channel.

5. The lock-in pyroelectric infrared readout device of claim 3, wherein the first and second phase-locked loops are configured to operate at a frequency of 10 kHz to 100 kHz. The thermal shorting pixel includes one or a combination of a plurality of series resistors, a plurality of parallel resistors, or a plurality of series-parallel resistors.

6. The lock-in pyroelectric infrared readout device of claim 3, wherein the first and second phase-locked loops are configured to operate at a frequency of 10 kHz to 100 kHz. The thermal shorting pixel in the mirror channel further includes L saturation tubes, L resistors, and L switches, wherein one end of each resistor is connected to the source terminal of one saturation tube, the other end of each resistor is connected to a common terminal with a voltage Vs1, the drain terminal of each saturation tube is connected to one switch and to the gate terminal of the first saturation tube of the mirror channel, and the gate terminal of each saturation tube is connected to a common terminal with a voltage Vgm1.

7. The lock-in pyroelectric infrared readout device of claim 1, wherein, The voltage comparison module further includes an in-column buffer module. The in-column buffer module is configured to receive the hold voltage and the ramp signal, respectively, and input the hold voltage and the ramp signal into the comparator.

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