A simulation method for an encapsulation box simulation circuit and a test method for an encapsulated chip

Abstract

The present application relates to a simulation method for a packaging box simulation circuit and a test method for a packaged chip, which are applied to the technical field of semiconductor microelectronics production. The method includes: establishing a simulation model of the packaging box; applying port excitation to the simulation model to generate S parameters; and obtaining the simulation circuit of the simulation model based on the S parameters, wherein the simulation circuit includes a plurality of electromagnetic parasitic elements. The present application has the effect of reducing the influence of electromagnetic parasitic parameters in the packaging box on the packaged chip when designing the packaged chip.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor microelectronics production, and in particular, to a simulation method for a packaging box simulation circuit and a testing method for a packaged chip. Background Art

[0002] The manufacturing process of a packaged chip includes steps such as spin coating, lithography, metal film plating, stripping, probe testing, dicing, packaging, and package testing on a wafer. Among them, probe testing is to test the electrical performance of the chips on the wafer through a network analyzer with a probe head. The wafers with qualified probe test results are then made into packaged chips after steps such as dicing and packaging.

[0003] In the packaging step, the packaging box is the carrier of the wafer. It is necessary to package the wafer with qualified probe test results in the packaging box. When packaging the wafer, electromagnetic parasitic parameters will be introduced into the packaging box. The electromagnetic parasitic parameters will cause changes in the performance of the wafer such as the passband width, center frequency, and passband rectangularity coefficient, and ultimately lead to unqualified electrical performance of the manufactured packaged chip. Summary of the Invention

[0004] In order to reduce the influence of electromagnetic parasitic parameters in the packaging box on the packaged chip when designing the packaged chip, the present application provides a simulation method for a packaging box simulation circuit and a testing method for a packaged chip.

[0005] In a first aspect, the present application provides a simulation method for a packaging box simulation circuit, adopting the following technical solutions:

[0006] A simulation method for a packaging box simulation circuit, the method comprising:

[0007] Establish a simulation model of the packaging box;

[0008] Perform port excitation on the simulation model to generate S parameters;

[0009] Obtain a simulation circuit of the simulation model based on the S parameters, wherein the simulation circuit includes a plurality of electromagnetic parasitic elements.

[0010] By adopting the above technical solutions, when considering the electromagnetic parasitic parameters of the packaging box, it is necessary to analyze the packaging box. By establishing a simulation model of the packaging box, the packaging box can be simulated and port excited, and an equivalent circuit including electromagnetic parasitic parameters can be obtained. Thus, when designing the parameters of the packaged chip, the electromagnetic parasitic parameters are considered, and further, the influence of the electromagnetic parasitic parameters on the designed packaged chip is reduced.

[0011] Optionally, the performing port excitation on the simulation model to generate S parameters includes:

[0012] Obtain several electromagnetic parasitic regions of the simulation model, and set lumped ports in each of the electromagnetic parasitic regions;

[0013] Excite the ports of the simulation model through the lumped ports to generate an excitation result;

[0014] Calculate the S-parameters of the lumped ports according to the excitation result

[0015] Optionally, the electromagnetic parasitic elements include: parasitic capacitance, parasitic inductance, and parasitic resistance. The simulation circuit of the simulation model obtained based on the S-parameters includes:

[0016] Convert the S-parameters into electromagnetic parasitic parameters of the simulation circuit based on a preset conversion formula;

[0017] Draw the simulation circuit of the simulation model based on the electromagnetic parasitic parameters.

[0018] Optionally, the conversion formula is:

[0019]

[0020] Among them, S11 is the input reflection coefficient, S12 is the reverse transmission coefficient, S21 is the forward transmission coefficient, S22 is the output reflection coefficient, f is the frequency of the excitation signal source, i is the imaginary number, R is the parameter of the resistor element, L is the parameter of the inductor element, and C is the parameter of the resistor element.

[0021] Optionally, after obtaining the simulation circuit of the simulation model based on the S-parameters, it further includes:

[0022] Verify the simulation circuit;

[0023] The verification of the simulation circuit includes:

[0024] Excite the ports of the simulation model to obtain the first frequency response value of the simulation model;

[0025] Calculate the simulation circuit according to the field energy calculation formula to obtain the second frequency response value of the simulation circuit;

[0026] Verify based on the first frequency response value and the second frequency response value:

[0027] If the first frequency response value is consistent with the second frequency response value, the verification passes; otherwise, the verification fails.

[0028] By adopting the above technical solution, the field energy analysis of the simulation model is compared with the field energy analysis of the equivalent circuit, and the equivalent circuit after simulation can be verified. When the verification passes, the influence of the equivalent circuit on the packaged chip can replace the influence of the package box on the packaged chip.

[0029] In a second aspect, the present application provides a method for testing a packaged chip, adopting the following technical solution:

[0030] A method for testing a packaged chip, the testing method comprising: a probe testing step and a packaging testing step;

[0031] Before the probe testing step, it further includes:

[0032] Fabricate an equivalent circuit on a mask plate according to the simulation circuit and fabricate it on a first chip, wherein the equivalent circuit is generated by applying the packaging box simulation circuit simulation method according to any one of claims 1 to 5; the first chip includes a chip that does not include the equivalent circuit

[0033] Before the packaging testing step, it further includes:

[0034] Dicing, cutting and removing the equivalent circuit to separate the equivalent circuit from the second chip to obtain a third chip, wherein the second chip includes a chip with the equivalent circuit, and the third chip includes a chip with the equivalent circuit removed.

[0035] By adopting the above technical solution, the simulation circuit is fabricated into an actual equivalent circuit by actual resistors, capacitors and inductors, and the fabricated equivalent circuit is fabricated on an unprocessed chip. When designing the chip, the influence of electromagnetic parasitic parameters on the packaged chip is reduced, and thus the qualification rate of the packaged chip is improved.

[0036] Optionally, fabricating the equivalent circuit on the mask plate according to the simulation circuit includes:

[0037] Obtain the electromagnetic parasitic parameters of the electromagnetic parasitic elements in the simulation circuit;

[0038] Fabricate an equivalent circuit according to the simulation circuit and the electromagnetic parasitic parameters.

[0039] By adopting the above technical solution, the simulation circuit can be fabricated into an actual equivalent circuit, and the equivalent circuit is lithographed on an unprocessed chip, so that the influence of the equivalent circuit on the packaged chip replaces the influence of the packaging box on the packaging box, thereby reducing the influence of the electromagnetic parasitic parameters of the packaging box on the packaged chip during the fabrication process of the packaged chip.

[0040] Optionally, the electromagnetic parasitic parameters include parasitic capacitance parameters, parasitic inductance parameters and parasitic resistance parameters;

[0041] Among them, the calculation formula for the parasitic capacitance parameter is:

[0042]

[0043] Wp = a / p;

[0044] C = N × C s ;

[0045] Wherein, Cs is the capacitance of a pair of interdigital fingers, w is the aperture, a is the width of the metal finger, p is the gate period, ε(∞) is the dielectric constant, P is the Legendre function, Wp is the metallization rate, and N is the number of pairs of interdigital fingers;

[0046] The calculation formula for the parasitic inductance parameter is:

[0047]

[0048] Wherein, Am is the area of the metal region; Atot is the total area of the inductor; W is the width of the metal wire; SS is the spacing between the metal wires; D is the outer dimension of the inductor;

[0049] The calculation formula for the parasitic resistance parameter is:

[0050]

[0051] Wherein, l is the length of the metal film, W is the width of the metal film, d is the thickness of the metal film, and ρ is the resistivity.

[0052] Optionally, the probe test step includes:

[0053] Applying an electrical signal excitation to the pins of the second chip to obtain the frequency response value of the second chip within a preset electrical signal excitation frequency band;

[0054] Calculating the performance index of the second chip based on the frequency response value;

[0055] Comparing the performance index with a preset performance index;

[0056] If the performance index is consistent with the preset performance index, it is determined that the second chip is qualified for production, otherwise it is unqualified.

[0057] Optionally, the test method further includes:

[0058] Photolithography, fabricating the equivalent circuit on the first chip, and photolithographically marking a scribing point at the connection between the equivalent circuit and the first chip, and the scribing point is used for reminder during the scribing step.

[0059] By adopting the above technical solution, it helps to cut off the equivalent circuit during the scribing step, so that when the packaged chip is under package testing, the influence of the equivalent circuit on the packaged chip is reduced. Description of the Drawings

[0060] Figure 1It is a schematic flow chart of a simulation method for an encapsulation box simulation circuit provided by an embodiment of the present application.

[0061] Figure 2 It is a circuit connection diagram of S parameters provided by an embodiment of the present application.

[0062] Figure 3 It is a schematic diagram of a simulation circuit principle of an electromagnetic parasitic region provided by an embodiment of the present application.

[0063] Figure 4 It is a schematic diagram of a circuit principle of an encapsulation box simulation circuit provided by an embodiment of the present application.

[0064] Figure 5 It is a schematic flow chart of a test method for an encapsulated chip provided by an embodiment of the present application.

[0065] Figure 6 It is a schematic diagram of the structure of parasitic inductance in an embodiment of the present application.

[0066] Figure 7 It is a schematic diagram of the structure of parasitic capacitance in an embodiment of the present application.

[0067] Figure 8 It is a schematic diagram of the structure of parasitic resistance in an embodiment of the present application.

[0068] Figure 9 It is a schematic diagram of the structure before dicing in an embodiment of the present application.

[0069] Figure 10 It is a schematic diagram of the structure after dicing in an embodiment of the present application. Detailed implementation manners

[0070] The following further describes the present application in detail with reference to the accompanying drawings.

[0071] Figure 1 It is a schematic flow chart of a simulation method for an encapsulation box simulation circuit provided by an embodiment of the present application.

[0072] As Figure 1 shown, the main process of this method is described as follows (Steps S101 to S104):

[0073] Step S101, establish a simulation model of the encapsulation box.

[0074] In this embodiment, the encapsulation box can be simulated and analyzed by finite element software. Among them, the finite element software is a modern calculation method that can analyze the electromagnetic field. Establishing a simulation model of the encapsulation box in the finite element software includes:

[0075] Establish a three-dimensional coordinate system;

[0076] Input the proportional dimensions of the encapsulation box;

[0077] Perform Boolean operations and geometric transformations;

[0078] Input the material properties of each part of the packaging box to generate a simulation model of the packaging box.

[0079] Specifically, since it is necessary to simulate the electromagnetic parasitic parameters on the packaging box, it is necessary to construct a proportional model of the packaging box on the finite element software. By performing simulation analysis on the proportional model, a simulation circuit corresponding to the electromagnetic parasitic parameters on the packaging box can be obtained.

[0080] In this embodiment, when analyzing the simulation model, the equivalent circuit method can be used to generate the simulation circuit of the simulation model. When applying the equivalent circuit method, it is necessary to, based on the field distribution, use the method of circuits to equivalent microwave components as reactance or resistance devices, and equivalent the actual waveguide transmission system as a transmission line. And generating S-parameters is the key to generating the simulation circuit, that is, obtaining the simulation circuit equivalent to the packaging box through the conversion of S-parameters.

[0081] Step S102, perform port excitation on the simulation model to generate S-parameters.

[0082] In this embodiment, performing port excitation on the simulation model to generate S-parameters includes: obtaining the electromagnetic parasitic region of the simulation model and setting lumped ports in the electromagnetic parasitic region;

[0083] Perform port excitation on the simulation model through the lumped ports to generate an excitation result;

[0084] Calculate the S-parameters of the lumped ports according to the excitation result.

[0085] Specifically, there are multiple bonding wires for connection inside the packaging box. When current flows through the bonding wires, parasitic resistance will be generated. When the current flowing through the bonding wires changes, parasitic inductance will be generated by the bonding wires. When current flows through two bonding wires simultaneously, parasitic capacitance will be formed between the two bonding wires. The electromagnetic parasitic region includes the regions in the packaging box where there are parasitic resistance, parasitic inductance, and parasitic capacitance.

[0086] In the finite element software, port excitation includes wave port excitation and lumped port excitation. Among them, wave port excitation is used to excite the outside of the simulation model, while the difference between the lumped port and the wave port is that the lumped port can be set inside the simulation model to excite the inside of the simulation model.

[0087] Step S103, obtain the simulation circuit of the simulation model based on the S-parameters, where the simulation circuit includes multiple electromagnetic parasitic components.

[0088] Specifically, convert the S-parameters into the electromagnetic parasitic parameters of the simulation circuit based on a preset conversion formula;

[0089] A simulation circuit for drawing a simulation model based on electromagnetic parasitic parameters.

[0090] In this embodiment, the conversion formula is:

[0091]

[0092] Among them, S11 is the input reflection coefficient, S12 is the reverse transmission coefficient, S21 is the forward transmission coefficient, S22 is the output reflection coefficient, f is the frequency of the excitation signal source, i is the imaginary number, R is the parameter of the resistor element, L is the parameter of the inductor element, and C is the parameter of the resistor element.

[0093] As Figure 2 shown, in this embodiment, when port 1 is matched, S12 is the reverse transmission coefficient from port 2 to port 1, S22 is the output reflection coefficient of port 1, S11 is the input reflection coefficient of port 1, and S21 is the forward transmission coefficient of port 1.

[0094] As Figure 3 shown, the S parameters are converted into the electromagnetic parasitic parameters of the simulation circuit according to the conversion formula, and the circuit diagram of the current electromagnetic parasitic region is obtained.

[0095] As Figure 4 shown, port excitation is performed on all electromagnetic parasitic regions in the simulation model, all calculated S parameters are converted into electromagnetic parasitic parameters using the conversion formula, and are summarized and integrated to draw the simulation circuit of the simulation model.

[0096] In this embodiment, after obtaining the simulation circuit of the simulation model based on the S parameters, it further includes:

[0097] Verifying the simulation circuit;

[0098] Verifying the simulation circuit includes:

[0099] Performing port excitation on the simulation model to obtain the first frequency response value of the simulation model;

[0100] Calculating the simulation circuit according to the field energy calculation formula to obtain the second frequency response value of the simulation circuit;

[0101] Judging based on the first frequency response value and the second frequency response value:

[0102] If the first frequency response value is consistent with the second frequency response value, the verification passes, otherwise the verification fails.

[0103] Specifically, in this embodiment, the field energy calculation formula is:

[0104]

[0105]

[0106]

[0107]

[0108] D = εE;

[0109] B = μH;

[0110] J = σE;

[0111] where J is the conduction current density, H is the magnetic field strength, is the displacement current density, is the magnetic flux density, ε is the permittivity of the medium, μ is the magnetic permeability of the medium, and σ is the conductivity of the medium.

[0112] Through the above field energy calculation formula, the second frequency response value of the simulation circuit is obtained. Among them, the second frequency response value is compared with the first frequency response value. When the second frequency response value is consistent with the first frequency response value, it proves that the function of the drawn simulation circuit is equivalent to the function of the encapsulation box; when the second frequency response value is inconsistent with the first frequency response value, it is necessary to go to step S101 and start the simulation of the encapsulation box again.

[0113] This application embodiment also discloses a testing method for encapsulating a chip, as Figure 5 shown, the testing method includes:

[0114] Manufacturing a circuit: manufacturing an equivalent circuit on a mask according to the simulation circuit, where the equivalent circuit is generated by applying the simulation method of the encapsulation box simulation circuit;

[0115] Spin coating: dropping photoresist on the first chip and evenly applying the photoresist on the surface of the first chip to form a photoresist film;

[0116] Photolithography: irradiating the area coated with photoresist on the first chip according to the mask, making the photoresist in the irradiated area of the first chip easy to dissolve;

[0117] Developing: using a developer to dissolve the photoresist in the irradiated area;

[0118] Coating: coating a metal film on the dissolved area;

[0119] Lifting off: lifting off the first chip so that only the circuit part remains on the first chip to obtain a second chip;

[0120] Probe testing: applying an electrical signal excitation to the signals on the pins of the second chip to obtain the first performance parameter of the second chip, and judging whether the manufacturing of the second chip is qualified based on the first performance parameter and the preset performance parameter;

[0121] Scribing: Cut and remove the equivalent circuit on the second chip to separate the equivalent circuit from the second chip, obtaining a third chip;

[0122] Packaging: Attach the third chip to the packaging box, bond the third chip to the packaging box through bonding wires, and seal the third chip and the packaging box to obtain a fourth chip;

[0123] Packaging test: Apply an electrical signal excitation to the ports of the packaged packaging box, obtain the second performance parameters of the fourth chip, and determine whether the production of the fourth chip is qualified based on the second performance parameters and the preset performance parameters.

[0124] In this embodiment, the first chip is a chip without an equivalent circuit, the second chip is a chip with an equivalent circuit, the third chip is a chip with the equivalent circuit removed after scribing, and the fourth chip is a packaged chip.

[0125] In this embodiment, fabricating the equivalent circuit on the mask according to the simulation circuit includes:

[0126] Obtain the electromagnetic parasitic parameters of the electromagnetic parasitic elements in the simulation circuit;

[0127] Fabricate the equivalent circuit according to the simulation circuit and the electromagnetic parasitic parameters.

[0128] Refer to Figure 6 、 Figure 7 and Figure 8 , further, the electromagnetic parasitic parameters include parasitic capacitance parameters, parasitic inductance parameters, and parasitic resistance parameters:

[0129] In this embodiment, the calculation formula for the parasitic capacitance parameter is:

[0130]

[0131] W p = a / p;

[0132] C = N × C s ;

[0133] where Cs is the capacitance of a pair of interdigital fingers, w is the aperture, a is the width of the metal finger strip, p is the grating period, ε(∞) is the dielectric constant, P is the Legendre function, Wp is the metallization rate, and N is the number of interdigital pairs;

[0134] The calculation formula for the parasitic inductance parameter is:

[0135]

[0136] where Am is the area of the metal region; Atot is the total area of the inductor; W is the width of the metal wire; SS is the metal wire spacing; D is the outer dimension of the inductor;

[0137] The calculation formula for the parasitic resistance parameter is as follows:

[0138]

[0139] Wherein, l is the length of the metal film, W is the width of the metal film, d is the thickness of the metal film, and ρ is the resistivity.

[0140] The size parameters of the parasitic capacitance, parasitic inductance, and parasitic resistance are obtained through calculation, and the parasitic capacitance, parasitic inductance, and parasitic resistance are connected according to the simulation circuit, and an equivalent circuit is fabricated on the mask plate.

[0141] Referring to FIG. 9 and Figure 10 , in this embodiment, when the equivalent circuit is lithographed on the first chip, a scribe mark point needs to be lithographed at each connection point between the first chip and the equivalent circuit, so that the equivalent circuit can be completely separated from the second chip during the scribing step, thereby reducing the possibility of inaccurate test results of the fourth chip during the packaging test.

[0142] In this embodiment, the probe test step includes:

[0143] Applying an electrical signal excitation to the pins of the second chip to obtain the frequency response value of the second chip within the preset electrical signal excitation frequency band;

[0144] Calculating the performance index of the second chip based on the frequency response value;

[0145] Comparing the performance index with the preset performance index;

[0146] If the performance index is consistent with the preset performance index, it is determined that the second chip is manufactured qualified, otherwise it is unqualified.

[0147] Specifically, when performing a probe test on the second chip, the pins of the second chip are electrically connected to the excitation signal source, and then the excitation signal source is controlled to apply an electrical signal excitation to the pins of the second chip to obtain the frequency response diagram of the second chip. Among them, the excitation signal source can be a network analyzer.

[0148] Furthermore, in the frequency response diagram, the frequency response value of the second chip within the preset electrical signal excitation frequency band is obtained, and the performance index of the second chip is obtained based on the frequency response value. The performance index includes the center frequency, passband width, and out-of-band rejection of the second chip. If the performance index is consistent with the preset performance index, it is determined that the second chip is manufactured qualified, and if not, it is determined that the second chip is unqualified.

[0149] After it is determined that the probe test of the second chip is unqualified, the circuit on the second chip needs to be erased and cleaned, and then the circuit is re-lithographed to fabricate the chip again.

[0150] After determining that the second chip probe test is qualified, the dicing operation is then carried out.

[0151] Since the equivalent circuit has been removed from the second chip during the dicing step, the third chip will not be affected by the equivalent circuit during the package test.

[0152] Introducing the equivalent circuit before the probe test of the second chip and then performing the probe test on the second chip can make the test results of the probe test consistent with those of the package test, so that it can be known whether the second chip is manufactured qualified before dicing, thereby reducing the waste of chip manufacturing materials and saving the cost of manufacturing packaged chips.

[0153] The term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device.

[0154] The above description is only a preferred embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the application involved in the present application is not limited to the technical solution formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the foregoing application concept. For example, the technical solution formed by the mutual replacement of the above features and the technical features (but not limited to) having similar functions applied in the present application.

Claims

1. A simulation method for a packaging box simulation circuit, characterized in that The method includes: Establishing a simulation model of the encapsulation box; Performing port excitation on the simulation model to generate S-parameters; Obtaining the simulation circuit of the simulation model based on the S-parameters, wherein the simulation circuit includes a plurality of electromagnetic parasitic elements; the electromagnetic parasitic elements include: parasitic capacitance, parasitic inductance, and parasitic resistance, and the obtaining of the simulation circuit of the simulation model based on the S-parameters includes: Converting the S-parameters into electromagnetic parasitic parameters of the simulation circuit based on a preset conversion formula; Drawing the simulation circuit of the simulation model based on the electromagnetic parasitic parameters.

2. The simulation method of an encapsulated box simulation circuit according to claim 1, characterized in that, The performing port excitation on the simulation model to generate S-parameters includes: Obtaining a plurality of electromagnetic parasitic regions of the simulation model, and setting lumped ports in each of the electromagnetic parasitic regions; Performing port excitation on the simulation model through the lumped ports to generate an excitation result; Calculating the S-parameters of the lumped ports according to the excitation result.

3. The simulation method of an encapsulation box simulation circuit according to claim 1, characterized in that The conversion formula is: Wherein, S11 is the input reflection coefficient, S12 is the reverse transmission coefficient, S21 is the forward transmission coefficient, S22 is the output reflection coefficient, f is the frequency of the excitation signal source, i is the imaginary number, R is the parameter of the resistance element, L is the parameter of the inductance element, and C is the parameter of the resistance element.

4. A simulation method for a simulation circuit of a packaging box according to claim 1, characterized in that After obtaining the simulation circuit of the simulation model based on the S-parameters, it further includes: Verifying the simulation circuit; The verifying the simulation circuit includes: Performing port excitation on the simulation model to obtain the first frequency response value of the simulation model; Calculating the simulation circuit according to the field energy calculation formula to obtain the second frequency response value of the simulation circuit; verifying based on the first frequency response value and the second frequency response value: If the first frequency response value is consistent with the second frequency response value, the verification passes; otherwise, the verification fails.

5. A method for testing a packaged chip, characterized in that, The testing method includes: a probe testing step and a packaging testing step; Before the probe testing step, it further includes: Fabricating an equivalent circuit on a mask and fabricating it on a first chip, wherein the equivalent circuit is generated by applying the encapsulation box simulation circuit simulation method according to any one of claims 1 to 4; the first chip is a chip that does not include the equivalent circuit; Before the packaging testing step, it further includes: Dicing, cutting off the equivalent circuit to separate the equivalent circuit from a second chip, and obtaining a third chip, wherein the second chip is a chip with the equivalent circuit, and the third chip is a chip with the equivalent circuit removed.

6. The testing method for an encapsulated chip according to claim 5, wherein The fabricating an equivalent circuit on a mask according to the simulation circuit includes: Obtaining the electromagnetic parasitic parameters of the electromagnetic parasitic elements in the simulation circuit; Fabricating an equivalent circuit according to the simulation circuit and the electromagnetic parasitic parameters.

7. A test method for packaging a chip according to claim 6, characterized in that The electromagnetic parasitic parameters include parasitic capacitance parameters, parasitic inductance parameters, and parasitic resistance parameters; Wherein, the calculation formula of the parasitic capacitance parameter is: W p = a / p; C = N × C s ; Among them, C s is a pair of interdigital capacitors, w is the aperture, a is the width of the metal finger, p is the grating period, ε(∞) is the dielectric constant, P is the Legendre function, W p is the metallization rate, and N is the number of interdigital pairs; The calculation formula of the parasitic inductance parameter is: Among them, A m is the area of the metal region; A tot is the total area of the inductor; W is the metal line width; S is the metal line spacing; The calculation formula of the parasitic resistance parameter is: Wherein, l is the length of the metal film, W is the width of the metal film, d is the thickness of the metal film, and ρ is the resistivity.

8. The test method for a packaged chip according to claim 7, characterized in that, The probe testing step includes: Apply an electrical signal excitation to the pins of the second chip to obtain the frequency response value of the second chip within a preset electrical signal excitation frequency band; Calculate the performance index of the second chip based on the frequency response value; Compare the performance index with a preset performance index; If the performance index is consistent with the preset performance index, determine that the production of the second chip is qualified; otherwise, it is unqualified.

9. The test method for an encapsulated chip according to claim 5, characterized in that, The test method further includes: Lithography, fabricate the equivalent circuit on the first chip, and lithograph scribe mark points at the connection between the equivalent circuit and the first chip, and the scribe mark points are used for reminder in the dicing step.

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