Wafer testing method, device and computer readable storage medium

Abstract

The application provides a wafer testing method, device and computer readable storage medium, and is applied to the technical field of semiconductor testing. The wafer testing method comprises the following steps: firstly, all dies containing dies to be tested in a Map diagram formed by a probe machine are divided into multiple Touchdown arrangement combinations according to random die arrangement parameter values of a probe card; then, a Touchdown arrangement combination (a Touchdown arrangement mode with the least number of Touchdowns) with the least number of Touchdowns is selected from the arrangement combinations; and finally, the wafer to be tested is tested according to the arrangement order. In the testing method provided by the application, the calculation method of the Touchdown of the probe machine is not used by default, but the least arrangement combination is selected by random combination, so that the dies to be tested in one Touchdown test are placed in one Touchdown instead of multiple Touchdowns, thereby achieving the purpose of reducing wafer testing time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, and in particular to a wafer testing method and device and a computer readable storage medium. BACKGROUND

[0002] In recent years, with the continuous progress of integrated circuit technology, the circuit structure is becoming more and more complex, and the integration is becoming higher and higher. In the manufacturing process of semiconductor products, it needs to go through hundreds of process steps to ensure the quality and reliability of the IC products, which is one of the key links to ensure the performance and quality of integrated circuits. Wafer acceptance test (WAT) plays an important role as a chip quality detection process. The purpose of WAT is to detect whether the wafer product meets the specification requirements of the process by testing the WAT parameter electrical properties of the specific test structure on the wafer product. Wafer acceptance test includes various test items, which is an important means to verify the design, monitor the production, ensure the quality, analyze the failure and guide the application, and is an indispensable step in chip manufacturing.

[0003] At present, in wafer testing, the wafer needs to be placed on the chuck of the probe station and connected to the tester through the probe card, and then the various electrical parameters and functions of the microchip on the wafer are tested. Many wafer tests are multi-site now, and the time for testing each group of memory products is very long. If the probe station moves according to the default algorithm of the machine, the number of tests will be more, and many things that can be tested in one touchdown may be divided into two or more times, which is a waste of time.

[0004] In addition, some products need the probe station to provide a high-temperature or low-temperature environment to test the performance of the chip. Usually, during the testing process, the chuck of the device is raised and lowered in temperature, and after the temperature rises and falls, the critical point of the probe contact is found, the distance between the needle tip and the wafer during the cold or hot process is judged, and then the probe directly tests the wafer under the test condition. However, in the current wafer testing, most of the sites are on the outside of the wafer. When testing high and low temperatures, the change of temperature will cause physical changes to the precise parts of the device, including the needle tip of the probe card, that is, the state of the needle tip of the probe card changes, which causes errors in the alignment of the probe and the pressure point during the testing of the product, and thus causes abnormal test data, which requires repeated testing, resulting in low test efficiency and delay in production time. SUMMARY

[0005] The purpose of the present application is to provide a wafer testing method, device and computer readable storage medium to reduce the testing time of the wafer and improve the testing stability of the wafer, and ultimately avoid the influence of the temperature change of the probe machine during the testing process on the test data, thereby improving the testing efficiency of the wafer.

[0006] In a first aspect, to solve the above technical problems, the present application provides a wafer testing method, comprising:

[0007] The present application is applied to multi-point testing of multiple dies on a wafer by a probe machine, wherein the probe machine comprises a probe card, and the testing method comprises the following steps:

[0008] Step S1: providing a wafer to be tested, wherein the wafer to be tested comprises multiple dies;

[0009] Step S2: determining die arrangement parameter values of the probe card and the number of dies to be tested on the wafer to be tested, and forming a Map corresponding to the wafer to be tested by using the probe machine, wherein the Map comprises coordinates of each die;

[0010] Step S3: according to a preset arrangement algorithm and the die arrangement parameter values of the probe card, dividing all dies containing dies to be tested in the Map into multiple arrangement combinations of multiple Touchdowns;

[0011] Step S4: traversing each arrangement combination containing multiple Touchdowns, finding out the optimal arrangement mode of multiple Touchdowns corresponding to the Map of the wafer to be tested, and testing the wafer to be tested by using the optimal arrangement mode of the Touchdown.

[0012] Further, the step S3 of dividing all dies containing dies to be tested in the Map into multiple arrangement combinations of multiple Touchdowns according to a preset arrangement algorithm and the die arrangement parameter values of the probe card can comprise:

[0013] According to the die arrangement parameter values of the probe card, randomly dividing all dies containing dies to be tested in the Map into multiple arrangement combinations of multiple Touchdowns, wherein each Touchdown has an equal size.

[0014] Further, the size of each Touchdown can be equal to the die arrangement parameter values of the probe card.

[0015] Further, the optimal arrangement mode of multiple Touchdowns corresponding to the Map of the wafer to be tested in the step S4 can be an arrangement mode with the least number of Touchdowns corresponding to the Map of the wafer to be tested.

[0016] Further, after the step S4 traverses each Touchdown-arrangement combination to find the arrangement mode with the least number of Touchdowns corresponding to the Map of the wafer under test, the wafer testing method provided by the present application can further include:

[0017] According to the temperature of the probe card, the arrangement order of the Touchdowns is adjusted so that the Touchdowns containing only the dies under test and the Touchdowns containing both the dies under test and the dies not under test are tested alternately.

[0018] In a second aspect, based on the same inventive concept, the present application further provides a wafer testing device applied in multi-point testing of multiple dies on a wafer by a probe machine, wherein the probe machine comprises a probe card, and specifically, the testing device can comprise:

[0019] a parameter determining module configured to determine a die arrangement parameter value of the probe card and determine the number of dies under test in the multiple dies contained in the wafer under test according to the wafer under test provided;

[0020] a Map forming module configured to form a Map corresponding to the wafer under test by the probe machine, wherein the Map contains the coordinates of each die;

[0021] a Touchdown-arrangement-combination forming module configured to divide all the dies containing the dies under test in the Map into multiple Touchdown-arrangement combinations according to a preset arrangement algorithm and the die arrangement parameter value of the probe card;

[0022] a testing module configured to traverse each Touchdown-arrangement combination to find the optimal arrangement mode of the multiple Touchdowns corresponding to the Map of the wafer under test, and test the wafer under test in the optimal arrangement mode of the Touchdowns.

[0023] Further, the Touchdown-arrangement-combination forming module can be specifically configured to:

[0024] divide all the dies containing the dies under test in the Map into multiple Touchdown-arrangement combinations according to the die arrangement parameter value of the probe card, wherein each Touchdown-arrangement combination has the same size.

[0025] Further, the optimal arrangement mode of the multiple Touchdowns corresponding to the Map of the wafer under test determined by the testing module can be the arrangement mode with the least number of Touchdowns corresponding to the Map of the wafer under test.

[0026] Further, the test device provided by the application can further comprise:

[0027] The Touchdown arrangement adjustment module is used for adjusting the arrangement sequence of the plurality of Touchdowns according to the temperature of the probe card, so as to alternately test the Touchdowns containing the die to be tested and the Touchdowns containing the die to be tested and the die not to be tested.

[0028] In a third aspect, the application further provides an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus.

[0029] The memory is used for storing a computer program.

[0030] The processor is used for executing the program stored on the memory, and realizes the following method steps.

[0031] Step S1, providing a wafer to be tested, wherein the wafer to be tested contains a plurality of dies;

[0032] Step S2, determining the die arrangement parameter value of the probe card and the number of dies to be tested on the wafer to be tested, and forming a Map corresponding to the wafer to be tested by using the probe machine, wherein the Map contains the coordinates of each die.

[0033] Step S3, according to a preset arrangement algorithm and the die arrangement parameter value of the probe card, dividing all the dies containing the dies to be tested in the Map into a plurality of arrangement combinations of the plurality of Touchdowns.

[0034] Step S4, traversing each arrangement combination containing the plurality of Touchdowns, finding out the best arrangement mode of the plurality of Touchdowns corresponding to the Map of the wafer to be tested, and testing the wafer to be tested in the best arrangement mode of the Touchdown.

[0035] In a fourth aspect, the application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize each step of the wafer testing method.

[0036] Compared with the prior art, the technical scheme of the application has at least one of the following beneficial effects:

[0037] In the wafer testing method provided by the present application, all dies in a Map diagram formed by a probe machine are divided into multiple Touchdowns in multiple arrangement combinations according to the die arrangement parameter values of a probe card randomly, then, the Touchdown arrangement combination with the least number of Touchdowns is selected from the multiple arrangement combinations, and then, the wafer is tested according to the arrangement order. In the testing method provided by the present application, the Touchdown calculation method of the probe machine is not used, but the least arrangement combination is selected by random combination, so that all the dies to be tested are placed in one Touchdown instead of multiple Touchdowns, thereby achieving the purpose of reducing the wafer testing time.

[0038] Further, in the testing method provided by the present application, after the Touchdown arrangement combination with the least number of Touchdowns is selected, the arrangement order of the multiple Touchdowns can be adjusted according to the preheating and precooling characteristics of the high-low temperature probe card, so that the Touchdowns containing only the dies to be tested and the Touchdowns containing the dies to be tested and the dies not to be tested are tested alternately, thereby avoiding the problem that the state of the probe tip changes due to the long-time absence of the probe tip in the testing area, and further causing the test data to be abnormal. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 The flowchart of the wafer testing method provided by an embodiment of the present application is shown in the figure.

[0040] Figure 2 The structure diagram of the arrangement of the multiple Touchdowns corresponding to the Map diagram of the wafer to be tested formed by the prior art is shown in the figure.

[0041] Figure 3 The structure diagram of the arrangement of the Touchdowns with the least number of Touchdowns corresponding to the Map diagram of the wafer to be tested provided by an embodiment of the present application is shown in the figure.

[0042] Figure 4 The structure diagram of the Touchdowns corresponding to the Map diagram of the wafer to be tested after the arrangement order of the multiple Touchdowns is adjusted provided by an embodiment of the present application is shown in the figure.

[0043] Figure 5 The structure diagram of the wafer testing device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0044] As described in the background, at present, in wafer testing, the wafer needs to be placed on the chuck of the probe station and connected to the tester through the probe card, and then the various electrical parameters and functions of the micro-chip on the wafer are tested. Many wafer tests are multi-site now, and the time for testing each group of memory products is very long. If the probe station walks according to the default algorithm of the machine, the number of tests will be more, and many chips that can be tested in one touchdown may be divided into two or more times, which is a waste of time.

[0045] In addition, some products need the probe station to provide a high-temperature or low-temperature environment to test the performance of the chip. Usually, during the test process, the chuck of the device is raised and lowered in temperature, and after the temperature is raised and lowered, the critical point of probe contact is found, the distance between the needle tip and the wafer during the cold or hot process is judged, and then the probe directly tests the wafer under the test condition. However, in the current wafer testing, most of the sites are on the outside of the wafer. When testing high and low temperatures, the change of temperature will cause physical changes to various precise parts of the device, including the needle tip of the probe card, that is, the state of the needle tip of the probe card changes, which causes errors in the alignment of the probe and the pressing point when testing the product, and further causes abnormal test data, which requires repeated testing, resulting in low test efficiency and delay in production time.

[0046] To solve this problem, the researchers of the present application propose a test method that can randomly divide all the dies containing the dies to be tested in the Map diagram formed by the probe station according to the die arrangement parameter value of the probe card into multiple Touchdowns, and then select the Touchdown arrangement combination with the least number of probe station walking times from all the arrangement combinations (the arrangement mode with the least number of Touchdowns), and then test the wafer to be tested according to the arrangement order. Since the test method provided by the present application does not use the default Touchdown calculation method of the probe station, but uses random combination and selects the least arrangement combination, the dies to be tested that can be tested in one Touchdown are placed in one Touchdown instead of multiple Touchdowns, thereby achieving the purpose of reducing wafer test time.

[0047] Further, after selecting the Touchdown arrangement combination with the least number of probe station walking times, the arrangement order of the multiple Touchdowns can also be determined according to the preheating and precooling characteristics of the high and low temperature probe card, so that the Touchdowns containing only the dies to be tested and the Touchdowns containing both the dies to be tested and the dies not to be tested are tested alternately, thereby avoiding the problem of abnormal test data caused by the change in the state of the probe needle tip due to the long absence of the probe needle in the test area.

[0048] To this end, the present application provides a wafer testing method, device and computer readable storage medium to reduce wafer testing time and improve wafer testing stability, and ultimately avoid the influence of temperature change of a probe machine on testing data in the testing process, thereby improving wafer testing efficiency. The wafer testing method provided by the present application can be applied in multi-point testing of multiple dies on a wafer by a probe machine, and the probe machine includes a probe card.

[0049] The wafer testing method, device and computer readable storage medium provided by the present application will be further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application. In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and therefore the present application is not limited to the specific embodiments disclosed below.

[0050] As shown in the present application and claims, unless the context clearly indicates otherwise, "one", "a", "an" and / or "the" do not refer to the singular, but can also include the plural. Generally, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements. In the detailed description of the embodiments of the present application, the cross-sectional view of the device structure is locally enlarged without general proportion for the purpose of illustration, and the schematic diagram is only an example, which should not limit the scope of protection of the present application. In addition, three-dimensional spatial dimensions including length, width and depth should be included in actual manufacture.

[0051] The wafer testing method provided by the present application will be introduced first by the accompanying drawings and embodiments. Specifically, reference can be made to Figure 1 , Figure 1 The flowchart of the wafer testing method provided by an embodiment of the present application is shown. The wafer testing method provided by the present application can include the following steps:

[0052] Step S1, providing a wafer to be tested, the wafer to be tested including multiple dies.

[0053] In the embodiment, a wafer to be tested can be provided first, wherein the wafer to be tested can include a plurality of chips, and the wafer to be tested can also be called a die. However, not all the chips (dies) on the wafer to be tested need to be tested in this test. Therefore, in the embodiment, the chip to be tested is called a die to be tested, and the other chip is called a die not to be tested. Then, the wafer to be tested is loaded on a chuck of a probe machine, and a probe card with probes is located at an initial probe position above the wafer to be tested.

[0054] It can be understood that, in the embodiment, the wafer to be tested is tested by using a probe test machine (or simply called a probe machine). The probe test machine includes a test machine and a probe station. The probe station loads the wafer to be tested on a chuck, and simultaneously loads a probe card with probes. In normal testing, the vertical distance between the tip of the probe and the wafer to be tested remains unchanged to ensure that the contact between the probe and the wafer to be tested is stable under constant needle pressure. The probe for testing is located above the wafer to be tested, and the vertical distance between the tip of the probe and the wafer to be tested is an initial probe height. The probe test machine contacts the wafer to be tested by using the tip of the probe to contact a test contact pad on the wafer to be tested. The probe test machine sends a test electrical signal (including a voltage and a current signal) to the wafer to be tested by using the tip of the probe to contact a die on the wafer to be tested, obtains test data, and feeds back the electrical signal to the test machine to realize parameter testing of the wafer to be tested, so as to judge the electrical performance of the wafer to be tested.

[0055] In step S2, the site arrangement parameter value of the probe card and the number of the dies to be tested on the wafer to be tested are determined, and a Map corresponding to the wafer to be tested is formed by using the probe machine. The Map includes the coordinates of each die.

[0056] In the embodiment, the site arrangement parameter value of the probe card included in the probe machine can be determined according to the configuration file of the probe machine, for example, 4*9=39 sites, 5*6=30 sites, and the like. Then, the number of the dies to be tested included in the wafer to be tested provided in step S1 is determined, and a Map corresponding to the wafer to be tested is formed by using the probe machine. The Map can include the coordinates of the dies to be tested on the wafer to be tested, or can include the coordinates of the dies not to be tested on the wafer to be tested. In order to distinguish the two, the dies to be tested on the wafer to be tested can be marked with a color different from that of the dies not to be tested. The present application does not make a specific limitation in this regard.

[0057] Step S3, according to the preset arrangement algorithm and the die arrangement parameter value of the probe card, dividing all the dies in the Map graph containing the to-be-tested dies into multiple Touchdown arrangement combinations.

[0058] In the embodiment, after the Map graph corresponding to the to-be-tested wafer is formed by using the above step S2, all the dies (including the to-be-tested dies and the non-to-be-tested dies) in the Map graph corresponding to the to-be-tested wafer are divided by using the Touchdown arrangement algorithm provided by the present application, and then multiple Touchdowns are formed, and each Touchdown is a single minimum test unit for wafer testing in the following step S4.

[0059] Specifically, the present application further provides a specific step for dividing all the dies in the Map graph containing the to-be-tested dies into multiple Touchdown arrangement combinations according to the preset arrangement algorithm and the die arrangement parameter value of the probe card in the above step S3:

[0060] Step S3.1, according to the die arrangement parameter value of the probe card, randomly dividing all the dies in the Map graph containing the to-be-tested dies into multiple arrangement combinations of equal size of each Touchdown. Wherein, the size of each Touchdown is equal to the die arrangement parameter value of the probe card.

[0061] In the embodiment, according to the die arrangement parameter value of the probe card, for example, 4*9=39 site, all the dies in the Map graph containing the to-be-tested dies are randomly divided into multiple Touchdowns with a size of 4*9 (4 rows and 9 columns). For example, the present application said randomly means that it can start from the first die in the first row and the first column in the Map graph corresponding to the to-be-tested wafer (at this time, the die can be a to-be-tested die or a non-to-be-tested die), and divide all the dies in the Map graph corresponding to the to-be-tested wafer according to the size of 4*9=39 site, so as to obtain a Touchdown arrangement combination, for example, the arrangement combination shown in the figure, that is, 21 Touchdowns are formed; then, starting from the first (or several) die in the second row and the second column (or other row and other column) in the Map graph corresponding to the to-be-tested wafer (at this time, the die can be a to-be-tested die or a non-to-be-tested die), all the dies in the Map graph corresponding to the to-be-tested wafer are divided according to the size of 4*9=39 site, so as to obtain another Touchdown arrangement combination, for example, 19 or 20 Touchdowns are formed, and the like can obtain all the possible arrangement combinations of the Map graph corresponding to the to-be-tested wafer. Figure 1 ​

[0062] Step S4, finding the best arrangement of the multiple Touchdowns corresponding to the Map of the wafer to be tested from each arrangement combination containing multiple Touchdowns, and testing the wafer to be tested according to the best arrangement of the Touchdowns.

[0063] In the embodiment, one of the multiple arrangement combinations of the multiple Touchdowns can be selected according to the actual test situation, and then the wafer to be tested is tested according to the arrangement order of the Touchdowns in the selected arrangement combination of the Touchdowns, for example, Figure 2 the numbers 1-21 in FIG. 1, Figure 3 and Figure 4 the numbers 1-19 in FIG. 1.

[0064] For example, in the embodiment, the best arrangement of the multiple Touchdowns corresponding to the Map of the wafer to be tested in the step S4 can be the arrangement of the least number of Touchdowns corresponding to the Map of the wafer to be tested, for example Figure 2 or Figure 3 as shown. Wherein Figure 2 is a structural schematic diagram of the arrangement of the multiple Touchdowns corresponding to the Map of the wafer to be tested formed by the prior art, Figure 3 is a structural schematic diagram of the arrangement of the least number of Touchdowns corresponding to the Map of the wafer to be tested provided in the embodiment of the present application. According to Figure 2 and Figure 3 it can be known that in the embodiment of the present application, the wafer to be tested is first divided into multiple arrangement combinations of multiple Touchdowns according to the random die arrangement parameter values of the probe card, and then the arrangement combination of the least number of Touchdowns (the arrangement of the least number of Touchdowns) is selected from all the arrangement combinations, and then the wafer to be tested is tested according to the arrangement order. The prior art does not select the arrangement combination of the Touchdowns, that is, the wafer to be tested is placed in one Touchdown in the embodiment of the present application, instead of being placed in multiple Touchdowns, so as to achieve the purpose of reducing the wafer test time.

[0065] Specifically, after the step S4 traverses each arrangement combination containing multiple Touchdowns and finds the arrangement of the least number of Touchdowns corresponding to the Map of the wafer to be tested, the wafer test method provided by the present application can further include the following steps:

[0066] Step S4.1: Adjust the arrangement order of multiple Touchdowns according to the temperature of the probe card, so that Touchdowns containing only the dies to be tested and Touchdowns containing both the dies to be tested and dies not to be tested are tested alternately.

[0067] In this embodiment, after selecting the Touchdown arrangement with the fewest probe card steps using step S4, if it is desired to further reduce the impact of different temperatures during wafer testing on test data and efficiency, the Touchdown arrangement with the fewest probe card steps can be adjusted. For example, from... Figures 2 to 3 This refers to the arrangement of TouchDowns after adjusting the order of multiple TouchDowns, from... Figure 3 As can be seen from the arrangement of the Touchdowns shown, in this embodiment of the invention, by adjusting the order of multiple Touchdowns, the Touchdowns that include all the dies to be tested and the Touchdowns that include both dies and non-dies to be tested are tested alternately. This allows each probe to be fully preheated or precooled, avoiding the influence of probe instrument temperature changes on the test data during the test, thereby improving the wafer testing efficiency.

[0068] It should be noted that the appendix provided by this invention... Figure 2 , 3 In section 4, the 4x9 box represents a Touchdown, and the number marked within each Touchdown is its sequence number, i.e., the test number. In the attached diagram, each small square marked with the number "1" in the darker area represents a die to be tested, while small squares of the same size as the die to be tested but not marked with the number "1" are non-die to be tested. Furthermore, the attached diagram... Figure 2 , 3 The coordinates of the core are marked on the four sides of section 4.

[0069] In addition, such as Figure 5 As shown, the present invention also provides a wafer testing apparatus, which can be applied to a prober station for multi-point testing of multiple dies on a wafer. The prober station includes probe cards. Specifically, the testing apparatus may include:

[0070] The parameter determination module 510 is used to determine the die arrangement parameter value of the probe card and the number of the die to be tested among the multiple dies contained on the wafer to be tested based on the provided wafer to be tested.

[0071] Map module 520 is configured to form a Map corresponding to the wafer to be tested by using the probe machine, wherein the Map includes coordinates of each die.

[0072] Touchdown arrangement combination module 530 is configured to divide all the dies including the dies to be tested in the Map into a plurality of Touchdown arrangement combinations according to a preset arrangement algorithm and die arrangement parameter values of the probe card.

[0073] Test module 540 is configured to find a best arrangement mode of a plurality of Touchdowns corresponding to the Map of the wafer to be tested by traversing each Touchdown arrangement combination including a plurality of Touchdowns, and test the wafer to be tested in the best arrangement mode of the Touchdown.

[0074] In some embodiments, the Touchdown arrangement combination module 530 can be specifically configured to:

[0075] According to the die arrangement parameter values of the probe card, randomly divide all the dies including the dies to be tested in the Map into a plurality of Touchdown arrangement combinations, each of which has an equal size.

[0076] Further, the best arrangement mode of the plurality of Touchdowns corresponding to the Map of the wafer to be tested determined by the test module 540 is an arrangement mode with the least number of Touchdowns corresponding to the Map of the wafer to be tested.

[0077] In some embodiments, the test device can further include:

[0078] Touchdown arrangement adjustment module 550 is configured to adjust an arrangement order of the plurality of Touchdowns according to a temperature of the probe card, so that a Touchdown including only the dies to be tested and a Touchdown including the dies to be tested and non-dies to be tested are alternately tested.

[0079] In summary, in the wafer testing method provided by the present application, all dies containing dies to be tested in a Map diagram formed by a probe machine are first divided into multiple Touchdown arrangement combinations according to the die arrangement parameter values of a probe card randomly, then, the Touchdown arrangement combination with the least number of Touchdowns (the arrangement mode with the least number of Touchdowns) is selected from all the arrangement combinations, and then, the wafer to be tested is tested according to the arrangement order. Since the testing method provided by the present application does not use the default Touchdown calculation method of the probe machine, but uses the random combination and selection of the least arrangement combination, the dies to be tested in one Touchdown test can be placed in one Touchdown instead of multiple Touchdowns, thereby achieving the purpose of reducing the wafer test time.

[0080] Further, in the testing method provided by the present application, after the Touchdown arrangement combination with the least number of Touchdowns is selected, the arrangement order of multiple Touchdowns can also be selected according to the preheating and precooling characteristics of the high-low temperature probe card, so that the Touchdowns containing only dies to be tested and the Touchdowns containing dies to be tested and dies not to be tested are tested alternately, thereby avoiding the problem of abnormal test data caused by the change of the state of the probe needle tip of the probe card due to the long-time absence of the probe needle tip in the test area.

[0081] The electronic device provided by the present application also includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete the communication among each other through the communication bus.

[0082] The memory is used to store a computer program.

[0083] The processor is used to execute the program stored on the memory, and realize the wafer testing method provided by the present application.

[0084] In addition, the other implementation modes of the wafer testing method realized by the processor executing the program stored on the memory are the same as the implementation modes mentioned in the foregoing method embodiment part, and will not be repeated here.

[0085] The communication bus mentioned by the control terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0086] The communication interface is used for communication between the electronic device and other devices.

[0087] The memory can include a Random Access Memory (RAM) and can also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory can also be at least one storage device located away from the aforementioned processor.

[0088] The processor mentioned above can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; can also be a Digital Signal Processing (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0089] In still another embodiment provided by the application, a computer readable storage medium is also provided, and the computer readable storage medium stores instructions, when the instructions run on a computer, the computer executes the wafer testing method in any of the above embodiments.

[0090] In the embodiments described above, all or some of the steps can be implemented by software, hardware or firmware, or any combination thereof. When implemented by software, all or some of the steps can be implemented in the form of one or more computer programs. The computer program can be stored in any computer readable medium, and loaded into the computer for execution. The computer readable medium includes computer storage media and communication media. The computer storage media includes any tangible or physical medium for storing or transmitting the program. The computer storage media can be a volatile (e.g., RAM) or non-volatile (e.g., ROM, disk, or CD) storage medium. The communication media typically include computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and includes any information delivery media. The computer readable media does not include carrier waves or other transient signals.

[0091] It should be noted that, in the present document, the terms such as first and second are used only to differentiate one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Also, the terms "comprising", "containing", or any other similar term are intended to encompass non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not necessarily include those elements only, but can include other elements not expressly listed, or can include elements inherent in such process, method, article or apparatus. Without more limitations, an element defined by the phrase "comprising a" does not exclude the existence of additional identical elements in the process, method, article or apparatus that includes the element.

[0092] Each of the embodiments in the present document is described in a related manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device, electronic device and computer readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0093] The above merely provides the preferred embodiments of the application, and not intended to limit the protection scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall fall within the protection scope of the application.

Claims

1. A method for testing a wafer, applied in a multi-point test of a plurality of dies on the wafer by a probe machine, the probe machine comprising a probe card, the method comprising: The test method comprises: ​ Step S1, providing a wafer to be tested, the wafer to be tested comprising a plurality of dies; Step S2, determining the die arrangement parameter value of the probe card and the number of dies to be tested on the wafer to be tested, and forming a Map corresponding to the wafer to be tested by using the probe machine, the Map comprising the coordinates of each die; Step S3, according to a preset arrangement algorithm and the die arrangement parameter value of the probe card, dividing all the dies comprising dies to be tested in the Map into a plurality of arrangement combinations of Touchdowns; Step S4, traversing each arrangement combination comprising a plurality of Touchdowns, finding the optimal arrangement mode of the plurality of Touchdowns corresponding to the Map of the wafer to be tested, and testing the wafer to be tested in the optimal arrangement mode of the Touchdowns; and According to the temperature of the probe card, adjusting the arrangement order of the plurality of Touchdowns, so that the Touchdowns comprising dies to be tested and the Touchdowns comprising dies to be tested and non-dies to be tested are tested alternately; In step S4, the optimal arrangement mode of the plurality of Touchdowns corresponding to the Map of the wafer to be tested is the arrangement combination of the Touchdowns with the least number of steps of the probe card.

2. The wafer testing method of claim 1, wherein In step S3, according to the preset arrangement algorithm and the die arrangement parameter value of the probe card, the step of dividing all the dies comprising dies to be tested in the Map into a plurality of arrangement combinations of Touchdowns comprises: According to the die arrangement parameter value of the probe card, randomly dividing all the dies comprising dies to be tested in the Map into a plurality of arrangement combinations of Touchdowns, each Touchdown having an equal size.

3. The method of claim 2, wherein the test is performed on the wafer while the wafer is in the test chamber. The size of each Touchdown is equal to the die arrangement parameter value of the probe card.

4. The method of claim 1, wherein In step S4, the optimal arrangement mode of the plurality of Touchdowns corresponding to the Map of the wafer to be tested is the arrangement mode with the least number of Touchdowns corresponding to the Map of the wafer to be tested.

5. A testing apparatus for a wafer, applied in a multi-point testing of a plurality of dies on the wafer by a probe machine, the probe machine comprising a probe card, characterized in that, The test device comprises: A parameter determination module for determining the die arrangement parameter value of the probe card and the number of dies to be tested in the plurality of dies comprising the wafer to be tested according to the provided wafer to be tested; A Map forming module for forming a Map corresponding to the wafer to be tested by using the probe machine, the Map comprising the coordinates of each die; A Touchdown arrangement combination forming module for dividing all the dies comprising dies to be tested in the Map into a plurality of arrangement combinations of Touchdowns according to a preset arrangement algorithm and the die arrangement parameter value of the probe card; A test module for traversing each arrangement combination comprising a plurality of Touchdowns, finding the optimal arrangement mode of the plurality of Touchdowns corresponding to the Map of the wafer to be tested, and testing the wafer to be tested in the optimal arrangement mode of the Touchdowns; and A Touchdown arrangement combination forming module for dividing all the dies comprising dies to be tested in the Map into a plurality of arrangement combinations of Touchdowns according to a preset arrangement algorithm and the die arrangement parameter value of the probe card; The Touchdown arrangement adjustment module is configured to adjust arrangement orders of a plurality of Touchdowns according to a temperature of the probe card, so that Touchdowns containing dies to be tested and Touchdowns containing dies including non-to-be-tested dies are alternately tested. The optimal arrangement mode of the plurality of Touchdowns corresponding to the Map of the wafer to be tested in the testing module is an arrangement combination of the Touchdowns with the least number of steps of the probe card.

6. The wafer testing apparatus of claim 5, wherein The Touchdown arrangement combination forming module is specifically configured to: According to the die arrangement parameter value of the probe card, randomly divide all the dies containing dies to be tested in the Map into a plurality of arrangement combinations each having a size equal to that of each Touchdown.

7. The wafer testing apparatus of claim 6, wherein The optimal arrangement mode of the plurality of Touchdowns corresponding to the Map of the wafer to be tested determined by the testing module is an arrangement mode with the least number of Touchdowns corresponding to the Map of the wafer to be tested.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement each step of the wafer testing method in any one of claims 1-4.

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