Edge termination of a semiconductor power device, method of manufacturing the same and semiconductor power device

Abstract

The application discloses a kind of semiconductor power device edge terminal and its manufacturing method and semiconductor power device, the edge terminal includes: N floating field limiting ring, floating field limiting ring surrounds the main junction region of semiconductor power device, wherein the junction depth of the first to the n floating field limiting ring is the same with the junction depth of main junction region, the junction depth of the n+i floating field limiting ring is greater than the junction depth of the n floating field limiting ring, and from the n+1 floating field limiting ring, the junction depth of floating field limiting ring gradually increases, N, n, i are positive integers, and 2≤n The edge terminal of the application improves the uniformity of electric field distribution and area of terminal region by optimizing the junction depth and doping distribution of floating field limiting ring, and further improves the terminal efficiency and blocking voltage.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor devices, and relates to an edge termination of a semiconductor power device and a manufacturing method thereof and a semiconductor power device. BACKGROUND

[0002] The most basic requirement of a semiconductor power device is to withstand a large terminal voltage with minimum leakage current in an off state, wherein the maximum terminal voltage that the semiconductor power device can withstand is referred to as a blocking voltage. The blocking voltage is usually determined by material characteristics and device design. The blocking voltage of a power device made by cutting a wafer into chips decreases due to the two-dimensional electric field concentration at the edge of the device, and is usually alleviated by using a special edge termination. The floating field ring termination includes a series of concentric p+ rings (i.e., floating field rings) surrounding the main junction region, which widens the potential distribution in the lateral direction along the surface, reduces the lateral electric field strength, and avoids avalanche breakdown in the main junction region, and is a technique for edge termination. However, in the existing conventional floating field ring termination, since the floating field rings have the same junction depth, the uniformity of the electric field distribution in the drift region is poor, and the electric field distribution area is small, resulting in low terminal efficiency and blocking voltage. In addition, other researchers have proposed edge terminations of other structures, in which the junction depth of the field limiting ring gradually decreases away from the main junction region (functional region). However, simulation results of the field limiting ring with gradually decreasing junction depth show that, as the junction depth of the field limiting ring gradually decreases, the blocking voltage decreases, resulting in lower terminal efficiency and blocking voltage than the floating field ring with the same junction depth. Therefore, how to improve the terminal efficiency and the blocking voltage is still a technical problem that needs to be solved by those skilled in the art at this stage, which is of great significance for promoting the wide application of semiconductor power devices. SUMMARY

[0003] The technical problem to be solved by the present application is to overcome the shortcomings of the prior art, and to provide an edge termination of a semiconductor power device, which optimizes the junction depth and doping distribution of the floating field ring, so that the uniformity of the electric field distribution in the drift region is better, and the electric field distribution area is larger, thereby facilitating the improvement of the terminal efficiency and the blocking voltage, and further provides a manufacturing method of the edge termination of the semiconductor power device and a semiconductor power device.

[0004] To solve the above technical problems, the present application adopts the following technical solutions:

[0005] An edge termination of a semiconductor power device, comprising:

[0006] N floating field rings, the floating field rings surrounding a main junction region of the semiconductor power device;

[0007] The junction depth of the first to the n-th floating field limit ring is the same as the junction depth of the main junction region, the junction depth of the n+i-th floating field limit ring is greater than the junction depth of the n-th floating field limit ring, and the junction depth of the floating field limit ring gradually increases from the n+1-th floating field limit ring, N, n, and i are positive integers, and 2≤n

[0008] The edge termination of the semiconductor power device is further improved, the first floating field limit ring surrounds the main junction region of the semiconductor power device, the n-th floating field limit ring surrounds the n-1-th floating field limit ring, and the n+i-th floating field limit ring surrounds the n+i-1-th floating field limit ring.

[0009] The edge termination of the semiconductor power device is further improved, the junction depth of the n+i-th floating field limit ring is the junction depth of the n-th floating field limit ring + i×step length, and the unit is μm; the step length is 0.1 μm-30 μm.

[0010] The edge termination of the semiconductor power device is further improved, the junction depth of the n-th floating field limit ring is 0.8 μm-1.3 μm.

[0011] The edge termination of the semiconductor power device is further improved, the doping distribution of the first to the n-th floating field limit ring is the same as that of the main junction region; the peak doping concentration of the floating field limit ring is 5e17 cm -3 -5e20 cm -3 .

[0012] As a general technical concept, the application also provides a manufacturing method of the edge termination of the semiconductor power device, comprising the following steps: forming a main junction region and floating field limit rings successively surrounding the main junction region in a drift region of a semiconductor substrate.

[0013] The manufacturing method is further improved, and the main junction region and the floating field limit rings successively surrounding the main junction region are prepared in the drift region of the semiconductor substrate by using photolithography and ion implantation processes.

[0014] The manufacturing method is further improved, and before the preparation by using the photolithography and ion implantation processes, the following treatment is further included: using photolithography and etching processes to groove the surface of the drift region where the floating field limit rings are located.

[0015] The manufacturing method is further improved, and an epitaxial process is used to prepare the drift region on the semiconductor substrate.

[0016] As a general technical concept, the application also provides a semiconductor power device comprising the edge termination of the semiconductor power device.

[0017] The semiconductor power device further comprises a semiconductor substrate, a drift region, a source metal and a drain metal; the semiconductor substrate comprises silicon, germanium silicon, gallium arsenide, silicon carbide, gallium nitride, gallium sesquioxide or diamond.

[0018] Compared with the prior art, the semiconductor power device has the advantages that:

[0019] The edge termination of the semiconductor power device comprises a floating field limiting ring close to the main junction region and having the same junction depth as the main junction region, and another part of the floating field limiting ring far from the main junction region and having a gradually increasing junction depth deeper than that of the main junction region, the curvature radius of the floating field limiting ring is increased by optimizing the junction depth and the doping distribution of the floating field limiting ring, the uniformity and area of the electric field distribution of the termination region are improved, and the termination efficiency and blocking voltage are improved. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application.

[0021] Figure 1 It is a sectional structure schematic diagram of the edge termination of the prior semiconductor power device.

[0022] Figure 2 It is a sectional structure schematic diagram of the edge termination of the semiconductor power device in Embodiment 1 of the present application.

[0023] Figure 3 It is a preparation process flow chart of the edge termination of the semiconductor power device in Embodiment 1 of the present application.

[0024] Figure 4 It is an electric field distribution simulation diagram of the edge termination of the prior semiconductor power device.

[0025] Figure 5 It is an electric field distribution simulation diagram of the edge termination of the semiconductor power device in Embodiment 1 of the present application.

[0026] Figure 6 It is an electric field distribution simulation diagram of the edge termination of the semiconductor power device in Embodiment 2 of the present application.

[0027] Figure 7 It is an electric field distribution simulation diagram of the edge termination of the semiconductor power device in Embodiment 3 of the present application.

[0028] Figure 8 It is an electric field distribution simulation diagram of the edge termination of the semiconductor power device in Embodiment 4 of the present application.

[0029] Figure 9This is a comparison diagram of the blocking voltages corresponding to the existing edge terminals of the semiconductor power devices in Embodiments 1-4 of the present invention.

[0030] Figure 10 The above is a simulation diagram of the electric field distribution at the edge terminal of the semiconductor power device in Comparative Example 1.

[0031] Figure 11 The above is a simulation diagram of the electric field distribution at the edge terminal of the semiconductor power device in Comparative Example 2.

[0032] Figure 12 The electric field curves of the edge terminals of the semiconductor power devices in Comparative Examples 1 and 2 are shown.

[0033] Figure 13 The potential curve distribution diagrams of the edge terminals of the semiconductor power devices in Comparative Examples 1 and 2 are shown.

[0034] Figure 14 This is a cross-sectional view of the edge terminal of the semiconductor power device in Embodiment 5 of the present invention.

[0035] Legend:

[0036] 1. Silicon carbide N-type substrate; 2. N-type drift region; 310. P-type main junction region; 311. First floating field confinement ring; 312. Second floating field confinement ring; 31 n The nth floating field confinement loop; 31 n+i The (n+i)th floating field limit loop; 32 n+i 1. The (n+i)th trench; 4. Source metal; 5. Drain metal. Detailed Implementation

[0037] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0038] like Figure 1 As shown, the edge termination of existing semiconductor power devices mainly includes a main junction region 310 and a series of concentric p+ rings (i.e., floating field limiting rings 311-312) surrounding the main junction region. n (where n is a positive integer and ≥2), and these floating field confinement loops are 311~31 n The junction depth and doping distribution are the same as those of the main junction region 310. The defect of this edge terminal is that the electric field distribution uniformity in the drift region is poor and the electric field distribution area is small. As a result, the terminal efficiency and blocking voltage are still low.

[0039] Aiming at the defects existing in the edge termination of the existing semiconductor power device, the application aims to provide an edge termination with good drift region electric field distribution uniformity and large electric field distribution area, so as to improve the terminal efficiency and blocking voltage. Specifically, the floating field limiting ring is improved in the application, and the junction depth and the doping distribution of the floating field limiting ring are optimized to optimize the uniformity and the distribution area of the electric field in the drift region, thereby improving the terminal efficiency and the blocking voltage. Figure 2 As shown in the figure, an improved edge termination of a semiconductor power device is provided in the application, which comprises N floating field limiting rings, wherein the first floating field limiting ring 311 surrounds the main junction region 310 of the semiconductor power device, the nth floating field limiting ring 31n surrounds the (n-1)th floating field limiting ring 31n-1 (such as the 6th floating field limiting ring 316 surrounding the 5th floating field limiting ring 315), and the (n+i)th floating field limiting ring surrounds the (n+i-1)th floating field limiting ring (such as the 13th floating field limiting ring 31 6+7 surrounds the 12th floating field limiting ring 31 6+6) N, n, i are positive integers (such as N can be 17, n can be 1-6, i can be 1-11, the values of N, n, i are selected according to the actual situation, this place will not limit the values of N, n, i, any value that can improve the uniformity and distribution area of the electric field is used in the application), and 2≤n n The junction depth and the doping distribution of the main junction 310 are the same, and the junction depth of the floating field limiting ring gradually deepens from 31 n+1 (the position near the inclination of the space charge region of the drift region, as shown in the figure), which increases the corresponding curvature radius, changes the electric field distribution of the terminal region, and improves the terminal efficiency and the blocking voltage. Figure 4

[0040] As a further improved technical solution, the junction depth of the floating field limiting ring is further optimized in the application. Specifically, the junction depth of the (n+i)th floating field limiting ring is the junction depth of the nth floating field limiting ring+i×step length, and the unit is μm, wherein the step length is 0.1 μm-30 μm. Specifically, the junction depth Xj n+1 of the floating field limiting ring 31 (31n+1) is the junction depth Xj n of the floating field limiting ring 31 (31n) +1×step length, the junction depth Xj n+2 of the floating field limiting ring 31 (31n+2) is the junction depth Xj n of the floating field limiting ring 31 (31n) ​+2x step size…and so on, the floating field limit ring 31 n+i the junction depth Xj of the floating field limit ring 31 (31n+i) = the junction depth Xj of the floating field limit ring 31 n the junction depth Xj of the floating field limit ring 31 (31n) +i x step size. In the present application, starting from the (n+1)th floating field limit ring 31 n+1 , the junction depth of the floating field limit ring gradually increases in the corresponding proportion, and the arrangement of the floating field limit ring thus obtained is more conducive to forming a more uniform and larger-area electric field in the drift region, thereby being able to more significantly improve the blocking voltage.

[0041] In the present application, the junction depth of the first to nth floating field limit rings is 0.8 μm to 1.3 μm; the junction depth and the doping distribution of the first to nth floating field limit rings are the same as those of the main junction region; the peak doping concentration of the floating field limit ring is 5e17 cm -3 ~5e20 cm -3 .

[0042] In the present application, a manufacturing method of an edge termination of a semiconductor power device is also provided, which comprises the following steps: forming a main junction region and floating field limit rings successively surrounding the main junction region in a drift region of a semiconductor substrate.

[0043] In the present application, the main junction region and the floating field limit rings successively surrounding the main junction region are prepared in the drift region of the semiconductor substrate by using a photolithography and ion implantation process; and the drift region is prepared on the semiconductor substrate by using an epitaxy process.

[0044] In the present application, in order to better realize the doping treatment of the region where the floating field limit ring is located, before the preparation (doping) by using the photolithography and ion implantation process, the following treatment is further included: a photolithography and etching process is used to groove the surface of the drift region where the floating field limit ring is located. For example, when the doping depth of the ion implantation equipment used is 3 μm, in order to better prepare a floating field limit ring with a junction depth of 3.2 μm, it is necessary to first groove the surface of the drift region where the floating field limit ring is located by using a photolithography and etching process, wherein the depth of the groove is 0.2 μm, and the width of the groove is the same as that of the corresponding floating field limit ring. In the present application, only the above case is described, and the process of the present application is not limited thereto. If the doping depth of the ion implantation equipment used can achieve the purpose of ion implantation / doping, the grooving treatment is not required additionally.

[0045] In the present application, a semiconductor power device is also provided, which comprises the above-described edge termination, and further comprises a semiconductor substrate, a drift region, a source metal and a drain metal, wherein the semiconductor substrate comprises silicon, germanium silicon, gallium arsenide, silicon carbide, gallium nitride, gallium sesquioxide or diamond.

[0046] The present application will be further described below in conjunction with specific embodiments.

[0047] Example 1

[0048] like Figure 2 As shown, an edge terminal of a semiconductor power device includes: N floating field limiting rings, wherein the first floating field limiting ring surrounds the main junction region of the semiconductor power device, the nth floating field limiting ring surrounds the (n-1)th floating field limiting ring, and the (n+i)th floating field limiting ring surrounds the (n+i-1)th floating field limiting ring, where N can be 17, n is 6, and i is 11. Specifically: the first floating field limiting ring 311 surrounds the main junction region 310 of the semiconductor power device, the second floating field limiting ring 312 surrounds the first floating field limiting ring 311, the third floating field limiting ring 313 surrounds the second floating field limiting ring 312, and so on, the sixth floating field limiting ring 316 surrounds the fifth floating field limiting ring 315, and the seventh floating field limiting ring 31... 6+1 Surrounding the 6th airfield confinement ring 316, the 8th airfield confinement ring 31 6+2 31 surrounding the 7th floating field limit ring 6+1 And so on, the 17th floating field limit ring 31 6+11 31 surrounding the 16th floating field limit ring 6+10 Meanwhile, the knot depths of the first to nth floating field limiting rings are the same as the knot depth of the main knot region. The knot depth of the (n+i)th floating field limiting ring is greater than that of the nth floating field limiting ring. Starting from the (n+1)th floating field limiting ring, the knot depth of the floating field limiting rings gradually increases (i.e., the knot depth of the floating field limiting rings gradually increases along the direction away from the main knot region). Specifically, the knot depths of the first to sixth floating field limiting rings (floating field limiting rings 311 to 316) are the same as the knot depth 310 of the main knot region, both being 1.2 μm. The knot depth of the seventh floating field limiting ring 31... 6+1 The knot depth is greater than the knot depth of the 6th floating field limiting ring, and the 7th floating field limiting ring 31 6+1 The knot depth is the knot depth Xj of the 6th floating field limiting ring 316. (316)+1 × step size, where the knot depth Xj of the 6th floating field limiting loop 316 is... (316) The value is 1.2 μm, with a step size of 0.1 μm, which corresponds to the 7th floating field limiting loop 31. 6+1 The depth of the knot Xj (316+1)＝ 1.2μm + 1 × 0.1μm = 1.3μm. Similarly, the knot depth (Xj) of the 8th to 17th floating field confinement loops... (316+2) ~Xj (316+11) The depths are 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2.0μm, 2.1μm, 2.2μm, and 2.3μm respectively, meaning that starting from the 7th floating field limiting ring, their knot depths gradually increase.

[0049] In this embodiment, the doping distribution of the floating field limiting rings 311-316 is the same as that of the main junction region 310, and the peak doping concentration of the floating field limiting rings and the main junction region is 2e18 cm -3 In this application, since the junction depth and the doping distribution of the floating field limiting rings 311-316 are the same as those of the main junction 310, and the junction depth of the floating field limiting rings gradually deepens from 311 6+1 , the uniformity of the electric field distribution in the drift region is better, and the electric field distribution area is larger by optimizing the junction depth and the doping distribution of the floating field limiting rings, thereby improving the terminal efficiency and the blocking voltage.

[0050] In order to more clearly illustrate the present application, a manufacturing method of the edge terminal of the semiconductor power device in the above embodiment is proposed in this application, only the manufacturing method of the floating field limiting ring is described, and a preparation process flow chart thereof is shown in Figure 3 , including the following steps:

[0051] Step 1: An epitaxial process is used to form an N-type drift region 2 on a silicon carbide N-type substrate 1, wherein the resistivity of the N-type substrate 1 is 0.025 Ω·cm, the thickness is 350 μm, the junction depth and the doping concentration of the N-type drift region 2 are 11 μm and 8e15 cm -3 , respectively, as shown in Figure 3 (a).

[0052] Step 2: A photolithography and ion implantation process is used to form a P-type main junction region 310 and P-type floating field limiting rings 311-316 in the N-type drift region 2, and the junction depth of them is 1.2 μm, and the peak doping concentration is 2e18 cm -3 , as shown in Figure 3 (b).

[0053] Step 3: A photolithography and ion implantation process is used to form a P-type floating field limiting ring 31 6+1 in the N-type drift region 2, and the junction depth is 1.3 μm, and the peak doping concentration is 2e18 cm -3 , as shown in Figure 3 (c).

[0054] Step 4: A photolithography and ion implantation process is used to form a P-type floating field limiting ring 31 6+2 in the N-type drift region 2, and the junction depth is 1.4 μm, and the peak doping concentration is 2e18 cm -3 , as shown in Figure 3 (d).

[0055] By analogy, a photolithography and ion implantation process is used to form a P-type floating field limiting ring 31 6+3 -31 6+11, their junction depths are 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, and the peak doping concentration is 2e18cm -3 As shown in FIG. 1, a semiconductor power device edge termination is formed. Figure 3 (e) to obtain the edge termination of the semiconductor power device.

[0056] A semiconductor power device including the edge termination of the above embodiment, including a semiconductor substrate, a drift region formed on the front surface of the semiconductor substrate, and an edge termination formed on the drift region, further including a source metal (anode) formed on the main junction region and a drain metal (cathode) formed on the back surface of the semiconductor substrate, and a cutoff ring is further formed on the drift region.

[0057] In this embodiment, the semiconductor substrate is silicon carbide, the thickness of the N-type drift region is 11 μm, and the doping concentration is 8e15cm -3 .

[0058] In this application, the dimensions in the figures (including lateral dimensions, layout dimensions, medium thickness, metal thickness, junction depth, etc.) do not represent actual dimensions, but only serve as examples of the method of forming the edge termination (floating field limiting ring) structure, and do not constitute a limitation on the technical solutions of the present application, including but not limited to Schottky diode, PiN diode, planar MOSFET, planar IGBT, trench MOSFET, trench IGBT; at the same time, the semiconductor substrate includes but is not limited to SiC, such as Si, germanium silicon, gallium arsenide, gallium nitride, gallium sesquioxide or diamond, etc., which can be used as needed.

[0059] Embodiment 2

[0060] An edge termination of a semiconductor power device is basically the same as that in Embodiment 1, the only difference is that the step size used in Embodiment 2 is 0.2 μm, specifically, the difference is that the junction depths (Xj (316+1) ~ Xj (316+11) ) of the 7th to 17th floating field limiting rings are 1.4 μm, 1.6 μm, 1.8 μm, 2.0 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3.0 μm, 3.2 μm, 3.4 μm.

[0061] Embodiment 3

[0062] An edge termination of a semiconductor power device is basically the same as that in Embodiment 1, the only difference is that the step size used in Embodiment 2 is 0.3 μm, specifically, the difference is that the junction depths (Xj (316+1) ~ Xj (316+11)) are 1.5μm, 1..8μm, 2.1μm, 2.4m, 2.7μm, 3.0μm, 3.3μm, 3.6μm, 3.9μm, 4.2μm, 4.5μm.

[0063] Example 4

[0064] An edge termination for a semiconductor power device is essentially the same as the edge termination in Example 1, except that the step size used in Example 2 is 0.4 μm. Specifically, the difference lies in the junction depth (Xj) of the 7th to 17th floating field limiting loops. (316+1) ~Xj (316+11) The corresponding micrometers are 1.6μm, 2.0μm, 2.4μm, 2.8μm, 3.2μm, 3.6μm, 4.0μm, 4.4μm, 4.8μm, 5.2μm, and 5.6μm, respectively.

[0065] Comparative Example 1

[0066] An edge terminal of a semiconductor power device mainly includes a main junction region 310 and a series of concentric p+ rings (i.e., floating field limiting rings 311-31) surrounding the main junction region. 17 These floating field confinement rings 311-31 17 The junction depth and doping distribution are the same as those of the main junction region 310, with a junction depth of 1 μm and a peak doping concentration of 2e18cm. -3 .

[0067] Comparative Example 2

[0068] An edge terminal of a semiconductor power device mainly includes a main junction region 310 and a series of concentric p+ rings (i.e., floating field limiting rings 311-31) surrounding the main junction region. 17 These floating field confinement rings 311-31 17 The knot depth gradually decreases, with the first field limiting ring having a knot depth of 1 μm, the second 0.95 μm, the third 0.9 μm, and so on, decreasing in increments of 0.05 μm, until the seventeenth field limiting ring has a knot depth of 0.2 μm. Simultaneously, these floating field limiting rings 311–31 17 The peak concentration was the same as that in the main junction region 310, which was 2e18cm. -3 In Comparative Examples 1 and 2, the floating field confinement rings 311 to 31... 17 The ring spacing and ring width are exactly the same.

[0069] The electric field distribution and blocking voltage of the edge terminals of the semiconductor power devices prepared in Examples 1-4 and the existing conventional edge terminals in Comparative Examples 1-2 were simulated. The results are as follows: Figures 4-13 As shown.

[0070] Existing floating field confinement ring 310-31 17 The simulation results of the electric field distribution at the edge terminals with a junction depth of 1.2 μm are as follows: Figure 4 As shown; simulation results of the electric field distribution at the edge terminals of the semiconductor power devices prepared in Examples 1-4, as follows. Figures 5-8 As shown. By Figures 4-8 It can be seen that in existing conventional edge terminals, from the 7th floating field limiting ring 31 6+1 Starting nearby, the space charge region of drift region 2 tilts. In the edge terminals of the semiconductor power devices prepared in Examples 1-4, the structural parameters and ring spacing of drift regions 2, 310-316 of the floating field limiting ring are similar to... Figure 4 The same applies, however, in changing the 7th floating field limit ring 31 6+1 Following the subsequent depth of the floating field confinement ring, as the step size of the floating field confinement ring increases, the space charge region gradually fills the drift region below the field confinement ring, and the electric field distribution fully utilizes the area of ​​the drift region. Simultaneously, due to... Figure 9 As can be seen, with the increase of the step size, starting from the 7th floating field limiting ring in the edge termination of the semiconductor power devices prepared in Examples 1-4, the junction depth of the floating field limiting ring gradually increases, resulting in a significant increase in the blocking voltage. Therefore, in this application, by optimizing the junction depth and doping distribution of the floating field limiting ring, the uniformity of the electric field distribution in the drift region and the distribution area of ​​the electric field can be significantly improved, thereby improving the termination efficiency and blocking voltage.

[0071] Comparative Example 1: Floating Field Confinement Ring 310-31 17 The edge terminals with a junction depth of 1.0 μm and the floating field confinement rings in Comparative Example 2 are 310–31. 17 Simulation results of the electric field distribution at the edge terminals where the junction depth gradually decreases from 1.0 μm to 0.2 μm, such as... Figures 10-13 As shown. By Figures 10-13 It can be seen that in the edge terminal of Comparative Example 1, the blocking voltage of the floating field limiting ring with uniform junction depth is 1546V, while in the edge terminal of Comparative Example 2, the blocking voltage of the floating field limiting ring with gradually decreasing junction depth is 1125V. It can be seen that as the junction depth of the field limiting ring gradually decreases, the blocking voltage shows a downward trend. The blocking voltage of the first floating field limiting ring to the seventeenth floating field limiting ring decreases from 1546V to 1125V. Obviously, the edge terminal with gradually decreasing junction depth of the floating field limiting ring has lower terminal efficiency and blocking voltage.

[0072] Example 5

[0073] It should be further noted that if the equipment used in the ion implantation process can only achieve ion implantation (doping) with a junction depth of 1.5 μm, the method for manufacturing the empty field confinement ring in the above embodiment can be:

[0074] Step 1: Using epitaxial technology, an N-type drift region 2 is formed on a silicon carbide N-type substrate 1. The resistivity of the N-type substrate 1 is 0.025 Ω·cm, and the thickness is 350 μm. The junction depth and doping concentration of the N-type drift region 2 are 11 μm and 8e15 cm, respectively. -3 .

[0075] Step 2: Using photolithography and ion implantation processes, a P-type main junction region 310 and P-type floating field confinement rings 311–316 are formed in the N-type drift region 2. Their junction depth is 1.2 μm, and the peak doping concentration is 2e18cm2. -3 .

[0076] Step 3: Using photolithography and ion implantation processes, a P-type floating field confinement ring 31 is formed in the N-type drift region 2. 6+1 Its junction depth is 1.3 μm, and its peak doping concentration is 2e18cm. -3 .

[0077] Step 4: Using photolithography and ion implantation processes, a P-type floating field confinement ring 31 is formed in the N-type drift region 2. 6+2 Its junction depth is 1.4 μm, and its peak doping concentration is 2e18cm. -3 .

[0078] Step 5: Using photolithography and ion implantation processes, a P-type floating field confinement ring 31 is formed in the N-type drift region 2. 6+3 Its junction depth is 1.5 μm, and its peak doping concentration is 2e18cm. -3 .

[0079] Step 6: Using photolithography and etching processes, grooves 0.1 μm deep are created on the surface of the N-type drift region 2 to form trench 32. 6+4 Then, using photolithography and ion implantation processes, trenches 32 are created on the surface of the N-type drift region 2. 6+4 The location forms a P-shaped floating field confinement loop 31 6+4 Its junction depth is 1.6 μm and its peak doping concentration is 2e18cm. -3 .

[0080] Step 7: Using photolithography and etching processes, grooves 0.2 μm deep are created on the surface of the N-type drift region 2 to form trench 32. 6+5 Then, using photolithography and ion implantation processes, trenches 32 are created on the surface of the N-type drift region 2. 6+5 The location forms a P-shaped floating field confinement loop 31 6+5 The junction depth is 1.7 μm, and the peak doping concentration is 2e18cm. -3 .

[0081] Similarly, using photolithography and etching processes, trenching is performed in the N-type drift region 2, with depths of 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, and 0.8μm respectively, forming trenches 32. 6+6～ 32 6+11 Then, using photolithography and ion implantation processes, trenches 32 are created on the surface of the N-type drift region 2. 6+6～ 32 6+11 The locations respectively form P-shaped floating field confinement loops 31 6+3 ~31 6+11 Their junction depths are 1.8 μm, 1.9 μm, 2.0 μm, 2.1 μm, 2.2 μm, and 2.3 μm, respectively, and their peak doping concentrations are all 2e18cm. -3 The edge terminals of the resulting semiconductor power devices, such as Figure 14 As shown. In this application, it is possible to choose whether or not to perform grooving treatment on the surface of the drift region, which makes the manufacturing process of preparing the floating field limiting ring of this application more adaptable and able to prepare a floating field limiting ring that meets the requirements according to actual needs.

[0082] In summary, the edge terminal of the semiconductor power device of the present invention optimizes the junction depth and doping distribution of the floating field limiting ring, increases the radius of curvature of the floating field limiting ring, improves the uniformity and area of ​​the electric field distribution in the terminal region, and thus improves the terminal efficiency and blocking voltage.

[0083] The above embodiments are merely preferred embodiments of the present invention, and the scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. An edge terminal for a semiconductor power device, characterized in that, include: N floating field confinement rings surround the main junction region of the semiconductor power device; The junction depth of the first to nth floating field confinement rings is the same as that of the main junction region. The junction depth of the (n+i)th floating field confinement ring is greater than that of the nth floating field confinement ring. Starting from the (n+1)th floating field confinement ring, the junction depth of the floating field confinement rings gradually increases. N, n, and i are positive integers, and 2 ≤ n < n+i ≤ N. The doping distribution of the first to nth floating field confinement rings is the same as that of the main junction region. The peak doping concentration of the floating field confinement rings is 5e17 cm⁻¹. -3 ~5e20 cm -3 .

2. The edge terminal of the semiconductor power device according to claim 1, characterized in that, The knot depth of the (n+i)th floating field limiting ring is the knot depth of the nth floating field limiting ring + i × step size, in μm; the step size is 0.1μm to 30μm.

3. The edge terminal of the semiconductor power device according to claim 2, characterized in that, The knot depth of the nth floating field limiting ring is 0.8μm to 1.3μm.

4. A method for manufacturing an edge terminal of a semiconductor power device as described in any one of claims 1 to 3, characterized in that, Includes the following steps: A main junction region and a floating field confinement ring are formed in the drift region of the semiconductor substrate.

5. The manufacturing method according to claim 4, characterized in that, A main junction region and a floating field confinement ring that surrounds the main junction region are fabricated in the drift region of a semiconductor substrate using photolithography and ion implantation processes.

6. The manufacturing method according to claim 5, characterized in that, Before fabrication using photolithography and ion implantation processes, the following treatment is also included: using photolithography and etching processes to perform grooving on the surface of the drift region where the floating field limiting ring is located.

7. The manufacturing method according to claim 5 or 6, characterized in that, The drift region is prepared on a semiconductor substrate using an epitaxial process.

8. A semiconductor power device, characterized in that, The edge terminal of the semiconductor power device as described in any one of claims 1 to 3.

9. The semiconductor power device according to claim 8, characterized in that, The semiconductor power device further includes a semiconductor substrate, a drift region, a source metal, and a drain metal; the semiconductor substrate includes silicon, germanium silicon, gallium arsenide, silicon carbide, gallium nitride, gallium trioxide, or diamond.

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