Serial peripheral interface SPI system and data transmission method thereof

Abstract

The present application discloses a serial peripheral interface SPI system and a data transmission method thereof, wherein the serial peripheral interface system includes a plurality of slave devices and a master device. The master device includes a chip selection control circuit and a chip selection mode selection circuit. The chip selection control circuit generates a first selection signal and a second selection signal. The chip selection mode selection circuit couples the chip selection control circuit and the dynamic chip selection pin circuit, and determines whether to select the dynamic chip selection pin circuit according to the first selection signal to select the chip selection pin. When the dynamic chip selection pin circuit is selected, the chip selection control circuit transmits a second selection signal to the dynamic chip selection pin circuit to select the above-mentioned chip selection pin from a plurality of chip selection pins, and transmits data to one of a plurality of slave devices corresponding to the selected chip selection pin. The serial peripheral interface system and data transmission method proposed by the present invention can avoid wasting pins.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to a serial peripheral interface (SPI) technology, and more particularly to a SPI technology for dynamically selecting chip select pins. Background Art

[0002] The Serial Peripheral Interface Bus (SPI) is a synchronous serial communication interface specification for chip communication. SPI is widely used in the field of single-chip (SoC) and microcontroller (MCU).

[0003] In current Serial Peripheral Interface (SPI) technology, when a master device connects to a slave device, one of the master device's SPI master ports is configured with a chip select pin to connect to a slave device. However, when a master device connects to multiple slave devices, the master device often must configure multiple SPI master ports, resulting in wasted pins. Summary of the Invention

[0004] In view of the above-mentioned problems in the background art, embodiments of the present invention provide a serial peripheral interface (SPI) system and a data transmission method.

[0005] According to one embodiment of the present invention, a serial peripheral interface system is provided. The serial peripheral interface system includes multiple slave devices and a master device. The master device includes a chip select control circuit and a chip select mode selection circuit. The chip select control circuit is used to generate a first selection signal and a second selection signal. The chip select mode selection circuit is coupled to the chip select control circuit and a dynamic chip select pin circuit, and determines whether to select the dynamic chip select pin circuit according to the first selection signal to select a chip select pin. When the dynamic chip select pin circuit is selected, the chip select control circuit transmits the second selection signal to the dynamic chip select pin circuit to select the chip select pin from multiple chip select pins, and transmits data to one of the multiple slave devices corresponding to the selected chip select pin.

[0006] In some embodiments, the chip selection mode selection circuit is further coupled to a static chip selection pin circuit, and the chip selection mode selection circuit decides to select the static chip selection pin circuit or the dynamic chip selection pin circuit according to the first selection signal to select the chip selection pin.

[0007] In some embodiments, the static chip select pin circuit, the dynamic chip select pin circuit, and the plurality of chip select pins are included in a universal input / output interface.

[0008] In some embodiments, the host device further includes a control interface, and the chip selection control circuit generates the first selection signal according to a control signal output from the control interface.

[0009] In some embodiments, the host device further includes a memory interface, and the chip select control circuit generates the second selection signal according to a determination result generated from the memory interface.

[0010] In some embodiments, the master device further includes a logic circuit to output data to be transmitted to the slave device corresponding to the selected chip select pin.

[0011] According to one embodiment of the present invention, a data transmission method is provided. The data transmission method is applicable to a serial peripheral interface (SPI) system. The data transmission method includes the following steps: generating a first selection signal by a chip select control circuit of a master device of the SPI system; determining whether to select a dynamic chip select pin circuit of the SPI system based on the first selection signal by a chip select mode selection circuit of the master device to select a chip select pin; when the dynamic chip select pin circuit is selected, transmitting a second selection signal to the dynamic chip select pin circuit by the chip select control circuit to select the chip select pin from multiple chip select pins of the SPI system; and transmitting data to one of multiple slave devices of the SPI system corresponding to the selected chip select pin.

[0012] The serial peripheral interface system and data transmission method proposed in the present invention utilize a dynamic chip select pin circuit to select the static chip select pin corresponding to the slave device with which communication is desired. Therefore, in the serial peripheral interface system proposed in the present invention, the master device only needs to configure a single set of master ports to achieve the goal of switching between different static chip select pins. Consequently, the serial peripheral interface system and data transmission method proposed in the present invention avoids wasted pins.

[0013] Regarding other additional features and advantages of the present invention, those skilled in the art may make slight changes and modifications based on the serial peripheral interface system and data transmission method disclosed in the implementation method of this case without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1FIG. 2 is a block diagram illustrating a serial peripheral interface system 100 according to an embodiment of the present invention.

[0015] Figure 2 is a flowchart of a data transmission method according to an embodiment of the present invention.

[0016] Reference numerals

[0017] 100: Serial Peripheral Interface System

[0018] 110: Advanced Microcontroller Bus Architecture

[0019] 120: Main device

[0020] 121: Memory Interface

[0021] 122: Control interface

[0022] 123: Logic Circuits

[0023] 124: Chip selection control circuit

[0024] 125: Chip selection mode selection circuit

[0025] 130: Universal input and output interface

[0026] 131: Static chip selection pin circuit

[0027] 132: Dynamic chip selection pin circuit

[0028] 140: First slave device

[0029] 150: Second slave device

[0030] MISO: Master input slave output pin

[0031] MISO1: Master input and slave output port

[0032] MOSI: Master output and slave input pin

[0033] MOSI1: Master output slave input port

[0034] CLK: clock pin

[0035] CLK1: Clock output port

[0036] CS0: First chip selection pin

[0037] CS1: Second chip selection pin

[0038] nCS: Chip Select Port

[0039] S1: Judgment result

[0040] S2: control signal

[0041] S3: First selection signal

[0042] S4: Second selection signal

[0043] S210~S250: Steps DETAILED DESCRIPTION

[0044] This section describes the preferred method of implementing the present invention, which is intended to illustrate the spirit of the present invention rather than to limit the scope of protection of the present invention. The scope of protection of the present invention must refer to the scope defined in the appended claims.

[0045] Figure 1 FIG. 1 is a block diagram showing a serial peripheral interface (SPI) system 100 according to an embodiment of the present invention. Figure 1 As shown, the serial peripheral interface system 100 may include an Advanced Microcontroller Bus Architecture (AMBA) (e.g., an Advanced High-Performance Bus (AHB)) 110, a master device 120, a general-purpose input / output (GPIO) interface 130, a first slave device 140, and a second slave device 150. Note that, in Figure 1 The block diagram shown in FIG is only for the convenience of explaining the embodiment of the present invention, but the present invention is not limited to Figure 1 The serial peripheral interface system 100 may also include other components.

[0046] According to an embodiment of the present invention, Figure 1 As shown, the host device 120 may include at least a memory interface 121, a control interface 122, a logic circuit 123, a chip select (CS) control circuit 124, and a chip select (CS) mode selection circuit 125. Figure 1 The main device 120 shown in FIG is only for the convenience of explaining the embodiment of the present invention, but the present invention is not limited to Figure 1 The main device 120 may also include other components.

[0047] In addition, according to an embodiment of the present invention, Figure 1 As shown, the universal input and output 130 may include a master input / slave output pin MISO (Master Input / Slave Output), a master output / slave input pin MOSI (Master Output / Slave Input), a clock pin CLK, a first chip select pin CS0, a second chip select pin CS1, a static chip select pin circuit 131, and a dynamic chip select pin circuit 132. In addition, according to an embodiment of the present invention, Figure 1 As shown, the first chip select pin CS0 is connected to the first slave device 140 , and the second chip select pin CS1 is connected to the second slave device 150 .

[0048] According to an embodiment of the present invention, the memory interface 121 can determine which slave device the memory address accessed by the advanced microcontroller bus architecture 110 corresponds to, thereby generating a determination result S1. For example, if the memory address range corresponding to the first slave device 140 is 0x1000-0x1ffff, and the memory address range corresponding to the second slave device 150 is 0x2000-0x2ffff, when the memory interface 121 determines that the memory address accessed by the advanced microcontroller bus architecture 110 is within the memory address range 0x1000-0x1ffff, the memory interface 121 determines that the memory address accessed by the advanced microcontroller bus architecture 110 corresponds to the first slave device 140. Note that the above example is merely illustrative of an embodiment of the present invention and is not intended to be limiting. The memory interface 121 transmits the determination result S1 to the logic circuit 123 and the chip select control circuit 124.

[0049] According to an embodiment of the present invention, the control interface 122 can generate a control signal S2 based on an instruction from the advanced microcontroller bus architecture 110 and transmit the control signal S2 to the logic circuit 123 and the chip select control circuit 124. The logic circuit 123 and the chip select control circuit 124 can determine whether to use the static chip select pin function or the dynamic chip select pin function (i.e., whether to select the static chip select pin circuit 131 or the dynamic chip select pin circuit 132) based on the control signal S2, and select the chip select pin.

[0050] According to an embodiment of the present invention, the logic circuit 123 can be regarded as a set of serial peripheral interface master ports (masterports). According to an embodiment of the present invention, the logic circuit 123 can include a master input slave output port MISO1, a master output slave input port MOSI1, a clock output port CLK1, and a chip select port nCS. The logic circuit 123 can transmit data or signals to the selected slave device via the master input slave output port MISO1, the master output slave input port MOSI1, the clock output port CLK1, and the chip select port nCS. Figure 1 As shown, the master input slave output port MISO1 is connected to the master input slave output pin MISO of the general-purpose input / output 130 to transmit the signal MISO_OUT to the master input slave output pin MISO. The master output slave input port MOSI1 is connected to the master output slave input pin MOSI of the general-purpose input / output 130 to transmit the signal MOSI_OUT to the master output slave input pin MOSI. The clock output port CLK1 is connected to the clock pin CLK of the general-purpose input / output 130 to transmit the clock signal CLK_OUT to the clock pin CLK. The chip select port nCS is connected to the chip select mode selection circuit 125 to transmit the signal nCS_OUT to the chip select mode selection circuit 125.

[0051] According to an embodiment of the present invention, the chip select control circuit 124 can determine, based on the control signal S2 received, whether to use the static chip select pin function or the dynamic chip select pin function (i.e., whether to select the static chip select pin circuit 131 or the dynamic chip select pin circuit 132), select the chip select pin, and generate a first selection signal S3 accordingly. The chip select control circuit 124 then transmits the first selection signal S3 to the chip select mode selection circuit 125. Based on the first selection signal S3, the chip select mode selection circuit 125 can determine whether to use the static chip select pin circuit 131 or the dynamic chip select pin circuit 132 to select the chip select pin and transmit the signal nCS_OUT.

[0052] When the static chip select pin circuit 131 is selected, the static chip select pin circuit 131 determines whether to activate the first chip select pin CS0 or the second chip select pin CS1 according to a value of a register (not shown) of the general-purpose input and output 130 .

[0053] When the dynamic chip select pin circuit 132 is selected, the dynamic chip select pin circuit 132 can determine whether to activate the first chip select pin CS0 or the second chip select pin CS1 according to the second select signal S4 from the chip select control circuit 124. This will be described in more detail below.

[0054] According to one embodiment of the present invention, when the chip select control circuit 124 determines, based on control signal S2, that the dynamic chip select pin function is to be used (i.e., dynamic chip select pin circuit 132 is selected) to select the chip select pin, the chip select control circuit 124 determines, based on determination result S1, which slave device to access, and determines whether to activate the first chip select pin CS0 or the second chip select pin CS1. Accordingly, the chip select control circuit 124 generates a second select signal S4. The chip select control circuit 124 then transmits the second select signal S4 to the dynamic chip select pin circuit 132. Based on the second select signal S4, the dynamic chip select pin circuit 132 determines whether to activate the first chip select pin CS0 or the second chip select pin CS1, thereby transmitting the data contained in the signal nCS_OUT to the first chip select pin CS0 or the second chip select pin CS1. In other words, the dynamic chip select pin circuit 132 can dynamically select the first chip select pin CS0 or the second chip select pin CS1 based on the second select signal S4.

[0055] When the first chip select pin CS0 is selected, the master device 120 can communicate with the first slave device 140 , and when the second chip select pin CS1 is selected, the master device 120 can communicate with the second slave device 150 .

[0056] Figure 2 FIG. 1 is a flow chart of a data transmission method according to an embodiment of the present invention. The data transmission method may be applicable to a Serial Peripheral Interface (SPI) system 100. Figure 2 As shown, in step S210 , a chip select control circuit of the master device of the SPI system 100 generates a first select signal.

[0057] In step S220 , a chip select mode selection circuit of the master device of the SPI system 100 determines whether to select a dynamic chip select pin circuit or a static chip select pin circuit of the SPI system according to the first selection signal to select a chip select pin.

[0058] When the dynamic chip select pin circuit is selected, step S230 is performed. In step S230, the chip select control circuit transmits a second selection signal to the dynamic chip select pin circuit, thereby selecting the chip select pin from the plurality of chip select pins of the serial peripheral interface system 100 according to the second selection signal. In step S250, a logic circuit of the serial peripheral interface system 100 outputs data to the slave device corresponding to the selected chip select pin to the slave device. In this embodiment, the static chip select pin circuit, the dynamic chip select pin circuit, and the plurality of chip select pins may be included in a universal input / output interface of the serial peripheral interface system 100.

[0059] When the static chip select pin circuit is selected, step S240 is performed. In step S240, a chip select pin is selected from a plurality of chip select pins of the serial peripheral interface system 100 via the universal input / output interface of the serial peripheral interface system 100. Then, step S250 is performed.

[0060] According to an embodiment of the present invention, the data transmission method further includes generating a first selection signal by a chip selection control circuit of the serial peripheral interface system 100 according to a control signal output from a control interface of the serial peripheral interface system 100 .

[0061] According to an embodiment of the present invention, the data transmission method further includes generating a second select signal by a chip select control circuit of the serial peripheral interface system 100 based on a determination result generated by a memory interface of the serial peripheral interface system 100. The memory interface can generate a determination result S1 by determining which slave device a memory address accessed by an advanced microcontroller bus architecture of the serial peripheral interface system 100 corresponds to.

[0062] The serial peripheral interface system and data transmission method proposed in the present invention utilize a dynamic chip select pin circuit to select the static chip select pin corresponding to the slave device with which communication is desired. Therefore, in the serial peripheral interface system proposed in the present invention, the master device only needs to configure a single set of master ports to achieve the goal of switching between different static chip select pins. Consequently, the serial peripheral interface system and data transmission method proposed in the present invention avoids wasted pins.

[0063] The serial numbers in this specification and the scope of the patent application, such as "first", "second", etc., are only for the convenience of explanation and there is no sequential relationship between them.

[0064] The methods and algorithm steps disclosed in the present invention can be directly applied to hardware and software modules, or a combination of the two, by executing a processor. A software module (including execution instructions and associated data) and other data can be stored in a data storage device, such as random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), temporary storage, hard disk, portable hard disk, compact disk read-only memory (CD-ROM), DVD, or any other computer-readable storage medium format known in the art. A storage medium can be coupled to a machine device, such as a computer or a processor (for ease of description, referred to as a processor in this specification), which can be used to read information (such as program code) and write information to the storage medium. A storage medium can integrate a processor. An application-specific integrated circuit (ASIC) includes a processor and a storage medium. A user device includes an application-specific integrated circuit. In other words, the processor and storage medium are included in the user device without being directly connected to the user device. Furthermore, in some embodiments, any suitable computer program product includes a readable storage medium, wherein the readable storage medium includes program code related to one or more disclosed embodiments. In some embodiments, the computer program product may include packaging materials.

[0065] The above paragraphs describe various aspects. Obviously, the teachings herein can be implemented in a variety of ways, and any specific architecture or functionality disclosed in the examples is merely representative. Based on the teachings herein, anyone skilled in the art will understand that each aspect disclosed herein can be applied independently or in combination.

[0066] Although the present disclosure has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the invention must refer to the scope defined by the appended claims.

Claims

1. A serial peripheral interface system, characterized in that: include: multiple slave devices; as well as A main device comprising: a chip selection control circuit, generating a first selection signal and a second selection signal; as well as a chip select mode selection circuit coupled to the chip select control circuit, a dynamic chip select pin circuit, and a static chip select pin circuit, and determining whether to select the static chip select pin circuit or the dynamic chip select pin circuit to select a chip select pin based on the first selection signal; When the static chip select pin circuit is selected, the static chip select pin circuit determines to activate the chip select pin from a plurality of chip select pins according to a value of a register of a universal input / output interface; When the dynamic chip select pin circuit is selected, the chip select control circuit transmits the second selection signal to the dynamic chip select pin circuit to select the chip select pin from a plurality of chip select pins and transmits data to one of the plurality of slave devices corresponding to the selected chip select pin.

2. The serial peripheral interface system according to claim 1, wherein: The static chip select pin circuit, the dynamic chip select pin circuit and the plurality of chip select pins are included in a universal input / output interface.

3. The serial peripheral interface system according to claim 1, wherein: The main device further includes a control interface, and the chip selection control circuit generates the first selection signal according to a control signal output from the control interface.

4. The serial peripheral interface system according to claim 1, wherein: The host device further includes a memory interface, and the chip selection control circuit generates the second selection signal according to a determination result generated from the memory interface.

5. The serial peripheral interface system according to claim 1, wherein: The master device further includes a logic circuit for outputting data to be transmitted to the slave device corresponding to the selected chip select pin.

6. A data transmission method, applicable to a serial peripheral interface system, characterized in that: include: A chip select control circuit of a master device of the serial peripheral interface system generates a first select signal; A chip select mode selection circuit of the master device determines, based on the first selection signal, whether to select a static chip select pin circuit or a dynamic chip select pin circuit of the serial peripheral interface system to select a chip select pin; When the static chip select pin circuit is selected, the static chip select pin circuit determines to activate the chip select pin from a plurality of chip select pins according to a value of a register of a universal input / output interface, or when the dynamic chip select pin circuit is selected, the chip select control circuit transmits a second selection signal to the dynamic chip select pin circuit to select the chip select pin from a plurality of chip select pins of the serial peripheral interface system; and The data is transmitted to one of the plurality of slave devices of the serial peripheral interface system corresponding to the selected chip selection pin.

7. The data transmission method according to claim 6, wherein: Also includes: The chip selection control circuit generates the first selection signal according to a control signal output from a control interface of the serial peripheral interface system.

8. The data transmission method according to claim 6, wherein: Also includes: The chip selection control circuit generates the second selection signal according to a determination result generated by a memory interface from the serial peripheral interface system.

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