An integrated circuit

Abstract

The present application discloses an integrated circuit, which includes: a detection subcircuit, which is used to detect optical fault injection attacks through photoelectric effect, and the detection subcircuit can output a first signal when the detection subcircuit itself is attacked by optical fault injection; an auxiliary subcircuit, which is used to enable the detection subcircuit to output the first signal when the detection subcircuit itself is attacked by optical fault injection. In this way, the protection capability of the laser detection circuit can be assisted to be expanded, and technical support can be provided for reducing chip area and chip cost.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an integrated circuit. Background Art

[0002] An important requirement for security chips is that their working environment is safe and reliable. There are many attack methods that threaten the safe working environment of chips, among which laser injection attack is one of the commonly used attack methods. This technology uses laser to irradiate the storage unit or logic unit of the semiconductor chip, and uses the light-sensitive characteristics of the parasitic diode in the semiconductor device to make the latch unit in the logic circuit change logic, thereby rewriting the logic state. Therefore, many security chips use laser detection circuits to detect laser injection attacks.

[0003] In the current commonly used detection technology, a single detection circuit requires multiple transistors. If such detection circuits are laid out in large quantities, the chip cost will increase. As laser attack technology improves, the irradiation spot gradually decreases, and the loose layout will lead to insufficient protection capabilities. Summary of the invention

[0004] Based on this, the present application provides an integrated circuit that can assist in expanding the protection capability of the laser detection circuit and provide technical support for reducing chip area and chip cost.

[0005] In a first aspect, the present application provides an integrated circuit, the integrated circuit comprising:

[0006] a detection subcircuit, used for detecting an optical fault injection attack through a photoelectric effect, wherein the detection subcircuit is capable of outputting a first signal when the detection subcircuit itself is attacked by an optical fault injection;

[0007] The auxiliary sub-circuit is used to enable the detection sub-circuit to output a first signal when the auxiliary sub-circuit itself is attacked by optical fault injection.

[0008] The embodiment of the present application provides an integrated circuit, the integrated circuit comprising: a detection subcircuit, which is used to detect an optical fault injection attack through a photoelectric effect, and the detection subcircuit can output a first signal when the integrated circuit is attacked by the optical fault injection; an auxiliary subcircuit, which is used to enable the detection subcircuit to output a first signal when the integrated circuit is attacked by the optical fault injection. Since the detection subcircuit detects the optical fault injection attack through the photoelectric effect, the auxiliary subcircuit can enable the detection subcircuit to output a first signal when the integrated circuit is attacked by the optical fault injection, that is, the auxiliary subcircuit can sense the optical fault injection attack and can transmit the sensed optical fault injection attack information to the detection subcircuit, so that the detection subcircuit outputs a first signal, and the first signal can indicate that the current integrated circuit is attacked by the optical fault injection. Therefore, there is no need to arrange multiple detection subcircuits, and only adding the auxiliary subcircuit can expand the protection capability of the detection subcircuit. Subsequently, an auxiliary subcircuit with a smaller area than the detection subcircuit and an auxiliary subcircuit with a lower cost than the detection subcircuit can be used, that is, the chip area can be reduced and the chip cost can be reduced; therefore, the integrated circuit of the embodiment of the present application can also provide technical support for reducing the chip area and reducing the chip cost.

[0009] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the structure of an integrated circuit according to an embodiment of the present application;

[0011] Figure 2 is a schematic structural diagram of another embodiment of the integrated circuit of the present application;

[0012] Figure 3 It is a structural schematic diagram of another embodiment of the integrated circuit of the present application;

[0013] Figure 4 It is a structural schematic diagram of another embodiment of the integrated circuit of the present application;

[0014] Figure 5 It is a structural schematic diagram of another embodiment of the integrated circuit of the present application;

[0015] Figure 6 It is a structural schematic diagram of another embodiment of the integrated circuit of the present application;

[0016] Figure 7 It is a structural diagram of another embodiment of the integrated circuit of the present application. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0019] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0020] There are many attack methods that threaten the safe working environment of the chip, among which laser injection attack is one of the common attack methods. Therefore, many security chips use laser detection circuits to detect laser injection attacks. Among the commonly used detection technologies, a single detection circuit requires multiple transistors, and a large number of detection circuits will increase the chip cost; as the irradiation spot gradually decreases, the loose layout will lead to insufficient protection capabilities.

[0021] The embodiment of the present application provides an integrated circuit, the integrated circuit comprising: a detection subcircuit, which is used to detect an optical fault injection attack through a photoelectric effect, and the detection subcircuit can output a first signal when the integrated circuit is attacked by the optical fault injection; an auxiliary subcircuit, which is used to enable the detection subcircuit to output a first signal when the integrated circuit is attacked by the optical fault injection. Since the detection subcircuit detects the optical fault injection attack through the photoelectric effect, the auxiliary subcircuit can enable the detection subcircuit to output a first signal when the integrated circuit is attacked by the optical fault injection, that is, the auxiliary subcircuit can sense the optical fault injection attack and can transmit the sensed optical fault injection attack information to the detection subcircuit, so that the detection subcircuit outputs a first signal, and the first signal can indicate that the current integrated circuit is attacked by the optical fault injection. Therefore, there is no need to arrange multiple detection subcircuits, and only adding the auxiliary subcircuit can expand the protection capability of the detection subcircuit. Subsequently, an auxiliary subcircuit with a smaller area than the detection subcircuit and a lower cost than the detection subcircuit can be used, that is, the chip area can be reduced and the chip cost can be reduced; therefore, the integrated circuit of the embodiment of the present application can also provide technical support for reducing the chip area and reducing the chip cost.

[0022] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0023] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of an integrated circuit according to an embodiment of the present application. The integrated circuit 100 includes: a detection sub-circuit 1 and an auxiliary sub-circuit 2.

[0024] The detection subcircuit 1 is used to detect optical fault injection attacks through the photoelectric effect. When it is attacked by optical fault injection, the detection subcircuit 1 can output a first signal. The auxiliary subcircuit 2 is used to enable the detection subcircuit 1 to output a first signal when it is attacked by optical fault injection.

[0025] When light shines on metal, it causes the electrical properties of the material to change. This kind of light-induced electrical phenomenon is collectively called the photoelectric effect. The photoelectric effect is divided into external photoelectric effect and internal photoelectric effect. The internal photoelectric effect is a phenomenon in which the carriers (free electrons or holes) generated by light excitation still move inside the material, causing the material's conductivity to change or generating photovoltaics. The external photoelectric effect is a phenomenon in which electrons generated by light excitation escape from the surface of the material and form electrons in a vacuum.

[0026] Fault injection is a verification technique that deliberately introduces faults into the system through controlled experiments and observes the behavior of the system when the fault exists. Fault injection attacks have the characteristics of low equipment requirements and good effects. They are currently often used in chip attacks. Fault injection attacks can inject faults into the chip during operation, causing its calculation results to be wrong, and calculate the key by analyzing the wrong results. Therefore, fault injection attacks pose a great threat to electronic information security. Among the many fault injection attack methods, optical fault injection attacks have become a very effective means of attacking smart card chips. The basic principle of optical fault injection affecting the circuit is the photoelectric effect. When light is irradiated on the chip, if the energy of the photon is greater than the bandgap width, it will cause the valence band electrons to jump to the conduction band, generating electron-hole pairs. Most of the time, these generated electron-hole pairs will recombine, but when light irradiates the reverse-biased PN junction, the two carriers will move in opposite directions under the action of the electric field, generating photocurrent. When the light stops, the photocurrent will last for hundreds of picoseconds, generating a short voltage pulse. When it propagates along the circuit and is captured by the register, an error occurs. Another possible scenario is that the transient voltage caused by laser fault injection is directly injected into the static random access memory (SRAM) or memory, which will directly cause the memory state to flip, thereby generating errors. Among them, the more common optical fault injection attack is the laser injection attack.

[0027] In this embodiment, the detection subcircuit 1 is a circuit for detecting optical fault injection attacks through the photoelectric effect. The detection subcircuit 1 can be a circuit for detecting optical fault injection attacks through the photoelectric effect in the prior art. For example, the detection subcircuit 1 can use an inverter structure circuit composed of a P-type transistor and an N-type transistor; it can also use a latch structure circuit composed of a P-type transistor and an N-type transistor; it can also be a circuit composed of at least one other photon sensitive element; and so on.

[0028] When the detection subcircuit 1 is attacked by optical fault injection, the detection subcircuit 1 can output a first signal, which can indicate that the current circuit is attacked by optical fault injection. If the first signal is sent to the alarm circuit, the alarm circuit can be triggered to alarm.

[0029] In this embodiment, when the auxiliary subcircuit 2 is attacked by optical fault injection, the auxiliary subcircuit 2 itself will not output the first signal, and the auxiliary subcircuit 2 can make the detection subcircuit 1 output the first signal. That is, the auxiliary subcircuit 2 can sense the optical fault injection attack, and transmit the sensed signal or information to the detection subcircuit 1, and the detection subcircuit 1 can output the first signal after receiving the signal or information transmitted by the auxiliary subcircuit 2. Therefore, the auxiliary subcircuit 2 can assist the detection subcircuit 1 in sensing the optical fault injection attack, which is equivalent to expanding the sensing range of the detection subcircuit 1, but the auxiliary subcircuit 2 will not output the first signal itself after sensing the optical fault injection attack, and still needs to rely on the detection subcircuit 1 to output the first signal, which is equivalent to the auxiliary subcircuit 2 is not a complete circuit capable of detecting optical fault injection attacks, the specific structure of the auxiliary subcircuit 2 depends on the specific structure of the detection subcircuit 1, and the specific structure of the auxiliary subcircuit 2 needs to cooperate with the specific structure of the detection subcircuit 1, so that the auxiliary subcircuit 2 can sense the optical fault injection attack, and transmit the sensed signal or information to the detection subcircuit 1, and the detection subcircuit 1 can output the first signal after receiving the signal or information transmitted by the auxiliary subcircuit 2.

[0030] Since the auxiliary sub-circuit 2 is not equivalent to a complete circuit capable of detecting optical fault injection attacks, the area of ​​the auxiliary sub-circuit 2 can be smaller than that of the detection sub-circuit 1 in actual applications, which provides technical support for reducing the chip area; and the cost of the auxiliary sub-circuit 2 can also be smaller than that of the detection sub-circuit 1, which provides technical support for reducing the chip cost.

[0031] The embodiment of the present application provides an integrated circuit 100, which includes: a detection subcircuit 1, which is used to detect an optical fault injection attack through a photoelectric effect, and the detection subcircuit 1 can output a first signal when the integrated circuit is attacked by the optical fault injection; and an auxiliary subcircuit 2, which is used to enable the detection subcircuit 1 to output a first signal when the integrated circuit is attacked by the optical fault injection. Since the auxiliary subcircuit 2 can enable the detection subcircuit 1 to output a first signal when the detection subcircuit 1 is attacked by the optical fault injection on the basis of detecting the optical fault injection attack through the photoelectric effect, that is, the auxiliary subcircuit 2 can sense the optical fault injection attack and transmit the sensed optical fault injection attack information to the detection subcircuit 1, so that the detection subcircuit 1 outputs a first signal, and the first signal can indicate that the current integrated circuit is attacked by the optical fault injection. Therefore, there is no need to arrange multiple detection subcircuits 1, and only adding the auxiliary subcircuit 2 can expand the protection capability of the detection subcircuit 1. Subsequently, an auxiliary sub-circuit 2 with a smaller area than the detection sub-circuit 1 and a lower cost than the detection sub-circuit 1 can be used, which can reduce the chip area and reduce the chip cost; therefore, the integrated circuit 100 of the embodiment of the present application can also provide technical support for reducing the chip area and reducing the chip cost.

[0032] In one embodiment, the area of ​​the detection subcircuit 1 is larger than the area of ​​the auxiliary subcircuit 2. In this way, the area of ​​the chip can be reduced on the basis of expanding the protection capability of the detection subcircuit 1.

[0033] A common detection subcircuit 1 usually includes more than one transistor. A diode is usually easier to work with a transistor, and a diode has a simple structure and low cost. Therefore, in one embodiment, the auxiliary subcircuit 2 includes a plurality of diodes 21 arranged in parallel, each of which is connected to the detection subcircuit 1. When any of the diodes 21 is attacked by an optical fault injection, the detection subcircuit 1 can output a first signal, such as Figure 2 shown.

[0034] In one embodiment, the detection subcircuit 1 is further configured to output a second signal different from the first signal when the detection subcircuit 1 is not attacked by optical fault injection; the auxiliary subcircuit 2 is further configured to not affect the detection subcircuit 1 when the detection subcircuit 1 is not attacked by optical fault injection. Since the detection subcircuit 1 outputs the second signal different from the first signal when it is not attacked by optical fault injection, and the auxiliary subcircuit 2 does not affect the detection subcircuit 1 when it is not attacked by optical fault injection, in this way, the detection subcircuit 1 can send out the first signal and the second signal different from the first signal when it is attacked by optical fault injection and when it is not attacked by optical fault injection, respectively, which can improve the sensitivity and sensitivity of the detection of the detection subcircuit 1.

[0035] In one embodiment, the first signal is a high level signal, and the second signal is a low level signal; or, the first signal is a low level signal, and the second signal is a high level signal.

[0036] See also Figure 3 In one embodiment, the detection subcircuit 1 includes: a latch subcircuit 11 and a reset subcircuit 12 .

[0037] The latch subcircuit 11 is used to output a second signal after receiving a reset signal and latch the second signal after the reset signal is disconnected, and can output a first signal when attacked by optical fault injection; the reset subcircuit 12 is used to output a reset signal to the latch subcircuit 11. The latch subcircuit 11 includes: two P-type transistors and two N-type transistors, and the two P-type transistors and the two N-type transistors form a latch structure.

[0038] See also Figure 4 , the latch sub-circuit 11 includes: a first P-type transistor M0, a second P-type transistor M2, a first N-type transistor M1 and a second N-type transistor M3;

[0039] The drain electrode D of the first P-type transistor M0 is respectively connected to the gate electrode G of the second P-type transistor M2, the drain electrode D of the first N-type transistor M1, and the gate electrode G of the second N-type transistor M3;

[0040] The gate G of the first P-type transistor M0 is connected to the drain D of the second P-type transistor M2, the gate G of the first N-type transistor M1, and the drain D of the second N-type transistor M3 respectively;

[0041] A source S of the first N-type transistor M1 and a source S of the second N-type transistor M3 are both grounded, and a source S of the first P-type transistor M0 and a source S of the second P-type transistor M2 are both connected to an external voltage.

[0042] See also Figure 4 In one embodiment, the reset sub-circuit 12 includes: a third P-type transistor M4 and a third N-type transistor M5.

[0043] The drain D of the third P-type transistor M4 is respectively connected to the drain D of the first P-type transistor M0, the gate G of the second P-type transistor M2, the drain D of the first N-type transistor M1 and the gate G of the second N-type transistor M3, the gate G of the third P-type transistor M4 can receive a low-level reset signal, and the source S of the third P-type transistor M4 is connected to an external voltage.

[0044] The drain D of the third N-type transistor M5 is respectively connected to the gate G of the first P-type transistor M0, the drain D of the second P-type transistor M2, the gate G of the first N-type transistor M1 and the drain D of the second N-type transistor M3, the gate G of the third N-type transistor M5 can receive a high-level reset signal, and the source S of the third N-type transistor M5 is grounded.

[0045] In actual design, the latch subcircuit 11 can make the drain active area of ​​the second P-type transistor M2 and the first N-type transistor M1 larger, so that when attacked by optical fault injection, especially by laser fault injection, the potential of node A is pulled up and the potential of node B is pulled down, so that the output signal changes from a low-level signal (second signal) to a high-level signal (first signal).

[0046] If one wants to fully protect the digital area of ​​the chip while also taking into account a smaller laser attack spot, the above-mentioned detection sub-circuits need to be arranged in large quantities and densely, which will incur a large area cost.

[0047] See also Figure 5 , the auxiliary sub-circuit 2 includes: a first auxiliary sub-circuit and a second auxiliary sub-circuit.

[0048] The first auxiliary subcircuit includes a plurality of first diodes arranged in parallel, respectively represented as Dn1, Dn2, ..., DnN, the cathode of each of the first diodes is connected to the drain D of the first P-type transistor M0 and the drain D of the first N-type transistor M1, the anode of each of the first diodes is grounded, and the area of ​​the first diode is greater than or equal to the area of ​​the drain active region of the first N-type transistor M1. The properties of the first diodes are consistent with the active region of the N-type transistor.

[0049] The second auxiliary subcircuit includes a plurality of second diodes arranged in parallel, respectively represented as Dp1, Dp2, ..., DpM, the anode of each second diode is connected to the drain D of the second P-type transistor M2 and the drain D of the second N-type transistor M3, the cathode of each second diode is connected to an external voltage, and the area of ​​the second diode is greater than or equal to the area of ​​the drain active region of the second P-type transistor M2. The properties of the second diode are consistent with the active region of the P-type transistor.

[0050] See also Figure 5 , the working process of the above circuit may include the following process:

[0051] In the initial state, the reset signal is input, the third P-type transistor M4 (the reset signal is a low-level signal) and the third N-type transistor M5 (the reset signal is a high-level signal) are turned on, M0 and M3 are turned on, the B node is a high-level signal, and the A node is a low-level signal, and the output signal (i.e., the second signal when not attacked by optical fault injection) is reset to a low potential. After working, the reset signal is disconnected, and the third P-type transistor M4 and the third N-type transistor M5 are turned off, but due to the latch structure of the circuit, the output signal (i.e., the second signal when not attacked by optical fault injection) remains at a low potential. When attacked by optical fault injection, the following situations occur:

[0052] (1) If the attack light spot irradiates any one of the multiple diodes Dn1-DnN (i.e., N first diodes), the potential of point B is pulled low, the output potential is pulled high (i.e., the first signal is a high-level signal), and is latched, and an alarm signal is issued.

[0053] (2) If the attack light spot is irradiated on any one of the multiple diodes Dp1-DpM (i.e., M second diodes), the potential of point A is pulled high, the output potential is pulled high (i.e., the first signal is a high-level signal), and is latched, and an alarm signal is issued.

[0054] (3) If the attack light spot is irradiated on the circuit composed of M0-M5, the potential of point B is pulled low, the potential of point A is pulled high, the output potential is pulled high (that is, the first signal is a high-level signal), and is latched, sending out an alarm signal.

[0055] (4) If the attack light spot illuminates any one of the multiple diodes Dp1-DpM and any one of the multiple diodes Dn1-DnN at the same time, the potential at point B is pulled low, the potential at point A is pulled high, the output potential is pulled high (that is, the first signal is a high-level signal), and is latched, and an alarm signal is issued.

[0056] In the integrated circuit of the embodiment of the present application, in addition to the protection function of the detection subcircuit 1 composed of M0 to M5, the extended diodes (multiple P-type transistors Dp connected to the A node, and multiple N-type transistors Dn connected to the B node) can also provide additional protection range, such as Figure 6 As shown. The area and cost requirements of the diode are much smaller than those of a main circuit, namely the detection subcircuit 1, so it is possible to expand the protection range with a smaller area and cost. Within the same protection range, the area and cost of the integrated circuit of the embodiment of the present application can be greatly reduced.

[0057] In another embodiment, the circuit can also be designed to output a high potential in the reset state (i.e., the second signal is a high potential signal when not attacked by optical fault injection), and output a low potential when attacked (i.e., the first signal is a low potential signal when attacked by optical fault injection) as an alarm, and the drain active area of ​​M3 and M0 is relatively large. Figure 5 That is, the reset sub-circuit 12 includes: a third P-type transistor M4 and a third N-type transistor M5, such as Figure 7 shown.

[0058] The drain D of the third P-type transistor M4 is respectively connected to the gate G of the first P-type transistor M0, the drain D of the second P-type transistor M2, the gate G of the first N-type transistor M1, and the drain D of the second N-type transistor M3, the gate G of the third P-type transistor M4 can receive a low-level reset signal, and the source S of the third P-type transistor M4 is connected to an external voltage. The drain D of the third N-type transistor M5 is respectively connected to the drain D of the first P-type transistor M0, the gate G of the second P-type transistor M2, the drain D of the first N-type transistor M1, and the gate G of the second N-type transistor M3, the gate G of the third N-type transistor M5 can receive a high-level reset signal, and the source S of the third N-type transistor M5 is grounded.

[0059] The auxiliary subcircuit 2 includes: a first auxiliary subcircuit and a second auxiliary subcircuit.

[0060] The first auxiliary subcircuit includes a plurality of first diodes arranged in parallel, respectively represented as Dn1, Dn2, ..., DnN, the cathode of each of the first diodes is connected to the drain D of the second P-type transistor M2 and the drain D of the second N-type transistor M3, the anode of each of the first diodes is grounded, and the area of ​​the first diode is greater than or equal to the area of ​​the drain active region of the second N-type transistor M3. The properties of the first diodes are consistent with the active region of the N-type transistor.

[0061] The second auxiliary subcircuit includes a plurality of second diodes arranged in parallel, respectively represented as Dp1, Dp2, ..., DpM, the anode of each second diode is connected to the drain D of the first P-type transistor M0 and the drain of the first N-type transistor M1, the cathode of each second diode is connected to an external voltage, and the area of ​​the second diode is greater than or equal to the area of ​​the drain active region of the first P-type transistor M0. The properties of the second diode are consistent with the active region of the P-type transistor.

[0062] See also Figure 7 , the working process of the above circuit may include the following process:

[0063] In the initial state, the reset signal is input to turn on the third P-type transistor M4 (the reset signal is a low-level signal) and the third N-type transistor M5 (the reset signal is a high-level signal), and the output signal (i.e., the second signal when not attacked by optical fault injection) is reset to a high potential. After operation, the reset signal is disconnected, and the third P-type transistor M4 and the third N-type transistor M5 are turned off, but due to the latch structure of the circuit, the output signal (i.e., the second signal when not attacked by optical fault injection) remains at a high potential. When attacked by optical fault injection, the following situations occur:

[0064] (1) If the attack light spot irradiates any one of the multiple diodes Dn1-DnN (i.e., N first diodes), the potential of point B is pulled high, the output potential is pulled low (i.e., the first signal is a low-level signal), and it is latched, and an alarm signal is issued.

[0065] (2) If the attack light spot is irradiated on any one of the multiple diodes Dp1-DpM (i.e., M second diodes), the potential of point A is pulled low, the output potential is pulled low (i.e., the first signal is a low-level signal), and is latched, and an alarm signal is issued.

[0066] (3) If the attack light spot is irradiated on the circuit composed of M0-M5, the potential of point B is pulled high, the potential of point A is pulled low, the output potential is pulled low (that is, the first signal is a low-level signal), and it is latched, and an alarm signal is issued.

[0067] (4) If the attack light spot illuminates any one of the multiple diodes Dp1-DpM and any one of the multiple diodes Dn1-DnN at the same time, the potential at point B is pulled high, the potential at point A is pulled low, the output potential is pulled low (that is, the first signal is a low-level signal), and is latched, and an alarm signal is issued.

[0068] It should be understood that the terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0069] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0070] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An integrated circuit, characterized in that: The integrated circuit comprises: a detection subcircuit, used for detecting a light fault injection attack by means of a photoelectric effect, wherein the detection subcircuit can output a first signal when the detection subcircuit itself is attacked by a light fault injection; the detection subcircuit comprises at least one of an inverter structure circuit composed of a P-type transistor and an N-type transistor, a latch structure circuit composed of a P-type transistor and an N-type transistor, and a circuit composed of at least one other photon sensitive element; The auxiliary subcircuit is used to enable the detection subcircuit to output a first signal when the auxiliary subcircuit itself is attacked by optical fault injection; the auxiliary subcircuit includes a plurality of diodes arranged in parallel, each of which is connected to the detection subcircuit, and when any one of the diodes itself is attacked by optical fault injection, the detection subcircuit can output the first signal.

2. The integrated circuit according to claim 1, characterized in that The area of ​​the detection sub-circuit is larger than the area of ​​the auxiliary sub-circuit.

3. The integrated circuit according to claim 1, characterized in that The detection subcircuit is further configured to output a second signal different from the first signal when the detection subcircuit itself is not attacked by optical fault injection; The auxiliary subcircuit is also used for not affecting the detection subcircuit when the auxiliary subcircuit itself is not attacked by optical fault injection.

4. The integrated circuit according to claim 3, characterized in that The detection subcircuit comprises: A latch subcircuit, configured to output a second signal after receiving a reset signal and latch the second signal after the reset signal is disconnected, and to output a first signal when attacked by an optical fault injection; The reset subcircuit is used to output a reset signal to the latch subcircuit.

5. The integrated circuit according to claim 4, characterized in that The latch subcircuit includes: two P-type transistors and two N-type transistors, and the two P-type transistors and the two N-type transistors form a latch structure.

6. The integrated circuit according to claim 5, characterized in that The latch subcircuit includes: a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor; The drain of the first P-type transistor is connected to the gate of the second P-type transistor, the drain of the first N-type transistor, and the gate of the second N-type transistor respectively. The gate of the first P-type transistor is connected to the drain of the second P-type transistor, the gate of the first N-type transistor, and the drain of the second N-type transistor respectively. The source of the first N-type transistor and the source of the second N-type transistor are both grounded, and the source of the first P-type transistor and the source of the second P-type transistor are both connected to an external voltage.

7. The integrated circuit according to claim 6, characterized in that The reset subcircuit comprises: a third P-type transistor, wherein the drain of the third P-type transistor is respectively connected to the drain of the first P-type transistor, the gate of the second P-type transistor, the drain of the first N-type transistor, and the gate of the second N-type transistor, the gate of the third P-type transistor is capable of receiving a low-level reset signal, and the source of the third P-type transistor is connected to an external voltage; A third N-type transistor, the drain of the third N-type transistor is respectively connected to the gate of the first P-type transistor, the drain of the second P-type transistor, the gate of the first N-type transistor and the drain of the second N-type transistor, the gate of the third N-type transistor can receive a high-level reset signal, and the source of the third N-type transistor is grounded.

8. The integrated circuit according to claim 6, characterized in that The auxiliary subcircuit comprises: a first auxiliary subcircuit, comprising a plurality of first diodes arranged in parallel, wherein a cathode of each of the first diodes is connected to a drain of the first P-type transistor and a drain of the first N-type transistor, an anode of each of the first diodes is grounded, and an area of ​​the first diode is greater than or equal to an area of ​​a drain active region of the first N-type transistor; The second auxiliary subcircuit includes a plurality of second diodes arranged in parallel, wherein the anode of each second diode is connected to the drain of the second P-type transistor and the drain of the second N-type transistor, the cathode of each second diode is connected to an external voltage, and the area of ​​the second diode is greater than or equal to the area of ​​the drain active region of the second P-type transistor.

9. The integrated circuit according to claim 6, characterized in that: The reset subcircuit comprises: a third P-type transistor, wherein the drain of the third P-type transistor is respectively connected to the gate of the first P-type transistor, the drain of the second P-type transistor, the gate of the first N-type transistor, and the drain of the second N-type transistor, the gate of the third P-type transistor is capable of receiving a low-level reset signal, and the source of the third P-type transistor is connected to an external voltage; A third N-type transistor, wherein the drain of the third N-type transistor is respectively connected to the drain of the first P-type transistor, the gate of the second P-type transistor, the drain of the first N-type transistor and the gate of the second N-type transistor, the gate of the third N-type transistor can receive a high-level reset signal, and the source of the third N-type transistor is grounded.

10. The integrated circuit according to claim 6, characterized in that The auxiliary subcircuit comprises: a first auxiliary subcircuit, comprising a plurality of first diodes arranged in parallel, wherein a cathode of each of the first diodes is connected to a drain of the second P-type transistor and a drain of the second N-type transistor, an anode of each of the first diodes is grounded, and an area of ​​the first diode is greater than or equal to an area of ​​a drain active region of the second N-type transistor; The second auxiliary subcircuit includes a plurality of second diodes arranged in parallel, wherein the anode of each of the second diodes is connected to the drain of the first P-type transistor and the drain of the first N-type transistor, the cathode of each of the second diodes is connected to an external voltage, and the area of ​​the second diode is greater than or equal to the area of ​​the drain active region of the first P-type transistor.

11. The integrated circuit according to claim 3, characterized in that The first signal is a high-level signal, and the second signal is a low-level signal; or, the first signal is a low-level signal, and the second signal is a high-level signal.

12. The integrated circuit according to claim 1, characterized in that The optical fault injection attack is a laser injection attack.

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