Method and device for checking clock in chip EDA simulation

Abstract

The present invention discloses a method and device for checking clock in chip EDA simulation, and relates to the field of chip development technology. The method comprises the steps of: obtaining simulation result waveform files generated by EDA pre-simulation and EDA post-simulation; determining the clock frequency of the pre-simulation clock signal clk and the clock frequency of the post-simulation clock signal clk respectively according to the waveform in the simulation result waveform file, generating a pre-simulation clk clock frequency file and a post-simulation clk clock frequency file; comparing the clock frequencies of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file, and generating a clk result file according to the comparison result. The present invention can automatically check the correctness of the simulation clock, ensure the accuracy of the clock in the EDA simulation, and improve the efficiency of EDA simulation.

Description

Technical Field

[0001] The present invention relates to the technical field of chip development, and in particular to a method and device for checking clock in chip EDA simulation. Background Art

[0002] As the scale of IC design increases, IC verification becomes more and more important. Verification runs through the entire chip design process, from behavioral HDL design to a large amount of EDA (Electronic Design Automation) simulation verification before chip tape-out. EDA simulation is performed on the chip to verify the correctness of the chip design and eliminate errors.

[0003] EDA simulation usually includes two levels of simulation tests: functional simulation and timing simulation. As an example of a typical method, after designing the chip architecture and dividing the module functions according to the chip requirements proposed by the customer, the module functions are described and implemented in code using a hardware description language (such as Verilog, etc.), that is, the actual hardware circuit functions are described in HDL language to form RTL (Resistor transistor logic, register transfer level) code, and then the aforementioned RTL code is stimulated to obtain the results of its operation to determine whether the RTL code can run correctly. The above-mentioned process of simulating and verifying the RTL code to verify the correctness of the logical function of the designed code is called functional simulation, also known as pre-simulation (abbreviated as pre-simulation). Subsequently, logic synthesis is performed - constraints, unit delays and other information are added, and the simulation of the netlist after logic synthesis is called timing simulation (the simulation includes delay information), also known as post-simulation (abbreviated as post-simulation).

[0004] The simulator and test stimulus used in the pre-simulation and post-simulation of chip EDA simulation are the same, but the files required for simulation are not exactly the same, the simulation result waveforms are different, and the clock generation methods are also different. In the actual chip EDA simulation verification, it was found that some simulation problems were introduced by clock problems: the main reason is that the clock generation methods in the pre-simulation and post-simulation are different, which makes it easy for the clock frequency information in the post-simulation to be inconsistent with the clock frequency information in the pre-simulation, resulting in the test case (case) that can run normally in the pre-simulation to report an error in the post-simulation. Obviously, improving the clock frequency accuracy in EDA simulation can reduce a lot of unnecessary iterations and help improve simulation efficiency.

[0005] However, currently, the clock frequency of chip simulation is usually checked and calibrated manually: when an error occurs in post-simulation, the post-simulation verification personnel often need to manually compare the simulated clock frequency information with the set reference clock signal (clk signal, clk is the abbreviation of clock) to check whether there is a problem with the clock frequency. The above-mentioned method of manually calibrating the clock frequency has a low degree of automation, requires more time for verification personnel, and has low inspection efficiency, which to some extent affects the entire development cycle. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method and device for checking the clock in chip EDA simulation. The present invention can determine the clock frequency of each clock signal clk according to the simulation result waveform files of pre-EDA simulation and post-EDA simulation, and compare it with the clock frequency in the reference clock signal file to check the correctness of the clock, thereby ensuring the accuracy of the clock in EDA simulation and improving the efficiency of EDA simulation.

[0007] To achieve the above objectives, the present invention provides the following technical solutions:

[0008] A method for checking a clock in chip EDA simulation comprises the following steps:

[0009] Obtain simulation result waveform files generated by pre-EDA simulation and post-EDA simulation;

[0010] Determine the clock frequency of the pre-simulation clock signal clk and the clock frequency of the post-simulation clock signal clk respectively according to the waveform in the simulation result waveform file, and generate a pre-simulation clk clock frequency file and a post-simulation clk clock frequency file;

[0011] The clock frequencies of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file are compared, and a clk result file is generated according to the comparison result.

[0012] Furthermore, the simulation result waveform file is a fsdb waveform file.

[0013] Further, the steps for calculating the clock frequency of the clock signal clk according to the fsdb waveform in the fsdb waveform file are as follows:

[0014] Analyze the edge information of the clock signal clk in the fsdb waveform, wherein the clock signal clk is a periodic pulse signal, and the edge information includes the time point information of the rising edge and the falling edge;

[0015] Get the time point information t1 and t2 of any two adjacent clk rising edges;

[0016] After calculating the time interval Δt=t2-t1 between adjacent rising edges, the clock frequency f of the clock signal clk is determined. The calculation formula of the clock frequency f is f=100 / Δt.

[0017] Further, the pre-EDA simulation is to perform simulation verification on the register transfer level RTL code, in which clk annotation information is set for the clk statement, and the clock frequency of the clock signal clk involved in the clk statement is annotated through the clk annotation information;

[0018] At this time, before performing pre-EDA simulation, the steps also include: extracting the clock signal clk and the corresponding clk annotation information in the register transfer level RTL code through a script, obtaining the name and clock frequency value of the clock signal clk, and writing them into a reference clock signal file in a preset data format.

[0019] Furthermore, the reference clock signal file is a clk table in Excel format, and the clk table is preset with two field information, namely, the name of the clock signal clk clk name and the clock frequency value clk freq value.

[0020] Furthermore, the clk result file displays the names of various clock signals clk, and for each clock signal clk, displays the clock frequency value of the clock signal clk in the reference clock signal file, the pre-simulation clk clock frequency file and the post-simulation clk clock frequency file.

[0021] Furthermore, when performing the aforementioned comparison, if it is determined that the clock frequency information of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file are inconsistent, the inconsistent clk clock frequency value is marked in the clk result file, or the inconsistent clk name and clock frequency value are marked.

[0022] Furthermore, the user is collected to open the aforementioned simulation result waveform file through a waveform tool, and after reading the aforementioned clk result file, the position of the clock signal clk with inconsistent clock frequency is marked in the waveform tool corresponding to the output simulation result waveform.

[0023] The present invention also provides a clock checking device in chip EDA simulation, comprising the following structure:

[0024] A clock frequency calculation module is used to obtain the simulation result waveform files generated by EDA pre-simulation and EDA post-simulation, and then determine the clock frequency of the pre-simulation clock signal clk and the clock frequency of the post-simulation clock signal clk according to the waveforms in the simulation result waveform files, and generate a pre-simulation clk clock frequency file and a post-simulation clk clock frequency file;

[0025] The clock information checking module is used to compare the clock frequencies of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file, and generate a clk result file according to the comparison result.

[0026] Further, the simulation result waveform file is an fsdb waveform file, and the clock frequency calculation module is configured to: obtain the fsdb waveform in the fsdb waveform file,

[0027] Analyze the edge information of the clock signal clk in the fsdb waveform, the clock signal clk is a periodic pulse signal, and the edge information includes the time point information of the rising edge and the falling edge; obtain the time point information t1 and t2 of any two adjacent clk rising edges; after calculating the adjacent rising edge time interval △t=t2-t1, determine the clock frequency f of the aforementioned clock signal clk, and the calculation formula of the clock frequency f is f=100 / △t.

[0028] Due to the adoption of the above technical scheme, the present invention has the following advantages and positive effects compared with the prior art, as an example: the present invention can determine the clock frequency information of each clock signal clk according to the simulation result waveform files of pre-EDA simulation and post-EDA simulation, and compare it with the clock frequency in the reference clock signal file to check the correctness of the clock, thereby ensuring the accuracy of the clock in EDA simulation and improving EDA simulation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The present invention provides a flowchart of a method for checking clock in chip EDA simulation in chip simulation verification according to an embodiment of the present invention.

[0030] Figure 2 A schematic diagram of information processing for generating a clk result file provided by an embodiment of the present invention.

[0031] Figure 3 This is a diagram showing an example of the data format of the clk table provided in an embodiment of the present invention.

[0032] Figure 4 This is a diagram showing an example of the data format of a clk result file provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following is a further detailed description of the method and device for checking the clock in the chip EDA simulation disclosed in the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered isolated, and they can be combined with each other to achieve better technical effects. In the drawings of the following embodiments, the same reference numerals appearing in each drawing represent the same features or components, which can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0034] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the invention. Any modification of the structure, change of the proportion relationship or adjustment of the size should fall within the scope of the technical content disclosed by the invention without affecting the effects and purposes that can be achieved by the invention. The scope of the preferred embodiments of the present invention includes other implementations, in which the functions can be performed in a substantially simultaneous manner or in a reverse order according to the functions involved, which should be understood by those skilled in the art of the technical field to which the embodiments of the present invention belong.

[0035] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values. Example

[0036] See also Figure 1 As shown, a method for checking clock in chip EDA simulation provided by the present invention comprises the following steps.

[0037] S100, obtaining simulation result waveform files generated by pre-EDA simulation and post-EDA simulation.

[0038] The pre-EDA simulation is the process of simulating and verifying the RTL (Resistor transistor logic, register transfer level) code to verify the correctness of the design code. Currently, it is mainly through applying stimulation to the RTL code (i.e. simulating external input signals) to obtain the results of its operation (whether it meets the expected value or preset value) to determine whether the RTL code can run correctly. The RTL code is the design code formed by describing the module functions of the design using a hardware description language (such as Verilog, etc.). In the front-end design stage, the chip design company designs the chip architecture and divides the aforementioned module functions according to the chip requirements proposed by the customer.

[0039] The EDA post-simulation is a process of simulating the netlist after logic synthesis.

[0040] The simulator and test stimulus used in chip pre-EDA simulation and post-EDA simulation are the same, but the simulation result waveform files are different. After the pre-EDA simulation is completed, the pre-simulation result waveform file can be obtained, and after the post-EDA simulation is completed, the post-simulation result waveform file can be obtained.

[0041] The generated simulation result waveform file is generally an fsdb (Fast Signal Data Base) waveform file.

[0042] S200 , determining the clock frequencies of the pre-simulation clock signal clk and the post-simulation clock signal clk respectively according to the waveforms in the simulation result waveform file, and generating a pre-simulation clk clock frequency file and a post-simulation clk clock frequency file.

[0043] The clock signal clk (short for Clock) is a pulse signal that is continuously sent at a certain voltage amplitude and a certain time interval. The clock edge trigger signal means that all state changes occur at the arrival of the clock edge. In the edge trigger mechanism, the rising edge or falling edge of the clock is used as a valid trigger signal to control the change of the state quantity of the logic unit.

[0044] Taking the fsdb waveform file as an example, the steps of calculating the clock frequency of the clock signal clk according to the fsdb waveform in the fsdb waveform file can be as follows: analyze the edge information of the clock signal clk in the fsdb waveform, the clock signal clk is a periodic pulse signal, and the edge information includes the time point information of the rising edge and the falling edge; obtain the time point information t1 and t2 of any two adjacent clk rising edges; after calculating the adjacent rising edge time interval △t=t2-t1, determine the clock frequency f of the aforementioned clock signal clk, and the calculation formula of the clock frequency f is f=100 / △t.

[0045] As an example but not a limitation, for example, the time points of two adjacent clk rising edges are t1 = 3ps, t2 = 3127ps, where ps represents picoseconds and 1s = 1012ps. Then, the adjacent rising edge time interval △t = t2-t1 = 3124ps can be calculated. According to f = 100 / △t, it can be concluded that the clock frequency of the clock signal clk is 100 / 3124ps = 320MHz.

[0046] The clock frequency information of the pre-simulation clock signal clk can be calculated based on the waveform in the pre-simulation result waveform file. Based on the clock frequency information of the pre-simulation clock signal clk, the pre-simulation clk clock frequency file pre_sim_clk.report can be generated. Figure 2 shown.

[0047] The clock frequency information of the post-simulation clock signal clk can be calculated based on the waveform in the post-simulation result waveform file. Based on the clock frequency information of the post-simulation clock signal clk, the post-simulation clk clock frequency file post_sim_clk.report can be generated. Figure 2 shown.

[0048] S300, comparing the clock frequencies of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file, and generating a clk result file according to the comparison result.

[0049] Continue to see Figure 2 As shown, the clk result file clk.report is generated according to the comparison results.

[0050] In this embodiment, the pre-EDA simulation is to simulate and verify the register transfer level RTL code, and the register transfer level RTL code is provided with clk annotation information for the clk statement, and the clock frequency of the clock signal clk involved in the clk statement is annotated by the clk annotation information. At this time, before the pre-EDA simulation is performed, the step of extracting the clock signal clk and the corresponding clk annotation information in the register transfer level RTL code through a script, obtaining the name and clock frequency value of the clock signal clk, and writing them into a reference clock signal file in a preset data format.

[0051] In the RTL code, add clk comment information after the clk statement to be detected. As an example but not a limitation, the way to add clk comment information can be as follows:

[0052] Input clk_axi / / auto_check: 400M

[0053] Among them, “ / / ” represents a comment symbol, and “auto_check: 400M” represents the specific comment content, which includes the clock frequency value of the clock signal clk involved in the clk statement, such as “400M” in the comment content.

[0054] The script can identify the clk statement "Input clk_axi" in the RTL code and the clk comment information " / / auto_check : 400M" corresponding to the clk statement, and then add the name "clk_axi" and the clock frequency value "400M" of the identified clock signal clk to the reference clock signal file of the preset data format. The reference clock signal file records the name of the clock signal clk and the corresponding clock frequency value.

[0055] In this embodiment, preferably, the reference clock signal file is a clk table in Excel format, and the clk table is preset with two field information, namely, the name clk name of the clock signal clk and the clock frequency value clk freqvalue.

[0056] The specific data format of the clk table can be found in Figure 3 The clk table is provided with two fields, namely the name of the clock signal clk "clk name" and the corresponding clock frequency value "clk freq value". As an example but not a limitation, for example Figure 3 The "clk name" recorded in includes CPU_clk, DDR_clk, AXI_clk and PCIE_clk, which represent the clk configuration information of the CPU, DDR, AXI and PCIE modules respectively. The configured clock frequency values ​​(in Hz) are 800M, 466M, 200M and 400M respectively.

[0057] When the simulation is running, the data in the clk table will be automatically read.

[0058] At the end of the pre-simulation run, a pre_sim_clk.report file is generated based on the pre-simulation result waveform file. The pre_sim_clk.report file records the clk information of the clock signal involved in the pre-simulation, including the clk name and the clock frequency value calculated from the waveform. At the end of the post-simulation run, a post_sim_clk.report file is generated based on the post-simulation result waveform file. The post_sim_clk.report file records the clk information of the clock signal involved in the post-simulation, including the clk name and the clock frequency value calculated from the waveform.

[0059] After merging the report files of the pre-simulation and post-simulation and comparing them with the reference clock signal file clk table, a clk result file clk.report can be obtained. Only when the clock information in the clk table is consistent with the clock information of the EDA pre-simulation and the clock information of the EDA post-simulation, the clock is judged to be error-free; otherwise, the simulation clock is judged to be wrong, and the wrong clk information is marked in the clk result file clk.report, so that the wrong clk information is displayed to the user.

[0060] The clk result file clk.report may display the names of various clock signals clk, and for each clock signal clk, display the clock frequency value of the clock signal clk in the reference clock signal file, the pre-simulation clk clock frequency file, and the post-simulation clk clock frequency file.

[0061] As an example of a typical approach, see Figure 4 As shown, the clk table is preset with 4 field information, namely the name information of the clock signal clk "Excel clk name" and 3 clock frequency values ​​"Excel clk value", "Pre_simclk value" and "Post_sim clk value", which are respectively used to record the corresponding clock frequency values ​​in the clk table Excel clk (reference clock signal file), the pre-simulation clk clock frequency file and the post-simulation clk clock frequency file.

[0062] In the clk result file clk.report, the clk information that is inconsistent with the clk table in the pre-simulation and post-simulation can be marked, and if it is consistent, it can be left unmarked. Specifically, when performing the aforementioned comparison, if it is determined that the clock frequency information of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file are inconsistent, the inconsistent clk clock frequency value is marked in the clk result file, or the inconsistent clk name and clock frequency value are marked in the clk result file.

[0063] Preferably, when the user opens the aforementioned simulation result waveform file through the waveform tool, after reading the aforementioned clk result file, the position of the clock signal clk with inconsistent clock frequency is marked in the waveform tool corresponding to the output simulation result waveform.

[0064] In one embodiment, when the user opens the simulation result waveform file through a waveform tool, the clk result file is directly read, and then the location of the inconsistent clock signal clk is marked in the output simulation result waveform according to the clk result file.

[0065] In another embodiment, a clk marking operation command is preset in the waveform tool, such as "nWave-report clk.report". At this time, when the user opens the simulation result waveform file through the waveform tool, the user can trigger the exclusive clk result file by inputting the command "nWave-report clk.report", and then mark the location of the inconsistent clock signal clk in the output simulation result waveform according to the clk result file, such as marking the inconsistent clk waveform in a distinctive red color on the graph.

[0066] In another embodiment, a clk result file import option is provided in the waveform tool, which is usually a trigger control. When the user triggers the aforementioned clk result file import option, the aforementioned clk result file is read, and then the location of the inconsistent clock signal clk is marked in the output simulation result waveform according to the clk result file, for example, the inconsistent clk waveform is marked on the graph with a distinctive red color.

[0067] Another embodiment of the present invention further provides a clock checking device in chip EDA simulation.

[0068] The clock checking device comprises a clock frequency calculation module and a clock information checking module.

[0069] The clock frequency calculation module is used to obtain the simulation result waveform files generated by EDA pre-simulation and EDA post-simulation, and then determine the clock frequency of the pre-simulation clock signal clk and the clock frequency of the post-simulation clock signal clk according to the waveforms in the simulation result waveform files, and generate a pre-simulation clk clock frequency file and a post-simulation clk clock frequency file.

[0070] The clock information checking module is used to compare the clock frequencies of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file, and generate a clk result file according to the comparison result.

[0071] In this embodiment, the simulation result waveform file is preferably an fsdb waveform file.

[0072] At this time, the clock frequency calculation module is configured to: obtain the fsdb waveform in the fsdb waveform file, analyze the edge information of the clock signal clk in the fsdb waveform, the clock signal clk is a periodic pulse signal, and the edge information includes the time point information of the rising edge and the falling edge; obtain the time point information t1 and t2 of any two adjacent clk rising edges; after calculating the adjacent rising edge time interval △t=t2-t1, determine the clock frequency f of the aforementioned clock signal clk, and the calculation formula of the clock frequency f is f=100 / △t.

[0073] In this embodiment, the pre-EDA simulation is to simulate and verify the register transfer level RTL code, and clk annotation information is set for the clk statement in the register transfer level RTL code, and the clock frequency of the clock signal clk involved in the clk statement is annotated through the clk annotation information.

[0074] At this time, before performing pre-EDA simulation, the steps also include: extracting the clock signal clk and the corresponding clk annotation information in the register transfer level RTL code through a script, obtaining the name and clock frequency value of the clock signal clk, and writing them into a reference clock signal file in a preset data format.

[0075] The reference clock signal file is preferably a clk table in Excel format, and the clk table is preset with two field information, namely, the name of the clock signal clk clk name and the clock frequency value clk freq value.

[0076] The clk result file may display the names of various clock signals clk, and for each clock signal clk, display the clock frequency value of the clock signal clk in the reference clock signal file, the pre-simulation clk clock frequency file and the post-simulation clk clock frequency file.

[0077] When performing the above-mentioned comparison, if it is determined that the clock frequency information of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file are inconsistent, the inconsistent clk clock frequency value is marked in the clk result file, or the inconsistent clk name and clock frequency value are marked.

[0078] For other technical features, please refer to the previous embodiments and will not be described in detail here.

[0079] In the above description, the disclosure of the present invention is not intended to limit itself to these aspects. Rather, within the scope of the target protection of the present disclosure, the components can be selectively and operatively combined in any number. In addition, terms such as "include", "encompass" and "have" should be interpreted as inclusive or open by default, rather than exclusive or closed, unless they are explicitly defined to the contrary. All technical, scientific or other terms are consistent with the meanings understood by those skilled in the art, unless they are defined to the contrary. Common terms found in dictionaries should not be interpreted too idealistically or too impractically in the context of relevant technical documents, unless the present disclosure explicitly defines them as such. Any changes and modifications made by a person of ordinary skill in the field of the present invention based on the above disclosure belong to the scope of protection of the claims.

Claims

1. A method for checking clock in chip EDA simulation, characterized in that Includes steps: Obtain simulation result waveform files generated by pre-EDA simulation and post-EDA simulation; Determine the clock frequency of the pre-simulation clock signal clk and the clock frequency of the post-simulation clock signal clk respectively according to the waveform in the simulation result waveform file, and generate a pre-simulation clk clock frequency file and a post-simulation clk clock frequency file; Compare the clock frequencies of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file, and generate a clk result file according to the comparison result; in, The pre-EDA simulation is to simulate and verify the register transfer level RTL code, in which clk annotation information is set for the clk statement, and the clock frequency of the clock signal clk involved in the clk statement is annotated through the clk annotation information; at this time, before performing the pre-EDA simulation, it also includes the steps of: extracting the clock signal clk and the corresponding clk annotation information in the register transfer level RTL code through a script, obtaining the name and clock frequency value of the clock signal clk, and writing them into a reference clock signal file in a preset data format.

2. The method according to claim 1, characterized in that: The simulation result waveform file is a fsdb waveform file.

3. The method according to claim 2, characterized in that: The steps to calculate the clock frequency of the clock signal clk according to the fsdb waveform in the fsdb waveform file are as follows: Analyze the edge information of the clock signal clk in the fsdb waveform, wherein the clock signal clk is a periodic pulse signal, and the edge information includes the time point information of the rising edge and the falling edge; Get the time point information t1 and t2 of any two adjacent clk rising edges; After calculating the time interval Δt=t2-t1 between adjacent rising edges, the clock frequency f of the clock signal clk is determined. The calculation formula of the clock frequency f is f=100 / Δt.

4. The method according to claim 1, characterized in that: The reference clock signal file is a clk table in Excel format, and the clk table is preset with two field information, namely, the name of the clock signal clk clk name and the clock frequency value clk freq value.

5. The method according to claim 1, characterized in that: The clk result file displays the names of various clock signals clk, and for each clock signal clk, displays the clock frequency value of the clock signal clk in the reference clock signal file, the pre-simulation clk clock frequency file, and the post-simulation clk clock frequency file.

6. The method according to claim 5, characterized in that: When performing the above-mentioned comparison, if it is determined that the clock frequency information of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file are inconsistent, the inconsistent clk clock frequency value is marked in the clk result file, or the inconsistent clk name and clock frequency value are marked.

7. The method according to claim 6, characterized in that: The user is collected to open the simulation result waveform file through the waveform tool, and after reading the clk result file, the position of the clock signal clk with inconsistent clock frequency is marked in the waveform tool corresponding to the output simulation result waveform.

8. A clock checking device in chip EDA simulation, characterized in that include: A clock frequency calculation module is used to obtain the simulation result waveform files generated by EDA pre-simulation and EDA post-simulation, and then determine the clock frequency of the pre-simulation clock signal clk and the clock frequency of the post-simulation clock signal clk according to the waveforms in the simulation result waveform files, and generate a pre-simulation clk clock frequency file and a post-simulation clk clock frequency file; The clock information checking module is used to compare the clock frequencies of the pre-simulation clk clock frequency file, the post-simulation clk clock frequency file and the reference clock signal file, and generate a clk result file according to the comparison result; in, The pre-EDA simulation is to simulate and verify the register transfer level RTL code, in which clk annotation information is set for the clk statement, and the clock frequency of the clock signal clk involved in the clk statement is annotated through the clk annotation information; at this time, before performing the pre-EDA simulation, it also includes the steps of: extracting the clock signal clk and the corresponding clk annotation information in the register transfer level RTL code through a script, obtaining the name and clock frequency value of the clock signal clk, and writing them into a reference clock signal file in a preset data format.

9. The device according to claim 8, characterized in that: The simulation result waveform file is an fsdb waveform file, and the clock frequency calculation module is configured to: obtain the fsdb waveform in the fsdb waveform file, Analyze the edge information of the clock signal clk in the fsdb waveform, the clock signal clk is a periodic pulse signal, and the edge information includes the time point information of the rising edge and the falling edge; obtain the time point information t1 and t2 of any two adjacent clk rising edges; after calculating the adjacent rising edge time interval △t=t2-t1, determine the clock frequency f of the aforementioned clock signal clk, and the calculation formula of the clock frequency f is f=100 / △t.

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