Method for identifying the resistance state of programmable elements of integrated circuits

Abstract

The present disclosure provides a method for identifying a resistance state of a programmable element of an integrated circuit. The method includes the steps of: setting a first programming voltage of a first polarity to program the programmable element of the integrated circuit; setting a first read voltage of the first polarity to the integrated circuit at a first temperature to obtain a first read current, and deriving a first resistance from the first read current; setting the first read voltage of the first polarity to the integrated circuit at a second temperature to obtain a second read current, the second temperature being at least 50°C higher than the first temperature, and deriving a second resistance from the second current; and comparing the first resistance and the second resistance to identify the resistance state of the programmable element.

Description

Technical Field

[0001] This disclosure relates to a method for identifying the resistance state of a programmable element. Background Technology

[0002] This application claims priority and benefits to U.S. Official Application No. 17 / 136,777, filed December 29, 2020, the contents of which are incorporated herein by reference in their entirety.

[0003] The performance of electronic components is almost entirely determined by their resistance state, thus a simple method for identifying the resistance state of electronic components is needed.

[0004] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a method for identifying the resistance state of a programmable element of an integrated circuit, comprising: setting a first programmable voltage of a first polarity to program the programmable element of the integrated circuit; setting a first read voltage of the first polarity to the integrated circuit at a first temperature to obtain a first read current, and deriving a first resistance from the first read current; setting the first read voltage of the first polarity to the integrated circuit at a second temperature at least 50°C higher than the first temperature, and deriving a second resistance from the second read current; and comparing the first resistance with the second resistance to identify the resistance state of the programmable element.

[0006] In some embodiments, the first temperature is between about 0°C and about 40°C.

[0007] In some embodiments, the second temperature is between approximately 90°C and approximately 110°C.

[0008] In some embodiments, the step of setting the first programmable voltage of the first polarity to program the programmable element of the integrated circuit is performed at a temperature between about 90°C and about 110°C.

[0009] In some embodiments, the first polarity is positive relative to the ground potential.

[0010] In some embodiments, the programmable element is electrically coupled between a first terminal of the integrated circuit and a voltage node, and the first programmable voltage is applied to the first terminal.

[0011] In some embodiments, the voltage node includes a ground potential.

[0012] In some embodiments, the integrated circuit includes a protection transistor coupled between the programmable element and the voltage node.

[0013] In some embodiments, the integrated circuit includes a selection transistor electrically coupled between the protection transistor and the voltage node.

[0014] In some embodiments, the programmable element includes an upper electrode and a lower electrode, the upper electrode being electrically coupled to the first terminal and the lower electrode being electrically coupled to the voltage node and separated from the upper electrode by an intermediate isolation layer.

[0015] In some embodiments, the programmable element includes a programming gate electrode, a first channel region, a first impurity region, and a second impurity region. The programming gate electrode is electrically coupled to the first terminal. The first channel region is separated from the programming gate electrode by a first isolation layer. The first impurity region and the second impurity region are respectively adjacent to both sides of the first channel region, and the first impurity region is electrically coupled to the voltage node.

[0016] In some embodiments, the second impurity region is electrically floated.

[0017] In some embodiments, the integrated circuit includes a first conductive line electrically coupled to the voltage node, and a first bias voltage of a second polarity applied to the first conductive line.

[0018] In some embodiments, the second polarity is negative relative to the ground potential.

[0019] In some embodiments, the first bias voltage is between approximately -1.0 volts and approximately -2.0 volts.

[0020] In some embodiments, the programming voltage is between approximately +5.0 volts and approximately +10.0 volts.

[0021] In some embodiments, the select transistor includes a third impurity region, a fourth impurity region, and a select gate electrode. The third impurity region is electrically coupled to the protection transistor, the fourth impurity region is electrically coupled to the voltage node and separated from the third impurity region by a second channel region, the select gate electrode is located on the second channel region, and a second isolation layer is inserted between the select gate electrode and the second channel region.

[0022] In some embodiments, the select transistor includes a first slightly impurity region and a second slightly impurity region, the first slightly impurity region being disposed adjacent to the third impurity region, the second slightly impurity region being disposed adjacent to the fourth impurity region, and the second channel region being located between the first slightly impurity region and the second slightly impurity region.

[0023] Another embodiment of this disclosure provides a method for determining the minimum programming current of a programmable element of an integrated circuit, comprising: setting a first programming voltage to program the programmable element of the integrated circuit and obtaining a first programming current; setting a first read voltage to the integrated circuit at a first temperature to obtain a first read current, and deriving a first resistance from the first read current; setting the first read voltage to the integrated circuit at a second temperature at least 50°C higher than the first temperature, and deriving a second resistance from the second read current; comparing the first resistance and the second resistance to determine that a resistance state of the programmable element is an ohmic state; and considering the first programming current as the minimum programming current.

[0024] Another embodiment of this disclosure provides a method for determining the minimum programming current of a programmable element of an integrated circuit, comprising: setting a first programming voltage to program the programmable element of the integrated circuit and obtaining a first programming voltage; setting a first read voltage to the integrated circuit at a first temperature to obtain a first read current, and deriving a first resistance from the first read current; setting the first read voltage to the integrated circuit at a second temperature, the second temperature being at least 50°C higher than the first temperature, and deriving a second resistance from the second read current; comparing the first resistance and the second resistance to determine whether a resistance state of the programmable element is a jumping state or a surface scattering state; adjusting the integrated circuit and setting the first programming voltage to reprogram the programmable element to obtain a post-adjustment programming current; setting a first read voltage to the integrated circuit at the first temperature to obtain a first read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a second read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a second read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a second read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a first ...; setting a first read voltage to the integrated circuit at a second temperature; setting a first read voltage to the integrated circuit at a second temperature; setting A first read voltage is applied to the integrated circuit to obtain a first post-stage adjustment read current, and a first post-stage adjustment resistor is derived from the first post-stage adjustment read current; at the second temperature, the first read voltage is applied to the integrated circuit to obtain a second post-stage adjustment read current, and a second post-stage adjustment resistor is derived from the second post-stage adjustment read current; the first post-stage adjustment resistor and the second post-stage adjustment resistor are compared to determine that the resistance state of the programmable element is in an ohmic state; the post-stage adjustment programming current is regarded as the minimum programming current; and if, in the step of comparing the first post-stage adjustment resistor and the second post-stage adjustment resistor, the resistance state of the programmable element is determined to be in a jumping state or a surface scattering state, then the step of adjusting the integrated circuit and setting the first programming voltage is repeated to the step of comparing the first post-stage adjustment resistor and the second post-stage adjustment resistor.

[0025] The identification method of this disclosure can easily identify the resistance state of the programmable element. Therefore, programmable elements that do not meet the specifications (i.e., are in a skip state or surface scattering state) can be easily screened out, and corresponding processing, such as reprogramming, can be performed immediately. This shortens the manufacturing time of the electronic component, which is determined using this method for identifying the resistance state of the programmable element.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0027] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 A flowchart illustrating a method for identifying a plurality of programmable elements of an integrated circuit according to an embodiment of the present disclosure is shown.

[0029] Figure 2 A circuit diagram of the integrated circuit according to an embodiment of the present disclosure is shown.

[0030] Figure 3 A cross-sectional schematic diagram illustrating one of the programmable elements of the integrated circuit according to an embodiment of the present disclosure is shown.

[0031] Figure 4 This illustration shows a schematic diagram of the resistance distribution of the programmable element in a jump state according to an embodiment of the present disclosure at a first temperature and a second temperature.

[0032] Figure 5 A schematic diagram illustrating the resistance distribution of a programmable element under a surface scattering state according to an embodiment of the present disclosure at the first temperature and the second temperature.

[0033] Figure 6 A schematic diagram illustrating the resistance distribution of the programmable element in an ohmic state according to an embodiment of the present disclosure at the first temperature and the second temperature.

[0034] Figure 7A flowchart illustrating a method for determining the minimum programming current of a programmable element of an integrated circuit according to another embodiment of the present disclosure.

[0035] Figure 8 An illustrative data graph of the programmed current for different resistance states is shown in another embodiment of this disclosure.

[0036] Figure 9 A circuit diagram of an integrated circuit according to another embodiment of the present disclosure is shown.

[0037] Figure 10 A cross-sectional schematic diagram illustrating one of the programmable elements of the integrated circuit according to another embodiment of the present disclosure.

[0038] Figure 11 A circuit diagram of an integrated circuit according to another embodiment of the present disclosure is shown.

[0039] Figure 12 A circuit diagram of an integrated circuit according to another embodiment of the present disclosure is shown.

[0040] Figure 13 A cross-sectional schematic diagram illustrating one of the selection transistors of the integrated circuit according to another embodiment of the present disclosure.

[0041] The reference numerals in the attached figures are explained as follows:

[0042] 10: Identification Methods

[0043] 20: Determine the method

[0044] 101: First terminal

[0045] 103: Voltage node

[0046] 105: First conductive line

[0047] 201: Programmable Components

[0048] 203: Upper electrode

[0049] 205: Lower electrode

[0050] 207: Intermediate isolation layer

[0051] 209: Base

[0052] 211: Programmable Gate Electrode

[0053] 213: First Passage Area

[0054] 215: First Isolation Layer

[0055] 217: First impurity region

[0056] 219: Second impurity region

[0057] 221: Upper conductive layer

[0058] 301: Protection transistor

[0059] 401: Select Transistor

[0060] 403: Select gate electrode

[0061] 405: Second Passage Area

[0062] 407: Second Isolation Layer

[0063] 409: Select gate spacer

[0064] 411: Third impurity region

[0065] 413: Fourth impurity region

[0066] 415: First light impurity zone

[0067] 417: Second light impurity zone

[0068] 419: First smudged impurity area

[0069] 421: Second smudged impurity area

[0070] 501: Barrier Transistor

[0071] 601: Control Logic Unit

[0072] R HT Second resistor

[0073] R' HT The second stage involves adjusting the reading resistor.

[0074] R LT First resistor

[0075] R' LT First, adjust the reading resistor in the later stage.

[0076] S11: Steps

[0077] S13: Steps

[0078] S15: Steps

[0079] S17: Steps

[0080] S21: Steps

[0081] S23: Steps

[0082] S25: Steps

[0083] S27: Steps

[0084] S27-1: Steps

[0085] S29: Steps

[0086] S31: Steps

[0087] S33: Steps

[0088] S35: Steps

[0089] S35-1: Steps Detailed Implementation

[0090] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0091] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0092] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0093] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0094] Unless otherwise specified herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as "same," "equal," "planar," or "coplanar" as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, that the orientation, layout, location, shape, size, amount, or other measure is substantially identical, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" means exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which can occur due to the manufacturing process.

[0095] It should be understood that in the description of this disclosure, "above" (or "up") refers to the direction corresponding to the Z-direction arrow, while "below" (or "down") refers to the relative direction corresponding to the Z-direction arrow.

[0096] Figure 1 A flowchart illustrating a method 10 for identifying a plurality of programmable elements 201 of an integrated circuit according to an embodiment of the present disclosure is shown. Figure 2 A circuit diagram of the integrated circuit according to an embodiment of the present disclosure is shown. Figure 3A cross-sectional schematic diagram of one programmable element 201 of the integrated circuit according to an embodiment of the present disclosure is shown.

[0097] Please refer to Figures 1 to 3 In step S11, a substrate 101 is provided; for example, the integrated circuit including a plurality of programmable elements 201 is provided, a first programming voltage can be applied to the integrated circuit to program the programmable elements 201, and a first programming current can be obtained.

[0098] Please refer to Figure 2 The integrated circuit has a first terminal 101, multiple voltage nodes 103, multiple programmable elements 201, multiple protection transistors 301, and multiple selection transistors 401.

[0099] Please refer to Figure 2 In some embodiments, the first terminal 101 may be electrically coupled to the programmable element 201. The programmable element 201 may be connected in parallel to form an array. The protection transistor 301 may be connected in parallel. The selection transistor 404 may be connected in parallel. For ease of description, only one programmable element 201, one protection transistor 301, and one selection transistor 401 are described. The programmable element 201 may be electrically coupled between the first terminal 101 and one of the corresponding voltage nodes 103. The protection transistor 301 may be electrically coupled between the programmable element 201 and the corresponding voltage node 103. The selection transistor 401 may be electrically coupled between the protection transistor 301 and the corresponding voltage node 103. In other words, the programmable element 201 may be electrically coupled between the first terminal 101 and the protection transistor 301, and the protection transistor 301 may be electrically coupled between the programmable element 201 and the selection transistor 401.

[0100] It should be understood that, such as Figure 2 The three programmable elements 201 shown are for illustrative purposes only. The number of programmable elements 201 may be greater than or less than three. For example, the number of programmable elements 201 may be four, five or more.

[0101] In some embodiments, the first terminal 101 may be an external pin to which the integrated circuit is associated. In some embodiments, the integrated circuit may include a plurality of first terminals 101. Each first terminal 101 may be electrically coupled to a corresponding programmable element 201.

[0102] Please refer to Figure 3In some embodiments, the programmable element 201 may have a capacitor-like structure and may have an upper electrode 203, a lower electrode 205, and an intermediate isolation layer 207. The upper electrode 203 and the lower electrode 205 may be separated by the intermediate isolation layer 207 inserted therebetween. The upper electrode 203 may be electrically coupled to the first terminal 101. The lower electrode 205 may be coupled to the protection transistor 301 or the voltage node 103.

[0103] For example, the upper electrode 203 and the lower electrode 205 may comprise polycrystalline silicon, doped polycrystalline silicon, polycrystalline silicon germanium, doped polycrystalline silicon germanium, or a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum). For example, the intermediate insulating layer 207 may comprise oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, high-k materials, or any combination thereof. The high-k material may have a k value greater than 7.0 and may be a metal oxide or a silicate of Hf, Al, La, Mg, Ba, Ti, or Pb, or a combination thereof. Examples of high dielectric constant materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. For example, the high dielectric constant material may also contain multiple dopants, such as lanthanum and aluminum. In some embodiments, the intermediate insulating layer 207 may have a thickness between approximately To about between.

[0104] In a programming process, the first programming voltage can be applied to the integrated circuit via the first terminal 101, and the voltage node 103 can be set to ground potential. An intermediate isolation layer 207 can be compressed under the first programming voltage. This causes the intermediate isolation layer 207 to break, forming a contiguous path connecting the upper electrode 203 and the lower electrode 205. After the initial breakage of the intermediate isolation layer 207, the programming voltage is applied for a specified time interval to allow current to flow through the programmable element 201, thereby reducing the resistance of the contiguous path through the programmable element 201. This specified time interval can be considered a soak interval. In some embodiments, the soak interval can be between approximately 10 microseconds and approximately 600 microseconds, between approximately 10 microseconds and approximately 50 microseconds, or between approximately 10 microseconds and approximately 20 microseconds.

[0105] In some embodiments, the first programming voltage may have a first polarity that is positive relative to ground potential. In some embodiments, the first programming voltage may be generated by a charge-pump circuit. In some embodiments, the first programming voltage may be between approximately +6.0 volts and approximately +10.5 volts, between approximately +6.0 volts and approximately +8.5 volts, or between approximately +6.0 volts and approximately +6.5 volts.

[0106] Because a relatively high programming voltage is required to programmable element 201, protection transistor 301 provides voltage insulation, thereby protecting other circuit elements from damage (e.g., selection transistor 401). In some embodiments, during the programming process, a first operating voltage between the first programming voltage and ground potential may be applied to protection transistor 301. In some embodiments, the first operating voltage may be between approximately +0.5 volts and approximately +2.0 volts. In some embodiments, ground potential may be set to some protection transistors 301. During this programming process, programmable element 201 having ground potential and electrically coupled to protection transistor 301 is not programmed.

[0107] In some embodiments, during the programming process, a second operating voltage between the first programming voltage and the ground potential may be applied to the select transistor 401. In some embodiments, the second operating voltage may be between approximately +0.5 volts and approximately +2.0 volts. In some embodiments, the ground potential may be set to some of the select transistors 401. In this programming process, the programmable element 201 having the ground potential and electrically coupled to the select transistor 401 is not programmed.

[0108] In some embodiments, some voltage nodes 103 may be set to a voltage greater than the ground potential. In this programming process, since the voltage difference is not greater than the breakdown voltage of the programmable element 201, the programmable element 201, which has a ground potential and is electrically coupled to the voltage node 103, is not programmed.

[0109] In some embodiments, the programmable elements 201 may be programmed together during a single programming process. In some embodiments, only one programmable element 201 is programmed during a single programming process. In some embodiments, several programming elements 201 may be programmed during a single programming process. In some embodiments, the programming process may be carried out at a temperature between approximately 90°C and approximately 110°C.

[0110] Please refer to Figure 1 and Figure 2 In step S13, at a first temperature, a first read voltage can be applied to the integrated circuit, and a first read current can be measured. This first read current derives a first resistance R. LT .

[0111] Please refer to Figure 2 Following the programming procedure, in a first read procedure, a first read voltage can be applied via the first terminal 101, and the voltage node 103 can be set to ground potential. The first read voltage may have the first polarity. The first read voltage may be between approximately +0.5 volts and approximately +2.0 volts, between approximately +1.0 volts and approximately +2.0 volts, between approximately +1.0 volts and approximately +1.5 volts, or between approximately +1.0 volts and approximately 1.2 volts. The first operating voltage for protecting transistor 301 and the second operating voltage for selecting transistor 401 can be set to approximately +1.5 volts. The first temperature may be between approximately 0°C and approximately 40°C. In the first read procedure, the first read current can be measured. The first read current can derive a first resistance R. LT .

[0112] Please refer to Figure 1 and Figure 2In step S15, at a second temperature, a second read voltage can be applied to the integrated circuit, and a second read current can be measured. This second read current derives a second resistance R. HT .

[0113] Please refer to Figure 2 Following the first read procedure, in a second read procedure, the second read voltage can be applied via the first terminal 101, and the voltage node 103 can be set to ground potential. The second read voltage may have the first polarity. The second read voltage may be between approximately +0.5 volts and approximately +2.0 volts, between approximately +1.0 volts and approximately +2.0 volts, between approximately +1.0 volts and approximately +1.5 volts, or between approximately +1.0 volts and approximately +1.2 volts. The first operating voltage for protecting transistor 301 and the second operating voltage for selecting transistor 401 can be set to +1.5 volts. The second temperature may be between approximately 90°C and approximately 110°C. In the second read procedure, the second read current can be measured. The second read current can derive a second resistance R. HT .

[0114] Figure 4 This diagram illustrates the resistance distribution of the programmable element 201 in a jump state according to an embodiment of the present disclosure at a first temperature and a second temperature. Figure 5 This diagram illustrates the resistance distribution of a programmable element 201 under a surface scattering state according to an embodiment of the present disclosure at the first temperature and the second temperature. Figure 6 This diagram illustrates the resistance distribution of the programmable element 201 in an ohmic state according to an embodiment of the present disclosure at the first temperature and the second temperature.

[0115] Please refer to Figure 1 and Figures 4 to 6 In step S17, the first resistor R can be compared. LT With the second resistor R HT To identify the state of a resistor in the programmable element 201.

[0116] Please refer to Figure 4 When the first resistance R is obtained at the first temperature LT The second resistance R obtained at the second temperature is lower than that obtained at the second temperature. HT When this occurs, the resistor state of the programmable element 201 is identified as the hopping state.

[0117] Please refer to Figure 5 When the first resistance R is obtained at the first temperature LT Approximately the same as the second resistance R obtained at that second temperature HTAt that time, the resistive state of the programmable element 201 is identified as the surface scattering state.

[0118] Please refer to Figure 6 When the first resistance R is obtained at the first temperature LT The second resistance R obtained at the second temperature is greater than that obtained at the second temperature. HT When this occurs, the resistance state of the programmable element 201 is identified as an ohmic state.

[0119] When the resistance state of the programmable element 201 is critical to its electronic performance, the programmable element 201 identified as the jumping state or the surface scattering state has relatively poor electronic performance compared to the programmable element 201 identified as the ohmic state.

[0120] Programmable element 201 identified as being in the jumping state or the surface scattering state may need to be reprogrammed at a larger programming voltage or the integrated circuit may need to be adjusted, for example, by adjusting the first operating voltage for the protection transistor 301, adjusting the second operating voltage for the selection transistor 401, adjusting the element length of the protection transistor 301, or adjusting the element length of the selection transistor 401.

[0121] Because of the design of method 10 according to an embodiment of this disclosure, the resistance state of the programmable element 201 can be easily identified. Therefore, programmable elements 201 that do not meet the specification criteria (i.e., are in a skip state or surface scattering state) can be easily screened out, and corresponding processing can be performed immediately. This shortens the manufacturing time of the electronic component, which is achieved using the method for identifying the resistance state of the programmable element 201.

[0122] Figure 7 A flowchart illustrating a method 20 for determining a minimum programming current of a programmable element 201 of a programmable integrated circuit according to another embodiment of the present disclosure is shown.

[0123] Please refer to Figure 7 In step S21, an integrated circuit including a plurality of programmable elements 201 may be provided, a first programming voltage may be applied to the integrated circuit to program the programming unit 201, and a first programming current may be measured.

[0124] The integrated circuit may have a design similar to that described in step S11. The first programming voltage may be applied to the first terminal 101 to program the programmable element 201. The programming process may be performed at a temperature between approximately 90°C and approximately 110°C. During the programming process, the protection transistor 301 and the selection transistor 401 may be turned on. The first programming current may be measured during the programming process.

[0125] Please refer to Figure 7 In step S23, at a first temperature, a first read voltage can be applied to the integrated circuit, and a first read current can be measured. This first read current derives a first resistance R. LT Step S23 can be performed in a procedure similar to step S13.

[0126] Please refer to Figure 7 In step S25, at a second temperature, a second read voltage can be applied to the integrated circuit, and a second read current can be measured. This second read current derives a second resistance R. HT Step S25 can be implemented in a procedure similar to that described in step S15.

[0127] Please refer to Figure 7 In step S27, the first resistor R can be compared. LT With the second resistor R HT The resistance state of the programmable element 201 is determined to be ohmic. If the resistance state of the programmable element 201 is ohmic, the first programming current can be considered as the minimum programming current in step S27-1. If the resistance state of the programmable element 201 is not ohmic, then step S29 is performed.

[0128] Please refer to Figure 7 In step S29, the integrated circuit can be fine-tuned, and the first programming voltage can be applied to the integrated circuit to reprogram it. A post-tuning programming current can be measured.

[0129] In some embodiments, the fine-tuning procedure of the integrated circuit may include adjusting the first operating voltage for the protection transistor 301, the second operating voltage for the selection transistor 401, the element length of the protection transistor 301, or the element length of the selection transistor 401. Following the fine-tuning procedure, a reprogramming procedure may be performed on the integrated circuit. In some embodiments, the first programming voltage may be applied to the first terminal 101, and the voltage node 103 may be set to ground potential. During the reprogramming procedure, the downstream adjustment programming current may be measured. During the reprogramming procedure, the protection transistor 301 and the selection transistor 401 may be turned on. The voltages applied to the protection transistor 301 and the selection transistor 401 may be similar to the voltages described in step S21.

[0130] In some embodiments, the fine-tuning procedure of the integrated circuit can be omitted. The programmable element 201, whose resistor is not in an ohmic state, can be reprogrammed by a programming voltage greater than the first programming voltage.

[0131] Please refer to Figure 7 In step S31, at the first temperature, the first read voltage can be applied to the integrated circuit, and a first post-stage adjustment read current can be measured. This first post-stage adjustment read current derives a first post-stage adjustment resistor R'. LT Step S31 can be performed in a procedure similar to that described in step S23.

[0132] Please refer to Figure 7 In step S33, at the second temperature, the first read voltage can be applied to the integrated circuit, and a second post-stage adjustment read current can be measured. This second post-stage adjustment read current derives a second post-stage adjustment resistor R'. HT Step S33 can be performed in a procedure similar to that described in step S25.

[0133] Please refer to Figure 7 In step S35, the first rear-stage adjustment resistor R' can be compared. LT With the second rear section adjustment resistor R' HT To determine whether a resistor in the programmable element 201 is in an ohmic state. If the resistor in the programmable element 201 is in an ohmic state, then the subsequent adjustment programming current can be considered as the minimum programming current in step S35-1. If the resistor in the programmable element 201 is not in an ohmic state, then steps S29 to S35 can be repeated.

[0134] Figure 8 An illustrative data graph of the programmed current for different resistance states is shown in another embodiment of this disclosure.

[0135] During a programming process, the minimum programming current can be used as a specification standard to quickly check the resistive state of a programmable element. For example, during the programming of another programmable element, if the measured programming current is less than the minimum programming current (i.e., 3E-03A), the programmable element will be considered defective and can be directly reprogrammed. Conversely, if the measured programming current is greater than the minimum programming current, the programmable element will be considered good and no further reprogramming is required.

[0136] Figure 9 A circuit diagram of an integrated circuit according to another embodiment of the present disclosure is shown. Figure 10 A cross-sectional schematic diagram of one of the programmable elements 201 of the integrated circuit, illustrating another embodiment of the present disclosure.

[0137] Please refer to Figure 9 The integrated circuit has a similarity to that in Figure 2 The design described. Figure 9 Zhongyu Figure 2 Identical or similar components are already labeled with similar component numbers, and redundant descriptions have been omitted. Figure 9 The programmable element 201 may have a transistor-like structure. For ease of description, only one programmable element 201 is described. A first terminal 101 may be electrically coupled to a programming gate electrode 211 of the programmable element 201. A protection transistor 301 may be electrically coupled to a first impurity region 217 of the programmable element 201. In some embodiments, a second impurity region 219 of the programmable element 201 may be left floating and show no connection.

[0138] Please refer to Figure 10 The programmable element 201 may include a programming gate electrode 211, a first channel region 213, a first isolation layer 215, a first impurity region 217, and a second impurity region 219. The first isolation layer 215 may be disposed on a substrate 209. The programming gate electrode 211 may be disposed on the first isolation layer 215 and electrically coupled to a first terminal 101. The first channel region 213 may be a part of the substrate 209 and may be disposed opposite to the programming gate electrode 211, with the first isolation layer 215 interposed between the first channel region 213 and the programming gate electrode 211. The first impurity region 217 and the second impurity region 219 may be disposed in the substrate 209 and adjacent to both sides of the first isolation layer 215. That is, the first impurity region 217 and the second impurity region 219 may be adjacent to both sides of the first channel region 213.

[0139] The substrate 209 may include a semiconductor material, such as an elemental semiconductor, a compound or alloy semiconductor, or a combination thereof; the elemental semiconductor includes Si and Ge; the compound or alloy semiconductor includes SiC, SiGe, GaAs, GaP, GAASP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, or GaInAsP. The substrate 209 may be doped or undoped. The first doped region 217 and the second doped region 219 may have an electrical type opposite to that of the substrate 209. The first doped region 217 and the second doped region 219 may be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. The doping concentration of the first isolation layer 215 and the first impurity region 217 may be between approximately 1E17 atoms / cm². 3 Up to approximately 1E18 atoms / cm 3 between.

[0140] For example, the first insulating layer 215 may comprise oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, high-k materials, or any combination thereof. The high-k material may have a k value greater than 7.0 and may be a metal oxide or a silicate of Hf, Al, La, Mg, Ba, Ti, Pb, or a combination thereof. Examples of the high-k material include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. For example, the high dielectric constant material may also contain multiple dopants, such as lanthanum and aluminum. In some embodiments, the first insulating layer 215 may have a thickness between approximately To about between.

[0141] For example, the programmable gate electrode 211 may comprise polysilicon, doped polysilicon, polysilicon germanium, doped polysilicon germanium, or a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum). In some embodiments, an upper conductive layer 221 may be disposed on the programmable gate electrode 211. For example, the upper conductive layer 221 may comprise titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0142] The programmable element 201 can be executed via the collapse or rupture of its first isolation layer 215. Figure 9 and Figure 10 The programming of the programmable element 201 in the middle. Due to the collapse of the first isolation layer 215, a conductive path is formed through the first isolation layer 215, thereby forming a programming connection between the programming gate electrode 211 and the first channel region 213 or the first impurity region 217.

[0143] Figure 11 A circuit diagram of an integrated circuit according to another embodiment of the present disclosure is shown.

[0144] Please refer to Figure 11 The integrated circuit has a similar feature to, for example Figure 2 The design described. Figure 9 Zhongyu Figure 2 Identical or similar components are already labeled with similar component numbers, and redundant descriptions have been omitted. Figure 9 The programmable element 201 may have a transistor-like structure. The integrated circuit may include a plurality of first conductive lines 105. The first conductive lines 105 may be electrically coupled to one of the corresponding voltage nodes 103.

[0145] For ease of description, only one first conductive line 105 is described. A first bias voltage of a second polarity may be applied to the first conductive line 105. This second polarity may be negative relative to ground potential. For example, the first bias voltage may be between approximately -0.5 volts and -2.5 volts, between approximately -1.0 volts and -2.5 volts, between approximately -1.0 volts and -2.0 volts, or between approximately -1.0 volts and -1.5 volts. Due to this first bias voltage, the programming voltage applied to the first terminal 101 may not need to be as high as the programming voltage described in step S11. Furthermore, the channel resistance of the select transistor 401 may be reduced. Moreover, due to the higher effective programming voltage and the lower impedance path, the programming current may be increased. Therefore, the duration of the first read program and the second read program may be shortened.

[0146] In some embodiments, the presence of the first bias voltage reduces the first operating voltage applied to the protection transistor 301 and the second operating voltage applied to the selection transistor 401. Therefore, the power consumption of the integrated circuit can be reduced.

[0147] Although the programmable element 201 is described as being in Figure 11 The programmable element 201 can be a capacitor-like structure, but is not limited to this. It can also be a transistor-like structure.

[0148] Figure 12 A circuit diagram of an integrated circuit according to another embodiment of the present disclosure is shown. Figure 13 A cross-sectional schematic diagram of one of the selection transistors 401 of the integrated circuit, exemplifying another embodiment of the present disclosure.

[0149] Please refer to Figure 11 The integrated circuit has a similar feature to, for example Figure 2 The design described. Figure 9 Zhongyu Figure 2 Identical or similar components are designated with similar component numbers, and redundant descriptions have been omitted. The integrated circuit may also include a blocking transistor 501 and a control logic unit 601. For example, the protection transistor 301 and the selection transistor 401 may be n-type transistors, but are not limited thereto.

[0150] For example, the blocking transistor 501 may be a p-type transistor, but is not limited thereto. The blocking transistor 501 may be coupled between the first terminal 101 and the programmable element 201 to selectively apply the programming voltage to a programmable element 201, which is selected by the associated selection transistor 401 during programming. Typically, the blocking transistor 501 can provide insulation between the programmable element 201 and a programming voltage located at the first terminal 101 between the programming steps.

[0151] The control logic unit 601 can be provided to generate various selection signals for programming the programmable element 201. For example, a programming voltage can be applied to the first terminal 101, and the blocking transistor 501 can be selected by establishing the selection signal. The corresponding selection transistor 401 can be enabled by establishing the selection signal to select the corresponding programmable element 201 to be programmed.

[0152] In some embodiments, after a programming process, the blocking transistor 501 can be controlled to block the select transistor 401 from the first terminal 101, thereby isolating the select transistor 401 from the programming voltage. This allows the select transistor 401 to exit a snapback mode without cycling the programming voltage, which will be described in detail later. In this method, a programming process for programming multiple programmable elements 201 can be implemented by cycling the blocking transistor 501 instead of cycling the programming voltage, thereby reducing the time required for the programming process.

[0153] In this programming procedure, the blocking transistor 501 and the selecting transistor 401 can be designed so that after the initial breakdown of the programmable element 201, the selecting transistor 401 can enter the breakback mode of the operation, while the blocking transistor 501 can remain in a normal mode of the operation. This can be achieved by adjusting the breakdown voltage of the selecting transistor 401. For example, if the programming voltage associated with the programmable element 201 is approximately +5.0 volts, then the breakdown voltage of the selecting transistor 401 can be between approximately +4.0 volts and approximately +4.5 volts.

[0154] In this break-through mode of operation, compared to a transistor operating in normal mode at the breakdown voltage, the select transistor 401 exhibits increased current conduction at a given applied voltage. Typically, this increased current conduction mode allows the select transistor 401 to conduct sufficient sink current to perfectly program the programmable element 201 without increasing the device size. Therefore, the area of ​​the integrated circuit can be reduced.

[0155] Please refer to Figure 13 The select transistor 401 may include a select gate electrode 403, a second channel region 405, a second isolation layer 407, a plurality of select gate spacers 409, a third impurity region 411, a fourth impurity region 413, a first lightly impurity region 415, a second lightly impurity region 417, a first halo-impurity region 419, and a second halo-impurity region 421.

[0156] Please refer to Figure 13 The second isolation layer 407 may be disposed on the substrate 209. The second isolation layer 407 may contain elements similar to... Figure 10 The material of the first isolation layer 215 is described. A select gate electrode 403 may be disposed on the second isolation layer 407 and electrically coupled to the control logic unit 601. The select gate electrode 403 may contain materials similar to... Figure 10 The described programmable gate electrode 211 is made of a material. The select gate spacer 409 may be disposed on the sidewalls of the select gate electrode 403 and the second isolation layer 407. The second channel region 405 may be part of the substrate 209 and may be disposed opposite the select gate electrode 403, and is interposed between the second channel region 405 and the select gate electrode 403 by the second isolation layer 407.

[0157] The third impurity region 411 and the fourth impurity region 413 may be disposed in the substrate 209, adjacent to both sides of the second isolation layer 407. That is, the third impurity region 411 and the fourth impurity region 413 may be disposed adjacent to both sides of the second channel region 405. The contours of the third impurity region 411 and the fourth impurity region 413 may be adjusted by the selected gate spacer 409. The third impurity region 411 may be electrically coupled to the protection transistor 301, and the fourth impurity region 413 may be electrically coupled to the voltage node 103. The third impurity region 411 and the fourth impurity region 413 may be doped with a dopant, such as phosphorus, arsenic, antimony, or boron.

[0158] The first slightly impurity region 415 and the second slightly impurity region 417 can be respectively disposed under the selected gate spacer 409 and adjacent to the third impurity region 411 and the fourth impurity region 413. The second channel region 405 can be disposed between the first slightly impurity region 415 and the second slightly impurity region 417. The first slightly impurity region 415 and the second slightly impurity region 417 can be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. The third impurity region 411, the fourth impurity region 413, the first slightly impurity region 415, and the second slightly impurity region 417 can have the same electrical type. The doping concentration of the first slightly impurity region 415 and the second slightly impurity region 417 can be less than the doping concentration of the third impurity region 411 and the fourth impurity region 413.

[0159] The first halo impurity region 419 and the second halo impurity region 421 can be respectively disposed adjacent to the first lightly impurity region 415 and the second lightly impurity region 417. The first halo impurity region 419 and the second halo impurity region 421 can be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. The first halo impurity region 419 and the second halo impurity region 421 can have a different electrical type than the first lightly impurity region 415 and the second lightly impurity region 417 to provide a sharp n+ / p- sub-junction. This sharp n+ / p- sub-junction design can reduce the breakdown voltage of the select transistor 401.

[0160] Although the programmable element 20 is as follows Figure 12 The described capacitor-like structure is not limited to this. The programmable element 201 may also be a transistor-like structure.

[0161] One embodiment of this disclosure provides a method for identifying the resistance state of a programmable element of an integrated circuit, comprising: setting a first programmable voltage of a first polarity to program the programmable element of the integrated circuit; setting a first read voltage of the first polarity to the integrated circuit at a first temperature to obtain a first read current, wherein the first read current leads to a first resistance; setting the first read voltage of the first polarity to the integrated circuit at a second temperature at least 50°C higher than the first temperature, wherein the second read current leads to a second resistance; and comparing the first resistance with the second resistance to identify the resistance state of the programmable element.

[0162] Another embodiment of this disclosure provides a method for determining the minimum programming current of a programmable element of an integrated circuit, comprising: setting a first programming voltage to program the programmable element of the integrated circuit and obtaining a first programming current; setting a first read voltage to the integrated circuit at a first temperature to obtain a first read current, wherein the first read current leads to a first resistance; setting the first read voltage to the integrated circuit at a second temperature at least 50°C higher than the first temperature, wherein the second read current leads to a second resistance; comparing the first resistance and the second resistance to determine that a resistance state of the programmable element is an ohmic state; and considering the first programming current as the minimum programming current.

[0163] Another embodiment of this disclosure provides a method for determining the minimum programming current of a programmable element of an integrated circuit, comprising: setting a first programming voltage to program the programmable element of the integrated circuit and obtaining a first programming voltage; setting a first read voltage to the integrated circuit at a first temperature to obtain a first read current, wherein the first read current leads to a first resistance; setting the first read voltage to the integrated circuit at a second temperature to obtain a second read current, the second temperature being at least 50°C higher than the first temperature, wherein the second read current leads to a second resistance; comparing the first resistance and the second resistance to determine whether a resistance state of the programmable element is a jump state or a surface scattering state; adjusting the integrated circuit and setting the first programming voltage to reprogram the programmable element to obtain a post-adjustment programming current; setting a first read voltage to the integrated circuit at the first temperature to obtain a first read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a second read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a second read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a second read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a second read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a second read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a second read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a second read current; setting a first read voltage to the integrated circuit at a second temperature to obtain a first ... A first read voltage is applied to the integrated circuit to obtain a first post-stage adjustment read current, and the first post-stage adjustment read current derives a first post-stage adjustment resistor; at the second temperature, the first read voltage is applied to the integrated circuit to obtain a second post-stage adjustment read current, and the second post-stage adjustment read current derives a second post-stage adjustment resistor; the first post-stage adjustment resistor and the second post-stage adjustment resistor are compared to determine that the resistance state of the programmable element is in an ohmic state; the post-stage adjustment programming current is regarded as the minimum programming current; and if, in the step of comparing the first post-stage adjustment resistor and the second post-stage adjustment resistor, the resistance state of the programmable element is determined to be in a jumping state or a surface scattering state, then the step of adjusting the integrated circuit and setting the first programming voltage is repeated to the step of comparing the first post-stage adjustment resistor and the second post-stage adjustment resistor.

[0164] An identification method according to an embodiment of this disclosure can easily identify the resistance state of the programmable element 201. Therefore, programmable elements 201 that do not meet the specifications (i.e., are in a skip state or surface scattering state) can be easily screened out, and corresponding processing can be performed immediately. This shortens the manufacturing time of the electronic component, which is achieved using the method for identifying the resistance state of the programmable element 201.

[0165] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0166] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for identifying the resistance state of a programmable element in an integrated circuit, comprising: A first programmable voltage of a first polarity is set to program the programmable element of the integrated circuit; A first read voltage of the first polarity is set to the integrated circuit at a first temperature to obtain a first read current, and a first resistance is derived from the first read current; A first read voltage of the first polarity is applied to the integrated circuit at a second temperature to obtain a second read current, the second temperature being at least 50°C higher than the first temperature, and a second resistance is derived from the second read current; and The resistance state of the programmable element is determined by comparing the first resistor with the second resistor.

2. The identification method as described in claim 1, wherein the first temperature is between 0°C and 40°C.

3. The identification method as described in claim 1, wherein the second temperature is between 90°C and 110°C.

4. The identification method of claim 1, wherein the step of setting the first programmable voltage of the first polarity to program the programmable element of the integrated circuit is performed at a temperature between 90°C and 110°C.

5. The identification method as described in claim 1, wherein the first polarity is positive relative to the ground potential.

6. The identification method of claim 1, wherein the programmable element is electrically coupled between a first terminal of the integrated circuit and a voltage node, and the first programmable voltage is applied to the first terminal.

7. The identification method as described in claim 6, wherein the voltage node includes a ground potential.

8. The identification method of claim 7, wherein the integrated circuit includes a protection transistor coupled between the programmable element and the voltage node.

9. The identification method of claim 8, wherein the integrated circuit includes a selection transistor electrically coupled between the protection transistor and the voltage node.

10. The identification method of claim 7, wherein the programmable element includes an upper electrode and a lower electrode, the upper electrode being electrically coupled to the first terminal, the lower electrode being electrically coupled to the voltage node, and separated from the upper electrode by an intermediate insulating layer.

11. The identification method of claim 7, wherein the programmable element includes a programming gate electrode, a first channel region, a first impurity region, and a second impurity region, the programming gate electrode is electrically coupled to the first terminal, the first channel region is separated from the programming gate electrode by a first isolation layer, the first impurity region and the second impurity region are respectively adjacent to both sides of the first channel region, and the first impurity region is electrically coupled to the voltage node.

12. The identification method of claim 11, wherein the second impurity region is electrically floating.

13. The identification method of claim 6, wherein the integrated circuit includes a first conductive line electrically coupled to the voltage node, and a first bias voltage of a second polarity applied to the first conductive line.

14. The identification method of claim 13, wherein the second polarity is negative relative to the ground potential.

15. The identification method of claim 14, wherein the first bias voltage is between -1.0 volts and -2.0 volts.

16. The identification method of claim 6, wherein the programming voltage is between +5.0 volts and +10.0 volts.

17. The identification method of claim 9, wherein the select transistor includes a third impurity region, a fourth impurity region, and a select gate electrode, the third impurity region is electrically coupled to the protection transistor, the fourth impurity region is electrically coupled to the voltage node and separated from the third impurity region by a second channel region, the select gate electrode is located on the second channel region, and a second isolation layer is inserted between the select gate electrode and the second channel region.

18. The identification method of claim 17, wherein the selection transistor includes a first slightly impurity region and a second slightly impurity region, the first slightly impurity region being disposed adjacent to the third impurity region, the second slightly impurity region being disposed adjacent to the fourth impurity region, and the second channel region being located between the first slightly impurity region and the second slightly impurity region.

19. A method for determining the minimum programming current of a programmable element in an integrated circuit, comprising: A first programming voltage is set to program the programmable element of the integrated circuit, and a first programming current is obtained; A first read voltage is applied to the integrated circuit at a first temperature to obtain a first read current, and a first resistance is derived from the first read current; A first read voltage is applied to the integrated circuit at a second temperature to obtain a second read current, the second temperature being at least 50°C higher than the first temperature, and a second resistance is derived from the second read current; Compare the first resistor with the second resistor to determine that a resistance state of the programmable element is an ohmic state; as well as The first programming current is considered as the minimum programming current.

20. A method for determining the minimum programming current of a programmable element in an integrated circuit, comprising: A first programming voltage is set to program the programmable element of the integrated circuit, and a first programming voltage is obtained; A first read voltage is applied to the integrated circuit at a first temperature to obtain a first read current, and a first resistance is derived from the first read current; A first read voltage is applied to the integrated circuit at a second temperature to obtain a second read current, the second temperature being at least 50°C higher than the first temperature, and a second resistance is derived from the second read current; Compare the first resistor with the second resistor to determine whether a resistor state of the programmable element is a jump state or a surface scattering state. Adjust the integrated circuit and set the first programming voltage to reprogram the programmable element to obtain a subsequent adjustment programming current; At the first temperature, the first read voltage is set to the integrated circuit to obtain a first post-stage adjustment read current, and a first post-stage adjustment resistor is derived from the first post-stage adjustment read current; At the second temperature, the first read voltage is set to the integrated circuit to obtain a second post-stage adjustment read current, and a second post-stage adjustment resistor is derived from the second post-stage adjustment read current; The first and second post-stage adjustment resistors are compared to determine that the resistance state of the programmable element is in the ohmic state. The subsequent adjustment programming current is regarded as the minimum programming current. as well as If, during the step of comparing the first and second post-stage adjustment resistors, it is determined that the resistance state of the programmable element is either in a jumping state or a surface scattering state, then the steps of adjusting the integrated circuit and setting the first programming voltage are repeated until the step of comparing the first and second post-stage adjustment resistors is reached.

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