Memory device and method of operating the same

Abstract

The present disclosure relates to a memory device and a method for operating the memory device. A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines. The memory device also includes a peripheral circuit configured to perform a plurality of programming loops to program memory cells connected to a selected word line among the plurality of word lines among the plurality of memory cells. The memory device further includes control logic configured to control the peripheral circuit to: set a step voltage based on the number of turned-off memory cells among the selected memory cells during a programming operation and a verification operation in each programming loop in the plurality of programming loops; and then, apply a programming voltage to the selected word line in a next programming loop, the step voltage being added to the programming voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0185061 filed on December 28, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to electronic devices, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0004] A storage device is a device that stores data under the control of a host device, such as a computer, smartphone, or tablet. Storage devices can include devices that store data on magnetic disks, such as hard disk drives (HDDs); devices that store data in semiconductor memory, such as solid-state drives (SSDs); or memory cards, particularly non-volatile memory.

[0005] A storage device may include a memory device in which data is stored and a memory controller that stores the data in the memory device. Memory devices may be classified as volatile memory or non-volatile memory. Here, non-volatile memory includes read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Summary of the Invention

[0006] Embodiments of the present disclosure relate to a memory device that controls a step voltage based on the number of memory cells turned off during a pre-verification operation or a main verification operation, and to a method of operating the memory device.

[0007] According to one embodiment of the present disclosure, a memory device may include a memory cell array including a plurality of memory cells connected to a plurality of word lines. The memory device may also include a peripheral circuit configured to execute a plurality of programming loops to program memory cells connected to a selected word line among the plurality of word lines among the plurality of memory cells. The memory device may further include control logic configured to control the peripheral circuit to: set a step voltage based on the number of turned-off memory cells among the selected memory cells during a program operation and a verification operation in each of the plurality of programming loops; and then, apply a programming voltage to the selected word line in the next programming loop, the step voltage being added to the programming voltage.

[0008] According to one embodiment of the present disclosure, a memory device may include a memory cell array including a plurality of memory cells connected to a plurality of word lines. The memory device may also include a peripheral circuit configured to execute a plurality of programming loops to program memory cells connected to a selected word line among the plurality of memory cells. The memory device may further include control logic including: a memory cell counter for counting the number of turned-off memory cells among the selected memory cells; and a step voltage controller for controlling the peripheral circuit to set a step voltage based on the number of turned-off memory cells during a verification operation in a program operation and a verification operation included in each of the plurality of programming loops, and then apply a programming voltage to the selected word line in the next programming loop, the step voltage being added to the programming voltage.

[0009] According to one embodiment of the present disclosure, a method for operating a memory device including a plurality of memory cells connected to each of a plurality of word lines may include: performing a programming operation by applying a program voltage to a selected word line among the plurality of word lines; and performing a verification operation by applying a verification voltage to the selected word line. The method may also include: counting the number of memory cells that are turned off among the selected memory cells connected to the selected word line during the verification operation; and setting a step voltage based on the counted number of memory cells that are turned off. The method may further include: applying a programming voltage to the selected word line, the step voltage being added to the programming voltage.

[0010] According to one embodiment of the present disclosure, a program operation speed may be increased by differently setting a step voltage based on the number of memory cells turned off during a pre-verification operation or a main verification operation included in a program loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram illustrating a storage device.

[0012] Figure 2 It is an icon Figure 1 A diagram of the structure of a memory device.

[0013] Figure 3 It is an icon Figure 2 FIG. 1 is a diagram of one embodiment of a memory cell array.

[0014] Figure 4 is a diagram illustrating dual verification programming.

[0015] Figure 5 The diagram illustrates a program loop performed when programming selected memory cells.

[0016] Figure 6 The diagram shows that every Figure 5 The threshold voltage distribution shifts as the programming cycle proceeds.

[0017] Figure 7 The diagram illustrates a configuration of control logic for generating a program voltage on which a step voltage set based on count information is reflected.

[0018] Figure 8 The diagram shows a programming loop and a step voltage determined when the reference value is 1.

[0019] Figure 9 An embodiment of a program loop and a step voltage determined when the number of reference values is plural is illustrated.

[0020] Figure 10 Another embodiment of a program loop and a step voltage determined when the number of reference values is plural is illustrated.

[0021] Figure 11 The diagram shows that every Figures 8 to 10 The threshold voltage distribution shifts as the programming cycle proceeds.

[0022] Figure 12 is a diagram illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0023] Figure 13 is a diagram illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0024] Figure 14 It is an icon Figure 1 FIG. 1 is a diagram of another embodiment of a memory controller.

[0025] Figure 15 is a block diagram illustrating a memory card system to which a storage device according to one embodiment of the present disclosure is applied.

[0026] Figure 16 is a block diagram illustrating a solid-state drive (SSD) system to which a storage device according to one embodiment of the present disclosure is applied.

[0027] Figure 17 is a block diagram illustrating a user system to which a storage device according to one embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0028] The specific structural or functional descriptions of the embodiments of the concepts disclosed in this specification or application are illustrated and are only used to describe the embodiments of the concepts of the present disclosure. The embodiments of the concepts of the present disclosure can be implemented in various forms and are not limited to the embodiments described in this specification or application.

[0029] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can implement the technical spirit of the present disclosure.

[0030] Figure 1 is a block diagram illustrating a storage device.

[0031] refer to Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 .

[0032] The storage device 50 may be a device that stores data under the control of the host 300 , such as a cellular phone, smart phone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0033] The storage device 50 may be manufactured as one of various types of storage devices according to a host interface as a communication method with the host 300. For example, the storage device 50 may be configured as any of various types of storage devices, such as an SSD; a multimedia card in the form of an MMC, an eMMC, an RS-MMC, and a micro MMC; a secure digital card in the form of an SD, a mini SD, and a micro SD; a universal serial bus (USB) storage device; a universal flash storage (UFS) device; a personal computer memory card international association (PCMCIA) card type storage device; a peripheral component interconnect (PCI) card type storage device; a PCI Express (PCI-E) card type storage device; a compact flash (CF) card; a smart media card; and a memory stick.

[0034] The memory device 50 may be manufactured in any of a variety of package types. For example, the memory device 50 may be manufactured in any of a variety of package types, such as package-on-package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-scale fabrication package (WFP), and wafer-scale stacked package (WSP).

[0035] The memory device 100 can store data. The memory device 100 operates in response to the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells storing data. The memory cell array may include a plurality of memory blocks. Each of the memory blocks may include a plurality of memory cells, and the plurality of memory cells may be configured as a plurality of pages. In one embodiment, a page may be a unit for storing data in the memory device 100 or for reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0036] In one embodiment, the memory device 100 may include double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, perpendicular NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. In this specification, for the convenience of description, it is assumed that the memory device 100 includes a NAND flash memory.

[0037] The memory device 100 can be implemented as a two-dimensional array structure or a three-dimensional array structure. Hereinafter, a three-dimensional array structure is described as an embodiment, but the present disclosure is not limited to the three-dimensional array structure. The present disclosure can be applied not only to flash memory devices in which the charge storage layer is configured by a conductive floating gate (FG), but also to charge trap flash memories (CTFs) in which the charge storage layer is configured by an insulating film.

[0038] In one embodiment, the memory device 100 may operate in a single-level cell (SLC) method, in which one data bit is stored in one memory cell. Alternatively, the memory device 100 may operate in a method of storing at least two data bits in one memory cell. For example, the memory device 100 may operate in a multi-level cell (MLC) method of storing two data bits in one memory cell, a triple-level cell (TLC) method of storing three data bits in one memory cell, or a quad-level cell (QLC) method of storing four data bits in one memory cell.

[0039] The memory device 100 is configured to receive commands and addresses from the memory controller 200 and access the area selected by the address in the memory cell array. That is, the memory device 100 can perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 can perform a write operation (program operation), a read operation, or an erase operation according to the received command. For example, when a program command is received, the memory device 100 can program data to the area selected by the address. When a read command is received, the memory device 100 can read data from the area selected by the address. When an erase command is received, the memory device 100 can erase the data stored in the area selected by the address.

[0040] In one embodiment, the memory device 100 may include a memory cell counter 150. The memory cell counter 150 may count the number of memory cells that pass or fail during a verification operation among operations included in a programming loop. Here, a programming loop may be a loop performed when programming selected memory cells connected to a selected word line, and may include a programming operation in which a program pulse is applied to the selected word line, and a verification operation in which a verification pulse is applied.

[0041] In one embodiment, the step voltage may be determined based on the number of passed or failed memory cells counted by the memory cell counter 150 .

[0042] In one embodiment, the memory device 100 may include a step voltage controller 170. The step voltage controller 170 may determine the step voltage based on the number of passed memory cells or the number of failed memory cells counted by the memory cell counter 150.

[0043] Specifically, during a programming operation on selected memory cells of the memory device 100, when the number of passed memory cells counted by the memory cell counter 150 is greater than a preset reference value (or when the number of failed memory cells is less than a preset reference value), the step voltage controller 170 can generate a voltage signal so that a pulse with a step voltage higher than the previous programming pulse is applied to the selected word line.

[0044] However, during a programming operation on selected memory cells of the memory device 100, when the number of passed memory cells counted by the memory cell counter 150 is less than or equal to a preset reference value (or when the number of failed memory cells is greater than or equal to the preset reference value), the step voltage controller 170 may generate a voltage signal such that a pulse that is additionally higher than the previous programming pulse by a step voltage at an offset voltage is applied to the selected word line.

[0045] At this time, the offset voltage can be set according to the number of times the program and erase operations are performed on the selected memory cell. For example, as the number of times the program and erase operations are performed on the selected memory cell increases, the offset voltage can be set to a lower level, and as the number of times the program and erase operations are performed on the selected memory cell decreases, the offset voltage can be set to a higher level.

[0046] Since the size of the step voltage is set differently according to the number of passed memory cells or the number of failed memory cells counted by the memory cell counter 150, the programming time can be shortened. That is, by applying a higher level of programming pulse to a memory cell having a low programming speed, the time consumed for programming can be shortened.

[0047] The memory controller 200 may control overall operations of the memory device 50 .

[0048] When power voltage is applied to the memory device 50, the memory controller 200 may execute firmware. When the memory device 100 is a flash memory device 100, the memory controller 200 may operate firmware such as a flash translation layer (FTL) for controlling communication between the host 300 and the memory device 100.

[0049] In one embodiment, the memory controller 200 may include firmware (not shown) that receives data and a logical block address (LBA) from the host 300 and converts the LBA into a physical block address (PBA), the PBA indicating an address of a memory cell in which data included in the memory device 100 is to be stored. In addition, the memory controller 200 may store a logical-physical address mapping table configuring a mapping relationship between the LBA and the PBA in a buffer memory.

[0050] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc., according to a request from the host 300. For example, when a program request is received from the host 300, the memory controller 200 may convert the program request into a program command and may provide the program command, the PBA, and data to the memory device 100. When a read request together with an LBA is received from the host 300, the memory controller 200 may change the read request into a read command, select a PBA corresponding to the LBA, and then provide the read command and the PBA to the memory device 100. When an erase request together with an LBA is received from the host 300, the memory controller 200 may change the erase request into an erase command, select a PBA corresponding to the LBA, and then provide the erase command and the PBA to the memory device 100.

[0051] In one embodiment, the memory controller 200 may generate a program command, address, and data without a request from the host 300, and transmit the program command, address, and data to the memory device 100. For example, the memory controller 200 may provide the command, address, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0052] In one embodiment, the storage device 50 may further include a buffer memory (not shown). The memory controller 200 may control data exchange between the host 300 and the buffer memory (not shown). Alternatively, the memory controller 200 may temporarily store system data used to control the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data input from the host 300 in the buffer memory, and then transmit the data temporarily stored in the buffer memory to the memory device 100.

[0053] In various embodiments, the buffer memory may be used as an operating memory and a cache memory for the memory controller 200. The buffer memory may store codes or commands executed by the memory controller 200. Alternatively, the buffer memory may store data processed by the memory controller 200.

[0054] In one embodiment, the buffer memory may be implemented as dynamic random access memory (DRAM) or static random access memory (SRAM), such as double data rate synchronous dynamic random access memory (DDR SDRAM), DDR4 SDRAM, low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), or Rambus dynamic random access memory (DRAM).

[0055] In various embodiments, a buffer memory may be connected from the outside of the storage device 50. In this case, a volatile memory device connected to the outside of the storage device 50 may be used as the buffer memory.

[0056] In one embodiment, the memory controller 200 may control at least two or more memory devices. In this case, the memory controller 200 may control the memory devices according to an interleaving method to improve operation performance.

[0057] The host 300 may communicate with the storage device 50 using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0058] Figure 2 It is an icon Figure 1 A diagram of the structure of a memory device.

[0059] refer to Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0060] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz can be connected to a page buffer group 123 via bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As one embodiment, the plurality of memory cells are nonvolatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block can include multiple pages.

[0061] The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0062] Each of the memory cells included in the memory cell array 110 may be configured as an SLC storing one data bit, an MLC storing two data bits, a TLC storing three data bits, or a QLC storing four data bits.

[0063] The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn, or discharge the applied voltages, under the control of the control logic 130.

[0064] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0065] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In one embodiment, the word lines may include normal word lines and dummy word lines. In one embodiment, the row lines RL may further include a pipe select line.

[0066] The row decoder 121 is configured to decode the row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block from among the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 can select at least one word line of the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0067] For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line and a program pass voltage having a level lower than the program voltage to unselected word lines. During a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage having a level higher than the verification voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line and a read pass voltage having a level higher than the read voltage to unselected word lines.

[0068] In one embodiment, the erase operation of the memory device 100 is performed in units of memory blocks. During the erase operation, the row decoder 121 may select a memory block according to the decoded address. During the erase operation, the row decoder 121 may apply a ground voltage to the word line connected to the selected memory block.

[0069] The voltage generator 122 operates in response to the control of the control logic 130. The voltage generator 122 is configured to generate a plurality of voltages using an external power voltage supplied to the memory device 100. Specifically, in response to the operation signal OPSIG, the voltage generator 122 can generate various operation voltages Vop for program, read, and erase operations. For example, in response to the control of the control logic 130, the voltage generator 122 can generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc.

[0070] As an embodiment, the voltage generator 122 may generate an internal power voltage by regulating an external power voltage. The internal power voltage generated by the voltage generator 122 is used as an operating voltage of the memory device 100.

[0071] As an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power voltage or an internal power voltage.

[0072] For example, the voltage generator 122 may include a plurality of pumping capacitors that receive the internal power voltage, and may selectively activate the plurality of pumping capacitors to generate a plurality of voltages in response to the control of the control logic 130 .

[0073] The generated plurality of voltages may be supplied to the memory cell array 110 through the row decoder 121 .

[0074] The page buffer group 123 includes first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn are connected to the memory cell array 110 through first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn operate in response to the control of the control logic 130. Specifically, the first to nth page buffers PB1 to PBn can operate in response to a page buffer control signal PBSIGNALS. For example, the first to nth page buffers PB1 to PBn can temporarily store data received through the first to nth bit lines BL1 to BLn, or can sense the voltage or current of the bit lines BL1 to BLn during a read or verify operation.

[0075] Specifically, during a program operation, when a program voltage is applied to a selected word line, the first to nth page buffers PB1 to PBn can transmit data DATA received through the input / output circuit 125 to selected memory cells through the first to nth bit lines BL1 to BLn. The memory cells of the selected page are programmed according to the transmitted data DATA. During a program verification operation, the first to nth page buffers PB1 to PBn can read page data by sensing a voltage or current received from the selected memory cells through the first to nth bit lines BL1 to BLn.

[0076] During a read operation, the first to nth page buffers PB1 to PBn read data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124 .

[0077] During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn or apply an erase voltage.

[0078] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL.

[0079] The input / output circuit 125 can be connected from the reference Figure 1 Description Figure 1 The memory controller 200 transmits the received command CMD and address ADDR to the control logic 130 , or may exchange data DATA with the column decoder 124 .

[0080] The sensing circuit 126 may generate a reference current in response to the enable bit signal VRYBIT during a read operation or a verification operation and compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0081] The control logic 130 can output an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT in response to a command CMD and an address ADDR to control the peripheral circuit 120. For example, the control logic 130 can control a read operation on a selected memory block in response to a sub-block read command and address. In addition, the control logic 130 can control an erase operation on a selected sub-block included in a selected memory block in response to a sub-block erase command and address. In addition, the control logic 130 can determine whether a verification operation passes or fails in response to a pass signal PASS or a fail signal FAIL.

[0082] The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code. In one embodiment, the control logic 130 may include a memory cell counter 150 and a step voltage controller 170. In another embodiment, the memory cell counter 150 and the step voltage controller 170 may be included outside the control logic 130.

[0083] In one embodiment, the memory cell counter 150 may count the number of on-memory cells or off-memory cells based on the pass signal PASS or the fail signal FAIL received from the sensing circuit 126 .

[0084] For example, when the memory device 100 performs a plurality of program loops, when the threshold voltage of the selected memory cell is greater than the verification voltage, the selected memory cell may be turned off, and when the threshold voltage of the selected memory cell is less than the verification voltage, the selected memory cell may be turned on. In one embodiment, the memory cell counter 150 may count the number of turned-off memory cells or the number of turned-on memory cells.

[0085] Here, when the memory device 100 programs the memory cells through dual verification programming (DPGM), the verification voltage used for the verification operation may be a pre-verification voltage or a main verification voltage. The main verification voltage may be a verification voltage corresponding to a target program state, and the pre-verification voltage may have a level lower than that of the main verification voltage and may be a voltage used to verify the extent to which the programming operation is performed.

[0086] In one embodiment, the step voltage controller 170 may determine the step voltage based on the number of memory cells counted by the memory cell counter 150 .

[0087] For example, when the number of off memory cells counted by the memory cell counter 150 is less than a preset reference value (or when the number of on memory cells counted by the memory cell counter 150 is greater than a preset reference value), in a program loop performed after a verification operation, the step voltage controller 170 may set the size of the program pulse to a size obtained by adding an offset voltage to the step voltage. At this time, the size of the offset voltage may be determined by the number of times the program operation and the erase operation are performed on the selected memory cell. For example, as the number of times the program operation and the erase operation are performed increases, the offset voltage may be set to be smaller, and as the number of times the program operation and the erase operation are performed decreases, the offset voltage may be set to be larger.

[0088] However, when the number of turned-off memory cells counted by the memory cell counter 150 is greater than or equal to the preset reference value (or when the number of turned-on memory cells counted by the memory cell counter 150 is less than or equal to the preset reference value), in the programming loop performed after the verification operation, the step voltage controller 170 can set the size of the programming pulse mainly by the step voltage.

[0089] Thereafter, also in the program loop, the memory cell counter 150 may count the number of turned-off memory cells or the number of turned-on memory cells, and the step voltage controller 170 may determine the size of the step voltage based on the counted number of memory cells.

[0090] As a result, the step voltage controller 170 can set the step voltage size differently as the program loop progresses. Therefore, the duration of programming performed on the selected memory cells can be shortened, and programming performance can be improved.

[0091] Figure 3 It is an icon Figure 2 FIG. 1 is a diagram of one embodiment of a memory cell array.

[0092] refer to Figure 2 and Figure 3 , Figure 3 It shows Figure 2 1 and 2. A circuit diagram of any one memory block BLKa among a plurality of memory blocks BLK1 to BLKz included in the memory cell array 110.

[0093] A first selection line, a word line, and a second selection line arranged in parallel with each other may be connected to the memory block BLKa. For example, the word lines may be arranged in parallel with each other between the first selection line and the second selection line. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL.

[0094] More specifically, the memory block BLKa may include a plurality of strings connected between bit lines BL1 to BLn and source lines SL. The bit lines BL1 to BLn may be connected to the strings separately, and the source line SL may be connected to the strings in common. Since the strings may be configured to be identical to each other, as an example, the string ST connected to the first bit line BL1 will be described in detail.

[0095] The string ST may include a source select transistor SST, a plurality of memory cells F1 to F16, and a drain select transistor DST connected in series between a source line SL and a first bit line BL1. One string ST may include at least one or more of the source select transistor SST and the drain select transistor DST, and may include more memory cells F1 to F16 than shown in the figure.

[0096] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. The memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings can be connected to the source select line SSL, the gates of the drain select transistors DST can be connected to the drain select line DSL, and the gates of the memory cells F1 to F16 can be connected to a plurality of word lines WL1 to WL16. Among the memory cells included in different strings, a group of memory cells connected to the same word line can be referred to as a physical page PPG. Therefore, the memory block BLKa can include the number of physical pages PPG of the word lines WL1 to WL16.

[0097] One memory cell can store one bit of data. This is commonly referred to as SLC. In this case, one physical page PPG can store one logical page (LPG) of data. One logical page (LPG) of data can include the same number of data bits as the number of memory cells included in one physical page PPG. Furthermore, one memory cell can store two or more bits of data. This is commonly referred to as MLC. In this case, one physical page PPG can store two or more logical pages (LPG) of data.

[0098] A memory cell in which two or more bits of data are stored in one memory cell is called an MLC. However, recently, as the number of bits of data stored in one memory cell increases, an MLC refers to a memory cell in which two bits of data are stored, a memory cell in which three or more bits of data are stored is called a triple-level cell (TLC), and a memory cell in which four or more bits of data are stored is called a quad-level cell (QLC). In addition, a memory cell method in which multi-bit data is stored has been developed, and the present embodiment can be applied to the memory device 100 in which two or more bits of data are stored.

[0099] In another embodiment, the memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such a plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction.

[0100] Figure 4 is a diagram illustrating dual verification programming.

[0101] refer to Figure 4 , Figure 4 The process of programming a memory cell from an erased state E to a programmed state P by double verify programming (DPGM) is shown. Figure 4 , the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells.

[0102] exist Figure 4 In, assuming Figure 1 The memory device 100 performs a programming operation by an SLC method. In another embodiment, Figure 4 Can be applied to Figure 1 The memory device 100 performs a program operation by the MLC method, the TLC method, or the QLC method.

[0103] refer to Figure 4 , the memory cells in the erase state E can be programmed to the program state P through DPGM. At this time, the memory cells in the erase state E can be programmed to the program state P through the P′ state.

[0104] In one embodiment, the DPGM may include a program pulse application operation and a verification operation. Here, the verification operation may be performed using two verification voltage levels. In this case, the two verification voltages may be a pre-verification voltage Vvfyp and a main verification voltage Vvfym. The main verification voltage Vvfym may be a verification voltage corresponding to the target program state P, and the pre-verification voltage Vvfyp may be a level lower than the level of the main verification voltage Vvfym and may be a voltage used to verify the extent to which the program operation is performed.

[0105] Therefore, the verification operation may include a verification operation performed using the pre-verification voltage Vvfyp and a verification operation performed using the main verification voltage Vvfym.

[0106] In one embodiment, after a program pulse is applied to the memory cells in the erase state E, a verification operation may be performed using a pre-verification voltage Vvfyp and a main verification voltage Vvfym. As a result of the verification operation, the memory cells may be divided into: first program-enabled memory cells PGM CELLS having a threshold voltage lower than the pre-verification voltage Vvfyp; second program-enabled memory cells DPGM CELLS having a threshold voltage higher than the pre-verification voltage Vvfyp and lower than the main verification voltage Vvfym; and program-inhibited memory cells INHIBIT CELLS having a threshold voltage higher than the main verification voltage Vvfym.

[0107] Because the program-inhibited memory cells INHIBIT CELLS having a threshold voltage higher than the main verification voltage Vvfym are already in the target program state P, a program pulse may no longer be applied to the gates of the program-inhibited memory cells INHIBIT CELLS.

[0108] However, since the first and second program-enabled memory cells PGM CELLS and DPGMCELLS have not reached the target program state P, a program pulse may be applied to the corresponding memory cells again.

[0109] At this time, voltage levels of bit lines connected to each of the first program enabled memory cells PGM CELLS and voltage levels of bit lines connected to each of the second program enabled memory cells DPGM CELLS may be set differently.

[0110] That is, the first program-enabled memory cells PGM CELLS having a threshold voltage lower than the pre-verification voltage Vvfyp are slow cells on which a programming operation is performed at a relatively slow speed, and the second program-enabled memory cells DPGM CELLS having a threshold voltage higher than the pre-verification voltage Vvfyp and lower than the main verification voltage Vvfym are fast cells on which an operation is performed at a relatively fast speed, and a programming operation can be performed by setting different voltage levels of bit lines respectively connected to the first program-enabled memory cells PGM CELLS and the second program-enabled memory cells DPGM CELLS.

[0111] For example, the voltage level of a bit line connected to each of the first program-enabled memory cells PGM CELLS may be set to the ground voltage GND, and the voltage level of a bit line connected to each of the second program-enabled memory cells PGMCELLS may be set to a specific level different from the ground voltage GND. That is, since the second program-enabled memory cells DPGM CELLS have a relatively higher programming speed than the first program-enabled memory cells PGM CELLS, the voltage of the bit line may be set to a specific level different from the ground voltage GND in consideration of the programming speed.

[0112] As a result, since the voltage levels of the bit lines connected to each of the first program-enabled memory cells PGM CELLS and the voltages of the bit lines connected to each of the second program-enabled memory cells DPGM CELLS are set differently, the threshold voltage distribution of the memory cells can be formed to be narrow.

[0113] Figure 5 The diagram illustrates a program loop performed when programming selected memory cells.

[0114] refer to Figure 4 and Figure 5 , Figure 5 Is the diagram when through Figure 4 A diagram of some of a plurality of programming loops performed on selected memory cells when programming the memory cells is shown in FIG.

[0115] exist Figure 5 In the embodiment, DPGM is performed from the first program loop PL1, but in one embodiment, DPGM may be started in a specific loop.

[0116] When DPGM is performed from the third program loop PL3, the first and second program loops PL1 and PL2 may be performed in a normal program method. That is, the first and second program loops PL1 and PL2 may include a program operation applying one program pulse and a verification operation applying one verification pulse.

[0117] In one embodiment, a selected memory cell among a plurality of memory cells included in a memory block may be programmed. To program the selected memory cell, at least one programming loop may be performed on the selected memory cell. The programming loop may include a programming operation of applying a programming voltage to a word line to which the selected memory cell is connected, and may include a verification operation of determining whether programming of the selected memory cell is complete.

[0118] In one embodiment, the first program loop PL1 may include a program operation of applying a first program voltage Vpgml to a word line, and may include a verification operation of applying a pre-verification voltage Vvfyp and a main verification voltage Vvfym to the word line. Here, the main verification voltage Vvfym may be a verification voltage corresponding to a target program state, and the pre-verification voltage Vvfyp may be a level lower than that of the main verification voltage Vvfym and may be a voltage for verifying the extent to which the program operation is performed.

[0119] Therefore, in order to program the selected memory cell, a first programming voltage Vpgm1 may be applied to the word line to which the selected memory cell is connected. After the first programming voltage Vpgm1 is applied to the word line to which the selected memory cell is connected, a pre-verification voltage Vvfyp and a main verification voltage Vvfym may be applied to the word line to check whether the selected memory cell is programmed.

[0120] In one embodiment, when the first program loop PL1 is executed but the selected memory cells are not programmed, a second program loop PL2 may be executed on the selected memory cells. The second program loop PL2 may include a program operation of applying a voltage Vpgm1+Vstep1 to a word line, where the voltage Vpgm1+Vstep1 is higher than the first program voltage Vpgm1 by a first step voltage Vstep1, and a verification operation of applying a pre-verification voltage Vvfyp and a main verification voltage Vvfym to the word line. When programming the selected memory cells using an incremental step pulse programming (ISPP) method, the first step voltage Vstep1 may be a preset default step voltage.

[0121] Thereafter, a plurality of program loops may be performed on the memory cells until the selected memory cells are programmed. In addition, as the program loops proceed, the voltage applied to the word line to which the selected memory cells are connected may sequentially increase in step voltages.

[0122] That is, in the third program loop PL3 performed after the second program loop PL2, a voltage Vpgm1+Vstep1+Vstep1 greater than the voltage applied in the second program loop PL2 by the first step voltage may be applied to the word line to which the memory cell is connected.

[0123] However, as the program loop proceeds, because the program voltage increases by the same size of the step voltage, ie, the first step voltage Vstep1, the time consumed to program the selected memory cell may increase.

[0124] Therefore, in the present disclosure, a method is provided for reducing the time consumed in programming selected memory cells by setting the size of a step voltage as a programming loop proceeds.

[0125] Figure 6 The diagram shows that every Figure 5 The threshold voltage distribution shifts as the programming cycle proceeds.

[0126] refer to Figure 5 and Figure 6 , Figure 6 Shown in Figure 5 When the programming loop is executed sequentially in , the threshold voltage distribution of the memory cells shifts. Figure 6 In FIG, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells. Figure 6 In, assuming Figure 1 The memory device 100 performs a program operation in an SLC method.

[0127] In one embodiment, a plurality of program loops may be performed when a program operation is performed on selected memory cells of the erase state E. At this time, the memory cells of the erase state E may be programmed to a target program state P through various states.

[0128] In one embodiment, when the first program loop PL1 is performed on selected memory cells, the threshold voltage distribution of memory cells in the erase state E may be programmed to a PX1 distribution.

[0129] However, since programming of the erased memory cells is not completed by the first program loop PL1, the second program loop PL2 may be performed after the first program loop PL1. When the second program loop PL2 is performed on the selected memory cells, the threshold voltage distribution of the memory cells may be changed from the PX1 distribution to the PX2 distribution.

[0130] Thereafter, in the nth program loop PLn, the threshold voltage distribution of the selected memory cells may be changed from the PXn-1 distribution to the P distribution. Thus, the selected memory cells may be programmed through the first to nth program loops PL1 to PLn.

[0131] However, when programming the selected memory cells through the above process, the speed at which the threshold voltage distribution of the selected memory cells shifts may be low, and thus the time consumed for programming may increase. That is, as the programming loop proceeds, since the programming voltage increases in step voltage magnitude, the width of the shift of the threshold voltage distribution of the selected memory cells may be relatively small, and thus the time consumed for programming may be relatively long.

[0132] Therefore, as the programming cycle progresses, a method of increasing the programming voltage becomes problematic.

[0133] Figure 7 The diagram illustrates a configuration of control logic for generating a program voltage on which a step voltage set based on count information is reflected.

[0134] refer to Figure 2 and Figure 7 , Figure 2 The control logic 130 may include a memory cell counter 150 and a step voltage controller 170 .

[0135] In one embodiment, the memory cell counter 150 may be based on Figure 2 The sensing circuit 126 receives the pass signal PASS or the fail signal FAIL to count the number of turned-on memory cells or turned-off memory cells.

[0136] Specifically, when Figure 2 When the memory device 100 performs multiple programming loops, when the threshold voltage of the selected memory cell is greater than the verification voltage, the memory cell can be programmed from the memory device 100. Figure 2 The sensing circuit 126 outputs a pass signal PASS. When the threshold voltage of the selected memory cell is less than the verification voltage, the selected memory cell can be detected from the sensing circuit 126. Figure 2 The sensing circuit 126 outputs a fail signal FAIL.

[0137] The memory cell counter 150 can be used to Figure 2 The memory cell counter 150 counts the pass signal PASS outputted by the sensing circuit 126 and outputs count information COUNT_INF. That is, the memory cell counter 150 may output count information COUNT_INF including information on the number of turned-off memory cells during the verification operation.

[0138] In another embodiment, the memory cell counter 150 may be configured to Figure 2 The memory cell counter 150 counts the fail signal FAIL outputted from the sensing circuit 126 and outputs count information COUNT_INF. That is, the memory cell counter 150 may output count information COUNT_INF including information on the number of turned-on memory cells during the verification operation.

[0139] In this figure, it is assumed that the memory cell counter 150 counts the number of turned-off memory cells.

[0140] In one embodiment, the step voltage controller 170 may output the operation signal OPSIG based on the count information COUNT_INF received from the memory cell counter 150. At this time, the operation signal OPSIG may be a signal instructing generation of a program voltage applied to a selected word line to which the selected memory cell is connected.

[0141] Specifically, the step voltage controller 170 may determine the size of the step voltage applied to the selected word line in the next program loop based on the count information COUNT_INF and output the operation signal OPSIG indicating generation of a program voltage reflecting the determined step voltage size.

[0142] For example, when the number of memory cells turned off included in the count information COUNT_INF is less than a preset reference value, the step voltage controller 170 may determine a voltage that is greater than the existing step voltage by an offset voltage as the step voltage. That is, the step voltage controller 170 may additionally increase the program voltage applied to the selected word line in the next programming loop.

[0143] Therefore, the step voltage controller 170 may output the operation signal OPSIG indicating generation of a program voltage of a size obtained by adding the step voltage and the offset voltage to the program voltage applied to the selected word line in the previous program loop.

[0144] However, when the number of turned-off memory cells included in the counting information COUNT_INF is greater than or equal to the preset reference value, the step voltage controller 170 may set the existing step voltage to the step voltage.

[0145] Therefore, the step voltage controller 170 may output the operation signal OPSIG indicating generation of a voltage of a magnitude obtained by adding the step voltage to the program voltage applied to the selected word line in the previous program loop.

[0146] Figure 8 The diagram shows a programming loop and a step voltage determined when the reference value is 1.

[0147] refer to Figure 7 and Figure 8 , Figure 8 Shown based on Figure 7 The step voltage is determined as a result of comparing the number of off-memory cells OFFCELL_NUM included in the count information COUNT_INF with the first reference value REF_VAL1, and a program loop performed using the determined step voltage is shown. The first reference value REF_VAL1 may be set in advance.

[0148] In one embodiment, Figure 2 The memory device 100 may perform multiple program loops to program selected memory cells.

[0149] exist Figure 8 middle, Figure 2 The memory device 100 can program selected memory cells through a normal program operation or DPGM. The normal program operation may be an operation in which a verification operation is performed using one verification voltage during a verification operation, and the DPGM operation may be an operation in which a pre-verification operation and a main verification operation are performed, i.e., a verification operation using two verification voltages. The DPGM operation may be performed from the first program loop PL1 or from a specific program loop.

[0150] Here, the pre-verification operation may be a verification operation performed by applying a pre-verification voltage Vvfyp to a selected word line, and the main verification operation may be a verification operation performed by applying a main verification voltage Vvfym to a selected word line. The main verification voltage Vvfym may be a verification voltage corresponding to a target program state, and the pre-verification voltage Vvfyp may be a level lower than that of the main verification voltage Vvfym and may be a voltage for verifying the extent to which the programming operation is performed.

[0151] first, Figure 2 The memory device 100 may perform a first program loop PL1. The first program loop PL1 may include a program operation and a verification operation. Figure 2 The memory device 100 may perform a program operation by applying a first program voltage Vpgm1 to a selected word line, and then perform a verification operation by applying a pre-verification voltage Vvfyp and a main verification voltage Vvfym.

[0152] exist Figure 8 In the first program loop PL1, the verification operation included in the first program loop PL1 is performed using the pre-verification voltage Vvfyp and the main verification voltage Vvfym. However, when the selected memory cells are programmed by the normal program operation, the verification operation may also be performed using only the main verification voltage Vvfym.

[0153] In one embodiment, when the verification operation included in the first program loop PL1 includes a pre-verification operation and a main verification operation, Figure 7 The memory cell counter 150 may be based on the memory cell counter 150 from the memory cell counter 150 during the pre-verification operation. Figure 2 The sense circuit 126 receives the fail signal FAIL or during the master verification operation from Figure 2 The sensing circuit 126 receives the fail signal FAIL to count the number of turned-off memory cells.

[0154] In one embodiment, when the number of turned-off memory cells is less than the first reference value REF_VAL1, the magnitude of the program voltage applied to the selected word line in the second programming loop PL2 can be set to a magnitude of Vpgm1+Vstep1+Voffset1, which is obtained by adding the first step voltage Vstep1 and the first offset voltage Voffset1 to the first programming voltage Vpgm1. Here, as the number of program operations and erase operations performed on the selected memory cells increases, the magnitude of the first offset voltage Voffset1 can decrease. When programming the selected memory cells using the ISPP method, the first step voltage Vstep1 can be a preset default step voltage.

[0155] That is, based on Figure 7 The memory cell counter 150 receives the counting information COUNT_INF, Figure 7 The step voltage controller 170 may set the size of the step voltage to a size obtained by adding the first step voltage Vstep1 and the first offset voltage Voffset1 .

[0156] However, when the number of turned-off memory cells is greater than or equal to the first reference value REF_VAL1, the magnitude of the program voltage applied to the selected word line in the second program loop PL2 may be set to a magnitude Vpgml+Vstep1 obtained by adding the first step voltage Vstep1 to the first program voltage Vpgm1. Figure 7 The memory cell counter 150 receives the counting information COUNT_INF, Figure 7 The step voltage controller 170 may set the magnitude of the step voltage to a first step voltage Vstep1 .

[0157] In one embodiment, when the verification operations included in the first program loop PL1 include only the main verification operation, Figure 7 The memory cell counter 150 can be based on the memory cell counter 150 from the master during the verification operation Figure 2 The sensing circuit 126 receives the fail signal FAIL to count the number of the turned-off memory cells. In addition, when the number of the turned-off memory cells is less than the first reference value REF_VAL1, Figure 7 The step voltage controller 170 may set the size of the step voltage to a size obtained by adding the first step voltage Vstep1 and the first offset voltage Voffset1, and when the number of turned-off memory cells is greater than or equal to the first reference value REF_VAL1, Figure 7 The step voltage controller 170 may set the magnitude of the step voltage to a first step voltage Vstep1 .

[0158] exist Figure 8 In, when Figure 2 When the memory device 100 performs the first program loop PL1, it is assumed that the number of turned-off memory cells is less than the first reference value REF_VAL1. Figure 2 When the memory device 100 performs the second programming loop PL2, the size of the step voltage can be set to a size obtained by adding the first step voltage Vstep1 and the first offset voltage Voffset1, and a programming voltage Vpgm1+Vstep1+Voffset1 of a size obtained by adding the first programming voltage Vpgm1, the first step voltage Vstep1, and the first offset voltage Voffset1 can be applied to the selected word line.

[0159] Thereafter, in a programming loop, when the number of memory cells turned off is less than the first reference value REF_VAL1, the size of the step voltage may be set to a size obtained by adding the first step voltage Vstep1 and the first offset voltage Voffset1. That is, as the programming loop proceeds, the size of the programming voltage may increase by a size obtained by adding the first step voltage Vstep1 and the first offset voltage Voffset1.

[0160] In one embodiment, in the a-1th programming loop PLa-1 executed before the a-1th programming loop PLa, the number of memory cells turned off during the pre-verification operation or the main verification operation may be greater than or equal to the first reference value REF_VAL1. In this case, in the a-1th programming loop PLa as the next programming loop, the size of the step voltage may be set to the first step voltage Vstep1. Therefore, the size of the program voltage Vpgma-1+Vstep1 obtained by adding the first step voltage Vstep1 and the a-1th programming voltage Vpgma-1 (in the a-1th programming loop PLa-1, the a-1th programming voltage Vpgma-1 is applied to the selected word line) can be applied to the selected word line in the a-1th programming loop PLa.

[0161] Thereafter, in a program loop, when the number of turned-off memory cells is greater than or equal to the first reference value REF_VAL1, the step voltage may be set to the first step voltage Vstep1. That is, as the program loop proceeds, the magnitude of the program voltage may increase by the first step voltage Vstep1.

[0162] As a result, as the program loop progresses, the size of the step voltage can be set differently based on the number of memory cells turned off, thereby increasing the programming speed.

[0163] Figure 9One embodiment of a program loop and a step voltage determined when the number of reference values is plural is illustrated.

[0164] refer to Figure 7 and Figure 9 , Figure 9 Shown based on Figure 7 The step voltage is determined by comparing the number of off-memory cells OFFCELL_NUM included in the count information COUNT_INF with the second reference value REF_VAL2 and the third reference value REF_VAL3, and a program loop performed using the determined step voltage is shown. The second reference value REF_VAL2 and the third reference value REF_VAL3 may be preset.

[0165] refer to Figure 9 , different from Figure 8 , Figure 9 A method of setting a step voltage based on two reference values is shown. That is, the step voltage can be set by subdividing the number of memory cells to be turned off.

[0166] Similar to Figure 8 ,exist Figure 9 middle, Figure 2 The memory device 100 may program the selected memory cells through a normal program operation or DPGM. In addition, DPGM may be performed from the first program loop PL1 or may be performed from a specific program loop.

[0167] first, Figure 2 The memory device 100 may perform a first program loop PL1. The first program loop PL1 may include a program operation and a verification operation. Figure 2 The memory device 100 may perform a program operation by applying a first program voltage Vpgm1 to a selected word line, and then perform a verification operation by applying a pre-verification voltage Vvfyp and a main verification voltage Vvfym.

[0168] Similar to Figure 8 ,exist Figure 9 In the first program loop PL1, the verification operation included in the first program loop PL1 is performed using the pre-verification voltage Vvfyp and the main verification voltage Vvfym. However, when the selected memory cells are programmed by the normal program operation, the verification operation may also be performed using only the main verification voltage Vvfym.

[0169] In one embodiment, during a pre-verification operation or a main verification operation, when the number of memory cells turned off is less than a second reference value REF_VAL2, the magnitude of the program voltage applied to the selected word line in the second programming loop PL2 can be set to a magnitude Vpgm1+Vstep1+Voffset2, which is obtained by adding the first step voltage Vstep1 and the second offset voltage Voffset2 to the first programming voltage Vpgm1. When programming the selected memory cells using the ISPP method, the first step voltage Vstep1 can be a preset default step voltage. Here, as the number of program operations and erase operations performed on the selected memory cells increases, the magnitude of the second offset voltage Voffset2 can decrease.

[0170] However, when the number of turned-off memory cells is greater than or equal to the second reference value REF_VAL2 and less than the third reference value REF_VAL3, the magnitude of the program voltage applied to the selected word line in the second programming loop PL2 may be set to a magnitude Vpgm1+Vstep1+Voffset3 obtained by adding the first step voltage Vstep1 and the third offset voltage Voffset3 to the first programming voltage Vpgm1. In this case, the magnitude of the third offset voltage Voffset3 may be smaller than the second offset voltage Voffset2. Furthermore, as the number of program operations and erase operations performed on the selected memory cells increases, the magnitude of the third offset voltage Voffset3 may decrease.

[0171] In addition, when the number of turned-off memory cells is greater than or equal to the third reference value REF_VAL3, the size of the programming voltage applied to the selected word line in the second programming loop PL2 can be set to a size Vpgm1+Vstep1 obtained by adding the first step voltage Vstep1 to the first programming voltage Vpgm1.

[0172] exist Figure 9 In, when Figure 2 When the memory device 100 performs the first program loop PL1, it is assumed that the number of turned-off memory cells is less than the second reference value REF_VAL2. Figure 2 When the memory device 100 performs the second programming loop PL2, the size of the step voltage can be set to a size obtained by adding the first step voltage Vstep1 and the second offset voltage Voffset2, and a programming voltage Vpgm1+Vstep1+Voffset2 of a size obtained by adding the first programming voltage Vpgm1, the first step voltage Vstep1, and the second offset voltage Voffset2 can be applied to the selected word line.

[0173] Thereafter, in a programming loop, when the number of memory cells turned off is less than the second reference value REF_VAL2, the size of the step voltage may be set to a size obtained by adding the first step voltage Vstep1 and the second offset voltage Voffset2. That is, as the programming loop proceeds, the size of the programming voltage may increase by a size obtained by adding the first step voltage Vstep1 and the second offset voltage Voffset2.

[0174] In one embodiment, in the b-1th programming loop PLb-1 executed before the b-1th programming loop PLb, during the pre-verification operation or the main verification operation, the number of memory cells turned off may be greater than or equal to the second reference value REF_VAL2 and less than the third reference value REF_VAL3. In this case, in the b-1th programming loop PLb, which is the next programming loop, the size of the step voltage may be set to a size obtained by adding the first step voltage Vstep1 and the third offset voltage Voffset3. Therefore, the program voltage Vpgmb-1+Vstep1+Voffset3 of a size obtained by adding the first step voltage Vstep1, the third offset voltage Voffset3, and the b-1th programming voltage Vpgmb-1 (the b-1th programming voltage Vpgmb-1 is applied to the selected word line in the b-1th programming loop PLb-1) may be applied to the selected word line in the b-1th programming loop PLb.

[0175] Thereafter, in a programming loop, when the number of memory cells turned off is greater than or equal to the second reference value REF_VAL2 and less than the third reference value REF_VAL3, the size of the step voltage may be set to a size obtained by adding the first step voltage Vstep1 and the third offset voltage Voffset3. That is, as the programming loop proceeds, the size of the programming voltage may increase by a size obtained by adding the first step voltage Vstep1 and the third offset voltage Voffset3.

[0176] In one embodiment, in the c-1th programming loop PLc-1 executed before the c-1th programming loop PLc, during the pre-verification operation or the main verification operation, the number of memory cells turned off may be greater than or equal to the third reference value REF_VAL3. In this case, in the c-1th programming loop PLc as the next programming loop, the size of the step voltage may be set to the first step voltage Vstep1. Therefore, the size of the program voltage Vpgmc-1+Vstep1 obtained by adding the first step voltage Vstep1 and the c-1th programming voltage Vpgmc-1 (in the c-1th programming loop PLc-1, the c-1th programming voltage Vpgmc-1 is applied to the selected word line) can be applied to the selected word line in the c-1th programming loop PLc.

[0177] Thereafter, in a program loop, when the number of turned-off memory cells is greater than or equal to the third reference value REF_VAL3, the step voltage may be set to the first step voltage Vstep1. That is, as the program loop proceeds, the magnitude of the program voltage may increase by the first step voltage Vstep1.

[0178] As a result, as the program loop progresses, the size of the step voltage can be set differently based on the number of memory cells turned off, thereby increasing the programming speed.

[0179] Figure 10 Another embodiment of a program loop and a step voltage determined when the number of reference values is plural is illustrated.

[0180] refer to Figure 7 and Figure 10 , Figure 10 Shown based on Figure 7 The step voltage is determined by comparing the number of off-memory cells OFFCELL_NUM included in the count information COUNT_INF with the second reference value REF_VAL2 and the third reference value REF_VAL3, and a program loop performed using the determined step voltage is shown. The second reference value REF_VAL2 and the third reference value REF_VAL3 may be preset.

[0181] refer to Figure 9 and Figure 10 , different from Figure 9 , Figure 10 An embodiment is shown in which the step voltage according to the present disclosure is reflected only in the second program loop PL2 .

[0182] In this figure, Figure 9 Descriptions of contents that overlap with the contents of the original are omitted.

[0183] In one embodiment, during a pre-verification operation or a main verification operation of a first programming loop PL1, when the number of memory cells turned off is less than a second reference value REF_VAL2, the magnitude of the program voltage applied to the selected word line in the second programming loop PL2 can be set to a magnitude Vpgm1+Vstep1+Voffset2, which is obtained by adding a first step voltage Vstep1 and a second offset voltage Voffset2 to the first programming voltage Vpgm1. When programming the selected memory cells using the ISPP method, the first step voltage Vstep1 can be a preset default step voltage. In addition, as the number of program operations and erase operations performed on the selected memory cells increases, the magnitude of the second offset voltage Voffset2 can decrease.

[0184] However, when the number of turned-off memory cells is greater than or equal to the second reference value REF_VAL2 and less than the third reference value REF_VAL3, the magnitude of the program voltage applied to the selected word line in the second programming loop PL2 may be set to a magnitude Vpgm1+Vstep1+Voffset3 obtained by adding the first step voltage Vstep1 and the third offset voltage Voffset3 to the first programming voltage Vpgm1. In this case, the magnitude of the third offset voltage Voffset3 may be smaller than the second offset voltage Voffset2. Furthermore, as the number of program operations and erase operations performed on the selected memory cells increases, the magnitude of the third offset voltage Voffset3 may decrease.

[0185] In addition, when the number of turned-off memory cells is greater than or equal to the third reference value REF_VAL3, the size of the programming voltage applied to the selected word line in the second programming loop PL2 can be set to a size Vpgm1+Vstep1 obtained by adding the first step voltage Vstep1 to the first programming voltage Vpgm1.

[0186] In one embodiment, in the programming loop after the third programming loop PL3, the magnitude of the programming voltage may be increased by the magnitude of the first step voltage Vstep1. That is, the magnitude of the voltage applied to the selected word line in the third programming loop PL3 may be set to a magnitude Vpgm2+Vstep1 obtained by adding the first step voltage Vstep1 to the second programming voltage Vpgm2 applied in the second programming loop PL2.

[0187] Therefore, the offset voltage and the step voltage determined based on the number of turned-off memory cells can be reflected only in the second programming loop PL2, and in the programming loop after the third programming loop PL3, a voltage that is greater than the programming voltage applied to the selected word line in the previous programming loop by the first step voltage Vstep1 can be applied to the selected word line.

[0188] As a result, the step voltage may be differently set based on the number of turned-off memory cells in the second program loop PL2 , thereby increasing the program speed.

[0189] Figure 11 The diagram shows that every Figures 8 to 10 The threshold voltage distribution shifts as the programming cycle proceeds.

[0190] refer to Figures 8 to 11 , Figure 11 Shown in Figures 8 to 10 The threshold voltage distribution of the memory cells shifts when the programming loops are executed sequentially. Figure 11 In FIG, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells. Figure 11 In, assuming Figure 1 The memory device 100 performs a program operation by an SLC method.

[0191] In one embodiment, when a program operation is performed on a selected memory cell in the erase state E, Figures 8 to 10 That is, as the programming loop progresses, multiple programming loops can be performed using a programming voltage that increases with a set step voltage. At this time, the memory cell in the erased state E can be programmed to the target program state P through various states.

[0192] When with Figure 6 In comparison, Figure 11 The width of the shift of the threshold voltage distribution of the selected memory cell can be greater than Figure 6 The width of the movement.

[0193] In one embodiment, when the first program loop PL1 is performed on selected memory cells, the threshold voltage distribution of memory cells in the erase state E may be programmed to a PX1 ′ distribution.

[0194] In one embodiment, the program voltage to be applied to the selected word line in the second programming loop PL2 may be determined based on a result of comparing the number of memory cells turned off in the first programming loop PL1 with a reference value. For example, the magnitude of the voltage applied to the selected word line in the second programming loop PL2 may be Vpgm1+Vstep1+Voffset, which is obtained by adding the first step voltage Vstep1 and the offset voltage Voffset to the first programming voltage Vpgm1.

[0195] Therefore, in the second programming loop PL2, a programming voltage of Vpgml+Vstepl+Voffset (obtained by adding the first step voltage Vstepl and the offset voltage Voffset to the first programming voltage Vpgml) instead of a programming voltage of Vpgm1+Vstep1 (obtained by adding the first step voltage Vstep1 to the first programming voltage Vpgm1) can be applied to the selected word line, and thus the moving width of the threshold voltage distribution of the selected memory cell can be large.

[0196] That is, when referring to Figure 6 When Figure 6 When the second program loop PL2 is executed in , the threshold voltage distribution of the memory cells changes from the PX1 distribution to the PX2 distribution. Figure 11 In the embodiment, when the second program loop PL2 is performed, the threshold voltage distribution of the memory cells may be changed from the PX1′ distribution to the PX2′ distribution.

[0197] As a result, the magnitude of the step voltage can be set differently as the programming loop progresses, thereby increasing the programming speed.

[0198] Figure 12 is a diagram illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0199] refer to Figure 12 In step S1201, the memory device may count the number of memory cells turned off based on the pass or fail signal. Specifically, when the memory device performs multiple program loops to program selected memory cells, the memory device may count the number of memory cells turned off in the pre-verification operation or the main verification operation.

[0200] When the memory device programs the selected memory cells through DPGM, the memory device can count the turned-off memory cells in the pre-verification operation or the main verification operation, and when the memory device programs the selected memory cells through the normal programming operation, the memory device can count the turned-off memory cells in the main verification operation.

[0201] In step S1203, the memory device may set a step voltage based on the counted number of memory cells and then apply a program voltage to the selected word line. For example, when the counted number of memory cells is less than a reference value, the memory device may set the step voltage to a magnitude obtained by adding an offset voltage to the existing step voltage. When the step voltage is set, the memory device may apply a voltage to the selected word line having a magnitude obtained by adding the set step voltage to the program voltage applied to the selected word line in the previous programming cycle.

[0202] In step S1205, the memory device may determine whether the verification operation passes. When the verification operation fails (No), the memory device may proceed to step S1201 again, count the number of memory cells turned off, and set the step voltage again based on the counted number of memory cells.

[0203] Figure 13 is a diagram illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0204] refer to Figure 12 and Figure 13 , Figure 13 Shows the Figure 12 The step S1203 is a step of subdividing.

[0205] In step S1301, the memory device may determine whether the number of counted memory cells is less than a reference value. That is, the memory device may compare the number of turned-off memory cells with the reference value.

[0206] When the number of counted memory cells is greater than or equal to the reference value (No), the operation may proceed to step S1303, and when the number of counted memory cells is less than the reference value (Yes), the operation may proceed to step S1305.

[0207] When the number of counted memory cells is greater than or equal to the reference value (No), then in step S1303, the memory device may determine a first step voltage as the step voltage. The first step voltage may be a preset default step voltage when programming the selected memory cells by the ISPP method.

[0208] However, when the number of counted memory cells is less than the reference value (Yes), then in step S1305, the memory device may determine a voltage greater than the first step voltage by an offset voltage as the step voltage. That is, when the number of counted memory cells is less than the reference value, the memory device may set the step voltage to be higher than the preset default step voltage by an offset voltage.

[0209] When the step voltage is set, the memory device may apply a program voltage to the selected word line in step S1307. At this time, the program voltage may be a voltage greater than the program voltage applied to the selected word line in the previous program loop by the set step voltage.

[0210] In step S1309, the memory device may perform a verification operation. In this case, the verification operation may be a pre-verification operation or a main verification operation. That is, when the selected memory cell is programmed by a normal programming operation, the verification operation may be a main verification operation, and when the selected memory cell is programmed by DPGM, the verification operation may be a pre-verification operation or a main verification operation.

[0211] In one embodiment, when the verification operation passes, the program loop may be ended, but when the verification operation fails, the next program loop may be performed. In the next program loop, the memory device may again determine the step voltage based on the number of turned-off memory cells.

[0212] As a result, until the number of turned-off memory cells is greater than or equal to the reference value, the step voltage may be set to a value greater than the preset default step voltage by the offset voltage. When the number of turned-off memory cells is greater than or equal to the reference value, the step voltage may be set to the preset default step voltage.

[0213] Figure 14 It is an icon Figure 1 FIG. 1 is a diagram of another embodiment of a memory controller.

[0214] The memory controller 1000 is connected to a host and a memory device. The memory controller 1000 is configured to access the memory device in response to a request from the host. For example, the memory controller 1000 is configured to control writing, reading, erasing, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

[0215] refer to Figure 14 , the memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction circuit (ECC) 1030 , a host interface 1040 , a buffer controller (or buffer control circuit) 1050 , a memory interface 1060 , and a bus 1070 .

[0216] The bus 1070 may be configured to provide a channel between the components of the memory controller 1000 .

[0217] The processor 1010 may control the overall operation of the memory controller 1000 and may perform logic operations. The processor 1010 may communicate with an external host through a host interface 1040 and with a memory device through a memory interface 1060. In addition, the processor 1010 may communicate with the memory buffer 1020 through a buffer controller 1050. The processor 1010 may use the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory to control the operation of the memory device.

[0218] The processor 1010 can perform the function of the Flash Translation Layer (FTL). The processor 1010 can convert the LBA provided by the host into a PBA through the FTL. The FTL can receive the LBA and convert the LBA into a PBA by using a mapping table. The address mapping method of the Flash Translation Layer includes multiple mapping methods based on the mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

[0219] The processor 1010 is configured to randomize data received from the host. For example, the processor 1010 may randomize the data received from the host using a randomization seed. The randomized data is provided to the memory device as data to be stored and is programmed into the memory cell array.

[0220] The processor 1010 may perform randomization and de-randomization through driving software or firmware.

[0221] The memory buffer 1020 may be used as an operating memory, a cache memory, or a buffer memory of the processor 1010. The memory buffer 1020 may store codes and commands executed by the processor 1010. The memory buffer 1020 may store data processed by the processor 1010. The memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0222] The error correction circuit 1030 may perform error correction. The error correction circuit 1030 may perform error correction encoding (ECC encoding) based on data to be written to the memory device via the memory interface 1060. The error correction encoded data may be transmitted to the memory device via the memory interface 1060. The error correction circuit 1030 may perform error correction decoding (ECC decoding) on the data received from the memory device via the memory interface 1060. For example, the error correction circuit 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

[0223] The host interface 1040 is configured to communicate with an external host under the control of the processor 1010. The host interface 1040 may be configured to perform communication using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI Express), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMediaCard (MMC), Embedded MMC (eMMC), Dual Inline Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0224] The buffer controller 1050 is configured to control the memory buffer 1020 under the control of the processor 1010 .

[0225] The memory interface 1060 is configured to communicate with the memory device under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory device through a channel.

[0226] For example, the memory controller 1000 may not include the memory buffer 1020 and the buffer controller 1050 .

[0227] For example, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a nonvolatile memory device (e.g., a read-only memory) provided inside the memory controller 1000. As another example, the processor 1010 may load code from a memory device through the memory interface 1060.

[0228] For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may be configured to transmit data within the memory controller 1000, and the control bus may be configured to transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus may be separated from each other and may not interfere with or affect each other. The data bus may be connected to the host interface 1040, the buffer controller 1050, the error correction circuit 1030, and the memory interface 1060. The control bus may be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1020, and the memory interface 1060.

[0229] Figure 15 is a block diagram illustrating a memory card system 2000 to which a storage device according to one embodiment of the present disclosure is applied.

[0230] refer to Figure 15 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0231] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 is configured to control reading, writing, erasing, and background operations of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and the host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory device 2200 can communicate with the reference Figure 1 Description Figure 1 The memory device 100 is implemented identically.

[0232] As one example, the memory controller 2100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error correction circuit.

[0233] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. As an example, the memory controller 2100 is configured to communicate with an external device through at least one of various communication standards, such as Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Minidisk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. As an example, the connector 2300 can be defined by at least one of the various communication standards mentioned above.

[0234] As an example, the memory device 2200 can be implemented using various non-volatile memory types, such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0235] The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure memory cards such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, MicroMMC, or eMMC), an SD card (SD, MiniSD, MicroSD, or SDHC), and a Universal Flash Storage (UFS).

[0236] In one embodiment, the memory device 2200 can program the selected memory cells. In this case, the memory device 2200 can program the selected memory cells through a normal programming operation or DPGM. In DPGM, the memory device 2200 can perform a pre-verification operation using a pre-verification voltage and a main verification operation using a main verification voltage greater than the pre-verification voltage.

[0237] In one embodiment, the memory device 2200 may count the number of memory cells turned off in a pre-verification operation or a main verification operation. In addition, the memory device 2200 may determine a step voltage to be reflected in the next programming loop based on a result of comparing the number of memory cells turned off with a reference value.

[0238] For example, when the number of memory cells turned off is less than the reference value, the memory device 2200 may set the step voltage of the next programming loop to be greater than the default step voltage by an offset voltage. Here, the offset voltage may decrease as the number of program operations and erase operations performed on the selected memory cells increases.

[0239] However, when the number of turned-off memory cells is greater than or equal to the reference value, the memory device 2200 may set the step voltage of the next program loop to a default step voltage.

[0240] Therefore, the memory device 2200 can set the step voltage to be greater than the default step voltage by the offset voltage until the number of turned-off memory cells is greater than or equal to the reference value. Thereafter, when the number of turned-off memory cells is greater than or equal to the reference value, the memory device 2200 can set the default step voltage to the step voltage.

[0241] Figure 16 is a block diagram illustrating a solid-state drive (SSD) system 3000 to which a storage device according to one embodiment of the present disclosure is applied.

[0242] refer to Figure 16, an SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges a signal SIG with the host 3100 via a signal connector 3001 and receives power PWR via a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power device 3230, and a buffer memory 3240.

[0243] In one embodiment, the SSD controller 3210 may perform a reference Figure 1 Description Figure 1 The functions of the memory controller 200 are as follows.

[0244] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. As an example, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced MiniDisk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0245] The auxiliary power device 3230 is connected to the host 3100 via the power connector 3002. The auxiliary power device 3230 can receive power PWR from the host 3100 and can be charged with this power. When the power supply from the host 3100 is not smooth, the auxiliary power device 3230 can provide power to the SSD 3200. As an example, the auxiliary power device 3230 can be located in the SSD 3200, or can be located outside the SSD 3200. For example, the auxiliary power device 3230 can be located on the motherboard and can provide auxiliary power to the SSD 3200.

[0246] The buffer memory 3240 operates as a buffer memory for the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or can temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0247] In one embodiment, each of the plurality of flash memories 3221 to 322n can program selected memory cells. In this case, the plurality of flash memories 3221 to 322n can program the selected memory cells using a normal programming operation or DPGM. In DPGM, the plurality of flash memories 3221 to 322n can perform a pre-verification operation using a pre-verification voltage and a main verification operation using a main verification voltage greater than the pre-verification voltage.

[0248] In one embodiment, the plurality of flash memories 3221 to 322n may count the number of memory cells turned off during a pre-verification operation or a main verification operation. Furthermore, the plurality of flash memories 3221 to 322n may determine a step voltage to be reflected in the next programming loop based on a result of comparing the number of memory cells turned off with a reference value.

[0249] For example, when the number of memory cells turned off is less than a reference value, the plurality of flash memories 3221 to 322n may set the step voltage of the next programming loop to be greater than the default step voltage by an offset voltage. Here, the offset voltage may decrease as the number of program operations and erase operations performed on the selected memory cells increases.

[0250] However, when the number of turned-off memory cells is greater than or equal to the reference value, the plurality of flash memories 3221 to 322n may set the step voltage of the next program loop to a default step voltage.

[0251] Therefore, the plurality of flash memories 3221 to 322n may set the step voltage to be greater than the default step voltage by the offset voltage until the number of the turned-off memory cells is greater than or equal to the reference value. Thereafter, when the number of the turned-off memory cells is greater than or equal to the reference value, the plurality of flash memories 3221 to 322n may set the default step voltage to the step voltage.

[0252] Figure 17is a block diagram illustrating a user system 4000 to which a storage device according to one embodiment of the present disclosure is applied.

[0253] refer to Figure 17 , the user system 4000 includes an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 and a user interface 4500 .

[0254] The application processor 4100 may drive components included in the user system 4000, an operating system (OS), a user program, etc. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. that controls the components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0255] The memory module 4200 can operate as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package-on-package (POP) method and provided as one semiconductor package.

[0256] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, WiMAX, WLAN, UWB, Bluetooth, and WI-FI. For example, the network module 4300 can be included in the application processor 4100.

[0257] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transmit the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 can be implemented using a non-volatile semiconductor memory such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, and a three-dimensional NAND flash memory. For example, the storage module 4400 can be provided as a removable storage device (removable drive) (such as a memory card) and an external drive of the user system 4000.

[0258] For example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be connected to the reference memory. Figure 2 and Figure 3 The memory module 4400 can be used with reference to Figure 1 The described storage device 50 operates identically.

[0259] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 may include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0260] In one embodiment, the memory module 4400 can program the selected memory cells. In this case, the memory module 4400 can program the selected memory cells through a normal programming operation or DPGM. In DPGM, the memory module 4400 can perform a pre-verification operation using a pre-verification voltage and a main verification operation using a main verification voltage greater than the pre-verification voltage.

[0261] In one embodiment, the memory module 4400 may count the number of memory cells turned off in the pre-verification operation or the main verification operation. In addition, the memory module 4400 may determine a step voltage to be reflected in the next programming loop based on a result of comparing the number of memory cells turned off with a reference value.

[0262] For example, when the number of memory cells turned off is less than the reference value, the memory module 4400 may set the step voltage of the next programming loop to be greater than the default step voltage by an offset voltage. Here, the offset voltage may decrease as the number of program operations and erase operations performed on the selected memory cells increases.

[0263] However, when the number of turned-off memory cells is greater than or equal to the reference value, the memory module 4400 may set the step voltage of the next program loop to a default step voltage.

[0264] Therefore, the memory module 4400 may set the step voltage to be greater than the default step voltage by the offset voltage until the number of memory cells turned off is greater than or equal to the reference value. Thereafter, when the number of memory cells turned off is greater than or equal to the reference value, the memory module 4400 may set the default step voltage to the step voltage.

Claims

1. A memory device comprising: a memory cell array comprising a plurality of memory cells connected to a plurality of word lines; a peripheral circuit configured to perform a plurality of programming loops to program memory cells connected to a selected word line among the plurality of word lines among the plurality of memory cells; as well as The control logic is configured to control the peripheral circuit to: set a step voltage based on the number of turned-off memory cells among the selected memory cells during the verification operation in the program operation and the verification operation included in each of the plurality of program loops; and then, apply a program voltage to the selected word line in a next program loop, the step voltage being added to the program voltage.

2. The memory device of claim 1 , wherein when the plurality of program loops are performed using double verify programming: The verification operation is any one of a pre-verification operation performed using a pre-verification voltage and a main verification operation performed using a main verification voltage, the main verification voltage being greater than the pre-verification voltage; and The control logic is configured to set the step voltage based on a number of memory cells turned off during the pre-verification operation or the main verification operation. 3 . The memory device according to claim 1 , wherein the control logic is configured to set the step voltage to a size obtained by adding an offset voltage to a default step voltage when the number of the turned-off memory cells is less than a preset reference value. 4 . The memory device of claim 3 , wherein the offset voltage is set based on a number of times the program operation and the erase operation are performed on the selected memory cell. 5 . The memory device of claim 4 , wherein the control logic is configured to decrease the offset voltage as the number of the program operations and the number of the erase operations increase.

6. The memory device of claim 3, wherein the control logic is configured to set the step voltage to the size obtained by adding the offset voltage to the default step voltage until the number of the turned-off memory cells is greater than or equal to the preset reference value. 7 . The memory device according to claim 6 , wherein the control logic is configured to set the default step voltage to the step voltage when the number of the turned-off memory cells is greater than or equal to the preset reference value.

8. The memory device according to claim 3 , wherein the control logic is configured to: apply the programming voltage to the selected word line, in which the step voltage is set to the size obtained by adding the offset voltage to the default step voltage; and then set the step voltage to the default step voltage. 9 . The memory device of claim 1 , wherein the control logic is configured to set a default step voltage to the step voltage when the number of the turned-off memory cells is greater than or equal to a preset reference value.

10. The memory device of claim 1 , wherein the control logic is configured to: When the number of the turned-off memory cells is less than a preset first reference value, setting the step voltage to a magnitude obtained by adding a first offset voltage to a default step voltage; and When the number of the turned-off memory cells is greater than or equal to the first reference value and less than a preset second reference value, the step voltage is set to a size obtained by adding a second offset voltage to the default step voltage. The memory device of claim 10 , wherein the first offset voltage is greater than the second offset voltage.

12. The memory device according to claim 10 , wherein the control logic is configured to, when the step voltage is determined to be the size obtained by adding the first offset voltage to the default step voltage, set the step voltage to the size obtained by adding the first offset voltage to the default step voltage until the number of the turned-off memory cells is greater than or equal to the first reference value and less than the second reference value.

13. The memory device of claim 12 , wherein the control logic is configured to set the step voltage to the size obtained by adding the second offset voltage to the default step voltage when the number of the turned-off memory cells is greater than or equal to the first reference value and less than the second reference value.

14. The memory device of claim 13, wherein the control logic is configured to set the step voltage to the size obtained by adding the second offset voltage to the default step voltage until the number of the turned-off memory cells is greater than or equal to the second reference value. 15 . The memory device of claim 14 , wherein the control logic is configured to set the default step voltage to the step voltage when the number of the turned-off memory cells is greater than or equal to the second reference value.

16. A memory device comprising: a memory cell array comprising a plurality of memory cells connected to a plurality of word lines; a peripheral circuit configured to perform a plurality of programming loops to program memory cells connected to a selected word line among the plurality of word lines among the plurality of memory cells; as well as The control logic includes: a memory cell counter for counting the number of turned-off memory cells among the selected memory cells; and a step voltage controller for controlling the peripheral circuit to: set a step voltage based on the number of the turned-off memory cells during the verification operation in the program operation and the verification operation included in each of the plurality of program loops; and then, apply a program voltage to the selected word line in a next program loop, the step voltage being added to the program voltage.

17. The memory device according to claim 16, wherein the step voltage controller is configured to control the peripheral circuit to: set the step voltage to a size obtained by adding an offset voltage to a default step voltage when the number of the turned-off memory cells is less than a preset reference value; and apply a programming voltage that is larger than the programming voltage in the previous programming loop by the step voltage to the selected word line in a next programming loop.

18. The memory device of claim 17, wherein the step voltage controller is configured to: setting the step voltage to the size obtained by adding the offset voltage to the default step voltage until the number of the turned-off memory cells is greater than or equal to the preset reference value; and When the number of the turned-off memory cells is greater than or equal to the preset reference value, the default step voltage is set to the step voltage.

19. A method of operating a memory device, the memory device comprising a plurality of memory cells connected to each of a plurality of word lines, the method comprising: performing a program operation by applying a program voltage to a selected word line among the plurality of word lines; performing a verification operation by applying a verification voltage to the selected word line; counting turned-off memory cells among selected memory cells connected to the selected word line during the verify operation; setting a step voltage based on a count number of turned-off memory cells; as well as A program voltage is applied to the selected word line, and the step voltage is added to the program voltage.

20. The method according to claim 19, wherein setting the step voltage comprises: When the number of the turned-off memory cells is less than a preset reference value, the step voltage is set to a size obtained by adding an offset voltage to a default step voltage.

21. The method according to claim 20, wherein setting the step voltage comprises: setting the step voltage to the size obtained by adding the offset voltage to the default step voltage until the number of the turned-off memory cells is greater than or equal to the preset reference value; as well as When the number of the turned-off memory cells is greater than or equal to the preset reference value, the step voltage is set to the default step voltage.

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