Semiconductor processing equipment and method

Abstract

The present application relates to a semiconductor processing device and method. In one embodiment of the present application, the semiconductor processing device comprises: a wafer carrier body, in which a lower electrode is disposed, the lower electrode is coupled to a DC power supply; and an upper electrode, which is disposed opposite to the wafer carrier body, the upper electrode is coupled to a radio frequency generator via a matching circuit, and is grounded via a low-pass filter.

Description

Technical Field

[0001] The present application relates generally to the field of semiconductor manufacturing equipment, and more particularly to a semiconductor processing apparatus and method. Background Art

[0002] Semiconductor processing equipment usually includes an electrostatic chuck. An electrostatic chuck is an ultra-clean wafer carrier suitable for vacuum and plasma working environments. It uses the principle of electrostatic adsorption to clamp the wafer flatly and evenly. In the semiconductor process, the electrostatic chuck is often used to maintain the temperature and warpage of the wafer. It is a core component of semiconductor processing equipment such as plasma enhanced chemical vapor deposition and ion implantation.

[0003] For a monopolar electrostatic chuck, when adsorption and desorption are performed, a DC current needs to pass through a DC power supply, a wafer carrier plate surface, plasma, and ground to form a DC current loop. However, the side walls of the process chamber in contact with the plasma are usually made of ceramic, which is not conducive to the free conduction of charges in the plasma, and thus cannot provide a stable and effective DC channel from the plasma to the ground. In addition, the upper electrode in contact with the plasma is usually used as an electrode for RF application, which is coupled to a matching circuit and is capacitively isolated from the ground, thereby hindering the DC loop current and affecting the stability of the DC current, thereby affecting the electrostatic adsorption and desorption effects. The electrostatic adsorption and desorption effects of the electrostatic chuck will further affect the process stability and production efficiency of semiconductor processing equipment. Summary of the invention

[0004] The solution of the present application can provide an effective DC current loop for the electrostatic chuck in the semiconductor processing equipment, enhance the stability of the DC current, improve the electrostatic adsorption and desorption functions, and improve the process stability and production efficiency of the semiconductor processing equipment.

[0005] On the one hand, the present application provides a semiconductor processing device, which may include: a wafer carrier body, in which a lower electrode is disposed, and the lower electrode is coupled to a DC power supply; and an upper electrode, which is arranged opposite to the wafer carrier body, and the upper electrode is coupled to a radio frequency generator via a matching circuit and grounded via a low-pass filter.

[0006] According to an embodiment of the present application, the low-pass filter may include a resistor and an inductor.

[0007] According to an embodiment of the present application, the resistance value of the resistor is fixed or adjustable.

[0008] According to an embodiment of the present application, the resistance value or resistance value range of the resistor is selected based on the leakage current requirement of the surface of the wafer carrier plate.

[0009] According to an embodiment of the present application, the low-pass filter may be connected to a radio frequency feeding conductor between the upper electrode and the matching circuit.

[0010] According to an embodiment of the present application, the low-pass filter may be grounded through a shielding cover.

[0011] According to an embodiment of the present application, the low-pass filter may be disposed in the matching circuit.

[0012] According to an embodiment of the present application, the low-pass filter may include a DC leakage channel in the matching circuit.

[0013] According to an embodiment of the present application, the low-pass filter may include a metal-doped ceramic chip capacitor in the matching circuit.

[0014] According to an embodiment of the present application, the wafer carrying plate may be made of insulating material.

[0015] According to an embodiment of the present application, the wafer carrier may include a JR type electrostatic chuck.

[0016] According to an embodiment of the present application, the semiconductor processing equipment may include a plasma enhanced chemical vapor deposition equipment.

[0017] On the other hand, the present application also provides a method for using the semiconductor processing equipment described in any embodiment of the present application, which may include: placing a wafer on a wafer carrier plate; and applying a voltage to the lower electrode in the wafer carrier plate through the DC power supply to adsorb the wafer to the surface of the wafer carrier plate.

[0018] According to an embodiment of the present application, the method may further include applying radio frequency power to the upper electrode through a radio frequency generator to generate plasma between the upper electrode and the wafer during the period of applying voltage to the lower electrode.

[0019] According to an embodiment of the present application, the method may further include stopping applying voltage to the lower electrode to desorb the wafer from the surface of the wafer carrier plate.

[0020] According to an embodiment of the present application, the method may further include applying radio frequency power to the upper electrode through the radio frequency generator to generate plasma between the upper electrode and the wafer during the period when the voltage applied to the lower electrode is stopped.

[0021] The details of one or more examples of the present application are set forth in the following drawings and description. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The disclosure in this specification refers to and includes the following figures:

[0023] Figure 1 is a schematic structural diagram of a semiconductor processing device according to some embodiments of the present application;

[0024] Figure 2 is a schematic structural diagram of another semiconductor processing device according to some embodiments of the present application;

[0025] Figure 3 is a schematic structural diagram of another semiconductor processing equipment according to some embodiments of the present application.

[0026] As a matter of practice, the various features illustrated in the drawings may not be drawn to scale. Therefore, the sizes of the various features may be arbitrarily enlarged or reduced for clarity. The shapes of the components illustrated in the drawings are exemplary shapes only and do not define the actual shapes of the components. In addition, the embodiments illustrated in the drawings may be simplified for clarity. Therefore, the drawings may not illustrate all components of a given device or apparatus. Finally, the same reference numerals may be used throughout the specification and the drawings to represent the same features. DETAILED DESCRIPTION

[0027] In order to better understand the spirit of the present invention, it is further described below in conjunction with some embodiments of the present invention.

[0028] The words "in one embodiment" or "according to one embodiment" used in this specification do not necessarily refer to the same specific embodiment, and the words "in other (some / certain) embodiments" or "according to other (some / certain) embodiments" used in this specification do not necessarily refer to different specific embodiments. The purpose is, for example, that the claimed subject matter includes a combination of all or part of the exemplary specific embodiments. The meaning of "upper" and "lower" referred to herein is not limited to the relationship directly presented in the drawings, and should include descriptions with clear corresponding relationships, such as "left" and "right", or the opposite of "upper" and "lower". The term "connected" as used herein should be understood to cover "directly connected" and "connected via one or more intermediate components". The names of the various components used in this specification are for illustrative purposes only and are not limiting. Different manufacturers may use different names to refer to components with the same functions.

[0029] Various embodiments of the present invention are discussed in detail below. Although specific implementations are discussed, it should be understood that these embodiments are for illustrative purposes only. Those skilled in the relevant art will recognize that other components and configurations may be used without departing from the spirit and scope of the present invention. The implementation of the present invention may not necessarily include all components or steps in the embodiments described in the specification, and the execution order of each step may also be adjusted according to actual application.

[0030] Figure 1 1 is a schematic diagram of a semiconductor processing device 10 according to some embodiments of the present application. In some embodiments, the semiconductor processing device 10 includes a plasma enhanced chemical vapor deposition device. The semiconductor processing device 10 may include a wafer carrier 101, a lower electrode 102, an upper electrode 103, a low-pass filter 104, a matching circuit 105, a radio frequency generator 106, and a direct current power supply 107.

[0031] The wafer carrier 101 is disposed in a process chamber limited by a side wall 111 and fixed above a support 109. The lower electrode 102 is disposed in the wafer carrier 101 and coupled to a DC power supply 107. In some embodiments, a filter 108 is disposed between the DC power supply 107 and the lower electrode 102. The DC current can flow to the lower electrode 102 through the filter 108, and the RF current can flow to the ground through the filter 108.

[0032] The upper electrode 103 is disposed above the wafer carrier plate 101 and opposite to the wafer carrier plate 101. The upper electrode 103 is coupled to the RF generator 106 via the matching circuit 105. The RF generator 106 can provide RF power to the upper electrode 103. The process gas in the process chamber generates a glow discharge under the RF electric field of the upper electrode 103 to form a plasma 113, which is finally deposited on the surface of the wafer 112 placed on the wafer carrier plate 101 to form a solid film. Figure 1 As shown by the dotted arrow in the figure, the RF current can flow out from the RF generator 106, through the matching circuit 105, the upper electrode 103, the plasma 113, the wafer 112, the wafer supporting plate 101 and the lower electrode 102, the filter 108, and finally flows to the ground to form a RF loop 114.

[0033] The upper electrode 103 is also grounded via a low pass filter 104. In some embodiments, the low pass filter 104 may include components such as a resistor and an inductor. A direct current may flow to the ground through the low pass filter 104, while the low pass filter 104 is a high impedance to a radio frequency current.

[0034] After the wafer 112 is sent into the process chamber by a transmission device (not shown) and placed on the wafer carrier plate 101, the DC power supply 107 can apply voltage to the lower electrode 102, so that the lower electrode 102 is electrically biased relative to the wafer carrier plate 101, and polarized charges (and free charges) are generated on the surface of the wafer carrier plate 101. The charges accumulated on the surface of the wafer carrier plate 101 will further affect the wafer 112, causing polarized charges to be generated on its surface. The charges on the surface of the wafer carrier plate 101 are opposite in polarity to the charges on the lower surface of the wafer 112, so an electrostatic adsorption force is generated between the two, causing the wafer 112 to be adsorbed to the surface of the wafer carrier plate 101. Figure 1In order to show the charge polarity of the wafer carrier 101 and the wafer 112, the wafer 112 is shown as being separated from the wafer carrier 101 by a distance. Those skilled in the art should understand that the wafer 112 may substantially contact the wafer carrier 101. Figure 1 As shown by the solid arrow in FIG. 1 , the DC current can flow out from the DC power supply 107, through the filter 108, the lower electrode 102 and the wafer carrier 101, the wafer 112, the plasma 113, the upper electrode 103, the low-pass filter 104, and finally flows to the ground to form a DC loop 115. The DC loop 115 can provide a stable DC current, thereby improving the stability of electrostatic adsorption and electrostatic force.

[0035] It should be noted that the DC current in the DC loop 115 is usually in the range of tens of mA, while the RF current in the RF loop 114 is in the range of several A to tens of A. Therefore, the DC current has little effect on the plasma and can play a role in isolating the RF.

[0036] After the DC power supply 107 stops applying voltage to the lower electrode 102, residual charges will exist on the surface of the wafer carrier 101 and the surface of the wafer 112. These residual charges can be derived through the low-pass filter 104, so as to desorb the wafer 112 from the surface of the wafer carrier 101. During the period when the voltage is stopped from being applied to the lower electrode 102, in order to form a complete DC loop to derive the residual charges, the RF power can continue to be applied to the upper electrode 103 through the RF generator 106 to generate plasma 113 between the upper electrode 103 and the wafer 112, but the process gas is removed and the deposition is stopped. For example, the RF generator 106 can be turned on again after the RF generator 106 is turned off after the process is completed, or the RF generator 106 is not turned off after the process is completed. The RF power provided here can be lower than that in the normal process to avoid affecting the removal of charges due to the high plasma self-bias. During the desorption process, the low-pass filter 104 provides a stable and good DC loop to improve the repeatability and stability of desorption.

[0037] In some embodiments, the wafer carrier 101 may be a JR type electrostatic chuck, and during the period when the DC power supply 107 applies voltage to the lower electrode 102, there are polarized charges and free charges on the surface of the wafer carrier 101. Compared with the Coulomb type electrostatic chuck, the JR type electrostatic chuck has a greater adsorption force (for example, it may be several orders of magnitude greater than the adsorption force of the Coulomb type electrostatic chuck), and thus has a better electrostatic adsorption effect.

[0038] In some embodiments, the wafer carrier 101 may be made of an insulating material. In some embodiments, the insulating material includes a ceramic material.

[0039] In some embodiments, the wafer carrier 101 further includes a heater to perform thermal treatment on the wafer 112 .

[0040] In some embodiments, the bottom electrode 102 is sintered in the wafer carrier 101 .

[0041] In some embodiments, the RF current generated by the RF generator 106 is a low frequency current, for example, a current with a frequency of 400kHz. In some embodiments, the RF current generated by the RF generator 106 is a high frequency current, for example, a current with a frequency of 13.56MHz. In some embodiments, the RF current generated by the RF generator 106 is a current of other frequencies. In some embodiments, the RF generator 106 can provide low frequency current and high frequency current at the same time. The low pass filter 104 is high impedance to these RF currents.

[0042] In some embodiments, the matching circuit 105 may include an inductor and a capacitor. In some embodiments, the matching circuit 105 may include an inductor and two capacitors, one of which is grounded. In some embodiments, the matching circuit 105 may include a ceramic chip capacitor.

[0043] In some embodiments, the resistance value of the resistor in the low-pass filter 104 is fixed. In other embodiments, the resistance value of the resistor in the low-pass filter 104 is adjustable, that is, the resistor has a certain resistance value range.

[0044] In some embodiments, the resistance value or resistance value range of the resistor in the low-pass filter 104 can be selected based on the leakage current requirement on the surface of the wafer carrier plate 101 to provide a suitable DC current and control the magnitude and stability of the electrostatic adsorption force. For example, when the process chamber temperature is around 400°C, the leakage current on the surface of the wafer carrier plate 101 is less than 1 mA, so providing a 1 mA level current channel can ensure the stable operation of the electrostatic chuck. According to the DC voltage provided by the DC power supply 107 and the current required to be provided, the total resistance value required for the DC loop 115 can be calculated using the formula R (resistance) = U (voltage) / I (current), and then the resistance value of the resistor in the low-pass filter 104 can be estimated. The electrostatic current can be limited by increasing the resistance value of the resistor in the low-pass filter 104.

[0045] Figure 2 FIG. 2 is a schematic diagram of another semiconductor processing device 20 according to some embodiments of the present application. The semiconductor processing device 20 may include a radio frequency generator 206, a matching circuit 205, an upper electrode 203, and a wafer carrier 201. Figure 2As shown, the upper electrode 203 is also covered with a shielding cover 218 to provide grounding for the semiconductor processing equipment 20. The matching circuit 205 is connected to the upper electrode 203 via the RF feed conductor 217 to provide a matched RF signal to the upper electrode 203. In some embodiments, the RF feed conductor 217 includes a copper strip or a copper column. The low-pass filter 204 is connected to the RF feed conductor 217 and is grounded through the shielding cover 218, thereby providing a stable DC loop for electrostatic adsorption and desorption. Figure 2 In FIG. 2 , the low-pass filter 204 is exemplarily shown as a resistor 2041 and an inductor 2042 connected in series. It should be understood by those skilled in the art that the low-pass filter 204 may also be implemented in other forms.

[0046] Figure 3 FIG. 2 is a schematic diagram of another semiconductor processing device 30 according to some embodiments of the present application. The semiconductor processing device 30 has substantially the same structure as the semiconductor processing device 20 , except that the low-pass filter 304 in the semiconductor processing device 30 is disposed in the matching circuit 305 . Figure 3 The structures of the low-pass filter 304 and the matching circuit 305 are provided for exemplary purposes only. It should be understood that other circuit structures with similar functions do not depart from the spirit and scope of the present invention.

[0047] In some embodiments, the low-pass filter 304 may be an additional low-pass filter circuit in the matching circuit 305. Figure 3 As shown, the low-pass filter 304 may be a low-pass filter circuit added outside the matching network 3051 in the matching circuit 305, the matching network 3051 may include a network composed of capacitors 3052 and 3054 and an inductor 3053, and the low-pass filter circuit may include a resistor and an inductor connected in series. In other embodiments, the low-pass filter 304 may include a DC leakage channel in the matching circuit 305. For example, the matching network component in the matching circuit 305 may include a ceramic chip capacitor. By doping the ceramic chip capacitor with metal, a mA-level leakage current can be formed, thereby forming a DC leakage channel, providing a DC loop for electrostatic adsorption and desorption. The mA-level leakage current in the matching circuit 305 will not affect its RF application and process performance.

[0048] In some embodiments, a method of using the semiconductor processing equipment of the present application (for example, semiconductor processing equipment 10, 20 or 30) may include: placing a wafer on a wafer carrier plate; and applying voltage to a lower electrode through a DC power supply to cause the wafer to be adsorbed to the surface of the wafer carrier plate.

[0049] In some embodiments, the method may further include applying radio frequency power to the upper electrode through a radio frequency generator to generate plasma between the upper electrode and the wafer during the application of voltage to the lower electrode.

[0050] In some embodiments, the method may further include stopping applying the voltage to the lower electrode to desorb the wafer from the surface of the wafer carrier.

[0051] In some embodiments, the method may further include applying radio frequency power to the upper electrode through a radio frequency generator to generate plasma between the upper electrode and the wafer during the period when the voltage application to the lower electrode is stopped.

[0052] Compared with existing semiconductor processing equipment, the semiconductor processing equipment of the present application can form a stable DC current loop through a grounded low-pass filter, solving the technical problem that traditional semiconductor processing equipment cannot form a stable DC loop because the charge cannot be extracted from the ceramic side wall. It also enhances the stability of the DC loop in the process chamber, improves the electrostatic adsorption and desorption functions, and improves the stability and efficiency of the deposition process.

[0053] The description herein is provided to enable those skilled in the art to make or use the invention. Various modifications to the invention will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but is to be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor processing apparatus for performing plasma enhanced chemical vapor deposition on a wafer, comprising: A wafer carrier plate, wherein a lower electrode is disposed therein, the lower electrode is coupled to a DC power supply, a first filter is disposed between the DC power supply and the lower electrode, a DC current flows to the lower electrode through the first filter, and a radio frequency current flows to the ground through the first filter; an upper electrode, which is arranged opposite to the wafer carrier, the upper electrode is coupled to the radio frequency generator via a matching circuit, and is grounded via a second filter, the second filter includes a resistor and an inductor, a direct current flows to the ground through the second filter, and the second filter is a low-pass filter, which has a high impedance to the radio frequency current; as well as The RF generator applies a relatively large first-power RF to the upper electrode during the process in which the DC power supply applies a DC voltage to the lower electrode, so as to process the wafer adsorbed by the wafer carrier plate, and after the DC power supply stops applying the DC voltage to the lower electrode, the RF generator resumes or continues to apply a relatively small second-power RF to the upper electrode, so as to derive residual charges on the surface of the wafer carrier plate and / or the surface of the wafer. 2 . The semiconductor processing equipment according to claim 1 , wherein the resistance value of the resistor is fixed or adjustable.

3. The semiconductor processing equipment of claim 2, wherein the resistance value or resistance value range of the resistor is selected based on a leakage current requirement of the surface of the wafer carrier. 4 . The semiconductor processing equipment according to claim 1 , wherein the second filter is connected to a radio frequency feed conductor between the upper electrode and the matching circuit. The semiconductor processing equipment according to claim 1 , wherein the second filter is grounded through a shielding cover. The semiconductor processing equipment according to claim 1 , wherein the second filter is provided in the matching circuit.

7. The semiconductor processing equipment of claim 6, wherein the second filter comprises a DC leakage path in the matching circuit.

8. The semiconductor processing equipment of claim 7, wherein the second filter comprises a metal-doped ceramic chip capacitor in the matching circuit.

9. The semiconductor processing equipment according to claim 1, wherein the wafer carrier is made of an insulating material.

10. The semiconductor processing equipment of claim 1, wherein the wafer carrier body comprises a JR type electrostatic chuck.

11. A method of using a semiconductor processing apparatus according to any one of claims 1 to 10, comprising: Placing a wafer on a wafer carrier plate of the semiconductor processing equipment; Applying a DC voltage to the lower electrode of the wafer carrier body through the DC power supply of the semiconductor processing equipment, so that the wafer is adsorbed to the surface of the wafer carrier body, and applying a radio frequency with a relatively large first power to the upper electrode of the semiconductor processing equipment through the radio frequency generator, so as to process the wafer adsorbed by the wafer carrier body; as well as After the DC power supply stops applying the DC voltage to the lower electrode, the RF generator re-applies or continues to apply a second smaller RF power to the upper electrode to derive residual charges on the surface of the wafer carrier plate and / or the surface of the wafer.

Images