A method for fabricating a vertical GaN-based trench field-effect transistor

Abstract

The embodiment of the application discloses a preparation method of a vertical GaN-based trench field effect transistor, comprising: growing a hetero-epitaxial film on a double-side polished n-type high-doped self-supporting GaN substrate; etching the epitaxial film to form a vertical trench and a vertical mesa structure, and evaporating a metal film in the vertical trench to form a p-body layer electrode; preparing an Al2O3 film on the surface of the device outside the p-body layer electrode area as a gate electrode, evaporating a metal film on the surface of the Al2O3 film after acid pickling and passivation, annealing to form an ohmic contact electrode; evaporating S on the surface of the p-body layer electrode, depositing a passivation layer on the metal film of the ohmic contact electrode to isolate the mesa, and adopting a field plate termination method to eliminate the peak electric field gathered around the PN junction edge of the isolated mesa.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a method for fabricating a vertical GaN-based trench field-effect transistor. Background Technology

[0002] Gallium nitride (GaN) is an important third-generation semiconductor material. Due to its superior properties such as large bandgap, high breakdown electric field, high thermal conductivity, high electron saturation drift velocity, and strong radiation resistance, it has excellent application prospects and market potential in fields such as solid-state light sources, power electronics, and microwave radio frequency devices. AlGaN / GaN has a high two-dimensional electron gas concentration and a large electron saturation velocity, enabling it to operate under high current conditions. Simultaneously, the material itself possesses a high critical breakdown electric field, an order of magnitude higher than that of Si, allowing devices to withstand higher voltages within the same size. Furthermore, its large bandgap allows it to withstand higher operating temperatures.

[0003] Currently, wide-bandgap gallium nitride (GaN)-based power devices, possessing superior material properties such as high electron mobility, large breakdown field strength, and high thermal stability, are considered potential candidate materials for next-generation high-efficiency power electronics and compact power systems. Compared to high electron mobility transistors (HEMTs) and current aperture vertical electron transistors (CAVETs), GaN-based trench metal-oxide-semiconductor field-effect transistors (MOSFETs) are more competitive in achieving inherently always-off operation, exhibiting higher current density, lower on-resistance (Ron,sp), and lower current breakdown. The development of lateral GaN-based MOSFETs has roughly reached saturation, as the breakdown voltage (VBR) is limited by the length of the lateral drift region. While increasing the length can increase VBR, the increased device size leads to a decrease in effective current density per unit chip area. In contrast, vertical GaN-based devices are fully advanced under the same breakdown voltage and rated ampere number conditions. Compared to Si, sapphire, SiC, and diamond, MOSFETs on a standalone GaN substrate can significantly reduce the occurrence of high-density trapping states and mismatches caused by lattice nonlinearity during high-power operation.

[0004] In recent years, significant progress has been made in the research of VBR, Ron, sp, and device reliability of GaN vertical MOSFETs. To improve the VBR performance of enhancement-mode vertical GaN, a p-body is introduced into the N-GaN drift region, and a "p-body / N-drift" junction is formed through TCAD simulation. The threshold voltage (Vth) of the vertical GaN interlayer base trench MOSFET (OG-FET) is 2.5V, Ron and sp are 0.98mΩ·cm2, and VBR is 700V. A 10nm unintentionally doped GaN interlayer is used as the channel, and a 50nm in-situ Al2O3 is used as the gate dielectric. Vertical GaN trench MOSFETs with MBE-regenerated UID-GaN channels were studied, which avoids the need to reactivate the buried p-GaN and ensures the same channel mobility benefits as MOCVD regeneration. Using Silvaco ATLAS two-dimensional simulation technology, the device characteristics of vertical GaN trench MOSFETs were improved to achieve the best trade-off between VBR and Ron and sp. Polarization-induced doping was employed to form unintentionally doped AlGaN on p-GaN, with a thickness of approximately 100-300 nm and a concentration ranging from 0-7%. Subsequently, p-AlGaN was grown on UID AlGaN, also with a thickness of approximately 100-300 nm and a concentration ranging from 0-7%. Polarization-induced doping utilizes the difference in polarizability between AlN and GaN (AlN has greater polarizability than GaN), gradually altering the composition of AlGaN material, accumulating fixed polarization charges, and inducing the generation of three-dimensional holes / electrons, thus forming a three-dimensional hole / electron gas. Pi doping offers the following advantages: 1) immunity to hydrogen passivation; 2) higher breakdown voltage for buried p-type layers; and 3) complete activation of Mg acceptors unaffected by temperature. Normal off-state operation of vertical GaN-based trench-gate MOSFETs (GaNtg-MOSFETs) in high-power applications was demonstrated on a 4-inch freestanding GaN substrate. The transmission, output, and breakdown voltage characteristic curves obtained through TCAD simulation showed good agreement with experimental data.

[0005] Although existing products have made significant progress in reverse breakdown capability, the heat dissipation problem in the devices is still not adequately addressed. At the same time, the use of Mg doping in p-GaN doping results in a high activation energy, leading to poor device activation performance. Summary of the Invention

[0006] This invention provides a method for fabricating a vertical GaN-based trench field-effect transistor, comprising:

[0007] Heteroepitaxial films are grown on double-sided polished n-type highly doped self-supporting GaN substrates;

[0008] Etching is performed on the epitaxial thin film to form vertical trenches and vertical mesa structures, and metal films are deposited in the vertical trenches to form p-body electrode layers.

[0009] An Al2O3 thin film is prepared as a gate on the device surface outside the p-body layer electrode region in the vertical trench. After acid pickling and passivation, a metal thin film is deposited on the surface of the Al2O3 thin film and annealed to form an ohmic contact electrode.

[0010] S is deposited on the surface of the p-body electrode, and a passivation layer isolation mesa is deposited on the metal thin film of the ohmic contact electrode. The peak electric field accumulated at the edge of the PN junction around the isolation mesa is eliminated by field plate termination.

[0011] In one embodiment of the present invention, when S is deposited on the surface of the p-body electrode, the source electrode (Ti / Al, 15nm / 35nm) and the drain electrode (Al, 50nm) are annealed at 550°C for 5 minutes in an N2 atmosphere to form a good ohmic contact; wherein the gate and the p-body electrode are composed of Ti (10nm) / Au (40nm) and Pd, respectively.

[0012] Furthermore, a heteroepitaxial film is grown on a double-sided polished n-type highly doped self-supporting GaN substrate, including:

[0013] A lightly doped carrier concentration of approximately 5.0 × 10⁻⁵ μm was grown on an n-type GaN substrate with a thickness of 10–15 μm. 15 cm -3 ~9.0×10 15 cm -3 n-type lightly Si-doped n-type GaN is used as a drift layer;

[0014] p-type AlGaN with a thickness of 200-300 nm is grown on an n-type GaN substrate and heavily doped. The Al content of the buried p-type AlGaN has a linear gradient from 7% to 0%, which is stored as a channel region.

[0015] A heavily doped n+ GaN layer with a thickness of 0.1–0.3 μm is grown on p-type AlGaN as the source contact layer, wherein the doping density is 2 × 10⁻⁶. 18 cm -3 Up to 5×10 18 cm -3 .

[0016] Further, etching is performed on the epitaxial film, including ion etching of the epitaxial film using a Cl2 flow rate of 15-50 sccm and a power of 50-100 W.

[0017] Further, etching is performed on the epitaxial film, including: etching the epitaxial film using inductively coupled plasma with a Cl2 flow rate of 40-60 sccm and a power of 10-30 W.

[0018] Furthermore, the width of the vertical groove is 0.1–0.3 μm.

[0019] Furthermore, the height of the vertical platform is 1.5–2 μm.

[0020] Furthermore, during the fabrication of the gate, an alloy with a Ni / Au metal structure is evaporated using an electron beam evaporation process.

[0021] Furthermore, the passivation isolation platform is a SiO2 thin film or a SiN4 thin film.

[0022] Furthermore, the thickness of the passivation isolation platform is 200–600 nm.

[0023] Furthermore, the gate and p-body layer electrodes are Ti / Au and Pd, respectively.

[0024] The beneficial effects of this invention are: by using polarization-induced doping to grow p+AlGaN to replace p+GaN as the p-body layer in a TG-MOS device with a stepped-doped channel structure, without the influence of H ions from Mg doping, the on-resistance of the device can be effectively reduced, the electric field at the edge of the pn junction around the isolation mesa can be effectively reduced, and the device can achieve higher breakdown characteristics and good thermal conductivity. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A planar view of a GaN-based device with vertical mesas and vertical trenches obtained by etching the epitaxial growth layer of a TG-MOS device using ICP, provided for an embodiment of the present invention.

[0027] Figure 2 A planar view of a GaN-based device with a gate and an ALD-deposited gate dielectric provided for an embodiment of the present invention.

[0028] Figure 3 A plan view of a GaN-based device having a source, drain, gate, and passivation layer provided for an embodiment of the present invention.

[0029] Figure 4This is a planar view of a TG-MOS device structure with a collectively doped channel after polarization-induced doping substitution of p+-GaN, provided in an embodiment of the present invention.

[0030] Figure 5 The electrical performance test diagram provided in the embodiment of the present invention.

[0031] Figure 6 The electron distribution performance test diagram provided for an embodiment of the present invention. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0033] like Figures 1-4 This is a schematic diagram of the process flow of an embodiment of the present invention, specifically including the following steps:

[0034] Step 1: Grow n-GaN / p-AlGaN / n+GaN on a double-sided polished n-type highly doped self-supporting GaN substrate, i.e., grow heteroepitaxial films using chemical vapor deposition (MOCVD).

[0035] Specifically:

[0036] 1) Prepare a dislocation density of 1×10 6 -2×10 6 cm -2 Commercially available n+- type GaN substrates within the range.

[0037] 2) A 12 μm lightly doped carrier mass is grown on an n-type +-GaN substrate using metal-organic chemical vapor deposition (MOCVD), with an optimal carrier concentration of 8.0 × 10⁻⁶. 15 cm -3 n-type lightly Si-doped n-GaN is used as the drift layer.

[0038] 3) P+-AlGaN, preferably 250 nm thick, heavily doped, is grown on an n-GaN substrate using metal-organic chemical vapor deposition (MOCVD). The Al content of the buried p-type AlGaN layer follows a linear gradient from 7% to 0%, storing the channel region. Based on this, a 0.2 μm thick heavily doped n+GaN layer is preferably grown as the source contact layer, with a preferred doping density of 3 × 10⁻⁶. 18 cm -3 .

[0039] Step 2, mesa formation and channel etching: Inductively coupled plasma etching (ICP) is performed using Cl2 at a flow rate of 50 sccm and a power of 20 W to form vertical trenches with a preferred width of 0.2 μm and vertical mesa structures with a preferred height of 1.7 μm.

[0040] Step 3: Prepare a 16 nm thick Al2O3 thin film as the gate dielectric using atomic layer deposition (ALD). First, perform a simple acid wash on the epitaxial wafer, then passivate it with (NH4)2S, and finally deposit the thin film in an ALD vacuum deposition apparatus.

[0041] Step 4: Anneal the source and drain electrodes at 550°C for 5 minutes in an N2 atmosphere to form good ohmic contact electrodes.

[0042] Step 5: Deposit a 200-1000 nm thick SiO2 film, preferably 400 nm thick, as a passivation isolation platform using plasma-enhanced chemical vapor deposition (PECVD).

[0043] Step 6: Eliminate the peak electric field accumulated at the edge of the PN junction around the isolation platform by using the field plate termination method, and connect the aluminum-based field plate to the source electrode.

[0044] like Figure 5 As shown, the performance test results of the fabricated device are as follows:

[0045] 1. Transmission IV characteristics (ID-VG) at VDS = 0.5V

[0046] 2. Output IV characteristics (ID-VD) at VGS = 0V, 5V, 10V, 15V and 20V

[0047] 3. Measure the off-state IV characteristics of the GaN TG-MOSFET at VG = 0V.

[0048] Conclusion: Low-density interface states are beneficial for reducing Ron, sp, and switching losses. The interface states in the simulation are defined as 10¹¹ cm⁻² eV⁻¹. GaN TG-MOSFETs were tested experimentally (Exp) and simulated (Sim), as shown below. Figure 5 As shown. Among them, Figure 5 (a) shows the ID-VG features at VDS = 0.5V, and the Vth value was determined from the measured ID-VG features using several extraction methods. Figure 5 (b) The output IV characteristics are shown for VGS = 0V, 5V, 10V, 15V and 20V respectively. The Ron,sp value in the linear region is 1.93mΩ·cm2 when VDS = 0.5V and VGS = 20V. Figure 5(c) shows the I-V characteristics in the off state measured at VGS = 0V. The corresponding obtained figure of merit (FOM) values are 0.88 GW / cm2 and 1.68 GW / cm2, obtained through experiment and simulation respectively.

[0049] As Figure 6 shown, the performance test of the fabricated device gives the following test results:

[0050] 1. Electron concentration distribution at VGS = 0V, VDS = 0.5V

[0051] 2. Energy band at VGS = 20V, VDS = 0.5V (on-state)

[0052] 3. Distributions in the off state and (d) on state

[0053] Conclusion: First, under normal conditions, Vth (IDS = 1 μA / mm) is 3.15V. Therefore, there is no electron distribution in the p-GaN channel region when VGS < Vth, as Figure 6 (a) shown.

[0054] Second, current cannot conduct between the source and drain because the channel has not formed a conduction path yet. In Figure 6 (b), only when VGS > Vth, thus generating drain-source current. Electrons can easily jump to the CB and generate conduction current. As Figure 6 (b) shows the output I-V characteristics at VGS = 0V, 5V, 10V, 15V, and 20V respectively. At VDS = 0.5V and VGS = 20V, the Ron,sp value in the linear region is 1.93 mΩ·cm2.

[0055] Third, the energy band distributions along line A and line B in the off and on states are respectively as Figure 6 (c) and Figure 6 (d) shown. From the off state to the on state, the conduction band energy decreases significantly until it approaches the quasi-Fermi level (QFL).

[0056] This invention utilizes PI doping to improve the fabrication method of buried p-body layer (i.e., p-GaN) on large-size independent GaN wafers to fabricate a vertical trench gate MOS transistor. This significantly reduces the difficulty of device activation caused by the high activation energy of Mg-H, while enhancing the reverse breakdown voltage. It achieves complete activation unaffected by temperature, exhibiting good temperature stability. In the stepped-doped channel structure TG-MOS device, polarization-induced doping is used to grow p+AlGaN using MOCVD to replace p+GaN as the p-body layer. Without the influence of H ions from Mg doping, the on-resistance of the device is effectively reduced, and the electric field at the edge of the pn junction around the isolation mesa is effectively lowered, resulting in higher breakdown characteristics and good thermal conductivity.

[0057] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a vertical GaN-based trench field effect transistor, comprising the steps of: The method comprises the following steps: ​ Growth of hetero-epitaxial film on double-side polished n-type high-doped self-supporting GaN substrate; Etching on the epitaxial film to form vertical trench and vertical mesa structure, and evaporating metal film in the vertical trench to form p-body layer electrode; Preparation of Al2O3 film as gate dielectric on the device surface except the p-body layer electrode area in the vertical trench, evaporation of metal film on the surface of Al2O3 film after acid pickling and passivation, annealing to form ohmic contact electrode; Evaporation of source level on the surface of p-body layer electrode, deposition of passivation layer to isolate mesa on the metal film of ohmic contact electrode, and elimination of peak electric field gathered around the PN junction edge of isolated mesa by field plate termination method; Growth of hetero-epitaxial film on double-side polished n-type high-doped self-supporting GaN substrate, comprising: n-type lightly Si-doped n-type GaN with a thickness of 10-15 μm and a lightly doped carrier concentration of 5.0 x 10 15 cm -3 ~9.0 x 10 15 cm -3 as a drift layer is grown on an n-type GaN substrate Growth of p-type AlGaN with thickness of 200-300 nm and heavy doping on n-type GaN drift layer, wherein the Al content of the buried layer p-type AlGaN is linearly graded from 7% to 0%, and the channel region is stored; A heavily doped n+ type GaN with a thickness of 0.1-0.3 μm is grown on a p type AlGaN as a source level contact layer, wherein the doping density is 2×10 18 cm -3 -5×10 18 cm -3 .

2. The production method according to claim 1, characterized by, Etching on the epitaxial film, comprising: ion etching on the epitaxial film by using Cl2 flow of 15-50 sccm and power of 50-100 W.

3. The production method according to claim 1, characterized by, Etching on the epitaxial film, comprising: inductively coupled plasma etching on the epitaxial film by using Cl2 flow of 40-60 sccm and power of 10-30 W.

4. The production method according to claim 1, characterized by, The width of the vertical trench is 0.1-0.3 μm.

5. The preparation method according to claim 1, characterized in that, The height of the vertical mesa is 1.5-2 μm.

6. The method of claim 1, wherein, In the preparation of the gate, the metal structure is evaporated by electron beam evaporation process to form an alloy of Ni / Au.

7. The preparation method according to claim 1, characterized in that, The passivation isolation mesa is SiO2 film or SiN4 film.

8. The production method according to claim 1 or 7, characterized by, The thickness of the passivation isolation mesa is 200-600 nm.

9. The method of claim 1, wherein, The gate and the p-body layer electrode are Ti / Au and Pd, respectively.

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