Chip packaging structure and manufacturing method thereof

Abstract

The present invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure includes a chip, a stress buffer layer, a first insulating layer, a reconfiguration circuit layer, a second insulating layer and a solder ball. The chip has an active surface, a back surface and a surrounding surface. The stress buffer layer covers the active surface and the surrounding surface, and the first insulating layer is arranged on the back surface of the chip. The bottom surface of the stress buffer layer is flush with the back surface of the chip. The reconfiguration circuit layer is electrically connected to the chip through the opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the reconfiguration circuit layer. The solder ball is arranged in a blind hole in the second insulating layer and is electrically connected to the reconfiguration circuit layer. The top surface of the solder ball protrudes from the upper surface of the second insulating layer. The chip packaging structure of the present invention can effectively protect the edge of the chip and increase the overall structural strength and structural reliability.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] Existing technologies utilize elastic materials, encapsulation materials, or overhanging structures beneath the die as anchors to protect the die edge or enhance the mechanical strength of the encapsulant. Currently, in some products, these elastic materials or encapsulation materials only protect the die back and spherical surface, failing to effectively protect the die edge. Alternatively, in other products, encapsulation materials are used to protect the die edge. While this can prevent chip cracking and failure during reliability testing, the difference in thermal expansion coefficients between the encapsulant and the die shortens reliability testing times and the product's lifespan. Summary of the Invention

[0003] The present invention is directed to a chip packaging structure, which can effectively protect the edge of the chip and increase the overall structural strength and structural reliability.

[0004] The present invention is also directed to a method for manufacturing a chip packaging structure, which is used to manufacture the above-mentioned chip packaging structure.

[0005] According to an embodiment of the present invention, a chip packaging structure includes a chip, a stress buffer layer, a first insulating layer, a reconfiguration circuit layer, a second insulating layer and solder balls. The chip has an active surface and a back surface opposite to each other and a surrounding surface connecting the active surface and the back surface. The stress buffer layer covers the active surface and the surrounding surface of the chip and has an opening exposing part of the active surface of the chip. The first insulating layer is arranged on the back surface of the chip. The stress buffer layer is extended and arranged on the first insulating layer, and the bottom surface of the stress buffer layer is flush with the back surface of the chip. The reconfiguration circuit layer is arranged on the active surface of the chip and extends into the opening of the stress buffer layer. The reconfiguration circuit layer is electrically connected to the chip through the opening. The second insulating layer covers the stress buffer layer and the reconfiguration circuit layer and has a blind hole exposing part of the reconfiguration circuit layer. The solder ball is arranged in the blind hole of the second insulating layer and is electrically connected to the reconfiguration circuit layer. The top surface of the solder ball protrudes from the upper surface of the second insulating layer.

[0006] In the chip packaging structure according to an embodiment of the present invention, the reconfigured circuit layer includes a circuit layer and conductive vias. The conductive vias are located between the circuit layer and the active surface of the chip. The chip is electrically connected to the circuit layer through the conductive vias.

[0007] In the chip package structure according to an embodiment of the present invention, the first insulating layer has a first peripheral surface, the second insulating layer has a second peripheral surface, and the stress buffer layer has a third peripheral surface. The second peripheral surface is aligned with the third peripheral surface and the first peripheral surface.

[0008] In the chip packaging structure according to an embodiment of the present invention, the chip packaging structure further includes a surface treatment layer disposed on the reconfiguration circuit layer exposed by the blind vias in the second insulating layer. The solder balls are electrically connected to the reconfiguration circuit layer through the surface treatment layer.

[0009] In the chip packaging structure according to the embodiment of the present invention, the thickness of the stress buffer layer is greater than 0 and less than or equal to 1 micron.

[0010] In the chip package structure according to the embodiment of the present invention, the material of the stress buffer layer is different from the material of the first insulating layer and the material of the second insulating layer.

[0011] In the chip package structure according to an embodiment of the present invention, the material of the stress buffer layer includes, but is not limited to, silane adhesion promoter, silicone rubber, epoxy, or photosensitive dielectric material (such as PI, PBO, BCB, or PID).

[0012] In the chip package structure according to an embodiment of the present invention, the first insulating layer includes an Ajinomoto Build Up Film (ABF) or an encapsulation adhesive layer.

[0013] In the chip packaging structure according to the embodiment of the present invention, the material of the first insulating layer is the same as that of the second insulating layer.

[0014] In the chip package structure according to the embodiment of the present invention, the material of the first insulating layer is different from the material of the second insulating layer.

[0015] According to an embodiment of the present invention, a method for manufacturing a chip packaging structure includes the following steps. A plurality of chips separated from each other are arranged on a first insulating layer. Each chip has an active surface and a back surface facing each other and a surrounding surface connecting the active surface and the back surface. The back surface of each chip directly contacts the first insulating layer. A stress buffer layer is formed on the first insulating layer. The stress buffer layer extends to cover the active surface and the surrounding surface of each chip, and the bottom surface of the stress buffer layer is flush with the back surface of the chip. A second insulating layer is formed to cover the stress buffer layer. A reconfiguration circuit layer is formed in the second insulating layer. The stress buffer layer has an opening that exposes a portion of the active surface of the chip, and the reconfiguration circuit layer is electrically connected to the chip through the opening. A plurality of blind holes separated from each other are formed in the second insulating layer, wherein the blind holes expose a portion of the reconfiguration circuit layer. A plurality of solder balls are formed in the blind holes, respectively, wherein the solder balls are electrically connected to the reconfiguration circuit layer exposed by the blind holes. The top surface of each solder ball protrudes from the upper surface of the second insulating layer. A singulation process is performed to cut the second insulating layer, the stress buffer layer and the first insulating layer to form a plurality of chip packaging structures separated from each other.

[0016] In the method for manufacturing a chip packaging structure according to an embodiment of the present invention, the reconfigured circuit layer includes a circuit layer and conductive vias. The conductive vias are located between the circuit layer and the active surface of the chip. The chip is electrically connected to the circuit layer through the conductive vias.

[0017] In a method for fabricating a chip package structure according to an embodiment of the present invention, the first insulating layer of each chip package structure has a first peripheral surface, the second insulating layer has a second peripheral surface, and the stress buffer layer has a third peripheral surface. The second peripheral surface is flush with the third peripheral surface and the first peripheral surface.

[0018] In a method for manufacturing a chip package structure according to an embodiment of the present invention, the method further includes forming a surface treatment layer in the blind vias before forming solder balls in the blind vias. The surface treatment layer is disposed on the reconfigured circuit layer exposed by the blind vias, and the solder balls are electrically connected to the reconfigured circuit layer through the surface treatment layer.

[0019] In the method for manufacturing a chip packaging structure according to an embodiment of the present invention, the thickness of the stress buffer layer is greater than 0 and less than or equal to 1 micron.

[0020] In the manufacturing method of the chip package structure according to the embodiment of the present invention, the material of the stress buffer layer is different from the material of the first insulating layer and the material of the second insulating layer.

[0021] In the method for manufacturing a chip package structure according to an embodiment of the present invention, the material of the stress buffer layer includes, but is not limited to, a silane adhesion promoter polymer, silicone rubber, epoxy resin, or a photosensitive dielectric material (such as PI, PBO, BCB, or PID).

[0022] In the method for manufacturing a chip package structure according to an embodiment of the present invention, the first insulating layer comprises an Ajinomoto build-up film or an encapsulation adhesive layer.

[0023] In the method for manufacturing a chip package structure according to an embodiment of the present invention, the material of the first insulating layer is the same as that of the second insulating layer.

[0024] In the method for manufacturing a chip package structure according to an embodiment of the present invention, the material of the first insulating layer is different from the material of the second insulating layer.

[0025] In a method for manufacturing a chip package structure according to an embodiment of the present invention, the method further includes providing a carrier and a release film on the carrier before placing the separated chips on the first insulating layer. The release film is positioned between the first insulating layer and the carrier. After the singulation process, the release film and carrier are removed to expose the lower surface of the first insulating layer.

[0026] Based on the above, in the chip package structure of the present invention, the stress buffer layer covers the active surface and surrounding surfaces of the chip, while the first insulating layer covers the back surface of the chip. In other words, the chip is directly enclosed between the stress buffer layer and the first insulating layer. Thus, the stress buffer layer protects the chip's edges, while the first and second insulating layers enhance the overall structural strength of the chip package. Consequently, the chip package structure of the present invention can achieve superior structural reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1A to 1G is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present invention;

[0028] Figure 1H FIG. 1 is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present invention.

[0029] Description of Reference Numerals

[0030] 10: carrier board;

[0031] 20: release film;

[0032] 100: chip packaging structure;

[0033] 110: chip;

[0034] 112: active side;

[0035] 114: back;

[0036] 116: surrounding surface;

[0037] 120: stress buffer layer;

[0038] 121: Opening;

[0039] 124: Bottom;

[0040] 132: first insulating layer;

[0041] 133: lower surface;

[0042] 134: second insulating layer;

[0043] 135: upper surface;

[0044] 140: reconfigure the circuit layer;

[0045] 142: circuit layer;

[0046] 144: conductive through hole;

[0047] 150: surface treatment layer;

[0048] 160: solder ball;

[0049] 162: top surface;

[0050] B: blind hole;

[0051] S1: first peripheral surface;

[0052] S2: second peripheral surface;

[0053] S3: third peripheral surface;

[0054] T: thickness. DETAILED DESCRIPTION

[0055] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0056] Figures 1A to 1G It is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present invention. Figure 1H FIG. 1 is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present invention.

[0057] Regarding the manufacturing method of the chip packaging structure of this embodiment, first, please refer to Figure 1A , providing a carrier board 10 and a release film 20 located on the carrier board 10. The release film 20 completely covers the surface of the carrier board 10, wherein the release film 20 is, for example, a thermal release film, but not limited thereto.

[0058] Next, please refer to Figure 1A A first insulating layer 132 is formed on the release film 20, wherein the first insulating layer 132 completely covers the surface of the release film 20, and the release film 20 is sandwiched between the first insulating layer 132 and the carrier 10. Here, the first insulating layer is, for example, an Ajinomoto build-up film (ABF) or an encapsulation adhesive layer, but is not limited thereto.

[0059] Next, please refer to Figure 1B A plurality of separated chips 110 are disposed on a first insulating layer 132. Each chip 110 has an active surface 112 and a back surface 114 facing each other, and a peripheral surface 116 connecting the active surface 112 and the back surface 114. Here, the back surface 114 of each chip 110 directly contacts the first insulating layer 132.

[0060] Next, please refer to Figure 1C A stress buffer layer 120 is formed on the first insulating layer 132. The stress buffer layer 120 extends to cover the active surface 112 and the surrounding surface 116 of each chip 110, and the bottom surface 124 of the stress buffer layer 120 is flush with the back surface 114 of the chip 110. In other words, the chip 110 of this embodiment is directly encapsulated between the stress buffer layer 120 and the first insulating layer 132.

[0061] Here, the thickness T of the stress buffer layer 120 is, for example, greater than 0 and less than or equal to 1 micron. The stress buffer layer 120 is formed by, for example, evaporation or immersion, but is not limited thereto. Furthermore, in this embodiment, the material of the stress buffer layer 120 is different from the material of the first insulating layer 132. Preferably, the material of the stress buffer layer 120 is, for example, a silane adhesion promoter, silicone rubber, epoxy resin, or a photosensitive dielectric material (such as PI, PBO, BCB, or PID), but is not limited thereto.

[0062] Next, please refer to Figure 1D, a second insulating layer 134 is formed to cover the stress buffer layer 120. Here, the material of the second insulating layer 134 may be the same as the material of the first insulating layer 132, that is, the material of the second insulating layer 134 is Ajinomoto build-up film (ABF) or an encapsulation glue layer. In another embodiment, the material of the second insulating layer 134 may be different from the material of the first insulating layer 132. In other words, the material of the stress buffer layer 120 of this embodiment is different from the material of the first insulating layer 132 and the material of the second insulating layer 134. Preferably, the thickness of the second insulating layer 134 is greater than the thickness of the first insulating layer 132, wherein the thickness of the second insulating layer 134 is at least 150 microns.

[0063] Next, please refer to Figure 1E , forming a reconfiguration circuit layer 140 within the second insulating layer 134. The stress buffer layer 120 has an opening 121 that exposes a portion of the active surface 112 of the chip 110, and the reconfiguration circuit layer 140 is electrically connected to the chip 110 through the opening 121. Here, the reconfiguration circuit layer 140 includes a circuit layer 142 and conductive vias 144, wherein the circuit layer 142 is embodied as a patterned circuit layer. The conductive vias 144 are located between the circuit layer 142 and the active surface 112 of the chip 110, wherein the chip 110 is electrically connected to the circuit layer 142 through the conductive vias 144.

[0064] Next, please refer to Figure 1E , forming a plurality of blind holes B separated from each other in the second insulating layer 134, wherein the blind holes B expose a portion of the reconfiguration circuit layer 140. Figure 1E As shown, a portion of the circuit layer 142 of the reconfigured circuit layer 140 is exposed by the blind hole B. Next, a surface treatment layer 150 is formed in the blind hole B, wherein the surface treatment layer 150 is disposed on the reconfigured circuit layer 140 exposed by the blind hole B. In other words, the surface treatment layer 150 is disposed on the circuit layer 142 exposed by the blind hole B. Here, the surface treatment layer 150 is, for example, nickel electroplated palladium immersion gold (ENEPIG), an organic solderability preservatives (OSP) layer, or electroless nickel immersion gold (ENIG), but is not limited thereto.

[0065] Next, please refer to Figure 1F A plurality of solder balls 160 are formed in the blind vias B, wherein the solder balls 160 are electrically connected to the reconfigured circuit layer 140 exposed by the blind vias B. More specifically, the solder balls 160 are electrically connected to the reconfigured circuit layer 140 through the surface treatment layer 150. Here, the top surface 162 of each solder ball 160 protrudes from the upper surface 135 of the second insulating layer 134 for electrical connection to an external circuit.

[0066] Afterwards, please also refer to Figure 1F and Figure 1G A singulation process is then performed to cut the second insulating layer 134, the stress buffer layer 120, and the first insulating layer 132, thereby forming a plurality of separated chip package structures 100. The release film 20 and the carrier 10 are then removed, exposing the lower surface 133 of the first insulating layer 132. At this point, the chip package structure 100 is completed.

[0067] In short, this embodiment utilizes wafer-level packaging technology. After placing the chip 110 on the carrier 10, the stress buffer layer 120 is first coated, and then the reconfiguration circuit layer 140 and the surface treatment layer 150 are produced and the ball planting process is performed. Finally, cutting and board removal are performed to complete the chip packaging structure 100 of this embodiment.

[0068] In terms of structure, please refer to Figure 1H The chip package structure 100 includes a chip 110, a stress buffer layer 120, a first insulating layer 132, a reconfiguration circuit layer 140, a second insulating layer 134, and solder balls 160. The chip 110 has an active surface 112 and a back surface 114 facing each other, and a peripheral surface 116 connecting the active surface 112 and the back surface 114. The stress buffer layer 120 covers the active surface 112 and the peripheral surface 116 of the chip 110 and has an opening 121 that exposes a portion of the active surface 112 of the chip 110. Here, the thickness T of the stress buffer layer 120 is, for example, greater than 0 and less than or equal to 1 micron. Preferably, the material of the stress buffer layer 120 is, for example, a silane adhesion promoter polymer, silicone rubber, epoxy resin, or a photosensitive dielectric material (such as PI, PBO, BCB, or PID), but is not limited thereto.

[0069] Furthermore, the first insulating layer 132 of this embodiment is configured on the back side 114 of the chip 110. The stress buffer layer 120 is extended and configured on the first insulating layer 132, and the bottom surface 124 of the stress buffer layer 120 is flush with the back side 114 of the chip 110. The reconfiguration circuit layer 140 is configured on the active surface 112 of the chip 110 and extends into the opening 121 of the stress buffer layer 120, wherein the reconfiguration circuit layer 140 is electrically connected to the chip 110 through the opening 121. Furthermore, the reconfiguration circuit layer 140 includes a circuit layer 142 and a conductive through-hole 144. The conductive through-hole 144 is located between the circuit layer 142 and the active surface 112 of the chip 110, and the chip 110 is electrically connected to the circuit layer 142 through the conductive through-hole 144. The second insulating layer 134 covers the stress buffer layer 120 and the reconfiguration circuit layer 140, and has a blind hole B exposing a portion of the reconfiguration circuit layer 140.

[0070] More specifically, the first insulating layer 132 has a first peripheral surface S1, the second insulating layer 134 has a second peripheral surface S2, and the stress buffer layer 120 has a third peripheral surface S3. Preferably, the second peripheral surface S2 is flush with the third peripheral surface S3 and the first peripheral surface S1. The material of the first insulating layer 132 and the second insulating layer 134 can be the same or different. For example, the first insulating layer 132 can be an Ajinomoto build-up film (ABF) or an encapsulant layer. The material of the stress buffer layer 120 is different from the material of the first insulating layer 132 and the material of the second insulating layer 134.

[0071] In addition, the solder ball 160 of the present embodiment is disposed in the blind hole B of the second insulating layer 134 and is electrically connected to the reconfiguration circuit layer 140, wherein the top surface 162 of the solder ball 160 protrudes from the upper surface 135 of the second insulating layer 134 for electrical connection to an external circuit. In addition, the chip packaging structure 100 of the present embodiment further includes a surface treatment layer 150, which is disposed on the reconfiguration circuit layer 140 exposed by the blind hole B of the second insulating layer 134. The solder ball 160 is electrically connected to the reconfiguration circuit layer 140 through the surface treatment layer 150. The surface treatment layer 150 is, for example, nickel electroplated palladium immersion gold (ENEPIG), an organic solderability preservatives (OSP) layer, or electroless nickel immersion gold (ENIG), but is not limited thereto.

[0072] In short, the chip 110 of this embodiment is directly encapsulated between the stress buffer layer 120 and the first insulating layer 132. Thus, the stress buffer layer 120 protects the chip's edges, while the first insulating layer 132 and the second insulating layer 134 enhance the structural strength of the overall chip package structure 100. Therefore, the chip package structure 100 of this embodiment has improved structural reliability.

[0073] In summary, in the chip package structure of the present invention, the stress buffer layer covers the active surface and surrounding surfaces of the chip, while the first insulating layer covers the back surface of the chip. In other words, the chip is directly enclosed between the stress buffer layer and the first insulating layer. Thus, the stress buffer layer protects the chip's edges, while the first and second insulating layers enhance the overall structural strength of the chip package. Consequently, the chip package structure of the present invention exhibits superior structural reliability.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A chip having an active surface and a back surface facing each other and a peripheral surface connecting the active surface and the back surface; a stress buffer layer, covering the active surface of the chip and the surrounding surface, and having an opening exposing a portion of the active surface of the chip; a first insulating layer disposed on the back surface of the chip, wherein the stress buffer layer is extended and disposed on the first insulating layer, and a bottom surface of the stress buffer layer is flush with the back surface of the chip; a reconfiguration circuit layer, configured on the active surface of the chip and extending into the opening of the stress buffer layer, wherein the reconfiguration circuit layer is electrically connected to the chip through the opening; a second insulating layer, covering the stress buffer layer and the reconfiguration circuit layer on the peripheral surface of the chip, and having a blind hole exposing a portion of the reconfiguration circuit layer; as well as A solder ball is disposed in the blind hole of the second insulating layer and electrically connected to the reconfiguration circuit layer, wherein a top surface of the solder ball protrudes from an upper surface of the second insulating layer.

2. The chip packaging structure according to claim 1, wherein: The reconfiguration circuit layer includes a circuit layer and conductive vias. The conductive vias are located between the circuit layer and the active surface of the chip. The chip is electrically connected to the circuit layer through the conductive vias.

3. The chip packaging structure according to claim 1, wherein: The first insulating layer has a first peripheral surface, the second insulating layer has a second peripheral surface, and the stress buffer layer has a third peripheral surface. The second peripheral surface is flush with the third peripheral surface and the first peripheral surface.

4. The chip packaging structure according to claim 1, wherein: Also includes: A surface treatment layer is disposed on the reconfiguration circuit layer exposed by the blind hole in the second insulating layer, wherein the solder ball is electrically connected to the reconfiguration circuit layer through the surface treatment layer.

5. The chip packaging structure according to claim 1, wherein: The thickness of the stress buffer layer is greater than 0 and less than or equal to 1 micron.

6. The chip packaging structure according to claim 1, wherein: The material of the stress buffer layer is different from the material of the first insulating layer and the material of the second insulating layer.

7. The chip packaging structure according to claim 6, wherein: The material of the stress buffer layer includes silane coupling agent polymer, silicone rubber, epoxy resin or photosensitive dielectric material.

8. The chip packaging structure according to claim 1, wherein: The first insulating layer includes an Ajinomoto build-up film or an encapsulating adhesive layer.

9. The chip packaging structure according to claim 8, wherein: The material of the first insulating layer is the same as that of the second insulating layer.

10. The chip packaging structure according to claim 8, wherein: The material of the first insulating layer is different from the material of the second insulating layer.

11. A method for manufacturing a chip packaging structure, characterized in that: include: Disposing a plurality of chips separated from each other on a first insulating layer, wherein each of the plurality of chips has an active surface and a back surface facing each other and a peripheral surface connecting the active surface and the back surface, and the back surface of each of the plurality of chips directly contacts the first insulating layer; forming a stress buffer layer on the first insulating layer, wherein the stress buffer layer extends to cover the active surface and the surrounding surface of each of the plurality of chips, and a bottom surface of the stress buffer layer is flush with the back surface of the chip; forming a second insulating layer to cover the stress buffer layer on the peripheral surface of the chip; forming a reconfiguration circuit layer in the second insulating layer, wherein the stress buffer layer has an opening exposing a portion of the active surface of the chip, and the reconfiguration circuit layer is electrically connected to the chip through the opening; forming a plurality of blind vias separated from each other in the second insulating layer, wherein the plurality of blind vias expose a portion of the reconfiguration circuit layer; forming a plurality of solder balls in the plurality of blind vias, wherein the plurality of solder balls are electrically connected to the reconfiguration circuit layer exposed by the plurality of blind vias, and a top surface of each of the plurality of solder balls protrudes from an upper surface of the second insulating layer; as well as A singulation process is performed to cut the second insulating layer, the stress buffer layer and the first insulating layer to form a plurality of chip packaging structures separated from each other.

12. The method for manufacturing a chip packaging structure according to claim 11, wherein: The reconfiguration circuit layer includes a circuit layer and conductive vias. The conductive vias are located between the circuit layer and the active surface of the chip. The chip is electrically connected to the circuit layer through the conductive vias.

13. The method for manufacturing a chip packaging structure according to claim 11, wherein: The first insulating layer of each of the plurality of chip packaging structures has a first peripheral surface, the second insulating layer has a second peripheral surface, the stress buffer layer has a third peripheral surface, and the second peripheral surface is flush with the third peripheral surface and the first peripheral surface.

14. The method for manufacturing a chip packaging structure according to claim 11, wherein: Also includes: Before forming the multiple solder balls in the multiple blind holes respectively, a surface treatment layer is formed in the multiple blind holes. The surface treatment layer is configured on the reconfiguration circuit layer exposed by the multiple blind holes, and the multiple solder balls are electrically connected to the reconfiguration circuit layer through the surface treatment layer.

15. The method for manufacturing a chip packaging structure according to claim 11, wherein: The thickness of the stress buffer layer is greater than 0 and less than or equal to 1 micron.

16. The method for manufacturing a chip packaging structure according to claim 11, wherein: The material of the stress buffer layer is different from the material of the first insulating layer and the material of the second insulating layer.

17. The method for manufacturing a chip packaging structure according to claim 16, wherein: The material of the stress buffer layer includes silane coupling agent polymer, silicone rubber, epoxy resin or photosensitive dielectric material.

18. The method for manufacturing a chip packaging structure according to claim 11, wherein: The first insulating layer includes an Ajinomoto build-up film or an encapsulating adhesive layer.

19. The method for manufacturing a chip packaging structure according to claim 18, wherein: The material of the first insulating layer is the same as that of the second insulating layer.

20. The method for manufacturing a chip packaging structure according to claim 18, wherein: The material of the first insulating layer is different from the material of the second insulating layer.

21. The method for manufacturing a chip packaging structure according to claim 11, wherein: Also includes: Before disposing the plurality of chips separated from each other on the first insulating layer, providing a carrier and a release film on the carrier, wherein the release film is located between the first insulating layer and the carrier; as well as After the singulation process is performed, the release film and the carrier are removed to expose the lower surface of the first insulating layer.

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