Array substrate and display panel

Abstract

The embodiments of the present application disclose an array substrate and a display panel, wherein the array substrate includes a plurality of data lines, an active layer arranged in a different layer from the data lines, a gate arranged in a different layer from the data lines and the active layer, a source electrode connected to the data lines, and a drain electrode arranged with an interval between the data lines and the source electrode; the active layer includes a first connecting segment, a second connecting segment, and a third connecting segment connected in sequence, the first connecting segment contacts the source electrode, the first connecting segment overlaps with the data line, the third connecting segment is located between two adjacent data lines, and the second connecting segment partially overlaps with the data line; the gate electrode overlaps with the active layer; the drain electrode overlaps with the portion of the active layer exposed between the two adjacent data lines, and the drain electrode contacts the portion of the active layer exposed between the two adjacent data lines, which can reduce the contact resistance between the drain electrode and the active layer and improve the response speed of the thin film transistor.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] With the development of science and technology, the concept of the metaverse has entered people's horizons. The metaverse is a virtual world connected and created through technological means, mirroring and interacting with the real world, and it represents a digital living space with a new social system. Due to the continued popularity of the metaverse, it has attracted strong attention from investors and the market. As the direction of the next generation of the internet, it has attracted a lot of attention from various parties in the development of software and hardware. Micro-displays are the foundation for hardware interaction in virtual reality (VR) and augmented reality (AR) devices, and are also one of the core technologies for entering the "metaverse."

[0003] The micro-display screen determines the resolution and susceptibility of VR devices to motion sickness. Improving the clarity of VR displays requires increasing screen resolution and adding more pixels. To increase screen resolution, the pixel pitch must be minimized. Consequently, the light-shielding area of ​​the array substrate must also be minimized. For example, the data lines, scan lines, and thin-film transistors must be minimized.

[0004] However, when the size of the thin film transistor is compressed to the extreme, the active layer of the thin film transistor will also shrink. Correspondingly, the part of the active layer extending below the drain will also become smaller. At this time, the contact area between the drain and the active layer below it is small, which will cause the contact resistance between the drain and the active layer to be high, reducing the response speed of the thin film transistor. Summary of the Invention

[0005] The embodiments of the present application provide an array substrate and a display panel, which can solve the technical problem that the contact resistance between the drain electrode and the active layer of the thin film transistor is high, resulting in a slow response speed of the thin film transistor.

[0006] An embodiment of the present application provides an array substrate, comprising:

[0007] Multiple data lines;

[0008] an active layer disposed in a different layer from the data line, the active layer comprising a first connecting segment, a second connecting segment, and a third connecting segment connected in sequence, the first connecting segment overlapping the data line in a direction perpendicular to the array substrate, the third connecting segment being located between two adjacent data lines, the second connecting segment connecting the first connecting segment and the third connecting segment, and the second connecting segment partially overlapping the data line in a direction perpendicular to the array substrate;

[0009] a gate electrode, which is provided in a different layer from the data line and the active layer, and the gate electrode and the active layer are overlapped in a direction perpendicular to the array substrate;

[0010] a source electrode connected to the data line, and the source electrode is in contact with the first connecting section; and

[0011] The drain electrode is spaced apart from the data line and the source electrode, and overlaps with the portion of the active layer exposed between two adjacent data lines in a direction perpendicular to the array substrate, and contacts the portion of the active layer exposed between two adjacent data lines.

[0012] Optionally, in some embodiments of the present application, the second connecting segment is linear, and an extension direction of the second connecting segment intersects with an extension direction of the data line.

[0013] Optionally, in some embodiments of the present application, an angle between an extension direction of the second connecting segment and an extension direction of the data line is 7°-22°.

[0014] Optionally, in some embodiments of the present application, the second connecting segment includes a plurality of sub-connecting segments connected in sequence.

[0015] Optionally, in some embodiments of the present application, the sub-connection segment is linear, and an extension direction of the sub-connection segment intersects with an extension direction of the data line.

[0016] Optionally, in some embodiments of the present application, there is an inclined angle between the extension direction of the sub-connection segment and the extension direction of the data line, and the inclined angles of the multiple sub-connection segments are gradually increased from the first connection segment toward the third connection segment.

[0017] Optionally, in some embodiments of the present application, the second connecting segment is arc-shaped.

[0018] Optionally, in some embodiments of the present application, an insulating layer is provided between the drain electrode and the data line, and a portion of the drain electrode is overlapped with the adjacent data line.

[0019] Optionally, in some embodiments of the present application, the source electrode and the data line are arranged in the same layer, and the drain electrode and the data line are arranged in different layers.

[0020] Optionally, in some embodiments of the present application, the array substrate further includes a substrate, a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer, the active layer is provided on the substrate, the gate insulating layer covers the active layer, the gate is provided on the gate insulating layer, the first interlayer insulating layer covers the gate, the source is provided on the first interlayer insulating layer, the second interlayer insulating layer covers the source, and the drain is provided on the second interlayer insulating layer; or,

[0021] The array substrate also includes a substrate, a gate insulating layer, a first interlayer insulating layer and a second interlayer insulating layer, the active layer is arranged on the substrate, the gate insulating layer covers the active layer, the gate is arranged on the gate insulating layer, the first interlayer insulating layer covers the gate, the drain is arranged on the first interlayer insulating layer, the second interlayer insulating layer covers the drain, and the source is arranged on the second interlayer insulating layer.

[0022] Optionally, in some embodiments of the present application, the distance between two adjacent data lines is less than 7 microns.

[0023] An embodiment of the present application further provides a display panel, comprising a liquid crystal layer, an opposite substrate, and the array substrate as described above, wherein the array substrate and the opposite substrate are arranged opposite to each other, and the liquid crystal layer is arranged between the array substrate and the opposite substrate.

[0024] The embodiment of the present application adopts an array substrate and a display panel. By making a portion of the second connecting segment of the active layer overlap with the data line, another portion of the second connecting segment is located between two adjacent data lines, and the third connecting segment is located between two adjacent data lines, the area of ​​the portion of the active layer exposed between the two adjacent data lines can be increased, and the drain electrode contacts the portion of the active layer exposed between the two adjacent data lines, thereby increasing the contact area between the drain electrode and the active layer, reducing the contact resistance between the drain electrode and the active layer, and effectively improving the response speed of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 is a schematic cross-sectional structural diagram of a first array substrate provided in an embodiment of the present application;

[0027] Figure 2This is a schematic diagram of the planar structure of the array substrate provided in the embodiment of the present application. Figure 1 ;

[0028] Figure 3 This is a schematic diagram of the planar structure of the first active layer provided in an embodiment of the present application;

[0029] Figure 4 1 is a schematic diagram of the planar structure of the second active layer provided in an embodiment of the present application;

[0030] Figure 5 Schematic diagram of the planar structure of the third active layer provided in an embodiment of the present application;

[0031] Figure 6 Schematic diagram of the planar structure of the active layer, scan line and gate after superposition provided by an embodiment of the present application;

[0032] Figure 7 This is a schematic diagram of a planar structure of an active layer, a scan line, a gate, a data line, a source electrode, and a drain electrode superimposed according to an embodiment of the present application;

[0033] Figure 8 is a schematic diagram of the planar structure of an array substrate provided in a comparative embodiment of the present application;

[0034] Figure 9 is a schematic cross-sectional structural diagram of a second array substrate provided in an embodiment of the present application;

[0035] Figure 10 This is a schematic diagram of the planar structure of the array substrate provided in the embodiment of the present application. Figure 2 ;

[0036] Figure 11 Schematic diagram of the structure of the display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0038] The present application provides an array substrate and a display panel. Detailed descriptions are provided below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0039] See also Figures 1 to 3 An embodiment of the present application provides an array substrate 10 including a plurality of data lines DL and source electrodes SE. The plurality of data lines DL are spaced apart along a first direction X, and the data lines DL extend along a second direction Y. The first direction X and the second direction Y intersect, and the first direction X and the second direction Y may be, but are not limited to, perpendicular to each other. The source electrodes SE are connected to the data lines DL, i.e., the source electrodes SE are in contact with the data lines DL, i.e., the source electrodes SE are electrically connected to the data lines DL. Each data line DL may be connected to one or more source electrodes SE.

[0040] like Figures 1 to 3 As shown, the array substrate 10 further includes an active layer 400, which is disposed in a different layer structure from the data lines DL. The active layer 400 includes a first connecting segment 410, a second connecting segment 420, and a third connecting segment 430, which are sequentially connected. The second connecting segment 420 connects the first connecting segment 410 and the third connecting segment 430. The first connecting segment 410 contacts the source electrode SE, which means the first connecting segment 410 is electrically connected to the source electrode SE. The first connecting segment 410 overlaps the data lines DL in a direction perpendicular to the array substrate 10. The second connecting segment 420 partially overlaps the data lines DL in a direction perpendicular to the array substrate 10. A portion of the second connecting segment 420 overlaps the data lines DL in a direction perpendicular to the array substrate 10, and another portion of the second connecting segment 420 is located between two adjacent data lines DL. In this embodiment of the present application, by arranging a portion of the second connecting segment 420 to overlap with the data line DL in a direction perpendicular to the array substrate 10, the light-shielding area of ​​the array substrate 10 can be reduced. By extending another portion of the second connecting segment 420 between two adjacent data lines DL, the area of ​​the active layer 400 exposed between the two adjacent data lines DL can be increased. The third connecting segment 430 is located between the two adjacent data lines DL, with the portion of the second connecting segment 420 extending between the two adjacent data lines DL and the third connecting segment 430 exposed between the two adjacent data lines DL.

[0041] like Figures 1 to 3As shown, the array substrate 10 further includes a gate electrode GE and a drain electrode DE. The gate electrode GE is arranged in a different layer from the data line DL and the active layer 400, and the gate GE and the active layer 400 are overlapped in a direction perpendicular to the array substrate 10; the drain electrode DE is arranged at intervals from the data line DL and the source electrode SE, and the drain electrode DE overlaps with a portion of the active layer 400 exposed between two adjacent data lines DL in a direction perpendicular to the array substrate 10, and the drain electrode DE contacts the portion of the active layer 400 exposed between the two adjacent data lines DL, that is, the drain electrode DE is electrically connected to the portion of the active layer 400 exposed between the two adjacent data lines DL.

[0042] The array substrate 10 of the embodiment of the present application is provided with a thin film transistor T, which includes the aforementioned active layer 400, a gate electrode GE, a source electrode SE, and a drain electrode DE. To minimize the light-shielding area of ​​the array substrate 10, a portion of the second connecting segment 420 and the first connecting segment 410 are arranged to overlap with the data line DL in a direction perpendicular to the array substrate 10. Because the thin film transistor T is very small, if contact with the drain electrode DE is only through the third connecting segment 430, the contact area between the drain electrode DE and the active layer 400 is small, resulting in a high contact resistance between the drain electrode DE and the active layer 400, thereby reducing the response speed of the thin film transistor T. In order to avoid the above problems, the present application exposes another portion of the second connecting segment 420 between two adjacent data lines DL, that is, extends the second connecting segment 420 between the two adjacent data lines DL, so that the portion of the second connecting segment 420 extending between the two adjacent data lines DL and the third connecting segment 430 are exposed between the two adjacent data lines DL, and the drain electrode DE contacts the portion of the active layer 400 exposed between the two adjacent data lines DL, thereby increasing the contact area between the drain electrode DE and the active layer 400, reducing the contact resistance between the drain electrode DE and the active layer 400, and effectively improving the response speed of the thin film transistor T.

[0043] Specifically, such as Figures 2 to 5 As shown, the extension direction of the first connecting segment 410 is the same as the extension direction of the data line DL, and the extension direction of the third connecting segment 430 intersects with the extension direction of the data line DL. Specifically, the extension direction of the first connecting segment 410 is the second direction, and the extension direction of the third connecting segment is the first direction.

[0044] Specifically, such as Figure 2 and Figure 3 As shown, the second connecting segment 420 is straight, and the extension direction of the second connecting segment 420 intersects with the extension direction of the data line DL, that is, the second connecting segment 420 is tilted relative to the data line DL, so that a portion of the second connecting segment 420 overlaps with the data line DL in a direction perpendicular to the array substrate 10, and the other portion of the second connecting segment 420 is located between two adjacent data lines DL.

[0045] Specifically, Figure 3 In the illustrated embodiment, the second connecting segment 420 is linear and is arranged at an angle relative to the data line DL. If the angle α between the extension direction of the second connecting segment 420 and the extension direction of the data line DL is too small, the contact area between the drain electrode DE and the active layer 400 cannot be effectively increased. If the angle α between the extension direction of the second connecting segment 420 and the extension direction of the data line DL is too large, the area of ​​the active layer 400 exposed between two adjacent data lines DL is likely to be too large, affecting the aperture ratio of the array substrate 10. To address the above issues, the angle α between the extension direction of the second connecting segment 420 and the extension direction of the data line DL is preferably controlled within a range of 7° to 22°. This effectively increases the contact area between the drain electrode DE and the active layer 400 while ensuring the aperture ratio of the array substrate 10. In this embodiment, the angle α between the extension direction of the second connecting segment 420 and the extension direction of the data line DL can be 7°, 10°, 12°, 14°, 16°, 18°, 20° or 22°. Of course, according to the actual situation and specific needs, the angle α between the extension direction of the second connecting segment 420 and the extension direction of the data line DL can be appropriately adjusted and is not limited here.

[0046] It is understandable that the second connecting section 420 can be Figure 3 The second connecting segment 420 can also be arranged in other ways, as long as a portion of the second connecting segment 420 overlaps with the data line DL in a direction perpendicular to the array substrate 10, and another portion of the second connecting segment 420 is located between two adjacent data lines DL. For example, the second connecting segment 420 can also be arranged in Figure 4 and Figure 5 The method is set up in this way, and there is no sole limitation.

[0047] Specifically, such as Figure 2 and Figure 4 As shown, the second connecting segment 420 may include multiple sub-connecting segments 421 connected in sequence. In this embodiment, the second connecting segment 420 includes three sub-connecting segments 421. Of course, according to the actual selection and specific needs, the second connecting segment 420 may include two, four or more sub-connecting segments 421. The specific number of sub-connecting segments 421 can be appropriately adjusted and is not limited here.

[0048] Specifically, such as Figure 2 and Figure 4As shown, the sub-connecting segments 421 are linear, and their extension direction intersects the extension direction of the data lines DL, meaning that the sub-connecting segments 421 are arranged at an angle relative to the data lines DL. A portion of each sub-connecting segment 421 overlaps the data lines DL in a direction perpendicular to the array substrate 10, while another portion of the sub-connecting segment 421 is positioned between two adjacent data lines DL. This arrangement ensures that a portion of the second connecting segment 420 overlaps the data lines DL in a direction perpendicular to the array substrate 10, while another portion of the second connecting segment 420 is positioned between two adjacent data lines DL. Of course, the sub-connecting segments 421 may also be curved, depending on actual needs and requirements, and this is not a strict limitation.

[0049] Specifically, such as Figure 2 and Figure 4 As shown, the sub-connecting segment 421 extends in a direction that is tilted at an angle β to the direction that the data lines extend. If the tilt angle β of the sub-connecting segment 421 is too small, the contact area between the drain electrode DE and the active layer 400 cannot be effectively increased. If the tilt angle β of the sub-connecting segment 421 is too large, the area of ​​the active layer 400 exposed between two adjacent data lines DL is too large, affecting the aperture ratio of the array substrate 10. To address the above issues, the tilt angle β of the sub-connecting segment 421 is preferably controlled within a range of 7°-22°, which effectively increases the contact area between the drain electrode DE and the active layer 400 while ensuring the aperture ratio of the array substrate 10. In this embodiment, the tilt angle β of the sub-connecting segment 421 can be 7°, 10°, 12°, 14°, 16°, 18°, 20°, or 22°. Of course, the tilt angle β of the sub-connecting segment 421 can be appropriately adjusted based on actual conditions and specific requirements, and is not a single limitation herein.

[0050] Specifically, such as Figure 2 and Figure 4 As shown, the tilt angle β of the plurality of sub-connection segments 421 is gradually increased from the first connection segment 410 toward the third connection segment 430. In this structure, from the first connection segment 410 toward the third connection segment 430, the area ratio of the portion of the sub-connection segment 421 extending between two adjacent data lines DL to the corresponding sub-connection segment 421 gradually increases, further illustrating that Figure 4In the active layer 400 shown in the embodiment, the second connecting segment 420 includes three sub-connecting segments 421, which are the first sub-connecting segment 421, the second sub-connecting segment 421 and the third sub-connecting segment 421 in order from the first connecting segment 410 toward the third connecting segment 430. The area ratio of the portion of the first sub-connecting segment 421 extending between two adjacent data lines DL to the first sub-connecting segment 421 is smaller than the area ratio of the portion of the second sub-connecting segment 421 extending between two adjacent data lines DL to the second sub-connecting segment 421. The area ratio of the portion of the second sub-connecting segment 421 extending between two adjacent data lines DL to the second sub-connecting segment 421 is smaller than the area ratio of the portion of the third sub-connecting segment 421 extending between two adjacent data lines DL to the third sub-connecting segment 421.

[0051] During the actual manufacturing process of the array substrate 10, the drain electrode DE will contact the underlying active layer 400 through a contact hole. In order to prevent the drain electrode DE from being electrically connected to other wirings, the contact hole will be made relatively small. The contact hole cannot completely expose the portion of the active layer 400 exposed between two adjacent data lines DL. The edge portion of the active layer 400 corresponding to the data line DL cannot be exposed in the contact hole. Therefore, the portion of the active layer 400 closer to the drain electrode DE is more likely to contact the drain electrode DE. In the active layer 400 of the embodiment of the present application, the tilt angles β of the multiple sub-connection segments 421 are gradually increased from the first connection segment 410 toward the third connection segment 430. The portion of the sub-connection segment 421 that is farther from the drain electrode DE and exposed between two adjacent data lines DL has a lower probability of contacting the drain electrode DE. By setting a smaller tilt angle β for this sub-connection segment 421, the area of ​​the sub-connection segment 421 exposed between the two adjacent data lines DL can be reduced. On the other hand, the portion of the sub-connection segment 421 that is closer to the drain electrode DE and exposed between two adjacent data lines DL has a higher probability of contacting the drain electrode DE. By setting a larger tilt angle β for this sub-connection segment 421, the area of ​​the sub-connection segment 421 exposed between the two adjacent data lines DL can be increased. With the above arrangement, the size of the active layer 400 can be controlled within an appropriate size range, thereby ensuring a compact design of the active layer 400 and reducing the contact resistance between the drain electrode DE and the active layer 400, thereby effectively improving the response speed of the thin film transistor T.

[0052] Specifically, such as Figure 2 and Figure 5 As shown, the second connecting segment 420 is arc-shaped, such that a portion of the second connecting segment 420 overlaps the data line DL in a direction perpendicular to the array substrate 10, and another portion of the second connecting segment 420 is located between two adjacent data lines DL. In this embodiment, the second connecting segment 420 can be formed by one arc, two arcs, or more arcs, which is not a limitation herein.

[0053] Specifically, such as Figure 1 、 Figure 2 and Figure 6 As shown, the array substrate 10 further includes a plurality of gate lines GL, which are arranged in the same layer as the gate electrode GE and are connected, that is, the gate electrode GE contacts the gate line GL, that is, the gate electrode GE is electrically connected to the gate line GL. The plurality of gate lines GL are arranged at intervals along the second direction Y, and the gate lines GL extend along the first direction X. The gate lines GL intersect with the data lines DL. The plurality of gate lines GL and the plurality of data lines DL define a plurality of sub-pixel areas sp, and a portion of the second connecting segment 420 overlaps with the data line DL in a direction perpendicular to the array substrate 10. Figure 4 From a perspective, when the second connection segment 420 includes a plurality of sub-connection segments 421 , a portion of each sub-connection segment 421 overlaps with the data line DL in a direction perpendicular to the array substrate 10 .

[0054] Specifically, such as Figure 1 、 Figure 2 and Figure 7 As shown, the source electrode SE and the first connecting segment 410 are overlapped in a direction perpendicular to the array substrate 10, and the source electrode SE is in contact with the first connecting segment 410; the drain electrode DE and the third connecting segment 430 are overlapped in a direction perpendicular to the array substrate 10, and the drain electrode DE is in contact with the third connecting segment 430; the gate electrode GE and the second connecting segment 420 are overlapped in a direction perpendicular to the array substrate 10, and the gate electrode GE is spaced apart from the active layer 400. In this structure, the gate electrode GE, the active layer 400, the source electrode SE and the drain electrode DE constitute a thin film transistor T.

[0055] Specifically, such as Figures 1 to 5 As shown, the first connecting segment 410 includes a first heavily ion-doped region 411 and a first lightly ion-doped region 412. The first lightly ion-doped region 412 is disposed between the first heavily ion-doped region 411 and the second connecting segment 420. The ion doping concentration of the first heavily ion-doped region 411 is higher than that of the first ion-doped region. The source electrode SE contacts the first heavily ion-doped region 411. With this structure, the carrier mobility and high output current characteristics of the thin film transistor T can be improved.

[0056] Specifically, such as Figures 1 to 5 As shown, the third connecting segment 430 includes a second heavily ion-doped region 431 and a second lightly ion-doped region 432. The second lightly ion-doped region 432 is disposed between the second heavily ion-doped region 431 and the second connecting segment 420. The ion doping concentration of the second heavily ion-doped region 431 is higher than that of the second ion-doped region. The drain DE contacts the second heavily ion-doped region 431. With this structure, the carrier mobility and output current characteristics of the thin film transistor T can be improved.

[0057] Specifically, such as Figures 1 to 5 As shown, the ions doped into the first heavily ion-doped region 411, the first lightly ion-doped region 412, the second heavily ion-doped region 431, and the second lightly ion-doped region 432 may be N-type doping ions, which may specifically include elements such as phosphorus and arsenic. Of course, depending on the actual situation and specific requirements, the ions doped into the first heavily ion-doped region 411, the first lightly ion-doped region 412, the second heavily ion-doped region 431, and the second lightly ion-doped region 432 may be P-type doping ions, which may specifically include elements such as boron and gallium.

[0058] Figure 8 The array substrate provided in the comparative embodiment of the present application includes data lines dl, scan lines gl, thin film transistors t and pixel electrodes (not shown), and the thin film transistor t is a dual-gate thin film transistor t. The thin film transistor t includes an active layer 41, two gates ge, a source electrode se and a drain electrode de, wherein the active layer 41 is U-shaped, the gate line is provided above the active layer 41, the data line dl, the source electrode se and the drain electrode de are provided in the same layer, the source electrode se is connected to one end of the active layer 41 through a first contact hole ch1, the drain electrode de is located between two adjacent data lines dl, the drain electrode de is connected to the other end of the active layer 41 through a second contact hole ch2, and the drain electrode de is also connected to the pixel electrode through a third contact hole ch3. Figure 8 As shown, to prevent shorting between the drain electrode de and the data line d1, a certain distance must be maintained between them. This increases the pixel pitch and hinders resolution improvement. Specifically, the width of a data line d1 is L1, the distance between the drain electrode de and an adjacent data line d1 is L2, the width of the drain electrode de is L3, and the distance between the drain electrode de and another adjacent data line d1 is L4. The width of the sub-pixel region, consisting of a data line d1, the transistor electrically connected to it, and the pixel electrode, is L1+L2+L3+L4. Limited by process capabilities such as panel exposure, the minimum size of the data line d1 can only be approximately 1.5 microns, and the minimum contact hole size is approximately 2-5 microns. This results in a minimum value of L1+L2+L3+L4 of 7-8 microns. Consequently, the maximum resolution can only reach approximately 1000 ppi, which cannot meet the immersive requirements of virtual reality technology.

[0059] Specifically, such as Figure 1 and Figure 2As shown, in the array substrate 10 of the embodiment of the present application, the source electrode SE is provided in the same layer as the data line DL, while the drain electrode DE and the data line DL are provided in different layers. An insulating layer IL is provided between the drain electrode DE and the data line DL, meaning that the drain electrode DE and the data line DL are located in different layers and are not short-circuited. In actual production, there is no need to consider whether a safe distance needs to be maintained between the drain electrode DE and the data line DL; it is only necessary to ensure that a certain distance D is maintained between two adjacent drain electrodes DE. In this embodiment, the spacing between the data lines DL is L5, and the spacing between two adjacent data lines DL is L6. The width of the sub-pixel region sp is L5 + L6. Under current process capabilities, the minimum value of L5 + L6 can be approximately 4 microns. Due to the significantly reduced width of the sub-pixel region sp, the resolution can be increased to over 1500 ppi, and even over 2000 ppi, thereby significantly improving the resolution of the display panel and meeting the high-resolution requirements of the virtual reality field. Furthermore, in the array substrate 10 of the embodiment of the present application, the thin film transistor T has a single-gate structure. Compared to Figure 8 The array substrate 10 shown in the embodiment of the present application has a larger aperture ratio.

[0060] Specifically, such as Figure 1 and Figure 2 As shown, the array substrate 10 further includes a substrate 100, a gate insulating layer 500, a first interlayer insulating layer 600, and a second interlayer insulating layer 700. The active layer 400 is disposed on the substrate 100, the gate insulating layer 500 covers the active layer 400, the gate GE is disposed on the gate insulating layer 500, the first interlayer insulating layer 600 covers the gate GE, the source electrode SE is disposed on the first interlayer insulating layer 600, the second interlayer insulating layer 700 covers the source electrode SE, and the drain electrode DE is disposed on the second interlayer insulating layer 700. In this structure, by disposing the source electrode SE (data line DL) and the drain electrode DE on different layers, the width of the sub-pixel region sp is reduced, thereby significantly improving the resolution of the display panel.

[0061] Specifically, such as Figure 1 and Figure 2As shown, the gate insulating layer 500 and the first interlayer insulating layer 600 are provided with a first via hole CH1. The source electrode SE contacts the first connection segment 410 of the active layer 400 through the first via hole CH1. Specifically, the source electrode SE contacts the first heavily ion-doped region 411 through the first via hole CH1, thereby electrically connecting the source electrode SE to the active layer 400. The gate insulating layer 500, the first interlayer insulating layer 600, and the second interlayer insulating layer 700 are provided with a second via hole CH2. The drain electrode DE contacts the third connection segment 430 of the active layer 400 through the second via hole CH2. Specifically, the drain electrode DE contacts the second heavily ion-doped region 431 through the second via hole CH2, thereby electrically connecting the drain electrode DE to the active layer 400.

[0062] Specifically, such as Figure 1 and Figure 2 As shown, the array substrate 10 further includes a first planar layer 800, a pixel electrode PE, a protective layer 900, a common electrode CE, and a second planar layer 910. The first planar layer 800 covers the drain electrode DE and the second interlayer insulating layer 700. The pixel electrode PE is disposed on the first planar layer 800 and contacts the drain electrode DE, that is, the pixel electrode PE and the drain electrode DE are electrically connected. The protective layer 900 covers the pixel electrode PE and the first planar layer 800. The common electrode CE is disposed on the protective layer 900. The second planar layer 910 is disposed on the protective layer 900 and the common electrode CE. The second planar layer 910 is used to fill the recessed area on the protective layer 900, thereby providing a planar area for the spacer to stand.

[0063] Specifically, such as Figure 1 and Figure 2 As shown, a third via hole CH3 is provided on the first planar layer 800 , and the pixel electrode PE contacts the drain electrode DE through the third via hole CH3 , that is, the pixel electrode PE is electrically connected to the drain electrode DE.

[0064] Specifically, such as Figure 2 and Figure 9 As shown, the array substrate 10 further includes a substrate 100, a gate insulating layer 500, a first interlayer insulating layer 600, and a second interlayer insulating layer 700. The active layer 400 is disposed on the substrate 100, the gate insulating layer 500 covers the active layer 400, the gate GE is disposed on the gate insulating layer 500, the first interlayer insulating layer 600 covers the gate GE, the drain electrode DE is disposed on the first interlayer insulating layer 600, the second interlayer insulating layer 700 covers the drain electrode DE, and the source electrode SE is disposed on the second interlayer insulating layer 700. In this structure, by disposing the source electrode SE (data line DL) and the drain electrode DE on different layers, the width of the sub-pixel region sp is reduced, thereby significantly improving the resolution of the display panel.

[0065] Specifically, such as Figure 2 and Figure 9 As shown, the gate insulating layer 500, the first interlayer insulating layer 600, and the second interlayer insulating layer 700 are provided with a first via hole CH1. The source electrode SE contacts the first connecting segment 410 of the active layer 400 through the first via hole CH1. Specifically, the source electrode SE contacts the first heavily ion-doped region 411 through the first via hole CH1, thereby electrically connecting the source electrode SE to the active layer 400. The gate insulating layer 500 and the first interlayer insulating layer 600 are provided with a second via hole CH2. The drain electrode DE contacts the third connecting segment 430 of the active layer 400 through the second via hole CH2. Specifically, the drain electrode DE contacts the second heavily ion-doped region 431 through the second via hole CH2, thereby electrically connecting the drain electrode DE to the active layer 400.

[0066] Specifically, such as Figure 2 and Figure 9 As shown, the array substrate 10 further includes a first planar layer 800, a pixel electrode PE, a protective layer 900, a common electrode CE, and a second planar layer 910. The first planar layer 800 covers the source electrode SE and the second interlayer insulating layer 700. The pixel electrode PE is disposed on the first planar layer 800 and contacts the drain electrode DE, that is, the pixel electrode PE and the drain electrode DE are electrically connected. The protective layer 900 covers the pixel electrode PE and the first planar layer 800. The common electrode CE is disposed on the protective layer 900. The second planar layer 910 is disposed on the protective layer 900 and the common electrode CE. The second planar layer 910 is used to fill the recessed area on the protective layer 900, thereby providing a planar area for the spacer to stand.

[0067] Specifically, such as Figure 2 and Figure 9 As shown, a third via hole CH3 is provided on the second interlayer insulating layer 700 and the first planar layer 800 , and the pixel electrode PE contacts the drain electrode DE through the third via hole CH3 , that is, the pixel electrode PE is electrically connected to the drain electrode DE.

[0068] Specifically, such as Figure 1 and Figure 9 As shown, the array substrate 10 also includes a light-shielding layer 200 and a buffer layer 300. The light-shielding layer 200 is arranged on the substrate 100 and corresponds to the active layer 400. The buffer layer 300 covers the light-shielding layer 200 and the substrate 100. The active layer 400 is arranged on the buffer layer 300. The gate insulating layer 500 covers the active layer 400 and the buffer layer 300.

[0069] Specifically, such as Figure 10 As shown, Figure 10 The embodiment shown is Figure 2 The differences between the shown embodiments are mainly: Figure 2 In the array substrate 10 of the embodiment shown, the drain electrode DE is located between two adjacent data lines DL; Figure 10In the array substrate 10 of the illustrated embodiment, a portion of the drain electrode DE is overlapped with an adjacent data line DL in a direction perpendicular to the array substrate 10. With this structure, the overlapping area between the drain electrode DE and the portion of the active layer 400 exposed between two adjacent data lines DL can be increased, which is beneficial for increasing the contact area between the drain electrode DE and the portion of the active layer 400 exposed between two adjacent data lines DL, thereby reducing the contact resistance between the drain electrode DE and the active layer 400, and effectively improving the response speed of the thin film transistor T.

[0070] It should be noted that the array substrate 10 of the embodiment of the present application adopts a thin film transistor T with a single-gate structure, and the drain DE and the data line DL are arranged in different layer structures, so that the distance between two adjacent data lines DL can be less than 7 microns, which can greatly reduce the width of the sub-pixel area sp, which is conducive to improving the resolution.

[0071] See also Figure 11 The present invention also provides a display panel according to an embodiment of the present invention, including a liquid crystal layer 30, an opposite substrate 20, and the array substrate 10 described above. The array substrate 10 and the opposite substrate 20 are disposed opposite each other, and the liquid crystal layer 30 is disposed between the array substrate 10 and the opposite substrate 20. Since the display panel according to the present invention includes the technical solutions of all the above embodiments, it also has the beneficial effects of all the above technical solutions, which will not be described in detail here.

[0072] The above is a detailed introduction to an array substrate and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: Multiple data lines; an active layer, arranged in a different layer from the data line, the active layer comprising a first connecting segment, a second connecting segment, and a third connecting segment connected in sequence, the extension direction of the second connecting segment intersecting with the extension direction of the data line, the extension direction of the third connecting segment intersecting with the extension direction of the data line and the extension direction of the second connecting segment respectively, the first connecting segment overlapping with the data line in a direction perpendicular to the array substrate, the third connecting segment being located between two adjacent data lines, the second connecting segment connecting the first connecting segment and the third connecting segment, the second connecting segment partially overlapping with the data line in a direction perpendicular to the array substrate; the second connecting segment being linear, and the angle between the extension direction of the second connecting segment and the extension direction of the data line being 12°-22°; a gate electrode, which is provided in a different layer from the data line and the active layer, and the gate electrode and the active layer are overlapped in a direction perpendicular to the array substrate; a source electrode connected to the data line, and the source electrode is in contact with the first connecting section; as well as The drain electrode is spaced apart from the data line and the source electrode, and overlaps with the portion of the active layer exposed between two adjacent data lines in a direction perpendicular to the array substrate, and contacts the portion of the active layer exposed between two adjacent data lines.

2. The array substrate according to claim 1, wherein: The source electrode and the data line are arranged in the same layer, and the drain electrode and the data line are arranged in different layers.

3. The array substrate according to claim 2, wherein: The array substrate further includes a substrate, a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer, wherein the active layer is provided on the substrate, the gate insulating layer covers the active layer, the gate is provided on the gate insulating layer, the first interlayer insulating layer covers the gate, the source is provided on the first interlayer insulating layer, the second interlayer insulating layer covers the source, and the drain is provided on the second interlayer insulating layer; or, The array substrate also includes a substrate, a gate insulating layer, a first interlayer insulating layer and a second interlayer insulating layer, the active layer is arranged on the substrate, the gate insulating layer covers the active layer, the gate is arranged on the gate insulating layer, the first interlayer insulating layer covers the gate, the drain is arranged on the first interlayer insulating layer, the second interlayer insulating layer covers the drain, and the source is arranged on the second interlayer insulating layer.

4. The array substrate according to any one of claims 1 to 3, wherein: The distance between two adjacent data lines is less than 7 microns.

5. An array substrate, characterized in that: include: Multiple data lines; an active layer, arranged in a different layer from the data line, the active layer comprising a first connecting segment, a second connecting segment, and a third connecting segment connected in sequence, the second connecting segment extending in a direction intersecting with the data line extending in a direction intersecting with the data line extending in a direction intersecting with the data line extending in a direction intersecting with the second connecting segment extending in a direction intersecting with the data line extending in a direction perpendicular to the array substrate, the third connecting segment being located between two adjacent data lines, the second connecting segment connecting the first connecting segment and the third connecting segment, the second connecting segment partially overlapping with the data line in a direction perpendicular to the array substrate; the second connecting segment comprising a plurality of sub-connecting segments connected in sequence; the sub-connecting segments extending in a direction intersecting with the data line extending in a direction intersecting with a portion of each sub-connecting segment overlapping with the data line in a direction perpendicular to the array substrate; the sub-connecting segments being linear, the sub-connecting segments extending in a direction having an inclined angle with the data line extending in a direction, the inclined angles of the plurality of sub-connecting segments gradually increasing from the first connecting segment toward the third connecting segment; a gate electrode, which is provided in a different layer from the data line and the active layer, and the gate electrode and the active layer are overlapped in a direction perpendicular to the array substrate; a source electrode connected to the data line, and the source electrode is in contact with the first connecting section; as well as The drain electrode is spaced apart from the data line and the source electrode, and overlaps with the portion of the active layer exposed between two adjacent data lines in a direction perpendicular to the array substrate, and contacts the portion of the active layer exposed between two adjacent data lines.

6. The array substrate according to claim 5, wherein: The source electrode and the data line are arranged in the same layer, and the drain electrode and the data line are arranged in different layers.

7. The array substrate according to claim 6, wherein: The array substrate further includes a substrate, a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer, wherein the active layer is provided on the substrate, the gate insulating layer covers the active layer, the gate is provided on the gate insulating layer, the first interlayer insulating layer covers the gate, the source is provided on the first interlayer insulating layer, the second interlayer insulating layer covers the source, and the drain is provided on the second interlayer insulating layer; or, The array substrate also includes a substrate, a gate insulating layer, a first interlayer insulating layer and a second interlayer insulating layer, the active layer is arranged on the substrate, the gate insulating layer covers the active layer, the gate is arranged on the gate insulating layer, the first interlayer insulating layer covers the gate, the drain is arranged on the first interlayer insulating layer, the second interlayer insulating layer covers the drain, and the source is arranged on the second interlayer insulating layer.

8. The array substrate according to any one of claims 5 to 7, wherein: The distance between two adjacent data lines is less than 7 microns.

9. A display panel, characterized in that: The invention comprises a liquid crystal layer, an opposite substrate, and the array substrate according to any one of claims 1 to 8, wherein the array substrate and the opposite substrate are arranged opposite to each other, and the liquid crystal layer is arranged between the array substrate and the opposite substrate.

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