Laterally diffused metal oxide semiconductor device and manufacturing method thereof

Abstract

The present invention relates to a laterally diffused metal oxide semiconductor (LDMOS) device and a method for manufacturing the same. The device comprises: a substrate having a second conductivity type; a drift region disposed on the substrate and having a first conductivity type, the first conductivity type and the second conductivity type being opposite; a multi-layer doped structure disposed in the drift region, each layer of the doped structure comprising at least one doped strip extending along the length of a conductive channel; and multiple doped polysilicon pillars disposed in the drift region and extending from top to bottom through at least one layer of the doped strips. The conductivity type of the doped ions in each doped polysilicon pillar is opposite to that of the doped ions in each doped strip. Due to the formation of injection holes in the present invention, ion implantation is not restricted by depth, and multiple RESURF structures / multiple conductive channels can be formed within the drift region. This can improve breakdown voltage and reduce on-resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a laterally diffused metal oxide semiconductor device and a manufacturing method of a laterally diffused metal oxide semiconductor. Background Art

[0002] For laterally diffused metal oxide semiconductor (LDMOS) devices, there is a mutually restrictive relationship between their breakdown voltage (BV) and on-resistance. While ensuring the breakdown voltage, minimizing the on-resistance of the LDMOS as much as possible becomes the goal pursued by designers. Summary of the Invention

[0003] Based on this, it is necessary to provide a laterally diffused metal oxide semiconductor device and a manufacturing method thereof that can improve the breakdown voltage and reduce the on-resistance.

[0004] A laterally diffused metal oxide semiconductor device comprises: a substrate having a second conductivity type; a drift region disposed on the substrate and having a first conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a multi-layer doped structure disposed in the drift region, each layer of the doped structure comprising at least one doped strip extending along the length direction of the conductive channel; and a plurality of doped polysilicon pillars disposed in the drift region and extending from top to bottom through at least one layer of the doped structure, the conductivity type of the doped ions in each of the doped polysilicon pillars being opposite to the conductivity type of the doped ions in each of the doped strips.

[0005] In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, each of the doped strips is N-type doped, and each of the doped polysilicon pillars is P-type doped.

[0006] In one embodiment, the concentration of doping ions in each of the doping strips is greater than the concentration of doping ions in the drift region.

[0007] In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, each of the doped strips is P-type doped, and each of the doped polysilicon pillars is N-type doped.

[0008] In one embodiment, it also includes: a source region having a first conductivity type; a drain region having a first conductivity type; a field oxide layer provided on each of the doped polysilicon pillars, the bottom of the field oxide layer being in contact with the top of each of the doped polysilicon pillars; a gate extending from a position of the field oxide layer adjacent to the source region toward the source region; and a substrate lead-out region having a second conductivity type, provided on a side of the source region facing away from the gate.

[0009] In one embodiment, the substrate lead-out region contacts the source region.

[0010] In one embodiment, each of the doped polysilicon pillars extends downward from the field oxide layer through each layer of doped strips and stops at the bottom doped strip.

[0011] In one embodiment, a plurality of mutually parallel doping strips are formed on the cross section of each layer of the doped structure, and the doped polysilicon columns are distributed in a matrix.

[0012] In one embodiment, the doping strips of each doping structure are not connected in the width direction of the conductive channel.

[0013] A method for manufacturing a laterally diffused metal oxide semiconductor device comprises: step A, obtaining a substrate having a drift region formed thereon, the drift region having a first conductivity type and formed on the substrate having a second conductivity type; the first conductivity type and the second conductivity type being opposite conductivity types; step B, etching a plurality of injection holes in the drift region; step C, injecting dopant ions into the bottom of each of the injection holes; step D, filling each of the injection holes with a certain thickness of doped polysilicon, the conductivity type of the doped polysilicon being opposite to the conductivity type of the doped ions; step E, injecting dopant ions of a conductivity type opposite to that of the doped polysilicon into the drift region at the top of the doped polysilicon in each of the injection holes; repeating steps D and E for a preset number of times, after which the injection holes are filled with the doped polysilicon, and dopant ions injected in different times form doped regions of different depths in the drift region; and step F, causing the doped regions of the same depth to diffuse through heat treatment and then connect in the length direction of the conductive channel to form doped strips extending along the length direction of the conductive channel.

[0014] In one embodiment, the step D further comprises: etching the doped polysilicon in each of the injection holes, the etching depth being shallower than the previous etching of the injection holes, so that part of the doped polysilicon remains in the hole.

[0015] In one embodiment, after step F, the method further includes: forming a field oxide layer above each of the injection holes; forming a gate; and forming a source region of the first conductivity type, a drain region of the first conductivity type, and a substrate lead-out region of the second conductivity type.

[0016] The above-mentioned laterally diffused metal oxide semiconductor device and its manufacturing method form a mesh structure in which longitudinal doped polysilicon columns and lateral doped strips are cross-arranged in the drift region. For the structure in which the doped strips are of the first conductive type and the doped polysilicon columns are of the second conductive type, the doped polysilicon columns penetrate deep into the drift region, which can optimize the electric field in the body, so that the device reaches the maximum breakdown voltage when the reverse withstand voltage is reached. The lateral first conductive type doped strips can form conductive channels of different depths to achieve the purpose of reducing the on-resistance; for the structure in which the doped strips are of the second conductive type and the doped polysilicon columns are of the first conductive type, the doped strips and the drift region of the first conductive type form a multiple RESURF (reduced surface electric field) structure. When the device withstands the reverse withstand voltage, the doped strips of different depths in the drift region can significantly assist in the depletion of the first conductive type impurities in the drift region to achieve the optimized breakdown voltage. At the same time, the longitudinal doped polysilicon columns in the drift region can effectively increase the concentration of the first conductive type impurity ions in the drift region and reduce the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0018] Figure 1 is a schematic diagram of an exemplary LDMOS structure having a P-type buried layer formed in a drift region;

[0019] Figure 2 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device in one embodiment;

[0020] Figure 3a 、 Figure 3b Each is a flow chart of a method for manufacturing a laterally diffused metal oxide semiconductor device in one embodiment;

[0021] Figure 4 is a top view of an injection hole in one embodiment;

[0022] Figure 5 is a schematic cross-sectional view of the device after step S320 is completed in one embodiment;

[0023] Figure 6 is a schematic cross-sectional view of the device after step S330 is completed in one embodiment;

[0024] Figure 7 This is a schematic cross-sectional view of the device after step S340 is completed in one embodiment;

[0025] Figure 8This is a schematic cross-sectional view of the device after step S350 is completed in one embodiment;

[0026] Figure 9 is Figure 8 The structure obtained by repeating steps S340 and S350 once more based on the obtained structure;

[0027] Figure 10 This is a schematic cross-sectional view of the device after step S360 is completed in one embodiment;

[0028] Figure 11 yes Figure 2 Schematic cross-section of the structure shown. DETAILED DESCRIPTION

[0029] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0031] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0032] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0035] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0036] Figure 1 This is a schematic diagram of an exemplary LDMOS structure having a P-type buried layer formed in the drift region. In this structure, P-type ions (such as boron ions) are directly injected into the drift region 202 (Nwell) through ion implantation to form a P-type buried layer 204 (Pburied). This structure has a conductive channel in the drift region 202 above the P-type buried layer 204, and also has a conductive channel in the drift region 202 below the P-type buried layer 204 (as shown by the two arrows in the figure). When the LDMOS device is in the reverse withstand voltage state, the P-type buried layer 204 can significantly assist in the depletion of N-type impurities in the drift region 202, thereby increasing the concentration of N-type impurities in the drift region and reducing the on-resistance.

[0037] The inventors believe that the N-type conductive channel above the P-type buried layer 204 is the shortest conductive path between the source and the drain. The deeper the channel, the lower the overall on-resistance of the LDMOS. However, due to limitations on the implantation energy and other factors, the implantation depth of P-type ions in ion implantation equipment is limited. This results in a narrow N-type conductive channel region above the P-type buried layer 204, resulting in weak conductivity and preventing significant reduction in the on-resistance of the LDMOS.

[0038] The present application proposes a novel LDMOS manufacturing method and structure, which can improve the reverse withstand voltage of the LDMOS and reduce the on-resistance of the LDMOS. Figure 2 1 is a schematic diagram of the structure of a laterally diffused metal oxide semiconductor device in an embodiment, comprising a substrate 101, a drift region 102, a plurality of doped polysilicon pillars 106, and a multi-layer doped structure. Each layer of the doped structure is provided in the drift region 102, and each layer of the doped structure includes at least one doped structure along the length direction of the conductive channel (i.e., Figure 2 The doping strips 105 extend in the X direction. Figure 2 In the illustrated embodiment, the device is an NLDMOS, the substrate 101 is a P-type substrate, and the drift region 102 is an N-type drift region (specifically, an N-drift region) disposed on the substrate 101. Each doped polysilicon pillar 106 is disposed in the drift region 102 and extends from top to bottom through at least one layer of doped strips 105 of the doping structure, forming a mesh structure within the drift region 102 in which the vertically doped polysilicon pillars 106 and the horizontally doped strips 105 (i.e., along the length of the conductive channel) intersect. The conductivity type of the doped ions in each doped polysilicon pillar 106 is opposite to that of the doped ions in each doped strip.

[0039] In one embodiment of the present application, the doped strips 105 are N-type doped, and the doped polysilicon pillars 106 are P-type doped. The P-type doped polysilicon pillars 106 extend deep into the N-type drift region 102, optimizing the internal electric field and allowing the device to achieve a maximum breakdown voltage when subjected to reverse withstand voltage. The lateral N-type doped strips can form conductive channels of varying depths, thereby reducing on-resistance. Furthermore, the concentration of doped ions in the doped strips 105 is greater than that in the drift region 102, resulting in a lower resistance in the conductive channel formed by the N-type doped strips.

[0040] In another embodiment of the present application, the doped strips 105 are P-type doped, and the doped polysilicon pillars 106 are N-type doped. The P-type doped strips 105 and the N-type drift region 102 form a multi-RESURF (reduced surface field) structure. During reverse withstand voltage testing of the device, the doped strips 105 at different depths within the drift region 102 can significantly assist in depleting the N-type impurities in the drift region 102, achieving an optimized breakdown voltage. At the same time, the longitudinal P-type doped polysilicon pillars within the drift region 102 can effectively increase the concentration of N-type impurity ions within the drift region 102, thereby reducing on-resistance.

[0041] exist Figure 2 In the embodiment shown, the LDMOS device further includes a source region 104, a drain region 110, a field oxide layer 112, a gate 108 and a substrate lead-out region 103. The doped polysilicon column 106 is arranged in the lateral direction (i.e., the conductive channel length direction). Figure 2 The N-type source region 104 and the N-type drain region 110 are located between the N-type source region 104 and the N-type drain region 110 in the X direction ( Figure 2 The source region 104 and the drain region 110 of the embodiment shown are both N+ regions). Figure 2 The ellipsis in the figure indicates that the multiple doped polysilicon pillars 106 are not drawn. The field oxide layer 112 is provided on the drift region 102, and the bottom of the field oxide layer 112 contacts the top of the doped polysilicon pillar 106. Figure 2 To illustrate the location of the doped polysilicon pillars 106, the structure of the field oxide layer 112 in the Y direction is not depicted. The polysilicon gate 108 extends from the field oxide layer 112 adjacent to the source region 104 toward the source region 104. The substrate lead-out region 103 is a P-type doped region (specifically, a P+ doped region) located on the side of the source region 104 facing away from the gate 108 and in contact with the source region 104.

[0042] exist Figure 2In the illustrated embodiment, the LDMOS device further includes a second conductivity type well region 107. The second conductivity type well region 107 serves as the second conductivity type region at the source end of the LDMOS device. The source region 104 and the substrate lead-out region 103 are located within the second conductivity type well region 107. The concentration of the second conductivity type well region 107 affects drift region depletion and threshold voltage. In one embodiment of the present application, the concentration of the second conductivity type ions in the second conductivity type well region 107 is lower than that in the substrate lead-out region 103.

[0043] exist Figure 2 In the embodiment shown, the LDMOS device further includes a first conductivity type well region 109. The first conductivity type well region 109 is an N-type region around the drain terminal. The drain region 110 is disposed in the first conductivity type well region 109 to optimize the forward conduction current.

[0044] exist Figure 2 In the illustrated embodiment, the doped polysilicon pillars 106 extend downward from below the field oxide layer 112 through each layer of the doped strips 105 and stop at the bottommost doped strip 105. Furthermore, multiple parallel doped strips 105 are formed on the cross section of each layer of the doped structure, and the doped polysilicon pillars 106 are arranged in a matrix pattern on the cross section.

[0045] exist Figure 2 In the illustrated embodiment, the doping strips 105 of each layer of the doping structure are not connected in the Y direction (ie, the width direction of the conductive channel).

[0046] In one embodiment, the substrate 101 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). Figure 2 In the embodiment shown, the substrate 101 is made of single crystal silicon.

[0047] exist Figure 2 In the embodiment shown, the gate 108 is made of polysilicon. In other embodiments, metal, metal nitride, metal silicide or similar compounds may be used as the material of the gate 108 .

[0048] In one embodiment, the field oxide layer 112 is made of silicon dioxide.

[0049] The present application accordingly provides a method for manufacturing a laterally diffused metal oxide semiconductor device, which can be used to manufacture the laterally diffused metal oxide semiconductor device described in any of the above embodiments. Figure 3a1 is a flow chart of a method for manufacturing a laterally diffused metal oxide semiconductor device in one embodiment, comprising:

[0050] S310 , obtaining a substrate with a drift region formed thereon.

[0051] A drift region of the first conductivity type is formed on a substrate of the second conductivity type. In this embodiment, the laterally diffused metal oxide semiconductor device is an NLDMOS device, wherein the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0052] S320 , etching a plurality of injection holes in the drift region.

[0053] In this embodiment, the injection hole is etched locally in the drift region after photolithography. In one embodiment of the present application, the depth of the injection hole is set according to the depth to be reached by the doping strip in the bottom layer. Figure 4 306 is a top view of the injection holes in one embodiment. These injection holes 306 are arranged in a matrix. In one embodiment of the present application, after step S310 and before step S320, a step of forming a second conductive type well region 107 on the substrate is further included. Figure 5 The second conductive type well region 107 serves as the channel formation region of the device, and its concentration will also affect the depletion of the drift region and the threshold voltage.

[0054] S330 , injecting dopant ions into the bottom of each injection hole.

[0055] In one embodiment of the present application, ion implantation is performed while retaining the photoresist pattern formed by photolithography in step S320 , thereby forming a doped region 105 a at the bottom of the injection hole 306 . Figure 6 FIG. 1 is a schematic cross-sectional view of the device after step S330 is completed in one embodiment.

[0056] S340 , filling each injection hole with doped polysilicon.

[0057] Fill with a certain thickness of doped polysilicon, the conductivity type of the doped polysilicon is opposite to the conductivity type of the doping ions implanted in step S330. Figure 3b In one embodiment of the present application, step S340 is to fill N-type or P-type polysilicon by physical vapor deposition (PVD) or chemical vapor deposition (CVD), and then in step S342, the polysilicon on the surface of the wafer is removed by a process such as CMP (chemical mechanical polishing), and then the doped polysilicon 106 filled in the injection hole 306 is etched to a certain depth again, and the etching depth is shallower than the previous etching of the injection hole 306, so that part of the doped polysilicon 106 remains in the hole. Figure 7 FIG. 1 is a schematic cross-sectional view of the device after step S340 is completed in one embodiment.

[0058] S350 , implanting doping ions of opposite conductivity type to the doped polysilicon into the drift region at the top of the doped polysilicon in each implantation hole.

[0059] See also Figure 8 After the ion implantation, a doped region 105a is formed at the bottom of the new implantation hole 306 formed by the previous etching. The junction depth of the doped region 105a formed by this implantation is different from that of the previous implantation.

[0060] Then, steps S340 and S350 are repeated multiple times until a predetermined number of doping regions 105 a are formed. It is understood that doping ions implanted at different times form doping regions 105 a of different depths in the drift region 102 . Figure 9 is Figure 8 The structure obtained by repeating steps S340 and S350 once more is based on the obtained structure.

[0061] S360, filling the injection hole by doping polysilicon.

[0062] The filled doped polysilicon is the same as step S340 . Figure 10 This is a schematic cross-sectional view of a device after step S360 is completed in one embodiment. In one embodiment of the present application, N-type or P-type polysilicon is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD), and then the polysilicon on the wafer surface is removed using a process such as CMP (chemical mechanical polishing).

[0063] S370, through heat treatment, the doped regions at the same depth are diffused and connected in the length direction of the conductive channel.

[0064] After step S360, the device structure is subjected to heat treatment (thermal diffusion). After diffusion, the doped regions 105a are connected along the length of the conductive channel, forming doped strips 105 extending along the length of the conductive channel. In one embodiment of the present application, the doped strips 105 of each layer are not connected along the width of the conductive channel.

[0065] Because the injection holes are formed in this laterally diffused metal oxide semiconductor (LDMOS) manufacturing method, ion implantation is not restricted by depth, and multiple RESURF structures / multiple conductive channels can be formed within the drift region. In the LDMOS device fabricated using this method, the actual junction depth of each doped strip 105 closely matches the desired junction depth.

[0066] In one embodiment of the present application, the doped strip 105 is N-type doped, and the doped polysilicon column 106 is P-type doped. The P-type doped polysilicon column 106 penetrates deep into the N-type drift region 102, which can optimize the electric field in the body so that the device reaches the maximum breakdown voltage when it withstands reverse voltage; the lateral N-type doped strip can form conductive channels of different depths to achieve the purpose of reducing the on-resistance. Step S380 can activate the injected P-type impurity ions and diffuse them in the drift region 102, and repair the damage to the N-type doped polysilicon. Furthermore, the concentration of the doped ions in the doped strip 105 is greater than the concentration of the doped ions in the drift region 102, so that the resistance of the conductive channel formed by the N-type doped strip is lower.

[0067] In another embodiment of the present application, the doped strips 105 are P-type doped, and the doped polysilicon pillars 106 are N-type doped. The P-type doped strips 105 and the N-type drift region 102 form a multi-RESURF (reduced surface field) structure. During reverse withstand voltage testing of the device, the doped strips 105 at different depths within the drift region 102 can significantly assist in depleting the N-type impurities in the drift region 102, achieving an optimized breakdown voltage. At the same time, the longitudinal P-type doped polysilicon pillars within the drift region 102 can effectively increase the concentration of N-type impurity ions within the drift region 102, thereby reducing on-resistance.

[0068] After step S370 is completed, the remaining structures of the LDMOS device are formed (step S380). In one embodiment of the present application, step S380 can be manufactured according to the existing technology.

[0069] In one embodiment of the present application, step S380 includes:

[0070] A first conductivity type well region 109 is formed. The first conductivity type well region 109 serves as a drift region buffer layer at the drain end, increasing the on-state breakdown voltage of the LDMOS during forward operation and optimizing the forward conduction current. In this embodiment, the first conductivity type well region 109 is an N-well, and the second conductivity type well region 107 is a P-well.

[0071] A field oxide layer 112 is formed on the drift region 102 .

[0072] The gate 108 is formed. In this embodiment, the gate 108 is made of polysilicon and extends from the edge of the field oxide layer 112 so that the field oxide layer 112 overlaps the second conductivity type well region 107 .

[0073] The source region 104, the drain region 110 and the substrate lead-out region 103 are formed. By ion implantation, the source region 104 and the substrate lead-out region 103 are formed in the second conductivity type well region 107, and the drain region 110 is formed in the first conductivity type well region 109. In this embodiment, the source region 104 and the drain region 110 are N+ doped regions, and the substrate lead-out region 103 is a P+ doped region. Figure 11 .

[0074] An interlayer dielectric layer (ILD) is formed on the wafer surface obtained in the previous step.

[0075] Contact holes are formed by etching the structure that needs to be brought out to the device surface to form contact holes that penetrate the ILD.

[0076] Form the metal electrodes of gate, drain and source.

[0077] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0078] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A laterally diffused metal oxide semiconductor device, characterized in that: include: a substrate having a second conductivity type; a drift region, provided on the substrate, having a first conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; a multi-layer doping structure, provided in the drift region, each layer of the doping structure comprising at least one doping strip extending along the length direction of the conductive channel; a plurality of doped polysilicon pillars, disposed in the drift region and extending from top to bottom through the doped strips of the multi-layer doped structure, wherein the conductivity type of the doped ions in each of the doped polysilicon pillars is opposite to the conductivity type of the doped ions in each of the doped strips; The first conductivity type is N-type, the second conductivity type is P-type, each of the doped strips is P-type doped, and each of the doped polysilicon columns is N-type doped.

2. The laterally diffused metal oxide semiconductor device according to claim 1, wherein: Also includes: a source region having a first conductivity type; a drain region having a first conductivity type; A field oxide layer is provided on each of the doped polysilicon pillars, wherein the bottom of the field oxide layer contacts the top of each of the doped polysilicon pillars; a gate extending from a position of the field oxide layer adjacent to the source region toward the source region; The substrate lead-out region has the second conductivity type and is arranged on a side of the source region away from the gate.

3. The laterally diffused metal oxide semiconductor device according to claim 2, wherein: Each of the doped polysilicon columns extends downward from the bottom of the field oxide layer through each layer of doped strips and stops in the doped strip of the lowest layer.

4. The laterally diffused metal oxide semiconductor device according to claim 3, wherein: On the cross section of each layer of the doped structure, a plurality of mutually parallel doped strips are formed and the doped polysilicon columns are distributed in a matrix.

5. A laterally diffused metal oxide semiconductor device, characterized in that: include: a substrate having a second conductivity type; a drift region, provided on the substrate, having a first conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; a multi-layer doping structure provided in the drift region, each layer of the doping structure comprising at least one doping strip extending along the length direction of the conductive channel; a plurality of doped polysilicon pillars, disposed in the drift region and extending from top to bottom through the doped strips of the multi-layer doped structure, wherein the conductivity type of the doped ions in each of the doped polysilicon pillars is opposite to the conductivity type of the doped ions in each of the doped strips; Among them, the first conductivity type is N-type, the second conductivity type is P-type, each of the doped strips is N-type doped, each of the doped polysilicon columns is P-type doped, and the concentration of doped ions in each of the doped strips is greater than the concentration of doped ions in the drift region.

6. The laterally diffused metal oxide semiconductor device according to claim 5, characterized in that Also includes: a source region having a first conductivity type; a drain region having a first conductivity type; a field oxide layer, disposed on each of the doped polysilicon pillars, wherein the bottom of the field oxide layer contacts the top of each of the doped polysilicon pillars; a gate extending from a position of the field oxide layer adjacent to the source region toward the source region; The substrate lead-out region has the second conductivity type and is arranged on a side of the source region away from the gate.

7. The laterally diffused metal oxide semiconductor device according to claim 6, wherein: Each of the doped polysilicon columns extends downward from the bottom of the field oxide layer through each layer of doped strips and stops in the doped strip of the lowest layer.

8. The laterally diffused metal oxide semiconductor device according to claim 7, wherein: On the cross section of each layer of the doped structure, a plurality of mutually parallel doped strips are formed and the doped polysilicon columns are distributed in a matrix.

9. A method for manufacturing a laterally diffused metal oxide semiconductor device, comprising: Step A, obtaining a substrate having a drift region formed thereon, wherein the drift region has a first conductivity type and is formed on the substrate having a second conductivity type; The first conductivity type and the second conductivity type are opposite conductivity types, the first conductivity type is N type, and the second conductivity type is P type; Step B, etching a plurality of injection holes in the drift region; Step C, injecting dopant ions into the bottom of each injection hole; Step D, filling each of the injection holes with doped polysilicon, wherein the conductivity type of the doped polysilicon is opposite to the conductivity type of the doped ions, and the doped polysilicon is N-type doped; Step E, injecting dopant ions of opposite conductivity type to that of the doped polysilicon into the drift region at the top of the doped polysilicon in each of the injection holes; Repeating step D and step E for a preset number of times, and then filling the injection hole with the doped polysilicon, so that the doping ions injected in different times form doping regions of different depths in the drift region; In step F, the doped regions of the same depth are diffused by heat treatment to connect in the length direction of the conductive channel, thereby forming doped strips extending along the length direction of the conductive channel, wherein each doped strip is P-type doped.

10. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 9, wherein: The step D further includes: etching the doped polysilicon in each of the injection holes, with the etching depth being shallower than the previous etching of the injection holes, so that part of the doped polysilicon remains in the hole.

11. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 9, wherein: After step F, the method further includes: forming a field oxide layer above each of the injection holes; forming a gate; A source region of the first conductivity type, a drain region of the first conductivity type, and a substrate lead-out region of the second conductivity type are formed.

12. A method for manufacturing a laterally diffused metal oxide semiconductor device, comprising: Step A, obtaining a substrate having a drift region formed thereon, wherein the drift region has a first conductivity type and is formed on the substrate having a second conductivity type; The first conductivity type and the second conductivity type are opposite conductivity types, the first conductivity type is N type, and the second conductivity type is P type; Step B, etching a plurality of injection holes in the drift region; Step C, injecting dopant ions into the bottom of each injection hole; Step D, filling each of the injection holes with doped polysilicon, wherein the conductivity type of the doped polysilicon is opposite to the conductivity type of the doped ions, and the doped polysilicon is P-type doped; Step E, injecting dopant ions of opposite conductivity type to that of the doped polysilicon into the drift region at the top of the doped polysilicon in each of the injection holes; Repeating step D and step E for a preset number of times, and then filling the injection hole with the doped polysilicon, so that the doping ions injected in different times form doping regions of different depths in the drift region; Step F, through heat treatment, the doped regions of the same depth are diffused and connected in the length direction of the conductive channel to form doped strips extending along the length direction of the conductive channel, each of the doped strips is N-type doped, and the concentration of doped ions in each of the doped strips is greater than the concentration of doped ions in the drift region.

13. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 12, wherein: The step D further includes: etching the doped polysilicon in each of the injection holes, with the etching depth being shallower than the previous etching of the injection holes, so that part of the doped polysilicon remains in the hole.

14. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 12, wherein: After step F, the method further includes: forming a field oxide layer above each of the injection holes; forming a gate; A source region of the first conductivity type, a drain region of the first conductivity type, and a substrate lead-out region of the second conductivity type are formed.

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