High-power GaN RF devices based on gold-free processes and their fabrication methods

Abstract

This invention discloses a silicon-based gallium nitride high-power radio frequency device based on a gold-free process and its fabrication method. The fabrication method includes: obtaining and cleaning an epitaxial substrate, wherein the epitaxial substrate comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, and a barrier layer; etching mesa along the edge of the active region of the epitaxial substrate down to the buffer layer to form an active region isolation; etching patterned array trenches on the barrier layer and depositing an alloy ohmic metal in the patterned array trenches to form an ohmic pre-deposition layer; forming a source electrode and a drain electrode on the barrier layer, the source electrode and the drain electrode being located above the ohmic pre-deposition layer; forming a passivation layer on the barrier layer, the source electrode, and the drain electrode; forming a trapezoidal gate electrode on the barrier layer between the source electrode and the drain electrode; fabricating a back via and forming a complete source electrode interconnect layer and a passivation layer in the back via. This power device uses an ohmic pre-deposition layer and a gate with a tilted field plate to reduce contact resistance and improve the channel electric field distribution.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a silicon-based gallium nitride high-power radio frequency device based on a gold-free process and its fabrication method. This silicon-based gallium nitride high-power radio frequency device can be used in 5G base station systems, satellite navigation, and radar systems. Background Technology

[0002] Due to its large bandgap, high breakdown field strength, and the ability to form a high-concentration two-dimensional electron gas channel with AlGaN through heterojunction, GaN exhibits a higher breakdown voltage and lower on-resistance than Si and SiC, making AlGaN / GaN HEMTs (High Electron Mobility Transistors) highly advantageous in power switching applications. However, due to the poor thermal conductivity of sapphire and the high cost of SiC, high-power AlGaN / GaNHEMTs based on sapphire and SiC substrates are limited in power applications, necessitating the production of Si-based GaN HEMTs in low-cost, high-volume CMOS production lines. On one hand, current GaN-based HEMTs generally employ gold-containing processes, where Au diffusion into Si forms minority carrier recombination centers, making conventional GaN processes incompatible with CMOS processes. On the other hand, conventional GaN ohmic electrodes typically require annealing at temperatures above 800°C to form ohmic contacts; however, high-temperature annealing not only limits the compatibility of GaN processes with CMOS processes but also causes device reliability issues. The most critical issue is that Au-containing metal alloying causes surface roughening, which in turn leads to uneven current flow and affects device performance. Therefore, the development of CMOS-compatible gold-free processes based on GaN HEMTs is a key condition for realizing the fabrication of Si-based GaN HEMT devices in mature CMOS production lines.

[0003] Currently, both domestically and internationally, gold-containing processes are commonly used to fabricate SiC-based GaN devices, which can achieve higher power. However, these methods all have the following problems: (1) SiC-based GaN has a high cost per unit, and the small wafer size leads to low production capacity and low wafer fabrication efficiency; (2) SiC-based GaN using traditional gold-containing processes cannot be compatible with Si-based CMOS processes and cannot be heterogeneously integrated with Si-based CMOS control elements. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a silicon-based gallium nitride high-power radio frequency device based on a gold-free process and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] One aspect of the present invention provides a method for fabricating a silicon-based gallium nitride high-power radio frequency device based on a gold-free process, the method comprising:

[0006] An epitaxial substrate is obtained and cleaned. The epitaxial substrate includes, from bottom to top, a substrate, a nucleation layer, a buffer layer, and a barrier layer.

[0007] A mesa is etched at the edge of the active region of the epitaxial substrate down to the buffer layer to form an active region isolation.

[0008] Patterned array grooves are etched on the barrier layer, and an alloy ohmic metal is deposited in the patterned array grooves to form an ohmic pre-deposition layer;

[0009] A source electrode and a drain electrode are formed on the barrier layer, and the source electrode and the drain electrode are located above the ohmic pre-deposition layer;

[0010] A passivation layer is formed on the barrier layer, the source electrode, and the drain electrode;

[0011] A trapezoidal gate electrode is formed on the barrier layer between the source electrode and the drain electrode;

[0012] A back-through hole is formed on the back side of the substrate, and a metal interconnect layer and a passivation layer are formed in the back-through hole.

[0013] In one embodiment of the present invention, the substrate is a Si substrate, the nucleation layer is an AlN nucleation layer, the buffer layer is a GaN buffer layer, and the barrier layer is an AlGaN barrier layer.

[0014] In one embodiment of the present invention, etching patterned array grooves on the barrier layer and depositing an alloy ohmic metal in the patterned array grooves to form an ohmic pre-deposition layer includes:

[0015] Patterned array grooves are etched into the AlGaN barrier layer, wherein the patterned array grooves are two rows of grooves arranged in parallel on the AlGaN barrier layer, and the bottom surface shape of the patterned array grooves is square, circular or rhomboid.

[0016] The sample with patterned array groove etching completed was then subjected to a plasma stripper to remove the thin layer of photoresist that had not been properly developed.

[0017] An alloy metal is sputtered inside the patterned array grooves to form an ohmic pre-deposited layer, wherein the alloy ohmic metal is Si. x Ta y Al z alloy.

[0018] In one embodiment of the present invention, a source electrode and a drain electrode are formed on the barrier layer, the source electrode and the drain electrode being located above the ohmic pre-deposition layer, including:

[0019] Photoresist is applied to the AlGaN barrier layer and source electrode patterned regions and drain electrode patterned regions are photolithographically formed, wherein the source electrode patterned regions and the drain electrode patterned regions are respectively located above the patterned array grooves on the corresponding side.

[0020] An alloy ohmic metal is deposited in the source electrode pattern region, the drain electrode pattern region, and above the ohmic pre-deposition layer, and then annealed to form an ohmic contact.

[0021] In one embodiment of the present invention, depositing an alloy ohmic metal within the source electrode pattern region, the drain electrode pattern region, and above the ohmic pre-deposition layer, and annealing it to form an ohmic contact includes:

[0022] Remove the undeveloped photoresist film from the source electrode pattern area and the drain electrode pattern area:

[0023] A Ta contact layer, an Al catalyst layer, a Ta barrier layer, and a TaN cap layer are sequentially sputtered onto the upper surface of the barrier layer in the source electrode pattern region and the drain electrode pattern region.

[0024] The sputtered sample is annealed at 700°C for 60 seconds in a nitrogen atmosphere to allow the metal in the source electrode, the drain electrode, and the patterned array groove to sink into the GaN buffer layer, forming an ohmic contact.

[0025] In one embodiment of the present invention, a trapezoidal gate electrode is formed on the barrier layer between the source electrode and the drain electrode, comprising:

[0026] Photoresist is applied to the passivation layer, and a gate electrode pattern area is photolithographically formed between the source electrode and the drain electrode. The passivation layer below the electrode pattern area is removed to generate a tilted gate trench.

[0027] Gate electrode metal is deposited above the inclined gate groove to form a trapezoidal gate electrode that is narrow at the bottom and wide at the top, wherein the angle between the upper surface and the side surface of the gate electrode is 10° to 80°.

[0028] In one embodiment of the present invention, a back-through hole is formed on the back side of the substrate, and a metal interconnect layer and a passivation layer are formed in the back-through hole, including:

[0029] A back via is formed on the back side of the substrate, the back via extending from the lower surface of the substrate to the lower surface of the source electrode;

[0030] A Ti interface layer, a Cu conductive layer, and a W protective layer are sequentially grown inside the back through-hole to form a metal stack structure composed of three metal layers: Ti, Cu, and W.

[0031] A SiN passivation layer is formed on the metal stack structure.

[0032] Another aspect of the present invention provides a silicon-based gallium nitride high-power radio frequency device based on a gold-free process. The power device, from bottom to top, comprises a Si substrate layer, an AlN nucleation layer, a GaN buffer layer, and an AlGaN barrier layer.

[0033] The upper surface of the AlGaN barrier layer has two parallel rows of patterned array grooves. The upper surface of the AlGaN barrier layer is respectively provided with a source electrode and a drain electrode. The two rows of patterned array grooves are located below the source electrode and the drain electrode, respectively. An ohmic pre-deposited layer is provided in the patterned array grooves.

[0034] A passivation layer is disposed on the AlGaN barrier layer, the source electrode, and the drain electrode;

[0035] A trapezoidal gate electrode is formed on the passivation layer between the source electrode and the drain electrode;

[0036] A back via is formed on the back side of the Si substrate, extending from the lower surface of the Si substrate to the lower surface of the source electrode. A metal interconnect layer and a passivation layer are sequentially disposed within the back via.

[0037] In one embodiment of the present invention, the angle between the upper surface and the side surface of the gate electrode is 10° to 80°.

[0038] In one embodiment of the present invention, the alloy ohmic metal is Si. x Ta y Al z The alloy; the metal interconnect layer includes a Ti interface layer, a Cu conductive layer and a W protective layer deposited sequentially; the source electrode and the drain electrode each include a Ta contact layer, an Al catalyst layer, a Ta barrier layer and a TaN cap layer deposited sequentially; the gate electrode includes two metal layers, TiN and Pt, deposited sequentially.

[0039] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0040] 1. This invention utilizes Si x Ta y Al zAlloy ohmic pre-deposited layers can form ohmic contacts with low contact resistance and smooth, sharp surface morphology under low-temperature annealing, avoiding the problem of edge expansion after high-temperature annealing of ohmic contacts. Furthermore, due to the edge-concentration effect of ohmic electrodes, the current is mainly concentrated at the electrode edges. Therefore, etching a patterned array of AlGaN barrier layers in the source and drain ohmic edge regions can effectively increase the contact area between the metal layer and the barrier layer, improve the electron tunneling probability of the barrier layer at the etched deep holes, thereby reducing ohmic contact resistance, and significantly reduce damage to the 2EDG. This results in high-current, low-resistance, gold-free ohmic contacts, greatly reducing contact resistance, thus consistently lowering the device knee voltage, improving power-added efficiency, increasing saturation current, and significantly improving efficiency and power density.

[0041] 2. This invention uses an ICP device to dry etch tilted gate trenches and then adjusts the relative height between the electron beam evaporation source and the sample on an electron beam evaporation stage to change the direction of metal inflow to prepare a gate electrode with a tilted field plate. This increases the breakdown voltage while reducing parasitic capacitance, increasing the current gain cutoff frequency (fT) and power gain cutoff frequency (fMAX) of the device, and significantly improving the operating voltage, making it suitable for high-power applications.

[0042] 3. This invention uses back-through-hole technology to reduce the grounding inductance of the device and increase grounding flexibility, while reducing the impact of source parasitic parameters on device performance. It is suitable for source interconnection of high-power devices and microwave devices.

[0043] 4. This invention adopts a complete set of gold-free processes, is compatible with Si-based CMOS production lines, can greatly improve production capacity, and can be heterogeneously integrated with Si-based CMOS control elements in the future.

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0045] Figure 1 This is a flowchart of a method for fabricating a silicon-based gallium nitride high-power radio frequency device based on a gold-free process, provided by an embodiment of the present invention.

[0046] Figures 2a to 2k A schematic diagram of the fabrication process of a silicon-based gallium nitride high-power radio frequency device based on a gold-free process is provided in this embodiment of the invention;

[0047] Figure 3 This is a schematic diagram of the structure of a silicon-based gallium nitride high-power radio frequency device based on a gold-free process, provided in an embodiment of the present invention;

[0048] Figure 4 This is a top view of several ohmic contact selection area graphical arrays provided in the embodiments of the present invention. Detailed Implementation

[0049] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of a silicon-based gallium nitride high-power radio frequency device based on a gold-free process and its fabrication method.

[0050] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0052] Example 1

[0053] Please see Figure 1 , Figures 2a to 2k , Figure 1 This is a flowchart illustrating a method for fabricating a silicon-based gallium nitride high-power radio frequency device based on a gold-free process, according to an embodiment of the present invention. Figures 2a to 2k This invention provides a schematic diagram of the fabrication process for a silicon-based gallium nitride high-power radio frequency device based on a gold-free process. The fabrication method of this embodiment includes:

[0054] S1: Obtain an epitaxial substrate and clean it. The epitaxial substrate includes, from bottom to top, a substrate, a nucleation layer, a buffer layer and a barrier layer.

[0055] Specifically, the device in this embodiment is fabricated on an epitaxial substrate containing a substrate, a nucleation layer, a buffer layer, and a barrier layer, wherein the substrate, nucleation layer, buffer layer, and barrier layer are arranged sequentially from bottom to top. The substrate is a Si substrate, the nucleation layer is an AlN nucleation layer, the buffer layer is a GaN buffer layer, and the barrier layer is an AlGaN barrier layer, as shown below. Figure 2a As shown.

[0056] The epitaxial substrate was placed in acetone and sonicated for 2 minutes, then boiled in a positive stripping solution heated in a 60°C water bath for 10 minutes. Next, the epitaxial substrate was placed in acetone and ethanol and sonicated for 3 minutes each, and then rinsed with deionized water to remove residual acetone and ethanol. Finally, it was rinsed with HF solution for 30 seconds, then rinsed with deionized water and dried with ultrapure nitrogen.

[0057] S2: Etch the mesa at the edge of the active region of the epitaxial substrate down to the buffer layer to form an active region isolation.

[0058] In this embodiment, etching is performed using an ICP (Inductive Coupled Plasma) device.

[0059] Specifically, S2 includes:

[0060] S21: Photolithographically etch an electrically isolated region on the barrier layer of the epitaxial substrate:

[0061] First, the epitaxial substrate containing the substrate, nucleation layer, buffer layer, and barrier layer is baked on a hot plate at 200°C for 5 minutes. Then, the epitaxial substrate is spun with photoresist at a spin coater speed of 3500 rpm. After spin coating, it is baked on a hot plate at 90°C for 1 minute. The epitaxial substrate is then placed in a photolithography machine to expose the photoresist in the electrically isolated area. Finally, the exposed epitaxial substrate is placed in a developing solution to remove the photoresist in the electrically isolated area, and then rinsed with ultrapure water and dried with nitrogen.

[0062] S22: Etching the electrically isolated region on the AlGaN barrier layer:

[0063] For the photolithography-completed sample, the edge of the AlGaN barrier layer to the GaN buffer layer was etched using the ICP process to achieve mesa isolation of the active region. The etching gas used was Cl2 / BCl3, the pressure was 5 mTorr, the upper electrode power was 100 W, the lower electrode power was 10 W, and the etching time was 40 s.

[0064] S23: Remove residual photoresist after etching.

[0065] The sample with the etched electrical isolation region was sequentially immersed in acetone solution, stripping solution, acetone solution, and ethanol solution for cleaning to remove the photoresist outside the electrical isolation region. It was then rinsed with deionized water and dried with nitrogen gas. Figure 2b As shown.

[0066] S3: Etch patterned array grooves on the barrier layer and deposit alloy ohmic metal in the patterned array grooves to form an ohmic pre-deposition layer.

[0067] In this embodiment, a patterned array pattern is photolithographically etched on the AlGaN barrier layer, and a patterned array groove is etched. Then, an alloy metal is deposited in the patterned array groove using a sputter magnetron sputtering or electron beam evaporation process to form an ohmic pre-deposition layer.

[0068] Specifically, S3 includes:

[0069] S31: Photolithographically patterned array region on the barrier layer

[0070] Specifically, the sample with the completed mesa etching is baked on a hot plate at 200°C for 5 minutes; a stripper is applied to the sample and baked on a hot plate at 200°C for 5 minutes, with a stripper thickness of 0.35 μm; then photoresist is applied again to the sample and baked on a hot plate at 90°C for 1 minute, with this time the stripper thickness of 0.77 μm; the sample is placed in a lithography machine to expose the photoresist in the patterned area; the exposed sample is placed in a developer to remove the photoresist and stripper in the patterned area, and then rinsed with ultrapure water and dried with nitrogen.

[0071] S32: Patterned array of grooves are etched into the AlGaN barrier layer.

[0072] For the photolithographically completed sample, using a mask with patterned array vias at corresponding positions, the barrier layer is dry-etched using ICP process to achieve patterned array groove etching in the ohmic region. The etching gas used is Cl2 / BCl3, with a BCl3 flow rate of 20 sccm, a Cl2 flow rate of 8 sccm, a pressure of 5 mTorr, an upper electrode power of 50 W, a lower electrode power of 15 W, and an etching time of 60 s. Figure 2c As shown. It should be noted that the patterned array of grooves consists of two parallel rows of grooves arranged on the AlGaN barrier layer. The shape of the grooves can be square, circular, or rhomboid. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a top view of several ohmic contact selection area graphical arrays provided in the embodiments of the present invention.

[0073] S33: Base coat

[0074] After patterned array photolithography and etching, the undeveloped photoresist layer in the patterned area is removed using a plasma stripper. The processing time is 5 minutes, which greatly improves the yield of the stripped product.

[0075] S34: Sputter alloy metal inside the patterned array grooves to form an ohmic pre-deposited layer.

[0076] Specifically, the sample after plasma resist removal is placed in the Sputter magnetron sputtering stage, and the vacuum level in the reaction chamber of the magnetron sputtering stage reaches 2×10⁻⁶.-6 Following the Torr process, a 20nm thick Si layer is sputtered within the patterned array recesses. x Ta y Al z Alloy ohmic pre-deposited layer, where x, y, z are the atomic ratios of different elements.

[0077] In other embodiments, the pre-deposited layer may also be Si, Ge, or Si. x Ge y Si x Ti y or Si x Ti y Al z .

[0078] S35: Stripping Metal

[0079] Specifically, the patterned array sputtered sample is immersed in acetone for at least 40 minutes and then ultrasonically treated; the sample is then placed in a stripping solution at 60°C and heated in a water bath for 5 minutes; subsequently, the sample is ultrasonically cleaned in acetone and ethanol solutions sequentially for 3 minutes each; the sample is then rinsed with ultrapure water and dried with nitrogen gas. Figure 2d As shown.

[0080] S4: A source electrode and a drain electrode are formed on the barrier layer, the source electrode and the drain electrode being located above the ohmic pre-deposition layer.

[0081] Further, S4 includes:

[0082] S41: Apply photoresist to the AlGaN barrier layer and photolithographically pattern the source electrode and drain electrode patterns.

[0083] Specifically, the sample with patterned array alloy ohmic metal deposition completed is baked on a hot plate at 200°C for 5 minutes; then, stripping adhesive is applied to the sample and the sample is baked on a hot plate at 200°C for 5 minutes, with a stripping thickness of 0.35 μm; next, photoresist is applied to the sample again and the sample is baked on a hot plate at 90°C for 1 minute, with a stripping thickness of 0.77 μm; then, the sample is placed in a lithography machine to expose the photoresist in the source and drain electrode regions; finally, the exposed sample is placed in a developing solution to remove the photoresist and stripping adhesive in the source and drain electrode regions, and then rinsed with ultrapure water and dried with nitrogen.

[0084] S42: Deposit alloy ohmic metal over the ohmic pre-deposited layer in the source electrode patterned region, the drain electrode patterned region, and the patterned array groove, and anneal to form ohmic contacts.

[0085] In this embodiment, sputter magnetron sputtering or electron beam evaporation is used to deposit the alloy ohmic metal. Specifically, step S42 includes:

[0086] S421: Base coat

[0087] The sample with completed source and drain electrode areas photolithography is used to remove the thin layer of photoresist that has not been developed in the patterned area using a plasma stripper. The processing time is 5 minutes, which greatly improves the yield of the stripped product.

[0088] S422: Sputtering source electrode metal and drain electrode metal

[0089] The sample after plasma stripping is placed in the Sputter magnetron sputtering stage. The vacuum level in the reaction chamber of the magnetron sputtering stage reaches 2 × 10⁻⁶. -6 Following the Torr process, the following layers are sequentially sputtered onto the barrier layers within the source and drain electrode pattern regions: a 20 nm thick Ta contact layer, a 20 nm thick Al catalyst layer, a 30 nm thick Ta barrier layer, and a 60 nm thick TaN cap layer. Figure 2e As shown.

[0090] In other embodiments, the contact layer metal may also be selected as Ti, Ti x Al y Or Ta x Al y The barrier layer metal can also be selected as Ti, Ni or Mo, and the cap layer metal can also be selected as TiN, TiW, W or TiC.

[0091] S423: Stripping Metal and Annealing

[0092] Specifically, the sample with sputtered source and drain electrodes is immersed in acetone for more than 40 minutes and then ultrasonically treated. Subsequently, the sample is placed in a stripping solution at 60°C and heated in a water bath for 5 minutes. The sample is then ultrasonically cleaned in acetone and ethanol solutions for 3 minutes in sequence. The sample is rinsed with ultrapure water and dried with nitrogen. Next, the sample is placed in a rapid annealing furnace, and nitrogen is introduced into the furnace for 10 minutes. The furnace temperature is set to 700°C in a nitrogen atmosphere and subjected to high-temperature annealing for 60 seconds. This allows the ohmic metal on the source, drain electrodes, and patterned array region to sink to the GaN buffer layer, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel, thus forming the source and drain electrodes.

[0093] S5: A SiN thin film is deposited on the barrier layer using plasma-enhanced chemical vapor deposition (PECVD) to form a SiN passivation layer, such as... Figure 2g As shown.

[0094] Specifically, step S5 includes:

[0095] S51: Perform surface cleaning on the sample after completing the source-drain ohmic contact.

[0096] First, the sample was ultrasonically cleaned in acetone solution for 3 minutes with an ultrasonic intensity of 3.0. Then, the sample was heated in a water bath at 60°C for 5 minutes. Next, the sample was ultrasonically cleaned in acetone solution and ethanol solution for 3 minutes in sequence with an ultrasonic intensity of 3.0. Finally, the sample was rinsed with ultrapure water and dried with nitrogen.

[0097] S52: A 60 nm thick SiN passivation layer is grown on the barrier layer, source electrode, and drain electrode using plasma-enhanced chemical vapor deposition (PECVD). The growth process conditions are as follows: NH3 and SiH4 are used as Si source and N source, respectively, with a preferred flow ratio of SiH4:NH3 = 2:1, a deposition temperature of 250 °C, a reaction chamber pressure of 600 mTorr, an RF power of 22 W, and a reaction time of 7.5 min.

[0098] S6: A trapezoidal gate electrode is formed on the barrier layer between the source electrode and the drain electrode.

[0099] Further, S6 includes:

[0100] S61: Photoresist is applied to the SiN passivation layer and the gate trench pattern is photolithographically formed. The passivation layer in the exposed area is removed by dry etching using an ICP device to generate a tilted gate trench.

[0101] Specifically, S611: Photolithographically etch the gate trench region on the passivation layer:

[0102] First, the sample was baked on a hot plate at 200°C for 5 minutes. Then, a stripper was applied to the passivation layer, and the sample was baked on a hot plate at 200°C for 5 minutes, with a stripper thickness of 0.35 μm. Next, photoresist was applied to the sample, and the sample was baked on a hot plate at 90°C for 1 minute, with a stripper thickness of 0.77 μm. Afterward, the sample was placed in a lithography machine to expose the photoresist in the gate trench area. Finally, the exposed sample was placed in a developing solution to remove the photoresist and stripper in the gate trench area, and then rinsed with ultrapure water and dried with nitrogen.

[0103] S612: Dry etching produces tilted gate trenches

[0104] The passivation layer at the location of the gate electrode is removed by dry etching using an ICP device to expose the barrier layer and form an inclined gate trench. The etching reaction gas is CF4 with a flow rate of 30 sccm, the reaction chamber pressure is 10 mTorr, and the RF power of the upper and lower electrodes is 100 W and 0 W, respectively.

[0105] S613: Base coat

[0106] After the gate electrode photolithography is completed, the undeveloped photoresist layer in the patterned area is removed using a plasma stripper. The processing time is 5 minutes.

[0107] S62: Employing electron beam evaporation technology, by altering the relative height between the electron beam evaporation source and the sample, the direction of metal inflow is changed, depositing gate metal above the tilted gate trench to form a tilted field gate. Subsequently, the photoresist is removed. Figure 2h As shown.

[0108] Specifically, step S62 includes:

[0109] S621: Evaporation gate electrode metal

[0110] The sample with the completed grid openings is placed in the E-beam electron beam evaporation stage, and the vacuum level in the reaction chamber of the evaporation stage is brought to 1×10⁻⁶. -6 After the torsion, the relative height between the electron beam evaporation source and the sample is changed, and the gate metal is evaporated on the sample gate electrode region and the photoresist outside the gate electrode region on the rotating plating disk at a tilt angle of 15°. The gate metal is a metal stack structure composed of two metal layers, 80nm TiN and 50nm Pt, arranged sequentially from bottom to top.

[0111] In other embodiments, the contact layer of the gate electrode may also be selected as Ni, Ti, Ta, TixAly or TaxAly, and the cap layer may also be selected as TiN, TiW, W, TiC or TaN.

[0112] S622: Stripping Metal

[0113] After the sample with the gate electrode sputtered was immersed in acetone for more than 40 minutes, it was ultrasonically treated; then it was placed in a stripping solution at 60°C and heated in a water bath for 5 minutes; then it was ultrasonically cleaned in acetone solution and ethanol solution for 3 minutes in sequence; finally, the sample was rinsed with ultrapure water and dried with nitrogen.

[0114] S7: A back-through hole is formed on the back side of the substrate, and a metal interconnect layer and a passivation layer are formed in the back-through hole to complete the source electrode interconnection and interconnect layer passivation.

[0115] Specifically, step S7 includes:

[0116] S71: Create a through hole

[0117] First, the front side of the sample is bonded to the carrier using high-temperature paraffin to protect the front pattern and ensure that the substrate will not crack during subsequent back-side processes after thinning.

[0118] Next, the substrate thickness is first reduced to near the target thickness through coarse grinding (generally 100µm more than the target thickness is sufficient), and then fine grinding is performed to adjust the substrate thickness to 100µm. After grinding, polishing is required to improve the surface smoothness and flatness of the polished wafer.

[0119] Subsequently, the back via pattern is photolithographically patterned, and a release agent with a thickness of 0.35mm is applied to the back of the sample. Then, a negative photoresist with a thickness of 0.77mm is applied to the sample, and the sample is baked on a 90° hot plate for 1 minute. After that, the sample is placed in a photolithography machine to expose the photoresist in the back via area. Finally, the exposed sample is placed in a developing solution to remove the photoresist and release agent in the non-back via areas, and then rinsed with ultrapure water and dried with nitrogen.

[0120] Afterwards, the sample with the photolithographic pattern is placed in a plasma stripper for 5 minutes for bottom film treatment. The sample is then placed in a Supper magnetron sputtering machine to sputter 300nm of Ni. A low current density electroplating process is used to thicken the nickel layer to more than 5um as a hard mask. The sputtered sample is then stripped of metal to remove the Ni metal in the back via area.

[0121] Subsequently, back-through etching was performed using an ICP dry etching machine. The wafer was placed in the reaction chamber and cleaned by N2 purging. The N2 flow rate was 1200 sccm. SF6 source was introduced with an SF6 flow rate of 80 sccm and a pressure of 15 mTorr. The upper electrode power was 300 W, the lower electrode power was 100 W, and the DC bias voltage was 130 V.

[0122] Finally, the Ni metal mask is etched using a 3:1 mixture of concentrated nitric acid and hydrogen peroxide. The sample is then rinsed with ultrapure water and dried with nitrogen gas. This completes the fabrication of the back-side via. Figure 2i As shown.

[0123] S72: Source electrode interconnect

[0124] First, interconnect photolithography is performed on the sample. The sample is baked on a hot plate at 200°C for 5 minutes; then, a release agent is sprayed onto the back of the sample to a thickness of 0.35 μm, and the sample is baked on a hot plate at 200°C for 5 minutes; next, photoresist is sprayed onto the back of the sample to a thickness of 0.77 μm, and the sample is baked on a hot plate at 90°C for 1 minute.

[0125] Next, the sample is placed in a lithography machine to expose the photoresist in the interconnect area;

[0126] Afterward, the exposed sample is placed in the developer to remove the photoresist and stripper in the interconnect area, and then rinsed with ultrapure water and dried with nitrogen.

[0127] Then, the sample with the metal interconnect photolithography pattern is placed in a plasma resist stripper for 5 minutes for underfilm treatment; then, the sample after underfilm treatment is placed in a magnetron sputtering instrument until the vacuum degree of the reaction chamber reaches 2×10⁻⁶. 6 Following the torsion process, a 10 nm Ti interface layer, a 100 nm Cu conductive layer, and a 30 nm W protective layer were sequentially deposited on the electrodes within the interconnect metal region and on the photoresist outside the metal interconnect region using magnetron sputtering, forming a metal stack structure consisting of three layers of metal from bottom to top: Ti, Cu, and W. The sample after interconnect metal sputtering was then stripped to remove the interconnect metal, photoresist, and release adhesive outside the metal interconnect layer region, while also removing the front-side protective adhesive; the sample was then rinsed with ultrapure water and dried with nitrogen.

[0128] Finally, a 60 nm thick SiN passivation layer was grown on the metal interconnect layer using plasma-enhanced chemical vapor deposition (PECVD). The growth conditions were as follows: NH3 and SiH4 were used as the Si and N sources, respectively, with an optimized flow ratio of SiH4:NH3 = 2:1; the deposition temperature was 250 °C; the reaction chamber pressure was 600 mTorr; the RF power was 22 W; and the reaction time was 7.5 min.

[0129] It should be noted that, in this embodiment, the Ta-based ohmic contact exhibits excellent performance in terms of solid-state reactions and surface morphology between metals, through Si x Ta y Al z Si prepared by alloy target or Si, Ta, Al co-sputtering x Ta y Al z The alloy ohmic pre-deposited layer can form ohmic contacts with low contact resistance and smooth, sharp surface morphology under low-temperature annealing. Furthermore, due to the edge-concentration effect of ohmic electrodes, the current is mainly concentrated at the electrode edges. Therefore, by etching a patterned array of AlGaN barrier layers in the source and drain ohmic edge regions, it is possible to effectively increase the contact area between the metal layer and the barrier layer, improve the electron tunneling probability of the barrier layer at the etched deep holes, thereby reducing the ohmic contact resistance, and significantly reduce damage to the 2EDG. This allows for the formation of high-current, low-resistance, gold-free ohmic contacts.

[0130] The high critical breakdown electric field is a key reason why GaN-based HEMTs can be used in power devices; their breakdown voltage largely depends on the electric field spike generated at the gate edge near the drain. Typically, using a gate with a tilted field plate (i.e., a trapezoidal gate electrode that is wider at the top and narrower at the bottom) can reduce the peak electric field, thereby increasing the breakdown voltage of GaN-based HEMTs. Employing a gate with a tilted field plate improves the channel electric field distribution, increasing the breakdown field strength of GaN-based HEMTs while reducing parasitic capacitance, and increasing the current gain cutoff frequency (fT) and power gain cutoff frequency (fMAX), making it suitable for power devices with large gate widths. Therefore, combining patterned array ohmic contacts and a tilted field plate can realize high-power, high-breakdown, CMOS-compatible high-power RF devices.

[0131] In summary, this embodiment utilizes Si x Ta y Al z Alloy ohmic pre-deposited layers can form ohmic contacts with low contact resistance and smooth, sharp surface morphology under low-temperature annealing, avoiding the problem of edge expansion after high-temperature annealing of ohmic contacts. Furthermore, due to the edge-concentration effect of ohmic electrodes, the current is mainly concentrated at the electrode edges. Therefore, etching a patterned array of AlGaN barrier layers in the source and drain ohmic edge regions can effectively increase the contact area between the metal layer and the barrier layer, improve the electron tunneling probability of the barrier layer at the etched deep holes, thereby reducing ohmic contact resistance, and significantly reduce damage to the 2EDG. This results in high-current, low-resistance, gold-free ohmic contacts, greatly reducing contact resistance, thus consistently lowering the device knee voltage, improving power-added efficiency, increasing saturation current, and significantly improving efficiency and power density. This embodiment fabricates a gate electrode with a tilted field plate by dry etching a tilted gate trench using ICP equipment and then adjusting the relative height between the electron beam evaporation source and the sample on an electron beam evaporation stage to change the direction of metal inflow. This improves the breakdown voltage while reducing parasitic capacitance, increasing the current gain cutoff frequency (fT) and power gain cutoff frequency (fMAX) of the device, and significantly improving the operating voltage, making it suitable for high-power applications. Furthermore, this invention employs through-hole technology to reduce the device's grounding inductance and increase grounding flexibility, while also reducing the impact of source parasitic parameters on device performance. This makes it suitable for source interconnects in high-power devices and microwave devices. This embodiment utilizes a completely gold-free process, making it compatible with Si-based CMOS production lines, which can greatly increase production capacity and allows for subsequent heterogeneous integration with Si-based CMOS control elements.

[0132] Example 2

[0133] Based on the above embodiments, this embodiment provides a silicon-based gallium nitride high-power radio frequency device based on a gold-free process. Please refer to... Figure 3 , Figure 3This is a schematic diagram of the structure of a silicon-based gallium nitride high-power radio frequency device based on a gold-free process, provided by an embodiment of the present invention. The silicon-based gallium nitride high-power radio frequency device of this embodiment includes a Si substrate layer 1, an AlN nucleation layer 2, a GaN buffer layer 3, and an AlGaN barrier layer 4 arranged sequentially from bottom to top. The upper surface of the AlGaN barrier layer 4 has two parallel rows of patterned array grooves 5. A source electrode 6 and a drain electrode 7 are respectively disposed on both sides of the upper surface of the AlGaN barrier layer 4. The two rows of patterned array grooves 5 are located below the source electrode 6 and the drain electrode 7, and an ohmic pre-deposition layer 5 is disposed within the patterned array grooves 5. A passivation layer 8 is disposed on the AlGaN barrier layer 4, the source electrode 6, and the drain electrode 7. A trapezoidal gate electrode 9 is formed on the passivation layer 8 between the source electrode 6 and the drain electrode 7. A back via 10 is fabricated on the back side of the Si substrate layer 1, extending from the lower surface of the Si substrate 1 to the lower surface of the source electrode 6. A metal interconnect layer 11 and a passivation layer 12 are sequentially disposed within the back via 10.

[0134] Furthermore, the angle between the upper surface and the side surface of the gate electrode is 10° to 80°.

[0135] Furthermore, the alloy ohmic metal is Si. x Ta y Al z The alloy; the metal interconnect layer 11 includes a Ti interface layer, a Cu conductive layer and a W protective layer deposited sequentially; the source electrode 6 and the drain electrode 7 both include a Ta contact layer, an Al catalyst layer, a Ta barrier layer and a TaN cap layer deposited sequentially; the gate electrode 9 includes two metal layers, TiN and Pt, deposited sequentially.

[0136] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a silicon-based gallium nitride high-power radio frequency device based on a gold-free process, characterized in that, The preparation method includes: An epitaxial substrate is obtained and cleaned. The epitaxial substrate comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, and a barrier layer. The substrate is a Si substrate, the nucleation layer is an AlN nucleation layer, the buffer layer is a GaN buffer layer, and the barrier layer is an AlGaN barrier layer. A mesa is etched at the edge of the active region of the epitaxial substrate down to the buffer layer to form an active region isolation. Patterned array grooves are etched into the AlGaN barrier layer, wherein the patterned array grooves are two rows of grooves arranged in parallel on the AlGaN barrier layer, and the bottom surface shape of the patterned array grooves is square, circular or rhomboid. The sample with patterned array groove etching completed was then subjected to a plasma stripper to remove the thin layer of photoresist that had not been properly developed. An alloy metal is sputtered inside the patterned array grooves to form an ohmic pre-deposited layer, wherein the alloy ohmic metal is Si. x Ta y Al z alloy; A source electrode and a drain electrode are formed on the barrier layer, and the source electrode and the drain electrode are located above the ohmic pre-deposition layer; A passivation layer is formed on the barrier layer, the source electrode, and the drain electrode; A trapezoidal gate electrode is formed on the barrier layer between the source electrode and the drain electrode; A back-through hole is formed on the back side of the substrate, and a metal interconnect layer and a passivation layer are formed in the back-through hole.

2. The method for fabricating a silicon-based gallium nitride high-power radio frequency device based on a gold-free process according to claim 1, characterized in that, A source electrode and a drain electrode are formed on the barrier layer, the source electrode and the drain electrode being located above the ohmic pre-deposition layer, including: Photoresist is applied to the AlGaN barrier layer and source electrode patterned regions and drain electrode patterned regions are photolithographically formed, wherein the source electrode patterned regions and the drain electrode patterned regions are respectively located above the corresponding patterned array grooves; An alloy ohmic metal is deposited in the source electrode pattern region, the drain electrode pattern region, and above the ohmic pre-deposition layer, and then annealed to form an ohmic contact.

3. The method for fabricating a silicon-based gallium nitride high-power radio frequency device based on a gold-free process according to claim 2, characterized in that, Depositing an alloy ohmic metal within the source electrode pattern region, the drain electrode pattern region, and above the ohmic pre-deposition layer, followed by annealing to form an ohmic contact, includes: Remove the undeveloped photoresist film from the source electrode pattern area and the drain electrode pattern area: A Ta contact layer, an Al catalyst layer, a Ta barrier layer, and a TaN cap layer are sequentially sputtered onto the upper surface of the barrier layer in the source electrode pattern region and the drain electrode pattern region. The sputtered sample is annealed at 700°C for 60 seconds in a nitrogen atmosphere to allow the metal in the source electrode, the drain electrode, and the patterned array groove to sink into the GaN buffer layer, forming an ohmic contact.

4. The method for fabricating a silicon-based gallium nitride high-power radio frequency device based on a gold-free process according to claim 1, characterized in that, A trapezoidal gate electrode is formed on the barrier layer between the source electrode and the drain electrode, comprising: Photoresist is applied to the passivation layer, and a gate electrode pattern area is photolithographically formed between the source electrode and the drain electrode. The passivation layer below the electrode pattern area is removed to generate a tilted gate trench. Gate electrode metal is deposited above the inclined gate groove to form a trapezoidal gate electrode that is narrow at the bottom and wide at the top, wherein the angle between the upper surface and the side surface of the gate electrode is 10° to 80°.

5. The method for fabricating a silicon-based gallium nitride high-power radio frequency device based on a gold-free process according to any one of claims 1 to 4, characterized in that, A back-through hole is formed on the back side of the substrate, and a metal interconnect layer and a passivation layer are formed in the back-through hole, including: A back via is formed on the back side of the substrate, the back via extending from the lower surface of the substrate to the lower surface of the source electrode; A Ti interface layer, a Cu conductive layer, and a W protective layer are sequentially grown inside the back through-hole to form a metal stack structure composed of three metal layers: Ti, Cu, and W. A SiN passivation layer is formed on the metal stack structure.

6. A silicon-based gallium nitride high-power radio frequency device based on a gold-free process, characterized in that, The silicon-based gallium nitride high-power radio frequency device comprises, from bottom to top, a Si substrate layer (1), an AlN nucleation layer (2), a GaN buffer layer (3), and an AlGaN barrier layer (4), wherein, The upper surface of the AlGaN barrier layer (4) has two parallel rows of patterned array grooves (5). The upper surface of the AlGaN barrier layer (4) is provided with a source electrode (6) and a drain electrode (7). The two rows of patterned array grooves (5) are located below the source electrode (6) and the drain electrode (7), and an ohmic pre-deposited layer is provided in the patterned array grooves (5). A passivation layer (8) is provided on the AlGaN barrier layer (4), the source electrode (6) and the drain electrode (7); A trapezoidal gate electrode (9) is formed on the passivation layer (8) between the source electrode (6) and the drain electrode (7); A back via (10) is formed on the back side of the Si substrate (1). The back via (10) extends from the lower surface of the Si substrate (1) to the lower surface of the source electrode (6). A metal interconnect layer (11) and a passivation layer (12) are sequentially disposed in the back via (10).

7. The silicon-based gallium nitride high-power radio frequency device based on a gold-free process according to claim 6, characterized in that, The angle between the upper surface and the side surface of the gate electrode is 10° to 80°.

8. The silicon-based gallium nitride high-power radio frequency device based on a gold-free process according to claim 6 or 7, characterized in that, The alloy ohmic metal of the ohmic pre-deposited layer is Si. x Ta y Al z Alloy; the metal interconnect layer (11) includes a Ti interface layer, a Cu conductive layer and a W protective layer deposited sequentially; the source electrode (6) and the drain electrode (7) both include a Ta contact layer, an Al catalyst layer, a Ta barrier layer and a TaN cap layer deposited sequentially; the gate electrode (9) includes two metal layers, TiN and Pt, deposited sequentially.

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