Light emitting display apparatus and multi-screen display apparatus including the same

Abstract

A light emitting display apparatus includes a plurality of pixels arranged along a first direction and a second direction different from the first direction over a first substrate; a circuit layer including a pixel common voltage line disposed between the plurality of pixels in parallel with the second direction and along the first direction; a light emitting device layer including a self-light emitting device disposed on the circuit layer and a common electrode disposed on the self-light emitting device; a common electrode connection part electrically coupling the pixel common voltage line to the common electrode; and an internal isolation part surrounding the common electrode connection part and isolating the self-light emitting device disposed on the internal isolation part.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0189783, filed on December 31, 2020, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a light-emitting display device and a multi-screen display device including the light-emitting display device. Background Art

[0004] Unlike liquid crystal displays (LCDs), emissive display devices, as self-luminous display devices, do not require a separate light source, allowing them to be manufactured light and thin. Furthermore, emissive display devices are driven by low voltage, reducing power consumption. Furthermore, emissive display devices excel in color realization, response time, viewing angle, and contrast, making them a highly anticipated next-generation emissive display device.

[0005] The light-emitting display device displays an image based on the light emission of a light-emitting device layer including a light-emitting device interposed between two electrodes. In this case, the light emitted by the light-emitting device is released to the outside through the electrodes and the substrate.

[0006] A light-emitting display device includes a display panel configured to display an image. The display panel may include a display area including a plurality of pixels for displaying the image, an encapsulation layer including an organic encapsulation layer disposed in the display area, a dam for preventing diffusion of the encapsulation layer, and a frame area surrounding the display area.

[0007] The light-emitting display device in the related art may require a frame (or mechanism) for enclosing a frame area provided at the edge (or peripheral portion) of the display panel, and the frame width may increase due to the width of the frame. Furthermore, if the frame width of the light-emitting display device is significantly reduced, the reliability of the display panel may be reduced due to degradation of the light-emitting device caused by water penetration, and the reliability of the display panel may be reduced due to the lack of filling of the organic light-emitting layer or the overflow of the organic light-emitting layer.

[0008] Recently, a multi-display device that realizes a large screen by arranging a plurality of light-emitting display devices in a lattice type has been commercialized.

[0009] However, in related art multi-screen light-emitting display devices, due to the frame area or frame of each of the multiple light-emitting display devices, a boundary portion such as a seam is formed between adjacent light-emitting display devices. When an image is displayed on the entire screen of the multi-screen light-emitting display device, the boundary portion causes a sense of discontinuity (or discontinuity) in the image, and for this reason, the immersion of the viewer viewing the image may be reduced. Summary of the Invention

[0010] Accordingly, the present invention is directed to a light-emitting display device and a multi-screen display device including the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0011] One aspect of the present disclosure is to provide a light-emitting display device that minimizes reliability degradation of a light-emitting display panel caused by water penetration and has a zero bezel width, and a multi-screen display device including the same.

[0012] Another aspect of the present disclosure is to provide a light-emitting display device having a zero border width and minimizing reliability degradation caused by water penetration through a connection portion between a common electrode and a pixel common voltage line, and a multi-screen display device including the light-emitting display device.

[0013] Additional advantages and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to one of ordinary skill in the art after studying the following or may be learned by practice of the present invention.

[0014] These objectives and other advantages of the present invention may be realized and attained by the structure particularly pointed out in the description and claims hereof as well as the appended drawings.

[0015] To achieve these and other advantages and in accordance with the intent of the present invention, as embodied and generally described herein, a light-emitting display device includes: a plurality of pixels arranged along a first direction and a second direction different from the first direction on a first substrate; a circuit layer, the circuit layer including a pixel common voltage line parallel to the second direction and arranged between the plurality of pixels along the first direction; a light-emitting device layer, the light-emitting device layer including a self-luminous device arranged on the circuit layer and a common electrode arranged on the self-luminous device; a common electrode connecting portion for electrically coupling the pixel common electrode line to the common electrode; and an internal isolation portion, the internal isolation portion surrounding the common electrode connecting portion and isolating the self-luminous device arranged on the internal isolation portion.

[0016] In another aspect of the present disclosure, a multi-screen display device includes: a plurality of display devices arranged along at least one of a first direction and a second direction intersecting the first direction, each of the plurality of display devices including a light-emitting display device, and the light-emitting display device including: a plurality of pixels arranged along the first direction and the second direction on a first substrate; a circuit layer including a pixel common voltage line parallel to the second direction and arranged between the plurality of pixels along the first direction; a light-emitting device layer including a self-luminous device arranged on the circuit layer and a common electrode arranged on the self-luminous device; a common electrode connecting portion for electrically coupling the pixel common electrode line to the common electrode; and an internal isolation portion, the internal isolation portion surrounding the common electrode connecting portion and isolating the self-luminous device arranged on the internal isolation portion.

[0017] Details of other illustrative embodiments are included in the detailed description and drawings of the disclosure.

[0018] One embodiment of the present disclosure may provide a light-emitting display device that minimizes reduction in reliability of a light-emitting display panel caused by water penetration and has a zero bezel width, and a multi-screen display device including the same.

[0019] An embodiment of the present disclosure can provide a light-emitting display device having a zero border width and minimizing the reduction in reliability of a light-emitting display panel caused by water penetration through a connection portion between a common electrode and a pixel common voltage line, and a multi-screen display device including the light-emitting display device.

[0020] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application. They illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0022] Figure 1 is a plan view illustrating a light emitting display device according to one embodiment of the present disclosure.

[0023] Figure 2A It shows that according to Figure 1 A diagram of one pixel of one embodiment of the present disclosure is shown.

[0024] Figure 2B It shows that according to Figure 1A diagram of a pixel of another embodiment of the present disclosure is shown.

[0025] Figure 2C It shows that according to Figure 1 A diagram of a pixel of another embodiment of the present disclosure is shown.

[0026] Figure 3 yes Figure 1 An enlarged view of area "A" is shown.

[0027] Figure 4 It shows Figure 1 and 3 The equivalent circuit diagram of a sub-pixel is shown.

[0028] Figure 5 It shows Figure 1 and 3 A diagram of the gate drive circuit is shown.

[0029] Figure 6 is a diagram illustrating a rear surface of a light-emitting display device according to one embodiment of the present disclosure.

[0030] Figure 7 is a diagram illustrating a rear surface of a light emitting display device according to another embodiment of the present disclosure.

[0031] Figure 8 It is along Figure 7 The cross-sectional view is taken along line II'.

[0032] Figure 9 yes Figure 8 An enlarged view of area "B" is shown.

[0033] Figure 10 It is along Figure 7 The cross-sectional view is taken along line II-II'.

[0034] Figure 11 yes Figure 10 An enlarged view of area "C" is shown.

[0035] Figure 12 yes Figure 3 An enlarged view of area "D" is shown.

[0036] Figure 13 It is a cross-sectional view taken along the line III-III' shown in FIG12.

[0037] Figure 14 FIG. 1 is a diagram illustrating a multi-screen display device according to an embodiment of the present disclosure.

[0038] Figure 15 It is along Figure 14The cross-sectional view is taken along line IV-IV'. DETAILED DESCRIPTION

[0039] Reference will now be made in detail to the exemplary embodiments of the present disclosure illustrated in the accompanying drawings. In the following description, detailed descriptions of known functions or structures associated with this document will be omitted when it is determined that such detailed descriptions would unnecessarily obscure the subject matter of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to that set forth herein, and except for steps and / or operations that must occur in a particular order, the order of these steps and / or operations may be changed as is known in the art. Like reference numerals refer to like elements throughout. The names of the various elements used in the following description have been selected solely for ease of writing the specification and may therefore differ from the names used in the actual product.

[0040] The advantages and features of the present disclosure and their implementation methods will be illustrated by the following embodiments described in conjunction with the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, by providing these embodiments, the present disclosure can be made comprehensive and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art.

[0041] The shapes, sizes, proportions, angles and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the embodiments of the present disclosure are not limited to these illustrated details. The same reference numerals always refer to the same components. In the following description, when it is determined that a detailed description of a related known function or configuration would unnecessarily confuse the main points of the present disclosure, the detailed description will be omitted. If "including", "having" and "comprising" described in this specification are used, other parts may be added unless "only..." is used. Unless otherwise indicated, terms in the singular may include plural forms.

[0042] When interpreting an element, although not explicitly described, the element is interpreted as including a range of error.

[0043] When describing a positional relationship, such as when describing a positional order as "on," "above," "below," and "after," one or more other parts may be set between the two parts, unless more restrictive terms (such as "immediately" or "directly") are used.

[0044] When describing a temporal relationship, for example, when describing a time sequence as "after," "subsequently," "next," and "before," discontinuous situations may be included unless "immediately" or "directly" is used.

[0045] It should be understood that although the terms "first," "second," and the like are used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and a second element may likewise be referred to as a first element without departing from the scope of this disclosure.

[0046] When describing the key elements of the present disclosure, terms such as first, second, A, B, (a), (b) etc. can be used. These terms are only used to distinguish the corresponding key elements from other key elements, and the corresponding key elements are not limited by these terms in terms of their essence, order or priority. It should be understood that when an key element or layer is referred to as being "on" or "coupled" with another key element or layer, the key element can be directly located on another key element or layer, or there can be an intermediate key element or layer. Furthermore, it should be understood that when an key element is arranged on or below another key element, this can represent that these key elements are arranged to be in direct contact with each other, or can represent that these key elements are arranged when there is no direct contact with each other.

[0047] The term "at least one" should be understood to include any one and all combinations of one or more associated listed elements. For example, the meaning of "at least one of the first element, the second element, and the third element" refers to all combinations of elements listed from two or more elements among the first, second, and third elements, as well as the first element, the second element, or the third element.

[0048] The term "surrounding" as used herein includes at least partially surrounding as well as completely surrounding one or more associated elements. Similarly, the term "covering" as used herein includes at least partially covering as well as completely covering one or more associated elements. For example, if the encapsulation layer surrounds the dam, then this can be interpreted as the encapsulation layer at least partially surrounding the dam. However, in some embodiments, the encapsulation layer may completely surround the dam. The meaning of the term "surrounding" used herein may be further defined based on the associated drawings and embodiments. The terms "surrounding", "at least partially surrounding" or "completely surrounding" and the like are used in this disclosure. According to the definition of "surrounding" set forth above, when only the term "surrounding" is used in an embodiment, this may mean at least partially surrounding or completely surrounding one or more associated elements. The same applies to the term "covering".

[0049] Those skilled in the art will fully understand that the features of different embodiments of the present disclosure may be partially or completely coupled or combined with each other, and may interoperate with each other in different ways and be driven by different technologies. The embodiments of the present disclosure may be implemented independently of each other or implemented together in an interdependent relationship.

[0050] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. When adding reference numerals to the elements of each drawing, even if the same elements are shown in other drawings, the same reference numerals may refer to the same elements. In addition, for ease of description, the scale of each element shown in the drawings may differ from the actual scale and is therefore not limited to the scale shown in the drawings.

[0051] Figure 1 is a plan view illustrating a light emitting display device according to one embodiment of the present disclosure.

[0052] refer to Figure 1 A light-emitting display device (or display panel) 10 according to one embodiment of the present disclosure may include a substrate 100 having a display area AA and a plurality of pixels P located in the display area AA of the substrate 100 .

[0053] The substrate 100 may be referred to as a first substrate, a base substrate, or a pixel array substrate. The substrate 100 may be a glass substrate, or a bendable or flexible thin glass substrate or a plastic substrate.

[0054] The display area AA of the substrate 100 may be an area where an image is displayed and may be referred to as an active portion, an active area, or a display screen. The size of the display area AA may be the same or substantially the same as that of the substrate 100 (or the light-emitting display device or the display panel). For example, the size of the display area AA may be the same as the total size of the first surface of the substrate 100. Therefore, the display area AA may be implemented (or provided) on the entire front surface of the substrate 100, whereby the substrate 100 may not include an opaque non-display portion provided along the peripheral portion (or edge portion) of the first surface to surround all of the display area AA. Accordingly, the display area AA may be implemented on the entire front surface of the light-emitting display device.

[0055] The end (or outermost portion) of the display area AA may overlap or be roughly aligned with the outer surface OS of the substrate 100. For example, relative to the thickness direction Z of the light-emitting display device, the side surface (or end line) of the display area AA may be roughly aligned with a vertical extension line extending vertically from the outer surface OS of the substrate 100. The side surface of the display area AA may not be surrounded by a separate mechanism and may only be adjacent to the surrounding air. For example, all side surfaces of the display area AA may be set to a structure that is in direct contact with the air and is not surrounded by a separate mechanism. Therefore, the outer surface OS of the substrate 100 corresponding to the end of the display area AA may only be surrounded by air (or adjacent to the surrounding air), and therefore, the light-emitting display device according to an embodiment of the present disclosure may have an air frame structure or a non-frame structure (or zero frame) in which the end (or side surface) of the display area AA is surrounded by air instead of an opaque non-display area.

[0056] A plurality of pixels P may be arranged (or disposed) on the display area AA of the substrate 100 so as to have a first interval D1 along a first direction X and a second direction Y. For example, the first direction X may intersect (or intersect or intersect) with the second direction Y. The first direction X may be a lateral direction, a horizontal direction, or a first longitudinal direction (e.g., a lateral longitudinal direction) of the substrate 100 or the light-emitting display device. The second direction Y may be a longitudinal direction, a vertical direction, or a second longitudinal direction (e.g., a longitudinal longitudinal direction) of the substrate 100 or the light-emitting display device.

[0057] Each of the plurality of pixels P may be implemented on a plurality of pixel regions defined on the display area AA of the substrate 100. Each of the plurality of pixels P may have a first length L1 parallel to the first direction X and a second length L2 parallel to the second direction Y. The first length L1 may be the same as the second length L2 or the first interval D1. The first length L1 and the second length L2 may be the same as the first interval D1. Therefore, all of the plurality of pixels (or pixel regions) P may have the same size.

[0058] In the absence of manufacturing process errors, two pixels P adjacent to each other along the first direction X and the second direction Y may have the same first interval D1. The first interval D1 may be the spacing (or pixel spacing) between the two adjacent pixels P. For example, the first length L1 or the second length L2 of the pixel P may be referred to as the pixel spacing. For example, the first interval (or pixel spacing) D1 may be the distance (or length) between the center portions of the two adjacent pixels P. For example, the first interval (or pixel spacing) D1 may be the shortest distance (or shortest length) between the center portions of the two adjacent pixels P.

[0059] Each of the plurality of pixels P according to one embodiment may include: a circuit layer including a pixel circuit implemented in a pixel region on a substrate 100; and a light-emitting device layer disposed on the circuit layer and connected to the pixel circuit. The pixel circuit outputs a data current corresponding to the data signal in response to a data signal and a scan signal provided from a pixel drive line disposed in the pixel region. The light-emitting device layer may include a self-luminous device that emits light using the data current provided by the pixel circuit. The pixel drive line, the pixel circuit, and the light-emitting device layer will be described below.

[0060] The plurality of pixels P may be divided (or classified) into outermost pixels Po and innermost pixels (or internal pixels) Pi.

[0061] The outermost pixel Po may be a pixel disposed closest to the outer surface OS of the substrate 100 among the plurality of pixels P.

[0062] The second interval D2 between the center portion of each outermost pixel Po and the outer surface OS of the substrate 100 may be half or less than the first interval D1. For example, the second interval D2 may be the distance (or length) between the center portion of the outermost pixel Po and the outer surface OS of the substrate 100. For example, the second interval D2 may be the shortest distance (or shortest length) between the center portion of the outermost pixel Po and the outer surface OS of the first substrate 100.

[0063] When the second interval D2 is greater than half the first interval D1, the substrate 100 may have a size greater than the display area AA by an area difference equal to the area between half the first interval D1 and the second interval D2. As a result, the area between the end of the outermost pixel Po and the outer surface OS of the substrate 100 constitutes a non-display area surrounding the entire display area AA. For example, when the second interval D2 is greater than half the first interval D1, the substrate 100 necessarily includes a border area based on the non-display area surrounding the entire display area AA. On the other hand, when the second interval D2 is half the first interval D1 or less, the end of each outermost pixel Po may be aligned with (or positioned at) the outer surface OS of the substrate 100, or the end of the display area AA may be aligned with (or positioned at) the outer surface OS of the substrate 100, thereby enabling the display area AA to be implemented (or positioned) across the entire front surface of the substrate 100.

[0064] The internal pixel Pi may be a pixel other than the outermost pixel Po among the plurality of pixels P, or may be a pixel surrounded by the outermost pixel Po among the plurality of pixels P. The internal pixel (or second pixel) Pi may be implemented to have a different configuration or structure from the outermost pixel (or first pixel) Po.

[0065] The light-emitting display device (or display panel) 10 according to one embodiment of the present disclosure may further include a pad portion 110 .

[0066] The pad portion 110 may be a first pad portion or a front pad portion and may include a plurality of pads to receive data signals, gate control signals, pixel driving power, reference voltage, pixel common voltage, etc. from the driving circuit portion.

[0067] The pad portion 110 can be included within the outermost pixels Po provided at a first peripheral portion of the first substrate 100 parallel to the first direction X. That is, the outermost pixels Po provided at the first peripheral portion of the substrate 100 can include at least one of the plurality of pads. Accordingly, the plurality of pads can be provided or included within the display area AA, whereby a non-display area (or a bezel area) based on the pad portion 110 can not be formed or exist on the first substrate 100. Accordingly, the outermost pixels (or first pixels) Po can include the pad portion 110, whereby can be implemented to have a different configuration or structure from inner pixels (or second pixels) Pi which do not include the pad portion 110.

[0068] For example, when the pad portion 110 is not provided within the outermost pixels Po and is provided between the outermost pixels Po and the outer surface OS of the first substrate 100, the substrate 100 can include a non-display area (or a non-display portion) corresponding to an area in which the pad portion 110 is provided, and due to the non-display area, a second interval D2 between the outermost pixels Po and the outer surface OS of the substrate 100 can be greater than half of the first interval D1, the entire substrate 100 can not be implemented as the display area AA, and a separate bezel (or a separate structure) for covering the non-display area can be required. On the other hand, the pad portion 110 according to one embodiment of the disclosure can be provided between the outermost pixels Po and the outer surface OS of the substrate 100 so as to be included within the outermost pixels Po, whereby a non-display area (or a bezel area) based on the pad portion 110 can not be formed or exist between the outermost pixels Po and the outer surface OS of the substrate 100.

[0069] The light emitting display apparatus (or display panel) 10 according to one embodiment of the disclosure can further include a gate driving circuit 150 provided in the display area AA.

[0070] The gate driving circuit 150 can be provided in the display area AA so as to provide a scan signal (or a gate signal) to the pixels P provided on the substrate 100. The gate driving circuit 150 can simultaneously provide the scan signal to the pixels P provided in a horizontal line parallel to the first direction X. For example, the gate driving circuit 150 can provide at least one scan signal to the pixels P provided in one horizontal line through at least one gate line.

[0071] The gate driving circuit 150 according to one embodiment can be implemented with a shift register including a plurality of stage circuit units. That is, the display apparatus according to one embodiment of the disclosure can include a shift register provided in the display area AA of the substrate 100 so as to provide a scan signal to the pixels P.

[0072] Each of the plurality of stage circuit units may include a plurality of branch circuits that are spaced apart from each other and arranged in each horizontal row along the first direction X of the substrate 100. Each of the plurality of branch circuits may include at least one thin film transistor (TFT) (or branch TFT) and may be disposed between two adjacent pixels among one or more pixels P (or pixel regions) in one horizontal row along the first direction X. Each of the plurality of stage circuit units may generate a scan signal by driving the plurality of branch circuits based on a gate control signal provided through a gate control line that is spaced apart from each other and disposed between the plurality of pixels P in the display area AA, and may provide the scan signal to the pixels P disposed in the corresponding horizontal row.

[0073] The light-emitting display device (or display panel) 10 according to one embodiment of the present disclosure may further include a dam 104 .

[0074] The dam 104 may be implemented in the peripheral portion of the substrate 100, or may be implemented in the peripheral portion of each outermost pixel Po provided in the display area AA. For example, the dam 104 may be provided to have a closed loop line shape (or a closed loop shape) between the center portion of each outermost pixel Po and the outer surface OS of the substrate 100. Therefore, the outermost pixel Po may include the dam 104 and thus may be implemented in a different structure or configuration from the inner pixel Pi that does not include the dam 104. The dam 104 may prevent the organic encapsulation layer provided on the light-emitting device layer from spreading or overflowing in the peripheral portion of each outermost pixel Po.

[0075] The light emitting display device (or display panel) 10 according to one embodiment of the present disclosure may further include an external device isolation portion 105 .

[0076] The external device isolation portion 105 may be implemented in the peripheral portion of the substrate 100, or may be implemented in the peripheral portion of each outermost pixel Po provided in the display area AA. For example, the external device isolation portion 105 may be provided around or near the dam 104. As an example, the external device isolation portion 105 may be provided in the peripheral portion of each outermost pixel Po to have a closed loop line shape (or closed loop shape) surrounded by or surrounding the dam 104. Accordingly, the outermost pixel Po may include the external device isolation portion 105, thereby being implemented in a structure or configuration different from that of the inner pixel Pi that does not include the external device isolation portion 105. In the following description, the external device isolation portion 105 may be referred to as the external isolation portion 105.

[0077] According to one embodiment, the external isolation portion 105 can isolate (or disconnect) the outer portion of each outermost pixel Po or the light-emitting device layer adjacent to or near the dam 104 to block the lateral water penetration path, thereby preventing or minimizing the reliability reduction of the light-emitting device layer due to the lateral penetration of water (or moisture). For example, the external isolation portion 105 can be referred to as the following terms, such as an external water penetration blocking portion, an external water penetration preventing portion, or an external eaves structure, etc.

[0078] The outer isolation portion 105 according to one embodiment may include at least two isolation structures. For example, the outer isolation portion 105 may include first to third isolation structures arranged in parallel to form a closed loop line shape. Each of the at least two isolation structures according to one embodiment may include an eaves structure for isolating (or disconnecting) the light-emitting device layer. As an example, each of the at least two isolation structures may include an eaves structure implemented by an insulating layer and a metal pattern layer (or metal layer) on the insulating layer.

[0079] According to one embodiment, some of the at least two isolation structures may be surrounded by dam 104, and other of the at least two isolation structures may surround dam 104. For example, dam 104 may be disposed between the at least two isolation structures.

[0080] Figure 2A It shows that according to Figure 1 A diagram of one pixel of one embodiment of the present disclosure is shown. Figure 2B It shows that according to Figure 1 FIG. 1 is a diagram of a pixel of another embodiment of the present disclosure, Figure 2C It shows that according to Figure 1 A diagram of a pixel of another embodiment of the present disclosure is shown.

[0081] refer to Figure 1 and 2A , one pixel (or unit pixel) P according to one embodiment of the present disclosure may include first to fourth sub-pixels SP1 to SP4.

[0082] The first subpixel SP1 may be disposed in the first subpixel region of the pixel area PA, the second subpixel SP2 may be disposed in the second subpixel region of the pixel area PA, the third subpixel SP3 may be disposed in the third subpixel region of the pixel area PA, and the fourth subpixel SP4 may be disposed in the fourth subpixel region of the pixel area PA.

[0083] According to one embodiment, the first to fourth sub-pixels SP1 to SP4 may be arranged in a 2×2 format or a quad structure. The first to fourth sub-pixels SP1 to SP4 may include a plurality of emission areas EA1 to EA4 and a plurality of circuit areas CA1 to CA4, respectively. As an example, the emission areas EA1 to EA4 may be referred to as opening areas, opening portions, or emission portions.

[0084] The light emitting areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a uniform quadrilateral structure or a square shape having the same size (or the same area). According to one embodiment, each of the light emitting areas EA1 to EA4 having a uniform quadrilateral structure may be arranged close to the central portion CP of the pixel P within the corresponding sub-pixel region, thereby having a size smaller than each of the four equally divided regions of the pixel P, or may be arranged to be concentrated in the central portion CP of the pixel P. According to another embodiment, each of the light emitting areas EA1 to EA4 having a uniform quadrilateral structure may be arranged in the central portion CP of the corresponding sub-pixel region, thereby having a size smaller than each of the four equally divided regions of the pixel P.

[0085] Reference Figure 1 and 2B According to another embodiment, each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform square structure with different sizes. For example, each of the emission areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform square structure with different sizes.

[0086] The size of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quadrilateral structure may be set based on resolution, luminous efficiency, or image quality. According to another embodiment, when the emission areas EA1 to EA4 have a non-uniform quadrilateral structure, among the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the emission area EA4 of the fourth sub-pixel SP4 may have the smallest size, and the emission area EA3 of the third sub-pixel SP3 may have the largest size. For example, each of the emission areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quadrilateral structure may be arranged to be concentrated around (or near) the center portion CP of the pixel P.

[0087] Reference Figure 1 and 2C According to another embodiment, each of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure. For example, the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure.

[0088] The light emitting areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 having the uniform stripe structure each have a rectangular shape including short sides parallel to the first direction X and long sides parallel to the second direction Y.

[0089] According to one embodiment, each of the light-emitting areas EA1 to EA4 having a uniform stripe structure can be arranged close to the central portion CP of the pixel P within the corresponding sub-pixel area, thereby having a size smaller than each of the four equally divided regions of the pixel P, or can be arranged to be concentrated in the central portion CP of the pixel P.

[0090] According to another embodiment, each of the light emitting areas EA1 to EA4 having a uniform stripe structure may be disposed at a center portion CP of a corresponding sub-pixel region, thereby having a size smaller than each of four equally divided regions of the pixel P.

[0091] According to another embodiment, each of the light emitting areas EA1 to EA4 having a uniform stripe structure may be disposed throughout the corresponding sub-pixel region, thereby having the same size as each of the four equally divided regions of the pixel P.

[0092] Alternatively, each of the light-emitting areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform stripe structure having different sizes. According to one embodiment, when the light-emitting areas EA1 to EA4 have the non-uniform stripe structure, among the light-emitting areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the light-emitting area EA4 of the fourth sub-pixel SP4 may have the smallest size, and the light-emitting area EA3 of the third sub-pixel SP3 may have the largest size, but embodiments of the present disclosure are not limited thereto.

[0093] refer to Figure 2A and 2B , the circuit areas CA1 to CA4 of each of the first to fourth sub-pixels SP1 to SP4 may be arranged around (or near) the corresponding light-emitting areas of the light-emitting areas EA1 to EA4. Each of the circuit areas CA1 to CA4 may include a pixel circuit and a pixel drive line for causing the corresponding sub-pixel of the first to fourth sub-pixels SP1 to SP4 to emit light. As an example, the circuit areas CA1 to CA4 may be referred to as a non-light-emitting area, a non-opening area, a non-light-emitting portion, a non-opening portion, or a peripheral portion.

[0094] Alternatively, to increase the aperture ratio of the subpixels SP1 to SP4 corresponding to the size of the emission areas EA1 to EA4 or to reduce the pixel pitch D1 as the resolution of the pixel P increases, the emission areas EA to EA4 of the first to fourth subpixels SP1 to SP4 may extend into the circuit areas CA1 to CA4 so as to overlap with some or all of the circuit areas CA1 to CA4. For example, since the emission areas EA1 to EA4 of the first to fourth subpixels SP1 to SP4 have a top-emission structure, each of the emission areas EA1 to EA4 may be arranged to overlap with a corresponding circuit area of ​​the circuit areas CA1 to CA4. In this case, each of the emission areas EA1 to EA4 may have a size equal to or larger than that of the corresponding circuit area CA1 to CA4.

[0095] exist Figures 2A to 2C In the embodiment, the first sub-pixel SP1 may be implemented to emit light of a first color, the second sub-pixel SP2 may be implemented to emit light of a second color, the third sub-pixel SP3 may be implemented to emit light of a third color, and the fourth sub-pixel SP4 may be implemented to emit light of a fourth color. As an example, each of the first to fourth colors may be different. As an embodiment, the first color may be red, the second color may be blue, the third color may be white, and the fourth color may be green. As another embodiment, some of the first to fourth colors may be the same. For example, the first color may be red, the second color may be a first green, the third color may be a second green, and the fourth color may be blue.

[0096] Alternatively, the white sub-pixel emitting white light among the first to fourth sub-pixels SP1 to SP4 having the uniform stripe structure or the non-uniform stripe structure may be omitted.

[0097] Figure 3 yes Figure 1 An enlarged view of area "A" is shown, Figure 4 It shows Figure 1 and 3 The equivalent circuit diagram of a sub-pixel is shown.

[0098] refer to Figure 1 、 3 and 4, the substrate 100 according to one embodiment of the present disclosure may include pixel driving lines DL, GL, PL, CVL, RL and GCL, a plurality of pixels P, a common electrode CE, a plurality of common electrode connection portions CECP, a plurality of internal device isolation portions 103, a dam 104, an external device isolation portion 105, and a pad portion 110.

[0099] The pixel driving lines DL, GL, PL, CVL, RL, and GCL may include a plurality of data lines DL, a plurality of gate lines GL, a plurality of pixel driving power lines PL, a plurality of pixel common voltage lines CVL, a plurality of reference voltage lines RL, and a gate control line GCL.

[0100] The plurality of data lines DL may be elongated along the second direction Y and may be arranged in the display area AA of the substrate 100 at predetermined intervals along the first direction X. For example, among the plurality of data lines DL, the odd-numbered data lines DLo may be arranged along the second direction Y at a first peripheral portion of each of the plurality of pixel areas PA arranged on the first substrate 100, and the even-numbered data lines DLe may be arranged along the second direction Y at a second peripheral portion of each of the plurality of pixel areas PA arranged on the substrate 100, but embodiments of the present disclosure are not limited thereto.

[0101] The plurality of gate lines GL may be elongated along the first direction X and may be arranged in the display area AA of the substrate 100 at predetermined intervals along the second direction Y. For example, the odd-numbered gate lines Glo among the plurality of gate lines GL may be arranged at a third peripheral portion of each of the plurality of pixel areas PA arranged on the substrate 100 along the first direction X. The even-numbered gate lines GLe among the plurality of gate lines GL may be arranged at a fourth peripheral portion of each of the plurality of pixel areas PA arranged on the substrate 100 along the first direction X, but embodiments of the present disclosure are not limited thereto.

[0102] The plurality of pixel driving power lines PL may extend along the second direction Y and may be arranged in the display area AA of the substrate 100 in a manner spaced apart from each other at predetermined intervals along the first direction X. For example, among the plurality of pixel driving power lines PL, the odd-numbered pixel driving power lines PL may be arranged at a first peripheral portion of the odd-numbered pixel area PA in the first direction X, and the even-numbered pixel driving power lines PL may be arranged at a second peripheral portion of the even-numbered pixel area PA in the first direction X, but embodiments of the present disclosure are not limited thereto.

[0103] Two adjacent pixel drive power lines PL among the plurality of pixel drive power lines PL can be connected to a plurality of power sharing lines PSL arranged in each pixel area PA arranged along the second direction Y. For example, the plurality of pixel drive power lines PL can be electrically coupled to each other through the plurality of power sharing lines PSL, thereby having a ladder structure (ladder structure) or a mesh structure. The plurality of pixel drive power lines PL can have a ladder structure or a mesh structure, thereby preventing or minimizing the voltage drop (or IR drop) of the pixel drive power caused by the line resistance of each of the plurality of pixel drive power lines PL. Accordingly, the light-emitting display device according to one embodiment of the present disclosure can prevent or minimize the degradation of image quality caused by the deviation of the pixel drive power provided to each pixel P arranged on the display area AA.

[0104] Each of the plurality of power share lines PSL may be branched from an adjacent pixel driving power line PL in parallel with the first direction X and may be disposed in a middle region of each pixel area PA, but embodiments of the present disclosure are not limited thereto.

[0105] The plurality of pixel common voltage lines CVL may be elongated along the second direction Y and may be disposed in the display area AA of the substrate 100 at predetermined intervals along the first direction X. For example, each of the plurality of pixel common voltage lines CVL may be disposed at a first peripheral portion of the even-numbered pixel area PA in the first direction X.

[0106] The plurality of reference voltage lines RL may extend along the second direction Y and may be arranged in the display area AA of the substrate 100 at predetermined intervals along the first direction X. Each of the plurality of reference voltage lines RL may be disposed at a central region of each pixel area PA arranged along the second direction Y.

[0107] Each of the plurality of reference voltage lines RL may be shared by two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) in each pixel area PA in the first direction X. To this end, each of the plurality of reference voltage lines RL may include a reference branch line RDL. The reference branch line RDL may branch (or protrude) to two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) in each pixel area PA in the first direction X, and may be electrically coupled to the two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)).

[0108] Each of the plurality of gate control lines GCL may be elongated along the second direction Y and may be disposed in the display area AA of the substrate 100 in a manner spaced apart from each other by a predetermined interval along the first direction X. For example, each of the plurality of gate control lines GCL may be disposed in a boundary region between a plurality of pixel areas PA or between two adjacent pixel areas PA in the first direction X.

[0109] Each of the plurality of pixels P may include at least three sub-pixels. For example, each of the plurality of pixels P may include first to fourth sub-pixels SP1 to SP4.

[0110] Each of the first to fourth sub-pixels SP1 to SP4 may include a pixel circuit PC and a light emitting device layer.

[0111] According to one embodiment, a pixel circuit PC may be disposed in a circuit region of the pixel area PA and may be coupled to an adjacent gate line GLo or GLe, an adjacent data line DLo or DLe, and a pixel driving power line PL. For example, a pixel circuit PC disposed in a first subpixel SP1 may be coupled to an odd-numbered data line DLo and an odd-numbered gate line GLo, a pixel circuit PC disposed in a second subpixel SP2 may be coupled to an even-numbered data line DLe and an odd-numbered gate line GLo, a pixel circuit PC disposed in a third subpixel SP3 may be coupled to an odd-numbered data line DLo and an even-numbered gate line GLe, and a pixel circuit PC disposed in a fourth subpixel SP4 may be coupled to an even-numbered data line DLe and an even-numbered gate line GLe.

[0112] The pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can sample the data signal provided from the corresponding data line DLo or DLe in response to the scan signal provided from the corresponding gate line GLo or GLe, and can control the current flowing from the pixel driving power line PL to the light emitting device layer based on the sampled data signal.

[0113] The pixel circuit PC according to one embodiment may include a first switching thin film transistor Tsw1, a second switching thin film transistor Tsw2, a driving thin film transistor Tdr, and a storage capacitor Cst, but the embodiments of the present disclosure are not limited thereto. In the following description, a thin film transistor may be referred to as a TFT.

[0114] The first switch TFT Tsw1 can include a gate electrode coupled with a corresponding gate line GL (GLo or GLe), a first source / drain electrode coupled with a corresponding data line DL (DLo or DL2), and a second source / drain electrode coupled with a gate node n1 of the driving TFT Tdr. The first switch TFT Tsw1 can be turned on by a scan signal provided through the corresponding gate line GL (GLo or GLe), and can transfer a data signal provided through the corresponding data line DL (DLo or DL2) to the gate node n1 of the driving TFT Tdr.

[0115] The second switch TFT Tsw2 can include a gate electrode coupled with a corresponding gate line GL (GLo or GLe), a first source / drain electrode coupled with a source node n2 of the driving TFT Tdr, and a second source / drain electrode coupled with a corresponding reference voltage line RL. The second switch TFT Tsw2 can be turned on by a scan signal provided through the corresponding gate line GL (GLo or GLe), and can transfer a reference voltage provided through the corresponding reference voltage line RL to the source node n2 of the driving TFT Tdr. As an example, the second switch TFT Tsw2 can be turned on at the same time as the first switch TFT Tsw1.

[0116] A storage capacitor Cst can be formed between the gate node n1 and the source node n2 of the driving TFT Tdr. The storage capacitor Cst according to an embodiment can include a first capacitor electrode coupled with the gate node n1 of the driving TFT Tdr, a second capacitor electrode coupled with the source node n2 of the driving TFT Tdr, and a dielectric layer formed in an overlapping area between the first capacitor electrode and the second capacitor electrode. The storage capacitor Cst can be charged with a difference voltage between the gate node n1 and the source node n2 of the driving TFT Tdr, and then can turn on or turn off the driving TFT Tdr based on the charged voltage.

[0117] The driving TFT Tdr can include a gate electrode (or a gate node n1) commonly coupled with the second source / drain electrode of the first switch TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst, a first source / drain electrode (or a source node n2) commonly coupled with the first source / drain electrode of the second switch TFT Tsw2, the second capacitor electrode of the storage capacitor Cst, and a pixel electrode PE of the light emitting device layer, and a second source / drain electrode (or a drain node) coupled with a corresponding pixel driving power line PL. The driving TFT Tdr can be turned on based on a voltage of the storage capacitor Cst, and can control an amount of current flowing from the pixel driving power line PL to the light emitting device layer.

[0118] The light emitting device layer may be disposed in the emission area EA of the pixel area PA and may be electrically coupled to the pixel circuit PC.

[0119] The light emitting device layer according to one embodiment of the present disclosure may include a pixel electrode PE electrically coupled to the pixel circuit PC, a common electrode CE electrically coupled to the pixel common voltage line CVL, and a self-luminous device ED interposed between the pixel electrode PE and the common electrode CE.

[0120] The pixel electrode PE may be referred to as an anode electrode, a reflective electrode, a lower electrode, an anode or a first electrode of the self-luminous device ED.

[0121] The pixel electrode PE may overlap the emission area EA of each of the plurality of pixel areas PA. The pixel electrode PE may be patterned into an island shape and disposed in each pixel area PA, and may be electrically coupled to the first source / drain electrodes (or source node n2) of the driving TFT Tdr of the corresponding pixel circuit PC. One side of the pixel electrode PE may extend onto the first source / drain electrodes of the driving TFT Tdr and may be electrically coupled to the first source / drain electrodes of the driving TFT Tdr via an electrode contact hole disposed in a planarization layer on the driving TFT Tdr.

[0122] The self-luminous device ED may be disposed on the pixel electrode PE and may directly contact the pixel electrode PE. The self-luminous device ED may be a common layer or a common device layer, formed in each of the multiple sub-pixels SP, and thus cannot be distinguished by the sub-pixel SP unit. The self-luminous device ED can respond to the current flowing between the pixel electrode PE and the common electrode CE, thereby emitting white light or blue light.

[0123] The common electrode CE may be disposed on the display area AA of the substrate 100 and may be electrically coupled to the self-luminous device ED of each of the plurality of sub-pixels SP. For example, the common electrode CE may be disposed on the remaining display area AA of the substrate 100 except for the pad portion 110 thereof.

[0124] Each of the plurality of common electrode connection portions CECP may be disposed between a plurality of pixels P, overlapped with a plurality of pixel common voltage lines CVL, and electrically couple the common electrode CE to each of the plurality of pixel common voltage lines CVL. With respect to each of the first direction X and the second direction Y, each of the plurality of common electrode connection portions CECP according to an embodiment of the present disclosure may be electrically coupled to each of the plurality of pixel common voltage lines CVL at a portion between two adjacent pixels P, and may be electrically coupled to a portion of the common electrode CE, thereby electrically coupling the common electrode CE to each of the plurality of pixel common voltage lines CVL. For example, the common electrode CE may be coupled to each of the plurality of common electrode connection portions CECP via a side contact structure corresponding to an undercut structure.

[0125] Each of the plurality of common electrode connection portions CECP may be disposed between two pixels along the first direction X and the second direction Y to electrically couple the common electrode CE to each of the plurality of pixel common voltage lines CVL, thereby preventing or minimizing a voltage drop (IR drop) in the pixel common voltage caused by the surface resistance of the common electrode CE. Accordingly, the light-emitting display device according to one embodiment of the present disclosure can prevent or minimize image quality degradation caused by a deviation in the pixel common voltage supplied to each pixel P arranged in the display area AA.

[0126] Each of the plurality of internal device isolation portions 103 can isolate (or disconnect) the light-emitting device layer surrounding or near each of the plurality of common electrode connection portions CECP to block or maximize the internal water permeation path, thereby preventing or minimizing the reduction in reliability of the light-emitting device layer caused by internal permeation of water (or moisture). For example, each of the plurality of internal device isolation portions 103 can be implemented to maximize the water permeation path between each of the plurality of common electrode connection portions CECP and the light-emitting area EA, thereby maximally delaying the internal water permeation time of water from each of the plurality of common electrode connection portions CECP into the light-emitting area EA. In the following description, the internal device isolation portion 103 may be referred to as an internal isolation portion 103 or an internal isolation element 103.

[0127] Each of the plurality of internal isolation portions (or internal isolation elements) 103 according to one embodiment may include first to n-th trench structures (where n is a natural number of 2 or greater) surrounding each of the plurality of common electrode connection portions CECP. For example, one internal isolation portion 103 may include first to n-th trench structures surrounding one common electrode connection portion CECP. This portion may be considered an element because it is a part of a structure or the structure itself.

[0128] The first to nth trench structures may include undercut structures (or eaves structures) for isolating (or disconnecting) the light-emitting device layer disposed around or near the corresponding common electrode connection portion CECP. For example, in a stacked structure of an insulating layer and a metal layer, the first to nth trench structures may include undercut structures implemented by the insulating layer or eaves structures implemented by the metal layer.

[0129] Each of the first to nth groove structures according to one embodiment may have an arc shape, one side of which may include an opening portion one-dimensionally. Each of the first to nth groove structures may have an arc shape arranged in a concentric circle shape and one side of which may be open. For example, in a top plan view, the first to nth groove structures may have a C-shape, but embodiments of the present disclosure are not limited thereto.

[0130] According to one embodiment, the opening portion of the kth trench structure among the first to nth trench structures may be surrounded by the k+1th trench structure (where k is 1 to n-1). For example, the opening portion of the kth trench structure and the opening portion of the k+1th trench structure may face different directions. As an example, the opening portion of the kth trench structure and the opening portion of the k+1th trench structure may face opposite directions.

[0131] According to one embodiment, each of the plurality of internal isolation portions 103 may include a labyrinth region between the first to nth trench structures based on the arrangement structure of the first to nth trench structures, and may maximize the length of a water permeation path between the plurality of common electrode connection portions CECP and the light emitting area EA. Accordingly, as an example, the internal isolation portion 103 may be referred to as a term such as an internal water permeation delay portion, an inner eaves structure, or a labyrinth water permeation delay portion.

[0132] Each of the dam 104 and the outer isolation portion 105 may be provided or implemented at the outermost pixel Po or the peripheral portion of the substrate 100 so as to have a closed loop line shape (or a closed loop shape). Figure 1 This has been described, and thus its repeated description is omitted.

[0133] The pad portion 110 may be provided in a first peripheral portion parallel to the first direction X in the first surface of the substrate 100. The pad portion 110 may be provided in a third peripheral portion of each outermost pixel area PAo provided in the first peripheral portion of the substrate 100. In the second direction Y, an end portion of the pad portion 110 may overlap or be aligned with an end portion of each outermost pixel area PAo. Therefore, the pad portion 110 may be included (or provided) in each outermost pixel area PAo provided in the first peripheral portion of the substrate 100, whereby a non-display area (or frame area) based on the first pad portion 110 is not formed or does not exist in the substrate 100.

[0134] The pad portion 110 may include a plurality of pads disposed parallel to one another at a first peripheral portion of the first substrate 100 along the first direction X. The plurality of pads may be divided (or classified) into a first data pad DP, a first gate pad GP, a first pixel driving power pad PPP, a first reference voltage pad RVP, and a first pixel common voltage pad CVP.

[0135] Each of the first data pads DP may be connected individually (or in a one-to-one relationship) to one side of each of a plurality of data lines DLo and DLe disposed on the substrate 100 .

[0136] Each of the first gate pads GP may be connected individually (or in a one-to-one relationship) to one side of each gate control line GCL disposed on the first substrate 100. The first gate pads GP according to one embodiment may be divided (or classified) into a first start signal pad, a plurality of first shift clock pads, a plurality of first carry clock pads, at least one first gate driving power pad, and at least one first gate common power pad.

[0137] Each of the first pixel driving power pads PPP may be connected individually (or in a one-to-one relationship) to one side of each of the plurality of pixel driving power lines PL provided on the substrate 100. Each of the first reference voltage pads RVP may be connected individually (or in a one-to-one relationship) to one side of each of the plurality of reference voltage lines RL provided on the substrate 100. Each of the first pixel common voltage pads CVP may be connected individually (or in a one-to-one relationship) to one side of each of the plurality of pixel common voltage lines CVL provided on the substrate 100.

[0138] The pad portion 110 according to one embodiment can include a plurality of pad groups PG arranged in a sequence of the first pixel driving power pad PPP, the first data pad DP, the first reference voltage pad RVP, the first data pad DP, the first gate pad GP, the first pixel common voltage pad CVP, the first data pad DP, the first reference voltage pad RVP, the first data pad DP, and the first pixel driving power pad PPP along the first direction X. Each of the plurality of pad groups PG can be connected to two adjacent pixels P disposed along the first direction X. For example, the plurality of pad groups PG can include a first pad group PG1 including the first pixel driving power pad PPP, the first data pad DP, the first reference voltage pad RVP, the first data pad DP, and the first gate pad GP disposed in sequence along the first direction X in the odd pixel area PA, and a second pad group PG2 including the first pixel common voltage pad CVP, the first data pad DP, the first reference voltage pad RVP, the first data pad DP, and the first pixel driving power pad PPP disposed in sequence along the first direction X in the even pixel area PA.

[0139] The substrate 100 according to one embodiment of the disclosure can further include a plurality of auxiliary voltage lines SVL and a plurality of auxiliary line connection portions SLCP. As an example, the auxiliary voltage lines can be referred to as additional voltage lines or sub voltage lines, etc.

[0140] Each of the plurality of auxiliary voltage lines SVL can be elongated along the second direction Y and can be disposed adjacent to a corresponding pixel common voltage line CVL of the plurality of pixel common voltage lines CVL. Each of the plurality of auxiliary voltage lines SVL can be electrically coupled to the adjacent pixel common voltage line CVL without being electrically coupled to the pixel common voltage pad CVP and can be supplied with the pixel common voltage through the adjacent pixel common voltage line CVL. To this end, the substrate 100 according to one embodiment of the disclosure can further include a plurality of line connection patterns LCP electrically coupling the pixel common voltage line CVL and the auxiliary voltage line SVL adjacent to each other.

[0141] Each of the plurality of line connection patterns LCP can be disposed on the substrate 100 to cross the pixel common voltage lines CVL and the auxiliary voltage lines SVL adjacent to each other, and can electrically couple the pixel common voltage lines CVL and the auxiliary voltage lines SVL adjacent to each other by using a line jumping structure. For example, one side of each of the plurality of line connection patterns LCP can be electrically coupled to a portion of the auxiliary voltage line SVL through a first line contact hole formed in an insulating layer above the auxiliary voltage line SVL, and the other side of each of the plurality of line connection patterns LCP can be electrically coupled to a portion of the pixel common voltage line CVL through a second line contact hole formed in the insulating layer above the pixel common voltage line CVL.

[0142] Each of the plurality of auxiliary line connection portions SLCP can overlap each of the plurality of auxiliary voltage lines SVL to electrically couple the common electrode CE to each of the plurality of auxiliary voltage lines SVL between the plurality of pixels P. In the second direction Y, each of the plurality of auxiliary line connection portions SLCP according to an embodiment can be electrically coupled to each of the plurality of auxiliary voltage lines SVL at a portion between the plurality of pixels P or at a boundary region between the plurality of pixels P, and can be electrically coupled to a portion of the common electrode CE, whereby the common electrode CE can be electrically coupled to each of the plurality of auxiliary voltage lines SVL. Accordingly, the common electrode CE can be additionally coupled to each of the plurality of auxiliary voltage lines SVL through the auxiliary line connection portion SLCP. Accordingly, the light emitting display apparatus according to one embodiment of the disclosure can prevent or minimize image quality deterioration caused by a deviation of the pixel common voltage provided to each of the pixels P arranged in the display area AA. Also, in the light emitting display apparatus according to one embodiment of the disclosure, although a pixel common voltage pad CVP coupled to each of the plurality of auxiliary voltage lines SVL is not additionally disposed (or formed), the pixel common voltage can be provided to each of the plurality of auxiliary voltage lines SVL through the pixel common voltage line CVL and each of the plurality of line connection patterns LCP.

[0143] Each of the plurality of auxiliary line connection portions SLCP according to one embodiment can have a symmetrical structure with each of the plurality of common electrode connection portions CECP with respect to the gate control line GCL. Accordingly, each of the plurality of auxiliary line connection portions SLCP can be surrounded by each of the plurality of internal isolation portions 103. For example, one internal isolation portion 103 can surround one common electrode connection portion CECP and one auxiliary line connection portion SLCP.

[0144] Accordingly, as Figure 3As shown, a plurality of pixels is formed on the substrate 100, and the pixels are arranged in adjacent rows and adjacent columns. A plurality of pixel driving power supply lines is located between the pixels of adjacent columns. As shown Figure 12 and 13 As shown, the plurality of electrode connection patterns SLCP having the patterns ECP1 and ECP2 are coupled to each of the pixel driving power supply lines at a position between the pixels of two adjacent columns and the pixels of two adjacent rows. The first isolation structure 103-1 surrounds the electrode connection patterns, and the first isolation structure is located between the pixels of two adjacent columns and the pixels of two adjacent rows.

[0145] The second isolation structure 103-2 surrounds the first isolation structure. The second isolation structure 103-2 is a circular element having openings adjacent to the wall portions of the first isolation structure 103-1. In addition, the openings of the first isolation structure 103-1 are reversed to the openings of the second isolation structure 103-2. Thus, each of the isolation structures 103-1 and 103-2 can have a C shape, and the openings of the C shape are reversed to each other and face the wall of the other opening.

[0146] The substrate 100 according to one embodiment of the present disclosure can further include an encapsulation layer.

[0147] The encapsulation layer can be implemented to surround the light emitting device layer. The encapsulation layer according to one embodiment can include a first inorganic encapsulation layer (or a first encapsulation layer) disposed on the light emitting device layer, the dam 104, and the external device isolation portion 105; a second inorganic encapsulation layer (or a third encapsulation layer) disposed on the first inorganic encapsulation layer; and an organic encapsulation layer (or a second encapsulation layer) disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer on an encapsulation area defined by the dam 104.

[0148] The organic encapsulation layer can cover a top surface (or an upper surface) of the light emitting device layer and flow toward an end portion of the substrate 100, and the diffusion (or flow) of the organic encapsulation layer can be blocked by the dam 104. The dam 104 can define or limit a disposition area (or an encapsulation area) of the organic encapsulation layer, and in addition, can block or prevent diffusion or overflow of the organic encapsulation layer.

[0149] Figure 5 is a diagram illustrating Figure 1 and 3 a gate driving circuit as shown.

[0150] Referring to Figure 1 , 35. A gate driving circuit 150 according to another embodiment of the present disclosure may be implemented inside (or embedded in) the display area AA of the substrate 100. The gate driving circuit 150 may generate a scan signal based on a gate control signal provided through the pad portion 110 and the gate control line GCL, and may sequentially provide the scan signal to the plurality of gate lines GL.

[0151] The gate control lines GCL may include a start signal line, a plurality of shift clock lines, at least one gate drive voltage line, and at least one gate common voltage line. The gate control lines GCL may extend along the second direction Y and may be arranged in the display area AA of the substrate 100 along the first direction X at predetermined intervals. For example, the gate control lines GCL may be arranged between at least one or more pixels P along the first direction X.

[0152] The gate driving circuit 150 according to one embodiment of the present disclosure may be implemented using a shift register including a plurality of stage circuit parts 1501 to 150m, where m is an integer of 2 or greater.

[0153] Each of the plurality of stage circuit portions 1501 to 150m may be individually disposed in each horizontal row of the first surface of the substrate 100 along the first direction X, and may be subsidiaryly coupled to one another along the second direction Y. Each of the plurality of stage circuit portions 1501 to 150m may generate a scan signal in a predetermined order in response to a gate control signal provided through the pad portion 110 and the gate control line GCL, and may provide the scan signal to the corresponding gate line GL.

[0154] Each of the plurality of stage circuit portions 1501 to 150 m according to one embodiment may include a plurality of branch circuits 1511 to 151 n and a branch network 153 .

[0155] The plurality of branch circuits 1511 to 151n may be selectively coupled to the gate control line GCL through the branch network 153, and may be electrically coupled to each other through the branch network 153. Each of the plurality of branch circuits 1511 to 151n may generate a scan signal based on a gate control signal provided through the gate control line GCL and a voltage of the branch network 153, and may provide the scan signal to a corresponding gate line GL.

[0156] Each of the plurality of branch circuits 1511 to 151n may include at least one TFT (or branch TFT) among the plurality of TFTs constituting one of the stage circuit sections 1501 to 150m. Any of the plurality of branch circuits 1511 to 151n may include a pull-up TFT coupled to the gate line GL. Another of the plurality of branch circuits 1511 to 151n may include a pull-down TFT coupled to the gate line GL.

[0157] Each of the plurality of branch circuits 1511 to 151n according to one embodiment of the present disclosure may be provided in a circuit region between two adjacent pixels P or in a circuit region between at least two adjacent pixels P in each horizontal row of the substrate 100, but the present disclosure is not limited thereto. For example, depending on the number of TFTs constituting each of the stage circuit portions 1501 to 150m and the number of pixels P provided in a horizontal row, each of the plurality of branch circuits 1511 to 151n may be provided in a circuit region (or boundary region) between at least one or more adjacent pixels P.

[0158] The branch network 153 may be provided in each horizontal row of the substrate 100 and may electrically couple the plurality of branch circuits 1511 to 151n to one another. The branch network 153 according to one embodiment of the present disclosure may include a plurality of control node lines and a plurality of network lines.

[0159] A plurality of control node lines may be provided in each horizontal row of the substrate 100 and may be selectively coupled to a plurality of branch circuits 1511 to 151n in one horizontal row. For example, in a pixel region arranged in each horizontal row of the substrate 100, a plurality of control node lines may be provided in an upper edge region (or a lower edge region).

[0160] The plurality of network lines may be selectively coupled to the gate control line GCL provided in the substrate 100 and may be selectively coupled to the plurality of branch circuits 1511 to 151n. For example, the plurality of network lines may transmit gate control signals provided from the gate control line GCL to corresponding branch circuits 1511 to 151n and may transmit signals between the plurality of branch circuits 1511 to 151n.

[0161] As described above, according to one embodiment of the present disclosure, since the gate driving circuit 150 is disposed inside the display area AA of the substrate 100, the second interval D2 between the center portion of the outermost pixel area PAo and the outer surface OS of the substrate can be equal to or less than half of the first interval (or pixel pitch) D1 between adjacent pixel areas PA. For example, when the gate driving circuit 150 is not disposed in the display area AA of the substrate 100 but is disposed in the peripheral portion of the substrate 100, the second interval D2 will not be equal to or less than half of the first interval D1. Accordingly, in a light-emitting display device according to one embodiment of the present disclosure, the gate driving circuit 150 may be disposed in the display area AA of the substrate 100, whereby the second interval D2 may be implemented to be equal to or less than half of the first interval D1, and the display device may be implemented as an air frame structure having a zero frame or no frame area.

[0162] Figure 6 is a diagram illustrating a rear surface of a light-emitting display device according to one embodiment of the present disclosure.

[0163] refer to Figure 1 、 3 and 6. The light-emitting display device according to one embodiment of the present disclosure may further include a second pad portion 210 provided on the rear surface (back surface) 100 b of the substrate 100 .

[0164] The second pad portion 210 may be provided at a peripheral portion (or first rear peripheral portion) of the rear surface 100b of the substrate 100 overlapping the pad portion 110 provided at the front surface of the substrate 100. Figure 6 In the description, the pad portion 110 disposed on the front surface of the substrate 100 may be referred to as a first pad portion 110 .

[0165] The second pad portion 210 may include a plurality of second pads (or wiring pads) arranged at intervals along the first direction X so as to overlap the pads of the first pad portion 110, respectively. Figure 6 In the description of FIG. 1 , the pads of the pad portion 110 may be referred to as first pads.

[0166] The plurality of second pads may be divided (or classified) into a second pixel driving power pad overlapping with each first pixel driving power pad PPP of the first pad portion 110, a second data pad overlapping with each first data pad DP of the first pad portion 110, a second reference voltage pad overlapping with each first reference voltage pad RVP of the first pad portion 110, a second gate pad overlapping with each first gate pad GP of the first pad portion 110, and a second pixel common voltage pad overlapping with each first pixel common voltage pad CVP of the first pad portion 110.

[0167] The light emitting display apparatus according to one embodiment of the disclosure can further include at least one third pad portion 230 disposed on the rear surface 100b of the substrate 100 and a wiring portion 250.

[0168] The at least one third pad portion 230 (or input pad portion) can be disposed on the rear surface 100b of the substrate 100. For example, the at least one third pad portion 230 can be disposed on a middle portion adjacent to the first peripheral portion of the rear surface 100b of the substrate 100. The at least one third pad portion 230 according to one embodiment of the disclosure can include a plurality of third pads (or input pads) spaced apart from each other by a certain interval. For example, the at least one third pad portion 230 can include a third pixel driving power pad, a third data pad, a third reference voltage pad, a third gate pad, and a third pixel common voltage pad.

[0169] The wiring portion 250 can include a plurality of wirings disposed between the second pad portion 210 and the at least one third pad portion 230.

[0170] The wiring portion 250 according to one embodiment of the disclosure can include a plurality of pixel driving power wirings individually (or in a one-to-one relationship) coupling the second pixel driving power pads to the third pixel driving power pads, a plurality of data wirings individually (or in a one-to-one relationship) coupling the second data pads to the third data pads, a plurality of reference voltage wirings individually (or in a one-to-one relationship) coupling the second reference voltage pads to the third reference voltage pads, a plurality of gate wirings individually (or in a one-to-one relationship) coupling the second gate pads to the third gate pads, and a plurality of pixel common voltage wirings individually (or in a one-to-one relationship) coupling the second pixel common voltage pads to the third pixel common voltage pads.

[0171] Each of the plurality of pixel common voltage wirings can include a first common wiring 251 and a second common wiring 253. The first common wiring 251 can be disposed between the second pad portion 210 and the at least one third pad portion 230 and commonly coupled to the plurality of second pixel common voltage pads. The second common wiring 253 can be commonly coupled to the plurality of third pixel common voltage pads and electrically coupled to the first common wiring 251. The second common wiring 253 can be disposed on a different layer from the first common wiring 251 and can be electrically connected to the first common wiring 251 through a via hole. The size of the second common wiring 253 can gradually increase in a direction from the third pad portion 230 to the peripheral portion of the substrate 100 so as to reduce (or minimize) a voltage drop of the pixel common voltage.

[0172] The light-emitting display device according to one embodiment of the present disclosure may further include a wiring portion 400 disposed on the outer surface OS of the substrate 100 .

[0173] The wiring portion 400 may be disposed to surround the first pad portion 110 , the outer surface OS, and the second pad portion 210 of the substrate 100 .

[0174] According to one embodiment, the wiring portion 400 may include a plurality of wirings 410. Each of the plurality of wirings 410 may be arranged at a certain interval along the first direction X, may be formed to surround the first pad portion 110, the outer surface OS, and the second pad portion 210 of the substrate 100, and may be electrically coupled to each of the first pad of the first pad portion 110 and the second pad of the second pad portion 210 in a one-to-one relationship. According to one embodiment, each of the plurality of wirings 410 may be formed by a printing process using a conductive paste. According to another embodiment, each of the plurality of wirings 410 may be formed by a transfer process of transferring a conductive paste pattern to a transfer pad made of a flexible material and transferring the conductive paste pattern transferred to the transfer pad to the wiring portion 400. As an example, the conductive paste may be a silver paste, but the embodiments of the present disclosure are not limited thereto.

[0175] The plurality of wirings 410 according to one embodiment of the present disclosure may be divided (classified) into a plurality of pixel power wirings 411 , a plurality of data wirings 413 , a plurality of reference voltage wirings 415 , a plurality of gate wirings 417 , and a plurality of pixel common voltage wirings 419 .

[0176] A plurality of pixel power wirings 411 may be formed to surround the first pad portion 110, the outer surface OS, and the second pad portion 210, and may be electrically coupled to the plurality of first pixel driving power pads of the first pad portion 110 and the plurality of second pixel driving power pads of the second pad portion 210 in a one-to-one relationship.

[0177] A plurality of data wirings 413 may be formed to surround the first pad portion 110, the outer surface OS, and the second pad portion 210, and may be electrically coupled to the plurality of first data pads of the first pad portion 110 and the plurality of second data pads of the second pad portion 210 in a one-to-one relationship.

[0178] A plurality of reference voltage wirings 415 may be formed to surround the first pad portion 110, the outer surface OS, and the second pad portion 210, and may be electrically coupled to the plurality of first reference voltage pads of the first pad portion 110 and the plurality of second reference voltage pads of the second pad portion 210 in a one-to-one relationship.

[0179] A plurality of gate wirings 417 may be formed to surround the first pad portion 110 , the outer surface OS, and the second pad portion 210 , and may be electrically coupled to the plurality of first gate pads of the first pad portion 110 and the plurality of second gate pads of the second pad portion 210 in a one-to-one relationship.

[0180] A plurality of pixel common voltage wirings 419 may be formed to surround the first pad portion 110, the outer surface OS, and the second pad portion 210, and may be electrically coupled to the plurality of first pixel common voltage pads of the first pad portion 110 and the plurality of second pixel common voltage pads of the second pad portion 210 in a one-to-one relationship.

[0181] The light emitting display device or the wiring portion 400 according to one embodiment may further include an edge coating layer.

[0182] The edge coating may be implemented to cover the plurality of wiring portions 400. The edge coating according to one embodiment may be implemented to cover all of the first peripheral portion and the first outer surface OS of the substrate 100 and the plurality of wirings 410. The edge coating may prevent corrosion of each of the plurality of wirings 410 comprising a metal material or an electrical short circuit between the plurality of wirings 410. Furthermore, the edge coating may prevent or minimize external light reflection caused by the plurality of wirings 410 and the first pad of the first pad portion 110. The edge coating according to one embodiment may include a light-shielding material containing black ink. For example, the edge coating may be an edge protection layer or an edge insulation layer.

[0183] The light emitting display device according to one embodiment of the present disclosure may further include a driving circuit part 500 .

[0184] The driver circuit portion 500 can drive the pixels P disposed on the first substrate 100 (or cause them to emit light) based on the digital video data and timing synchronization signals provided from the display driver system, so as to allow the display area AA to display an image corresponding to the image data. The driver circuit portion 500 can be coupled to at least one third pad portion 230 disposed on the rear surface 100b of the substrate 100, and can output data signals, gate control signals, and driving power for driving the pixels P disposed on the substrate 100 (or causing them to emit light) to the at least one third pad portion 230.

[0185] The driving circuit part 500 according to one embodiment may include a flexible circuit film 510 , a driving integrated circuit (IC) 530 , a printed circuit board (PCB) 550 , a timing controller 570 , and a power supply circuit 590 .

[0186] The flexible circuit film 510 may be connected to at least one third pad portion 230 provided on the rear surface 100 b of the substrate 100 .

[0187] The driving IC 530 can be mounted on the flexible circuit film 510. The driving IC 530 can receive sub-pixel data and data control signals provided from the timing controller 570, and can convert the sub-pixel data into analog data signals based on the data control signals, so as to provide the analog data signals to corresponding data lines DL. The data signals can be provided to corresponding third data pads in the at least one third pad portion 230 through the flexible circuit film 510.

[0188] The driving IC 530 can sense characteristic values of driving TFTs provided in the sub-pixels SP through a plurality of reference voltage lines RL (or pixel sensing lines) provided on the substrate 100, generate sensing raw data corresponding to the sensed values for each of the sub-pixels, and provide the sensing raw data for each of the sub-pixels to the timing controller 570.

[0189] The PCB 550 can be coupled to the other side peripheral portion of the flexible circuit film 510. The PCB 550 can transmit signals and power between the elements of the driving circuit portion 500.

[0190] The timing controller 570 can be mounted on the PCB 550, and can receive digital video data and a timing synchronization signal provided from a display driving system through a user connector provided on the PCB 550. Alternatively, the timing controller 570 can not be mounted on the PCB 550, but can be implemented in the display driving system, or can be mounted on a separate control board connected between the PCB 550 and the display driving system.

[0191] The timing controller 570 can arrange the digital video data based on the timing synchronization signal, so as to generate pixel data matching a pixel arrangement structure provided in the display area AA, and can provide the generated pixel data to the driving IC 530.

[0192] The timing controller 570 can generate each of data control signals and gate control signals based on the timing synchronization signal, control a driving timing of the driving IC 530 based on the data control signals, and control a driving timing of the gate driving circuit 150 based on the gate control signals. As an example, the timing synchronization signal can include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a main clock (or dot clock).

[0193] The data control signals according to one embodiment of the disclosure can include a source start pulse, a source shift clock, and a source output signal, etc. The data control signals can be provided to the driving IC 530 through the flexible circuit film 510.

[0194] The gate control signal according to one embodiment may include a start signal (or gate start signal), multiple shift clocks, a forward drive signal, and a reverse drive signal. In this case, the multiple shift clocks may include multiple scan clocks whose phases are sequentially shifted and multiple carry clocks whose phases are sequentially shifted. In addition, the gate control signal according to one embodiment may further include an external sensing line selection signal for sensing the characteristic value of the driving TFT set in the sub-pixel SP, an external sensing reset signal, and an external sensing control signal. The gate control signal can be provided to the gate drive circuit 150 through the flexible circuit film 510, at least one third pad portion 230, the connection portion 250, the second pad portion 210, the wiring portion 400, the first pad portion 110, and the gate control line GCL.

[0195] The timing controller 570 may drive each of the gate driver circuit 150 and the driver IC 530 based on an external sensing mode during a predetermined external sensing period, generate compensation data for each sub-pixel based on the raw sensing data provided by the driver IC 530 to compensate for characteristic variations of the driving TFT of each sub-pixel, and modulate the pixel data of each sub-pixel based on the generated compensation data for each sub-pixel. For example, the timing controller 570 may drive each of the gate driver circuit 150 and the driver IC 530 based on the external sensing mode during each external sensing period corresponding to the blanking period of the vertical synchronization signal (or the vertical blanking period). As an example, the external sensing mode may be executed during a power-on process of the display device, a power-off process of the display device, a process of powering off the display device after long-term driving, or a blanking period of a frame set in real time or periodically.

[0196] The timing controller 570 according to one embodiment may store the sensing raw data of each sub-pixel provided from the driver IC 530 in a storage circuit based on an external sensing mode. Furthermore, in the display mode, the timing controller 570 may correct the pixel data to be provided to each sub-pixel based on the sensing raw data stored in the storage circuit, and may provide the corrected pixel data to the driver IC 530. Here, the sensing raw data of each sub-pixel may include sequential change information related to each of the driving TFT and the self-luminous device provided in the corresponding sub-pixel. Therefore, in the external sensing mode, the timing controller 570 may sense the characteristic value (such as threshold voltage or mobility) of the driving TFT provided in each sub-pixel, and may correct the pixel data to be provided to each sub-pixel accordingly, thereby minimizing or preventing image quality degradation caused by changes in the characteristic values ​​of the driving TFTs of the plurality of sub-pixels. The external sensing mode of the display device may be a technology known to those skilled in the art, and thus its detailed description is omitted. As an example, the display device according to one embodiment of the present disclosure may sense a characteristic value of a driving TFT provided in each subpixel based on a sensing mode disclosed in Korean Patent Publication Nos. 10-2016-0093179, 10-2017-0054654, or 10-2018-0002099.

[0197] The power supply circuit 590 can be mounted on the PCB 550 and can use an externally supplied input power source to generate various source voltages required for displaying an image on the pixel P, thereby providing the generated source voltages to the corresponding circuits. For example, the power supply circuit 590 can generate and output the logic source voltages required to drive each of the timing controller 570 and the driver IC 530, multiple reference gamma voltages provided to the driver IC 530, and at least one gate drive power supply and at least one gate common power supply required to drive the gate driver circuit 150. Furthermore, the power supply circuit 590 can generate and output pixel drive power supplies and pixel common voltages, but embodiments of the present disclosure are not limited thereto. For example, the driver IC 530 can generate and output pixel drive power supplies and pixel common voltages based on multiple reference gamma voltages.

[0198] Figure 7 A rear perspective view of a light emitting display device according to another embodiment of the present disclosure is shown, and Figure 1 and Figure 6 In the illustrated light-emitting display device, an embodiment of a wiring substrate is additionally provided.

[0199] refer to Figure 7 , a light-emitting display device according to another embodiment of the present disclosure may include a substrate 100 , a second substrate 200 , a coupling member 300 , and a wiring portion 400 .

[0200] The substrate 100 may be referred to as a display substrate, a pixel array substrate, an upper substrate, a front substrate, or a base substrate. The substrate 100 may be a glass substrate, or may be a thin glass substrate or a plastic substrate that is bendable or flexible. Figure 7 In the description, the substrate 100 may be referred to as a first substrate 100 .

[0201] The first substrate 100 may be Figures 1 to 6 The substrate 100 of the illustrated light-emitting display device is substantially the same, and thus, the same reference numerals refer to the same elements, and repeated descriptions thereof may be omitted.

[0202] The second substrate 200 may be referred to as a wiring substrate, a circuit substrate, a wiring substrate, a lower substrate, a rear substrate, or wiring glass. The second substrate 200 may be a glass substrate, or a bendable or flexible thin glass substrate or a plastic substrate. For example, the second substrate 200 may be made of the same material as the first substrate 100. The size of the second substrate 200 may be the same as that of the first substrate 100, but the embodiments of the present disclosure are not limited thereto, and the size of the second substrate 200 may be smaller than that of the first substrate 100. For example, the second substrate 200 may be configured to have the same size as the first substrate 100 in order to maintain or ensure the rigidity of the first substrate 100.

[0203] The second substrate 200 may include a second pad portion 210, at least one third pad portion 230, and a wiring portion 250. In addition to being disposed on the rear surface (or backside) 200b of the second substrate 200, each of the second pad portion 210, at least one third pad portion 230, and the wiring portion 250 may be disposed on the rear surface 200b of the second substrate 200. Figure 6 Each of the illustrated second pad portion 210 , the at least one third pad portion 230 , and the wiring portion 250 is substantially identical, and thus like reference numerals refer to like elements, and repeated descriptions thereof may be omitted.

[0204] The second substrate 200 may be coupled (or connected) to the second surface (or rear surface) of the first substrate 100 using a coupling member 300. The coupling member 300 may be inserted between the first substrate 100 and the second substrate 200. Thus, the first substrate 100 and the second substrate 200 may be relatively coupled to each other via the coupling member 300.

[0205] The wiring portion 400 may be referred to as a side wiring portion, a side wiring portion, a printed wiring portion, or a printed line portion. The wiring portion 400 according to one embodiment may include a plurality of wirings 410 provided on each of the first outer surface (or one surface) OS1a of the outer surface OS of the first substrate 100 and the first outer surface (or one surface) OS1b of the outer surface OS of the second substrate 200. In addition to providing the plurality of wirings 410 to surround the first pad portion 110 and the first outer surface OS1a of the first substrate 100 and the second pad portion 210 and the first outer surface OS1b of the second substrate 200, the wiring portion 400 and Figure 6 The wiring portion 400 shown is substantially the same. Therefore, the same reference numerals refer to the same elements, and repeated descriptions thereof may be omitted.

[0206] The light emitting display device according to another embodiment of the present disclosure may further include a driving circuit part 500 .

[0207] The driving circuit portion 500 may include a flexible circuit film 510, a driving integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply circuit 590. In addition to connecting the flexible circuit film 510 to at least one third pad portion 230 provided on the rear surface 200b of the second substrate 200, the driving circuit portion 500 having such a configuration may be connected to Figure 6 The illustrated driving circuit portion 500 is substantially identical, and thus like reference numerals refer to like elements, and a repeated description thereof may be omitted.

[0208] Figure 8 It is along Figure 7 The cross-sectional view taken along line II' is shown. Figure 9 yes Figure 8 An enlarged view of area "B" is shown, Figure 10 It is along Figure 7 The cross-sectional view taken along line II-II' is shown. Figure 11 yes Figure 10 An enlarged view of area "C" is shown.

[0209] refer to Figure 7 And 8-11, the light emitting display device according to one embodiment of the present disclosure may include a first substrate 100 , a second substrate 200 , a coupling member 300 , and a wiring portion 400 .

[0210] The first substrate 100 according to an embodiment of the present disclosure may include a circuit layer 101 , a planarization layer 102 , a light emitting device layer EDL, a bank BK, and a first pad portion 110 .

[0211] The circuit layer 101 may be disposed on the first substrate 100. The circuit layer 101 may be referred to as a pixel array layer or a TFT array layer.

[0212] The circuit layer 101 according to one embodiment of the present disclosure may include a buffer layer 101 a and a circuit array layer 101 b .

[0213] The buffer layer 101a can prevent materials (e.g., hydrogen) included in the first substrate 100 from diffusing into the circuit array layer 101b during the high-temperature process of the TFT manufacturing process. Furthermore, the buffer layer 101a can prevent external moisture or humidity from penetrating into the light-emitting device layer EDL. The buffer layer 101a according to one embodiment may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof, but the embodiments of the present disclosure are not limited thereto. For example, the buffer layer 101a may include a first buffer layer BL1 containing SiNx and disposed on the first substrate 100, and a second buffer layer BL2 containing SiOx and disposed on the first buffer layer BL1.

[0214] The circuit array layer 101 b may include a pixel circuit PC including a driving TFT Tdr for each of a plurality of pixel areas PA disposed on the buffer layer 101 a .

[0215] The driving TFT Tdr disposed in the circuit region of each pixel area PA may include an active layer ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer 101 c , first and second source / drain electrodes SD1 and SD2 , and a passivation layer 101 d .

[0216] An active layer ACT may be disposed on the buffer layer 101a in each pixel area PA. The active layer ACT may include a channel region overlapping the gate electrode GE, and first and second source / drain regions interposed between adjacent channel regions and running parallel to each other. The active layer ACT may be rendered conductive during a conductive treatment, thereby directly connecting circuits in the display area AA. Furthermore, the active layer ACT may serve as a bridge wire in a jumper structure that electrically connects circuits disposed on different layers.

[0217] The gate insulating layer GI may be disposed on the channel region of the active layer ACT and may insulate the active layer ACT from the gate electrode GE.

[0218] The gate electrode GE may be disposed on the gate insulating layer GI and connected to the gate line. The gate electrode GE may overlap with the channel region of the active layer ACT with the gate insulating layer GI therebetween.

[0219] An interlayer insulating layer 101c may be provided on the first substrate 100 so as to cover the gate electrode GE and the active layer ACT. The interlayer insulating layer 101c may electrically insulate (or isolate) the gate electrode GE from the source / drain electrodes SD1 and SD2. As an example, the interlayer insulating layer 101c may be referred to as an insulating layer or a first insulating layer.

[0220] The first source / drain electrode SD1 may be disposed on the interlayer insulating layer 101c overlapping the first source / drain region of the active layer ACT and may be electrically connected to the first source / drain region of the active layer ACT through a first source / drain contact hole disposed in the interlayer insulating layer 101c. As an example, the first source / drain electrode SD1 may be a source electrode of the driving TFT Tdr, and the first source / drain region of the active layer ACT may be a source region.

[0221] The second source / drain electrode SD2 may be disposed on the interlayer insulating layer 101c overlapping the second source / drain region of the active layer ACT, and may be electrically connected to the second source / drain region of the active layer ACT through a second source / drain contact hole disposed in the interlayer insulating layer 101c. As an example, the second source / drain electrode SD2 may be a drain electrode of the driving TFT Tdr, and the second source / drain region of the active layer ACT may be a drain region.

[0222] A passivation layer 101d may be disposed on the first substrate 100 so as to cover the pixel circuit PC including the driving TFT Tdr.

[0223] According to one embodiment, the passivation layer 101d may be formed of an inorganic insulating material. For example, the passivation layer 101d may include a single layer structure containing one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof. As an example, the passivation layer 101d may be referred to as a protective layer, a circuit protection layer, a circuit insulating layer, an inorganic insulating layer, a first inorganic insulating layer, a second insulating layer, or the like.

[0224] Each of the first and second switching TFTs Tsw1 and Tsw2 constituting the pixel circuit PC may be formed together with the driving TFT Tdr, and thus a repeated description thereof may be omitted.

[0225] The circuit layer 101 according to one embodiment may further include a lower metal layer BML disposed between the first substrate 100 and the buffer layer 101 a .

[0226] The lower metal layer BML may further include a light shielding pattern (or light shielding layer) LSP disposed below (or under) the active layer ACT in each of the TFTs Tdr, Tsw1, and Tsw2 constituting the pixel circuit PC.

[0227] A light-shielding pattern LSP may be provided in an island shape between the first substrate 100 and the active layer ACT. The light-shielding pattern LSP may block light incident on the active layer ACT through the first substrate 100, thereby preventing or minimizing changes in the threshold voltage of each TFT caused by external light. Alternatively, the light-shielding pattern LSP may be electrically connected to the first source / drain electrode SD1 of the corresponding TFT, thereby functioning as a lower gate electrode of the corresponding TFT. In this case, changes in the characteristics of each TFT caused by light and changes in the threshold voltage of each TFT caused by bias voltage may be minimized or prevented.

[0228] The lower metal layer BML can serve as lines arranged parallel to one another among the gate lines GL, data lines DL, pixel driving power lines PL, pixel common voltage lines CVL, and reference voltage lines RL. For example, the lower metal layer BML can serve as a metal layer (or line) arranged parallel to the second direction Y among the pixel driving lines DL, GL, PL, CVL, RL, and GCL arranged on the first substrate 100. Each line that provides a signal and / or voltage to a pixel can be considered a pixel driving line, which includes the lines DL, GL, PL, CVL, RL, and GCL.

[0229] The planarization layer 102 may be disposed on the first substrate 100 and may provide a flat surface on the circuit layer 101. The planarization layer 102 may cover the circuit layer 101 including the driving TFT Tdr disposed in each of the plurality of pixel areas PA.

[0230] According to one embodiment, the planarization layer 102 may be disposed between the first substrate 100 and the light-emitting device layer EDL, or between the circuit layer 101 and the light-emitting device layer EDL. According to one embodiment, the planarization layer 102 may be formed of an organic insulating material, but the embodiments of the present disclosure are not limited thereto. For example, the planarization layer 102 may be formed of an organic insulating material including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide-based resin, a polyimide-based resin, or the like, but the embodiments of the present disclosure are not limited thereto.

[0231] The light emitting device layer EDL may be disposed on the planarization layer 102. The light emitting device layer EDL according to one embodiment may include a pixel electrode PE, a self-luminous device ED, and a common electrode CE.

[0232] The pixel electrode PE may be referred to as an anode electrode, a reflective electrode, a lower electrode, an anode or a first electrode of the self-luminous device ED.

[0233] The pixel electrode PE may be disposed over the planarization layer 102, overlapping the emission area EA of each of the plurality of sub-pixels SP in the first substrate 100. The pixel electrode PE may be patterned into an island shape and disposed in each sub-pixel SP, and may be electrically coupled to the first source / drain electrodes SD1 of the driving TFT Tdr of the corresponding pixel circuit PC. For example, one side of the pixel electrode PE may extend onto the first source / drain electrodes SD1 of the driving TFT Tdr, and may be electrically coupled to the first source / drain electrodes SD1 of the driving TFT Tdr via an electrode contact hole ECH disposed in the planarization layer 102.

[0234] The pixel electrode PE may include a metal material having a low work function and excellent reflection efficiency.

[0235] The pixel electrode PE according to one embodiment of the present disclosure may have a double-layer structure including a first pixel electrode layer (or a first metal layer) PEL1 and a second pixel electrode layer (or a second metal layer) PEL2. The first pixel electrode layer PEL1 and the second pixel electrode layer PEL2 may be sequentially deposited on the planarization layer 102 and then patterned simultaneously, but the embodiments of the present disclosure are not limited thereto.

[0236] The first pixel electrode layer PEL1 may be disposed on the planarization layer 102. The second pixel electrode layer PEL2 may be disposed (or stacked) on the first pixel electrode layer PEL1. As an example, the first pixel electrode layer PEL1 may act as an adhesive layer corresponding to the planarization layer 102, and may act as an auxiliary electrode of the self-luminous device ED, and may include indium tin oxide (ITO) or indium zinc oxide (IZO), but the embodiments of the present disclosure are not limited thereto. For example, the second pixel electrode layer PEL2 may act as a reflector and may perform a function of reducing the resistance of the pixel electrode PE, and may include one of aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti) and Mo-Ti alloy (MoTi), but the embodiments of the present disclosure are not limited thereto. For example, the pixel electrode PE according to one embodiment may be formed as a double-layer structure of ITO / MoTi or IZO / MoTi.

[0237] According to another embodiment, the pixel electrode PE may have a three-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, and a third pixel electrode layer (or third metal layer) PEL3 on the second pixel electrode layer PEL2. As an example, the third pixel electrode layer PEL3 may serve as an electrode of the self-luminous device ED and may include ITO or IZO. For example, according to another embodiment, the pixel electrode PE may be formed into a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0238] According to another embodiment, the pixel electrode PE may have a four-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, a third pixel electrode layer (or third metal layer) PEL3 on the second pixel electrode layer PEL2, and a fourth pixel electrode layer (or fourth metal layer) on the third pixel electrode layer PEL3.

[0239] In the four-layer pixel electrode PE, the first pixel electrode layer can serve as an adhesive layer corresponding to the planarization layer 102 and can serve as an auxiliary electrode of the self-luminous device ED, and can include one or more materials of ITO, Mo and MoTi. The second pixel electrode layer can play a function of reducing the resistance of the pixel electrode PE and can include Cu. The third pixel electrode layer can serve as a reflector and can include one or more materials of Al, Ag, Mo, Ti and MoTi. The fourth pixel electrode layer can serve as an electrode of the self-luminous device ED and can include ITO or IZO. For example, the pixel electrode PE according to another embodiment can be formed into a four-layer structure of ITO / Cu / MoTi / ITO.

[0240] The pixel electrode PE according to another embodiment may have a five-layer structure including a first pixel electrode layer made of ITO, a second pixel electrode layer made of MoTi, a third pixel electrode layer made of ITO, a fourth pixel electrode layer made of Ag, and a fifth pixel electrode layer made of ITO.

[0241] The self-luminous device ED may be disposed on the substrate 100. The self-luminous device ED may be formed on the pixel electrode PE and may directly contact the pixel electrode PE. The pixel electrode PE may be disposed below (or under) the self-luminous device ED. For example, the pixel electrode PE may be disposed between the planarization layer 102 and the self-luminous device ED.

[0242] The self-luminous device ED according to one embodiment may be a common layer formed in each of the plurality of sub-pixels SP, and thus is not distinguished per sub-pixel SP. The self-luminous device ED may respond to current flowing between the pixel electrode PE and the common electrode CE to emit white light (or blue light). For example, the self-luminous device ED according to another embodiment may include an organic light-emitting device, or may include a stacked or combined structure of an organic light-emitting device and a quantum dot light-emitting device.

[0243] An organic light-emitting device may include two or more organic light-emitting portions for emitting white light (or blue light). For example, the organic light-emitting device may include a first organic light-emitting portion and a second organic light-emitting portion that emit white light based on a combination of a first light and a second light. As an example, the first organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer that emits a second light that combines with the first light from the first organic light-emitting portion to produce white light.

[0244] The organic light emitting device according to one embodiment may further include at least one or more functional layers for improving luminous efficiency and / or lifespan. For example, the functional layer may be disposed above and / or below the light emitting layer.

[0245] The common electrode CE may be disposed on the display area AA of the first substrate 100 and may be electrically coupled to the self-luminous device ED of each of the plurality of pixels P. For example, the common electrode CE may be disposed on the remaining display area AA of the first substrate 100 excluding the first pad portion 110 of the first substrate 100 .

[0246] The common electrode CE may be referred to as a cathode electrode, a transparent electrode, an upper electrode, a cathode, or a second electrode of the self-luminous device ED. The common electrode CE may be formed on the self-luminous device ED and may directly contact the self-luminous device ED or may electrically directly contact the self-luminous device ED. The common electrode CE may include a transparent conductive material that transmits light emitted from the self-luminous device ED.

[0247] The common electrode CE according to one embodiment of the present disclosure may be formed in a single-layer structure or a multi-layer structure, and may include at least one of graphene with a relatively high work function and a transparent conductive material. For example, the common electrode CE may include a metal oxide such as ITO or IZO, or may include a combination of an oxide and a metal such as ZnO:Al or SnO2:Sb.

[0248] In addition, the light emitting device layer EDL may further include a capping layer disposed on the common electrode CE. The capping layer may be disposed on the common electrode CE and may improve light emission efficiency by adjusting a refractive index of light emitted from the light emitting device layer EDL.

[0249] The bank BK may be provided on the planarization layer 102 to define the pixel area PA on the first substrate 100. The bank BK may be provided on the planarization layer 102 to cover the peripheral portion of the pixel electrode PE. The bank BK may define the emission area EA (or opening portion) of each of the plurality of sub-pixels SP and may electrically isolate the pixel electrodes PE provided in adjacent sub-pixels SP. The bank BK may be formed to cover the electrode contact hole ECH provided in each of the plurality of pixel areas PA. The bank BK may be covered by the self-luminous device ED of the light-emitting device layer EDL. For example, the self-luminous device ED may be provided on the bank BK and on the pixel electrode PE of each of the plurality of sub-pixels SP.

[0250] Bank BK according to one embodiment may be a transparent bank including a transparent material or a black bank including a black pigment.

[0251] The first pad portion 110 may be disposed at one peripheral portion of the first substrate 100 and may be electrically coupled to the pixel driving lines DL, GL, PL, CVL, RL, and GCL in a one-to-one relationship.

[0252] The first pad portion 110 according to one embodiment of the present disclosure may include a plurality of first pads 111 .

[0253] The plurality of first pads 111 may be divided (or classified) into a first data pad DP, a first gate pad GP, a first pixel driving power pad PPP, a first reference voltage pad RVP, and a first pixel common voltage pad CVP.

[0254] Each of the plurality of first pads 111 can be electrically coupled to a corresponding line among the pixel drive lines DL, GL, PL, CVL, RL, and GCL through a pad contact hole PCH passing through the passivation layer 101d, the interlayer insulating layer 101c, and the buffer layer 101a. According to one embodiment, each of the plurality of first pads 111 can include the same material as the pixel electrode PE and can be formed together with the pixel electrode PE. According to another embodiment, each of the plurality of first pads 111 can include the same material as the source / drain electrodes of the TFT and can be formed together with the source / drain electrodes of the TFT.

[0255] The light emitting display device or the first substrate 100 according to one embodiment of the present disclosure may further include a first margin area MA1 , a second margin area MA2 , and a third margin area MA3 .

[0256] The first margin area MA1 may be provided between the emission area EA of the outermost pixel Po and the outer surface OS of the first substrate 100. The first margin area MA1 may be configured to have a first width between an end of the emission area EA (or the bank BK) of the outermost pixel Po and the outer surface OS of the first substrate 100 based on a reliability margin of the light emitting device layer EDL due to lateral penetration of water (or moisture).

[0257] The second margin area MA2 may be configured to have a second width between the outer surface OS of the first substrate 100 and the first margin area MA1 based on a reliability margin of the light emitting device layer EDL caused by lateral penetration of water (or moisture). For example, the second margin area MA2 may be a region including the first pad portion 110.

[0258] The third margin area MA3 may be disposed between the first margin area MA1 and the second margin area MA2 .

[0259] In the first direction X, the width of each of the first margin area MA1, the second margin area MA2, and the third margin area MA3 may be implemented such that the second interval D2 between the center portion of the outermost pixel and the outer surface OS of the first substrate 100 is half or less of the pixel pitch (or the first interval D1) between two adjacent pixel areas PA.

[0260] The light emitting display device or the first substrate 100 according to one embodiment of the present disclosure may further include a dam 104 , an external device isolation portion 105 , and an encapsulation layer 106 .

[0261] refer to Figure 1 、 8 , 10 and 11, the dam 104 according to one embodiment of the present disclosure may be provided at the outer portion of the first substrate 100 or the outer portion of the outermost pixel. For example, the outermost pixel provided at the outer portion of the first substrate 100 may include the dam 104 and thus may be implemented to have a structure different from that of the inner pixels.

[0262] The dam 104 may be provided in the third margin area MA3 of the first substrate 100. For example, the dam 104 may be provided in a closed loop shape surrounding the display area AA and an end portion of the planarization layer 102.

[0263] The dam 104 may be disposed above the circuit layer 101 in the outer portion of the first substrate 100 or the outermost pixel. For example, the dam 104 may be disposed above the passivation layer 101d of the circuit layer 101 so as to have a closed loop shape surrounding the display area AA. The dam 104 may prevent the encapsulation layer 106 disposed above the first substrate 100 from spreading or overflowing and covering the display area AA.

[0264] According to one embodiment, the dam 104 may include the same material as the planarization layer 102. The dam 104 may have the same height (or thickness) as the planarization layer 102, or may have a height higher than the planarization layer 102. For example, the height (or thickness) of the dam 104 may be twice the height (or thickness) of the planarization layer 102.

[0265] According to another embodiment, the dam 104 may include a first dam pattern (or lower dam) 104a formed of the same material as the planarization layer 102, and a second dam pattern (or upper dam) 104b stacked on the first dam pattern 104a and including the same material as the bank BL. The first dam pattern 104a may have the same height (or thickness) as the planarization layer 102, or may have a height higher than the planarization layer 102. For example, the height (or thickness) of the first dam pattern 104a may be twice the height (or thickness) of the planarization layer 102.

[0266] According to another embodiment, the first dam pattern 104a may be formed or implemented by a portion of the planarization layer 102 (or a non-patterned region) that has not been patterned (or removed) by performing a patterning process on the planarization layer 102 using an etching process. Furthermore, the second dam pattern 104b may be formed or implemented by a portion of the bank BK (or a non-patterned region) that has not been patterned (or removed) by performing a patterning process on the bank BK using an etching process.

[0267] refer to Figure 1 、 8 , 10 and 11, the external device isolation portion 105 according to one embodiment of the present disclosure may be provided in the peripheral portion of the first substrate 100 or the peripheral portion of the outermost pixel. For example, the outermost pixel provided in the peripheral portion of the first substrate 100 may include the external device isolation portion 105, and thus may be implemented to have a different structure from the inner pixel. In the following description, the external device isolation portion may be referred to as an external isolation portion.

[0268] The outer isolation portion 105 can be implemented to isolate (or separate) the self-emitting devices ED disposed in the second margin area MA2 of the first substrate 100. The outer isolation portion 105 can be implemented to prevent water (or moisture) from penetrating laterally across the first substrate 100, thereby preventing degradation of the self-emitting devices ED due to lateral water (or moisture) penetration. The outer isolation portion 105 can isolate (or separate) the self-emitting devices ED of the light-emitting device layer EDL at least once near or around the dam 104, thereby preventing lateral water (or moisture) penetration.

[0269] The outer isolation portion 105 may be implemented on the interlayer insulating layer 101c in the first substrate 100 to surround the display area AA. For example, the outer isolation portion 105 may be implemented in a closed loop shape over the interlayer insulating layer 101c to one-dimensionally surround the display area AA.

[0270] The outer isolation portion 105 according to one embodiment of the present disclosure may include a plurality of isolation structures 105a to 105c disposed above the interlayer insulating layer 101c in the outermost pixel. For example, the outer isolation portion 105 may include first to third isolation structures 105a, 105b, and 105c implemented in parallel to each other in a closed loop line shape.

[0271] According to one embodiment, first isolation structure 105a may be surrounded by dam 104, and second and third isolation structures 105b and 105c may be disposed in parallel to each other so as to surround dam 104. As an example, dam 104 may be disposed between first isolation structure 105a and second isolation structure 105b.

[0272] Each of the first to third isolation structures 105 a , 105 b , and 105 c according to one embodiment may include a lower structure BS, an eaves structure ES, and an upper structure US.

[0273] The lower structure BS may be implemented by the passivation layer 101d. The lower structure BS may be formed by performing a patterning process on the passivation layer 101d disposed on the outermost pixel. For example, the lower structure BS may be formed or implemented by a portion of the passivation layer 101d (or a non-patterned region) that has not been patterned (or removed) by performing a patterning process on the passivation layer 101d using an etching process.

[0274] The side surface of the lower structure BS according to one embodiment may be implemented as an inclined structure or a forward tapered structure. For example, a cross-section of the lower structure BS taken along the width direction may have a trapezoidal cross-sectional structure with a top side narrower than a bottom side. Therefore, the lower structure BS may be formed or implemented by a portion of the passivation layer 101d (or a non-patterned region) that has not been patterned (or removed) by performing a patterning process on the passivation layer 101d using an etching process.

[0275] The eaves structure ES may be arranged above the lower structure BS. The eaves structure ES may have at least a two-layer structure that is the same as the pixel electrode PE. For example, the eaves structure ES may include a first metal layer formed together with the first pixel electrode layer PEL1 of the pixel electrode PE and directly contacting the top surface of the lower structure BS, and a second metal layer formed together with the second pixel electrode layer PEL2 of the pixel electrode PE and arranged (or stacked) above the first metal layer. For example, in the eaves structure ES, the first metal layer may be made of an ITO material, and the second metal layer may be made of a Mo-Ti alloy (MoTi) material, but is not limited thereto.

[0276] According to one embodiment, the eaves structure ES may be formed or implemented by a portion of the pixel electrode PE (or a non-patterned region) that is not patterned (or removed) by a patterning process performed on the pixel electrode PE using an etching process.

[0277] The eaves structure ES may have a width greater than the top surface of the substructure BS. The side surfaces of the eaves structure ES may be shaped as an inclined structure or a forward tapered structure. For example, a cross-section of the eaves structure ES taken along the width direction may have the same trapezoidal cross-sectional structure as the substructure BS. In the width direction, each of the one side peripheral portion and the other side peripheral portion of the eaves structure ES may protrude beyond the side surface of the substructure BS.

[0278] The side surface of the lower structure BS may have an undercut structure relative to the eaves structure ES. For example, the boundary portion between the lower structure BS and the eaves structure ES or the upper side surface of the lower structure BS may have an undercut structure relative to the eaves structure ES. Accordingly, the eaves structure ES may have an eaves structure relative to the lower structure BS. According to one embodiment, the undercut structure between the lower structure BS and the eaves structure ES may be formed or achieved by an overetching process of the passivation layer 101d.

[0279] The upper structure US may be disposed above the eaves structure ES. The lower surface of the upper structure US may have the same width as the upper surface of the eaves structure ES. The upper surface of the upper structure US may have the same width as the lower surface or may have a narrower width. For example, the side surfaces of the upper structure US may be shaped as an inclined structure or a forward tapered structure.

[0280] The upper structure US according to one embodiment may include an organic insulating material or an inorganic insulating material. For example, the upper structure US may be stacked on the eaves structure ES and made of the same material as the bank BK. The upper structure US may be formed or implemented by a portion of the bank BK (or a non-patterned area) that is not patterned (or removed) by the patterning process performed on the bank BK. The upper structure US may prevent the eaves structure ES from being etched.

[0281] As described above, the outer isolation portion 105 including the first to third isolation structures 105a, 105b, and 105c can isolate (or separate) the self-luminous device ED, or can isolate (or separate) the self-luminous device ED and the common electrode CE. For example, the self-luminous device ED formed (or deposited) above the outer isolation portion 105 can be automatically isolated (or separated) during the deposition process by the undercut structure (or eaves structure) of each of the first to third isolation structures 105a, 105b, and 105c without a separate isolation process. Accordingly, the self-luminous device ED can include an isolation region isolated by the outer isolation portion 105.

[0282] According to one embodiment of the present disclosure, the deposited material of the self-luminous device ED made of an organic light-emitting device can have a linearity, thereby not being deposited on the side surface of the lower structure BS covered by the eaves structure ES based on each of the first to third isolation structures 105a, 105b and 105c. As a result, the self-luminous device ED formed (or deposited) on the external isolation portion 105 can be isolated (or separated) between the lower structure BS and the eaves structure ES of each of the first to third isolation structures 105a, 105b and 105c. Therefore, when performing the deposition process, the self-luminous device ED will be automatically isolated (or separated) by the first to third isolation structures 105a, 105b and 105c of the external isolation portion 105, and thus a separate patterning process for isolating (or separating) the self-luminous device ED can be omitted. Accordingly, the self-luminous device ED arranged above the first substrate 100 can be isolated (or separated) by the external isolation part 105 in the outer portion of the first substrate 100, thereby, the lateral water infiltration path of the first substrate 100 will be blocked by the first to third isolation structures 105a, 105b and 105c of the external isolation part 105.

[0283] Optionally, when a deposition-based deposition process is performed, the common electrode CE arranged above the self-luminous device ED will be automatically isolated (or separated) by the first to third isolation structures 105a, 105b and 105c of the external isolation part 105, or when a deposition-based deposition process is performed, a common electrode CE can be formed around all isolated island-shaped self-luminous devices ED and the first to third isolation structures 105a, 105b and 105c of the external isolation part 105.

[0284] In addition, if Figure 11 As shown, the eaves structure ES including the metal material in at least one of the first to third isolation structures 105a to 105c provided in the external isolation portion 105 can be electrically connected to at least one pixel common voltage line CVL through a through hole VH formed in the lower structure BS. As an example, the through hole VH can be formed to sequentially pass through the lower structure BS, the interlayer insulating layer 101c, and the buffer layer 101a at the intersection portion provided between the pixel common voltage line CVL and the eaves structure ES having a closed loop line shape. Thus, the eaves structure ES provided in at least one of the first to third isolation structures 105a to 105c can be electrically connected to at least one pixel common voltage line CVL through the corresponding through hole VH. Accordingly, the eaves structure ES can form an equipotential together with the plurality of pixel common voltage lines CVL, and can mainly block the flow of static electricity from the outside to the inside of the display area AA, so as to prevent defects caused by static electricity. For example, the eaves structure ES provided in at least one of the first to third isolation structures 105 a to 105 c may discharge static electricity flowing from the outside to the pixel common voltage line CVL, so as to prevent defects caused by static electricity.

[0285] refer to Figures 8 to 11 According to one embodiment of the present disclosure, the encapsulation layer 106 may be provided on the remaining portion of the first substrate 100 except for the outermost portion including the first pad portion 110, and may be implemented to cover the light-emitting device layer EDL. For example, the encapsulation layer 106 may be implemented to surround all front and side surfaces of the light-emitting device layer EDL, thereby preventing oxygen or water (or moisture) from penetrating into the light-emitting device layer EDL, thereby improving the reliability of the light-emitting device layer EDL.

[0286] The encapsulation layer 106 according to one embodiment of the present disclosure may include first to third encapsulation layers 106 a to 106 c .

[0287] The first encapsulation layer 106a may be implemented to prevent oxygen or water from penetrating into the light-emitting device layer EDL. The first encapsulation layer 106a may be disposed above the common electrode CE and may surround the light-emitting device layer EDL. Thus, all front and side surfaces of the light-emitting device layer EDL may be surrounded by the first encapsulation layer 106a. According to one embodiment, the first encapsulation layer 106a may include an inorganic insulating material.

[0288] When the self-luminous device ED and the common electrode CE are isolated by the outer isolation portion 105, the first encapsulation layer 106a may surround the isolation surface (or separation surface) of the self-luminous device ED and the common electrode CE isolated by the outer isolation portion 105. For example, the first encapsulation layer 106a may fill (or embed) the isolation space between the self-luminous device ED and the common electrode CE formed by the isolation structure (or undercut structure) of the outer isolation portion 105, so as to seal or completely surround the outer isolation portion 105, thereby completely surrounding or covering each of the isolated self-luminous device ED and the common electrode CE, thereby fundamentally (or completely) preventing lateral penetration of water (or moisture).

[0289] Second encapsulation layer 106b may be implemented on first encapsulation layer 106a, which is disposed within the encapsulation region defined by dam 104, and may be thicker than first encapsulation layer 106a. Second encapsulation layer 106b may be thick enough to completely cover particles (or undesirable materials or undesirable structural components) located or potentially located on first encapsulation layer 106a. Due to its relatively thick thickness, second encapsulation layer 106b may diffuse into the outer periphery of first substrate 100, but diffusion of second encapsulation layer 106b may be blocked by dam 104.

[0290] According to one embodiment of the present disclosure, the second encapsulation layer 106b may include an organic insulating material or a liquid organic insulating material. For example, the second encapsulation layer 106b may include an organic insulating material such as SiOCz, acrylic resin, or epoxy resin. The second encapsulation layer 106b may be referred to as a particle covering layer, an organic encapsulation layer, or the like.

[0291] The third encapsulation layer 106c may be implemented to primarily prevent oxygen or water from penetrating into the light-emitting device layer EDL. The third encapsulation layer 106c may be implemented to surround all of the second encapsulation layer 106b disposed inside the dam 104 and the first encapsulation layer 106a disposed outside the dam 104. According to one embodiment, the third encapsulation layer 106c may include the same or different inorganic insulating material as the first encapsulation layer 106a.

[0292] Reference again Figure 8 and 10The light-emitting display device or the first substrate 100 according to one embodiment of the present disclosure may further include a wavelength conversion layer 107 disposed above the encapsulation layer 106 .

[0293] The wavelength conversion layer 107 may convert the wavelength of light incident thereon from the light-emitting region of each pixel area PA. For example, the wavelength conversion layer 107 may convert white light (or blue light) incident thereon from the light-emitting region into color light corresponding to the sub-pixel SP, or may transmit only the color light corresponding to the sub-pixel SP. For example, the wavelength conversion layer 107 may include at least one of a wavelength conversion member and a color filter layer.

[0294] The wavelength conversion layer 107 according to one embodiment may include a plurality of wavelength conversion members 107 a and a protective layer 107 b .

[0295] A plurality of wavelength conversion members 107a may be disposed over the encapsulation layer 106 disposed in the emission area EA of each of the plurality of sub-pixels SP. For example, each of the plurality of wavelength conversion members 107a may be implemented to have a size equal to or larger than the emission area EA of each sub-pixel region.

[0296] According to one embodiment, the plurality of wavelength conversion members 107a may be divided (or classified) into a red filter that converts white light into red light, a green filter that converts white light into green light, and a blue filter that converts white light into blue light. For example, the red filter (or first filter) may be disposed above the encapsulation layer 106 in the emission area EA of the red sub-pixel SP, the green filter (or second filter) may be disposed above the encapsulation layer 106 in the emission area EA of the green sub-pixel SP, and the blue filter (or third filter) may be disposed above the encapsulation layer 106 in the emission area EA of the blue sub-pixel SP.

[0297] According to another embodiment, a plurality of wavelength conversion members 107a may be disposed over the encapsulation layer 106 of each sub-pixel region. For example, each of the plurality of wavelength conversion members 107a may be disposed over the encapsulation layer 106 so as to overlap the entire corresponding sub-pixel SP.

[0298] According to another embodiment, a plurality of wavelength conversion members 107a may be implemented to overlap one another on the encapsulation layer 106 that overlaps the circuit area CA (or non-emission area) of each sub-pixel SP, excluding the emission area EA. For example, two or more wavelength conversion members 107a having different colors may be provided on the encapsulation layer 106 that overlaps the circuit area CA (or non-emission area) of each sub-pixel SP, excluding the emission area EA. The two or more wavelength conversion members 107a provided on the encapsulation layer 106 that overlaps the circuit area CA (or non-emission area) may function as a light shielding pattern that prevents color mixing between adjacent sub-pixels SP or between adjacent pixels P.

[0299] The protective layer 107b may be implemented to cover the wavelength conversion member 107a and provide a flat surface above the wavelength conversion member 107a. The protective layer 107b may be provided to cover the wavelength conversion member 107a and the encapsulation layer 106 where the wavelength conversion member 107a is not provided. According to one embodiment, the protective layer 107b may include an organic insulating material. Alternatively, the protective layer 107b may further include a getter material for absorbing water and / or oxygen.

[0300] Alternatively, the wavelength conversion layer 107 according to another embodiment may include two or more wavelength conversion members 107a disposed above the encapsulation layer 106 and overlapping the circuit area CA (or non-light-emitting area) excluding the light-emitting area EA in each sub-pixel SP. The two or more wavelength conversion members 107a may serve as a light-shielding pattern.

[0301] Alternatively, the wavelength conversion layer 107 may be a plate-shaped wavelength conversion sheet and may be provided on the encapsulation layer 106. In this case, the wavelength conversion sheet (or quantum dot sheet) may include a wavelength conversion member 107a provided between a pair of thin films. For example, when the wavelength conversion layer 107 includes quantum dots for re-emitting the color light set in the sub-pixel SP, the light-emitting device layer EDL of the sub-pixel may be implemented to emit white light or blue light.

[0302] Reference Figure 8 and 10 , the light emitting display device or the first substrate 100 according to one embodiment of the present disclosure may further include a functional film 108 .

[0303] The functional film 108 may be disposed above the wavelength conversion layer 107. For example, the functional film 108 may be bonded to the wavelength conversion layer 107 via a transparent adhesive member. The functional film 108 according to one embodiment may include at least one of an anti-reflection layer (or anti-reflection film), a barrier layer (or barrier film), a touch sensing layer, and a light path control layer (or light path control film).

[0304] The anti-reflection layer may include a circular polarization layer (or a circular polarization film) for preventing external light reflected by the TFTs and / or pixel driving lines disposed on the substrate 100 from being transmitted to the outside.

[0305] The barrier layer may comprise a material with a low water permeability (eg, a polymeric material) and may primarily prevent the permeation of water or oxygen.

[0306] The touch sensing layer may include a touch electrode layer based on a mutual capacitance method or a self-capacitance method, and may output touch data corresponding to a user's touch through the touch electrode layer.

[0307] The light path control layer may include a stack structure in which high refractive index layers and low refractive index layers are alternately stacked, and may change a path of light incident from each pixel P so as to minimize color shift based on a viewing angle.

[0308] refer to Figure 8 and 10 The light-emitting display device or the first substrate 100 according to one embodiment of the present disclosure may further include a side sealing member 109 .

[0309] The side sealing member 109 may be formed between the first substrate 100 and the functional film 108 and may cover all side surfaces of the circuit layer 101 and the wavelength conversion layer 107. For example, the side sealing member 109 may cover all side surfaces of each of the circuit layer 101 and the wavelength conversion layer 107 between the functional film 108 and the first substrate 100 that are exposed to the outside of the display device. Furthermore, the side sealing member 109 may cover a portion of the wiring portion 400 coupled to the first pad portion 110 of the first substrate 100. The side sealing member 109 may prevent lateral light leakage caused by light emitted from the self-emitting device ED of each sub-pixel SP that travels from the interior to the exterior of the wavelength conversion layer 107. In particular, the side sealing member 109, overlapping the first pad portion 110 of the first substrate 100, may prevent or minimize light reflection caused by the first pad 111 provided in the first pad portion 110.

[0310] Optionally, the side sealing member 109 may further include a getter material for absorbing water and / or oxygen.

[0311] The display device or the first substrate 100 according to one embodiment of the present disclosure may further include a first chamfer 100c of a corner portion provided between the first surface 100a and the outer surface OS. The first chamfer 100c can reduce or minimize damage to the corner portion of the first substrate 100 caused by a physical impact applied from the outside, and can prevent disconnection of the wiring portion 400 caused by the corner portion of the first substrate 100. As an example, the first chamfer 100c can have a 45-degree angle, but the embodiments of the present disclosure are not limited thereto. The first chamfer 100c can be achieved by a chamfer process using a cutting wheel, a polishing wheel, or a laser. Accordingly, by removing or polishing the corresponding portion together with the corner portion of the first substrate 100 by means of a chamfer process, each outer surface of the first pad 111 of the first pad portion 110 provided to be in contact with the first chamfer 100c can include an inclined surface that is inclined at an angle corresponding to the angle of the first chamfer 100c. For example, when the first chamfer 100c is formed at an angle of 45 degrees between the outer surface OS of the first substrate 100 and the first surface 100a, the outer surface (or end) of the first pad 111 of the first pad part 110 may be formed at an angle of 45 degrees.

[0312] refer to Figure 7 、 8 and 10, the second substrate 200 according to one embodiment of the present disclosure may include as shown in reference Figure 7 The second pad portion 210 , the at least one third pad portion 230 , and the connection portion 250 are described, and therefore, repeated descriptions thereof will be omitted or brief.

[0313] The second substrate 200 according to one embodiment may include a metal pattern layer and an insulating layer insulating the metal pattern layer.

[0314] The metal pattern layer (or conductive pattern layer) may include multiple metal layers. According to one embodiment, the metal pattern layer may include a first metal layer 201, a second metal layer 203, and a third metal layer 205. The insulating layer may include multiple insulating layers. For example, the insulating layer may include a first insulating layer 202, a second insulating layer 204, and a third insulating layer 206. The insulating layer may be referred to as a rear insulating layer or a patterned insulating layer.

[0315] The first metal layer 201 may be implemented on the rear surface 200b of the second substrate 200. The first metal layer 201 according to one embodiment may include a first metal pattern. For example, the first metal layer 201 may be referred to as a first connection layer or a wiring layer.

[0316] The first metal pattern according to one embodiment may have a two-layer structure of Cu and MoTi (Cu / MoTi) The first metal pattern may be used as a wiring of the wiring portion 250 , and thus a repeated description thereof is omitted.

[0317] The first insulating layer 202 may be implemented on the rear surface 200b of the second substrate 200 so as to cover the first metal layer 201. The first insulating layer 202 according to one embodiment may include an inorganic insulating material.

[0318] The second metal layer 203 may be implemented on the first insulating layer 202. The second metal layer 203 according to one embodiment may include a second metal pattern. As an example, the second metal layer 203 may be referred to as a second connection layer, a jumper layer, or a bridge layer.

[0319] According to one embodiment, the second metal pattern may have a two-layer structure of Cu and MoTi (Cu / MoTi). The second metal pattern may be used as a plurality of gate lines among the plurality of lines of the wiring portion 250, but the embodiments of the present disclosure are not limited thereto. For example, the second metal layer 203 may be used as a jumper (or bridge line) for electrically connecting lines formed of different metal materials on different layers in the wiring portion 250.

[0320] Optionally, the connection lines (eg, multiple first connection lines) set in the second metal layer 203 may be changed to be set in the first metal layer 201 , and the connection lines (eg, multiple second connection lines) set in the first metal layer 201 may be changed to be set in the second metal layer 203 .

[0321] The second insulating layer 204 may be implemented on the rear surface 200b of the second substrate 200 so as to cover the second metal layer 203. The second insulating layer 204 according to one embodiment may include an inorganic insulating material.

[0322] The third metal layer 205 may be implemented on the second insulating layer 204. The third metal layer 205 according to one embodiment may include a third metal pattern. As an example, the third metal layer 205 may be referred to as a third connection layer or a pad electrode layer.

[0323] According to one embodiment, the third metal pattern may have a stacked structure of at least two materials selected from ITO (or IZO), Mo, Ti, and MoTi. For example, the third metal pattern may have a three-layer structure of any one of ITO / Mo / ITO, ITO / MoTi / ITO, IZO / Mo / ITO, or IZO / MoTi / ITO. The third metal pattern may be used as the pad 211 of the second pad portion 210. For example, the pad 211 of the second pad portion 210 formed by the third metal layer 205 may be electrically coupled to the first metal layer 201 through a pad contact hole formed in the first insulating layer 202 and the second insulating layer 204.

[0324] A third insulating layer 206 may be formed on the rear surface 200b of the second substrate 200 to cover the third metal layer 205. According to one embodiment, the third insulating layer 206 may include an organic insulating material. For example, the third insulating layer 206 may include an insulating material such as optical acrylic. The third insulating layer 206 may cover the third metal layer 205 to prevent the third metal layer 205 from being exposed to the outside. The third insulating layer 206 may be referred to as an organic insulating layer, a protective layer, a rear protective layer, an organic protective layer, a rear coating layer, or a rear cover layer.

[0325] Each of the plurality of second pads 211 provided in the second pad portion 210 can be electrically coupled to a line of the wiring portion 250 made of the first metal layer 201 or the second metal layer 203 provided on the rear surface 200b of the second substrate 200 through a second pad contact hole provided in the first and second insulating layers 202 and 204. For example, the second data pad can be electrically coupled to one end of the data line through the second pad contact hole provided in the first and second insulating layers 202 and 204.

[0326] refer to Figure 7 、 8 10, according to one embodiment of the present disclosure, a coupling member 300 may be disposed between the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 may be coupled relative to each other via the coupling member 300. According to one embodiment, the coupling member 300 may be a transparent adhesive member or a double-sided tape containing an optically clear adhesive (OCA), an optically clear resin (OCR), or a pressure-sensitive adhesive (PSA). According to another embodiment, the coupling member 300 may include glass fiber.

[0327] The coupling member 300 according to one embodiment may be provided in the entire space between the first substrate 100 and the second substrate 200. For example, the entire rear surface 100b of the first substrate 100 may be coupled to one entire surface of the coupling member 300, and the entire front surface 200a of the second substrate 200 may be coupled to the other entire surface of the coupling member 300.

[0328] According to another embodiment, the coupling member 300 may be provided between the first substrate 100 and the second substrate 200 in a patterned structure. For example, the coupling member 300 may have a line pattern structure or a grid pattern structure. The grid pattern structure may further include a curved portion that discharges air bubbles generated between the first substrate 100 and the second substrate 200 to the outside during the bonding process between the first substrate 100 and the second substrate 200.

[0329] refer to Figure 7 、 8 10, the wiring portion 400 according to one embodiment of the present disclosure may include a plurality of wirings 410 electrically coupling the first pad portion 110 and the second pad portion 210 in a one-to-one relationship. Figure 7 has been described, and thus its repeated description is omitted.

[0330] The light emitting display device or the wiring portion 400 according to one embodiment of the present disclosure may further include an edge coating layer 430 .

[0331] The edge coating 430 may be implemented to cover the wiring portion 400. The edge coating 430 may be implemented to cover the plurality of wirings 410. As an example, the edge coating 430 may be an edge protection layer or an edge insulation layer.

[0332] According to one embodiment, the edge coating 430 may be implemented to cover the entire first outer surface OS1a and first peripheral portion of the first substrate 100, as well as the entire first outer surface OS1b and first peripheral portion of the second substrate 200, in addition to the plurality of wirings 410. The edge coating 430 can prevent corrosion of each of the plurality of wirings 410, which may be made of a metallic material, or electrical shorts between the plurality of wirings 410. Furthermore, the edge coating 430 can prevent or minimize external light reflection caused by the plurality of wirings 410 and the first pads 111 of the first pad portion 110. In one embodiment, the edge coating 430 may include a light-shielding material containing black ink. In another embodiment, the edge coating 430 may implement (or constitute) the outermost surface (or sidewall) of the display device (or display panel) and may include an impact-absorbing material (or substance) or a ductile material to prevent damage to the outer surface OS of each of the first substrate 100 and the second substrate 200. In another embodiment, the edge coating 430 may include a hybrid of a light-shielding material and an impact-absorbing material.

[0333] According to one embodiment, the edge coating layer 430 may be formed to surround one outer surface OS of each of the first and second substrates 100 and 200 , where the wiring portion 400 is provided.

[0334] According to another embodiment, Figure 7 、 8 As shown in Figures 10 and 10, the edge coating 430 may be formed to surround all outer surfaces OS of each of the first substrate 100 and the second substrate 200, except for the one outer surface OS on which the wiring portion 400 is provided. For example, the edge coating 430 may be formed to surround all outer surfaces of each of the first substrate 100 and the second substrate 200. In this case, one outer surface OS (or the first outer surface) of each of the first substrate 100 and the second substrate 200 may be surrounded by the plurality of wirings 410 and the edge coating 430. The outer surfaces OS (or the second to fourth outer surfaces) of each of the first substrate 100 and the second substrate 200, except for the one outer surface OS, may be surrounded only by the edge coating 430. For example, the first outer surface of each of the first substrate 100 and the second substrate 200 may include the plurality of wirings 410 and the edge coating 430, and the second to fourth outer surfaces of each of the first substrate 100 and the second substrate 200, except for the first outer surface, may include only the edge coating 430.

[0335] According to one embodiment, when the plurality of wirings 410 and the edge coating 430 provided on the first outer surface are referred to as a first sidewall structure, and the edge coating 430 provided on the second to fourth outer surfaces is referred to as a second sidewall structure, the first sidewall structure and the second sidewall structure may have different thicknesses (or widths). For example, the thickness (or width) of the second sidewall structure may be thinner or narrower than the thickness (or width) of the first sidewall structure by the thickness of the plurality of wirings 410.

[0336] Figure 12 yes Figure 3 An enlarged view of area "D" is shown, Figure 13 12 is a cross-sectional view taken along line III-III'. These drawings are used to describe Figure 3 The common electrode connection part, auxiliary line connection part and internal isolation part are shown in FIG. Figure 12 and 13 In the process, Figure 3 Repeated descriptions of elements that are identical or corresponding to the elements in the present invention will be omitted or briefly given below.

[0337] refer to Figure 3 、 8 , 12 and 13, each of the multiple common electrode connection parts CECP according to an embodiment of the present disclosure can be set in the first electrode connection area ECA1 between the multiple pixels P, overlapping with each of the multiple pixel common voltage lines CVL, and can electrically connect the common electrode CE to each of the multiple pixel common voltage lines CVL.

[0338] Each of the plurality of common electrode connection parts CECP may include a first electrode connection pattern ECP1 , a groove GRV, a second electrode connection pattern ECP2 , and a connection trench CT.

[0339] The first electrode connection pattern ECP1 may be disposed in the circuit layer 101 in a first electrode connection area ECA1 disposed between the plurality of pixels P, and may be electrically connected to each of the plurality of pixel common voltage lines CVL in the first direction X through a first through hole VH1 .

[0340] According to one embodiment of the present disclosure, the first electrode connection pattern ECP1 may be disposed above the interlayer insulating layer 101c of the circuit layer 101 so as to extend along the first direction X and intersect with the corresponding pixel common voltage line CVL. A first through hole VH1 may be formed in the interlayer insulating layer 101c in an overlapping region between the first electrode connection pattern ECP1 and the pixel common voltage line CVL. The first electrode connection pattern ECP1 may be covered by a passivation layer 101d.

[0341] According to one embodiment, the first electrode connection pattern ECP1 may be formed together with the source / drain electrodes of a thin film transistor (TFT) provided in the pixel. According to another embodiment, the first electrode connection pattern ECP1 may include a metal line layer directly connected to the pixel common voltage line CVL through a first through hole VH1, and a cover metal layer covering only a portion of the metal line layer. The cover metal layer (or cladding layer) may prevent corrosion of the metal line layer.

[0342] The groove GRV may be formed to expose the top surface of the circuit layer 101 disposed in the first electrode connection area ECA1. The groove GRV may expose the passivation layer 101d of the circuit layer 101 disposed in the first electrode connection area ECA1. For example, the groove GRV may be formed by performing a patterning process on the planarization layer 102 disposed in the first electrode connection area ECA1 in the planarization layer 102 covering the circuit layer 101.

[0343] The second electrode connection pattern ECP2 may be disposed in, near, or around the groove GRV so as to be electrically connected to the first electrode connection pattern ECP1.

[0344] According to one embodiment, the second electrode connection pattern ECP2 may be disposed on the planarization layer 102 on the pixel common voltage line CVL and on the passivation layer 101d exposed in the first electrode connection area ECA1, and may be electrically connected to the first electrode connection pattern ECP1 through a second through hole VH2 formed in the passivation layer 101d above the first electrode connection pattern ECP1.

[0345] The second electrode connection pattern ECP2 according to one embodiment can be formed together with the pixel electrode PE provided in the pixel.

[0346] According to another embodiment, the second electrode connection pattern ECP2 can include only a metal material which is not damaged or eroded by a patterning process or a trench process which forms the connection trench CT. For example, the second electrode connection pattern ECP2 can include a first metal line pattern MLP1 directly connected to the first electrode connection pattern ECP1 through the second via VH2, and a second metal line pattern MLP2 stacked on the first metal line pattern MLP1. As an example, the first metal line pattern MLP1 can include indium tin oxide (ITO), and the second metal line pattern MLP2 can include a molybdenum titanium alloy (MoTi). For example, the pixel electrode PE can be implemented as a five-layer structure including a first pixel electrode layer including ITO, a second pixel electrode layer including MoTi, a third pixel electrode layer including ITO, a fourth pixel electrode layer including silver (Ag), and a fifth pixel electrode layer including ITO, in which case the second electrode connection pattern ECP2 can include only the first and second pixel electrode layers among the first to fifth pixel electrode layers of the pixel electrode PE except for the third to fifth pixel electrode layers.

[0347] The connection trench CT can be formed by performing a patterning process on the passivation layer 101d covering the peripheral portion of the first electrode connection pattern ECP1. For example, the connection trench CT can be formed by a patterning process performed on the passivation layer 101d after performing a patterning process on the pixel electrode PE and the second electrode connection pattern ECP2. That is, the connection trench CT can be formed together with a lower structure of the outer isolation portion 105 formed or provided in the outermost pixel by the same patterning process, whereby a repeated description thereof will be omitted or a brief description will be given hereinafter.

[0348] The connection trench CT according to one embodiment can be formed to expose the passivation layer 101d covering the peripheral portion of the first electrode connection pattern ECP1. The connection trench CT can be defined by a side surface of the passivation layer 101d provided between the end portion of the second electrode connection pattern ECP2 and the peripheral portion of the first electrode connection pattern ECP1. For example, the connection trench CT can have a bevel structure or a positive taper structure, but is not limited thereto. Thus, the connection trench CT can be an undercut region between the end portion of the second electrode connection pattern ECP2 and the peripheral portion of the first electrode connection pattern ECP1. The undercut region between the end portion of the second electrode connection pattern ECP2 and the peripheral portion of the first electrode connection pattern ECP1 can be formed or implemented by a over-etching process performed on the passivation layer 101d using the second electrode connection pattern ECP2 as a mask.

[0349] The second electrode connection pattern ECP2 may protrude beyond the side surface of the connection trench CT and may overlap or directly face the outer portion of the first electrode connection pattern ECP1. The second electrode connection pattern ECP2 may include a protruding tip PT that extends beyond the side surface of the connection trench CT and faces the first electrode connection pattern ECP1. Therefore, the end portion (or protruding tip PT) of each of the first metal line pattern MLP1 and the second metal line pattern MLP2 of the second electrode connection pattern ECP2 may have an eaves structure relative to the connection trench CT. For example, the protruding tip PT of the second electrode connection pattern ECP2 may have an eaves structure relative to the connection trench CT. For example, the protruding tip PT of the second electrode connection pattern ECP2 may be formed or implemented by an over-etching process performed on the passivation layer 101d using the second electrode connection pattern ECP2 as a mask. As an example, the protruding tip PT of the second electrode connection pattern ECP2 may be referred to as a first protruding tip.

[0350] The second electrode connection pattern ECP2 can be directly electrically connected to the common electrode CE based on a side contact method. For example, in the case of forming a self-luminous device ED through a deposition process, the deposited material of the self-luminous device ED can have a linearity, thereby being deposited on the top surface (or upper surface) of the second electrode connection pattern ECP2, but not on the side surface and bottom surface (or lower surface) of the second electrode connection pattern ECP2. Accordingly, the side surface and bottom surface of the second electrode connection pattern ECP2 will not be covered by the self-luminous device ED and can be exposed to the outside. For example, the side surface of the first metal line pattern MLP1 in the second electrode connection pattern ECP2 and the side surface and bottom surface of the second metal line pattern MLP2 will not be covered by the self-luminous device ED and can be exposed to the outside.

[0351] The second electrode connection pattern ECP2 can isolate (or disconnect) the self-luminous device ED disposed in the first electrode connection area ECA1. For example, the deposited material of the self-luminous device ED will not be deposited on the side surface of the connection trench CT covered by the protruding tip PT of the second electrode connection pattern ECP2, and thus can be isolated (or disconnected) in the undercut region based on the connection trench CT. Furthermore, the deposited material of the self-luminous device ED deposited on the peripheral portion of the first electrode connection pattern ECP1 can be covered by the protruding tip PT of the second electrode connection pattern ECP2, and thus can be spaced apart from the side surface of the connection trench CT. Accordingly, a portion of the first electrode connection pattern ECP1 that overlaps with or is covered by the protruding tip PT of the second electrode connection pattern ECP2 will not be covered by the deposited material of the self-luminous device ED and will be exposed.

[0352] The common electrode CE can be formed on the top surface of the self-luminous device ED and can also be deposited on the side and bottom surfaces of the second electrode connection pattern ECP2, thereby directly electrically connecting to the second electrode connection pattern ECP2 using a side contact method. For example, the common electrode CE can be formed using a physical deposition process or a chemical deposition process. In this case, the common electrode material can be deposited above the self-luminous device ED and can pass through the undercut region based on the connection trench CT and be deposited on the side and bottom surfaces of the second electrode connection pattern ECP2. As a result, the common electrode CE can be directly electrically connected to the side surfaces of the first metal line pattern MLP1 and the side and bottom surfaces of the second metal line pattern MLP2 in the second electrode connection pattern ECP2, thereby electrically connecting to the pixel common voltage line CVL via the second electrode connection pattern ECP2 and the first electrode connection pattern ECP1. Accordingly, even without forming a separate contact hole or a separate contact structure material, the common electrode CE can be electrically connected to the pixel common voltage line CVL via the common electrode connection portion CECP.

[0353] The common electrode CE can be formed to be continuous in the undercut region based on the connection trench CT without being isolated or disconnected, thereby being formed to completely surround the self-luminous device ED. According to one embodiment, the common electrode CE can be inserted into the undercut region based on the connection trench CT and can cover the side surface of the connection trench CT, a portion of the first electrode connection pattern ECP1 covered and exposed by the protruding tip PT of the second electrode connection pattern ECP2, and the self-luminous device ED isolated at the first electrode connection pattern ECP1. Therefore, in the undercut region between the protruding tip PT of the second electrode connection pattern ECP2 and the first electrode connection pattern ECP1, the common electrode CE can be directly electrically connected to a portion of the first electrode connection pattern ECP1. Accordingly, the common electrode CE can be directly electrically connected to the protruding tip PT of the second electrode connection pattern ECP2 and can also be directly connected to the first electrode connection pattern ECP1, thereby increasing the electrical contact area between the common electrode CE and the common electrode connection portion CECP.

[0354] Each of the plurality of common electrode connection parts CECP may be covered and planarized by the encapsulation layer 106. For example, the first encapsulation layer 106a of the encapsulation layer 106 may be disposed on the common electrode CE so as to surround or cover the common electrode CE. The second encapsulation layer 106b of the encapsulation layer 106 may be disposed on the first encapsulation layer 106a and may provide a flat surface on the first encapsulation layer 106a. Accordingly, the region overlapping with the groove GRV formed in each of the plurality of common electrode connection parts CECP may be planarized by the second encapsulation layer 106b. The second encapsulation layer 106b may be covered by the third encapsulation layer 106c of the encapsulation layer 106.

[0355] Each of the plurality of auxiliary line connection portions SLCP according to one embodiment of the present disclosure may be disposed in the second electrode connection area ECA2 between the plurality of pixels P, overlap each of the plurality of auxiliary voltage lines SVL, and may electrically connect the common electrode CE to the plurality of auxiliary voltage lines SVL.

[0356] Each of the plurality of auxiliary line connection parts SLCP may include a first electrode connection pattern ECP1, a groove GRV, a second electrode connection pattern ECP2, and a connection trench CT. Each of the plurality of auxiliary line connection parts SLCP may be substantially identical to each of the plurality of common electrode connection parts CECP, except that each of the plurality of auxiliary line connection parts SLCP electrically connects the common electrode CE to each of the plurality of auxiliary voltage lines SVL at a second electrode connection area ECA2 parallel to the first electrode connection area ECA1. Thus, like reference numerals denote like components, and repeated description thereof will be omitted.

[0357] In a light-emitting display device according to an embodiment of the present disclosure, each pixel common voltage line CVL of each pixel P arranged in the display area AA can be electrically connected to the common electrode CE through the common electrode connection portion CECP and the auxiliary line connection portion SLCP in each pixel P. Therefore, the pixel common voltage applied to each pixel P can be uniform, thereby preventing or minimizing image quality degradation or uneven brightness due to regional non-uniformity (or deviation) of the pixel common voltage applied to each pixel P.

[0358] Each of the plurality of inner isolating portions 103 may be disposed near or around each of the plurality of common electrode connection portions CECP so as to surround each of the plurality of common electrode connection portions CECP. One inner isolating portion 103 may be disposed near or around the common electrode connection portion CECP so as to surround one common electrode connection portion CECP.

[0359] Each of the plurality of inner isolation portions 103 may be disposed to surround each of the plurality of auxiliary line connection portions SLCP. For example, each of the plurality of inner isolation portions 103 may be disposed to surround all of one common electrode connection portion CECP and one auxiliary line connection portion SLCP.

[0360] Each of the plurality of inner isolation portions 103 according to an embodiment of the present disclosure may include first to n-th trench structures 103 - 1 to 103 - 2 .

[0361] Each of the first to nth groove structures according to one embodiment may have an arc shape including an opening portion one-dimensionally on one side. Each of the first to nth groove structures may have an arc shape arranged in a concentric circle shape and open on one side. Multiple isolation structures may be nested, with one isolation structure inside another isolation structure, and their openings are opposite to each other. For example, the first to nth groove structures may have a C-shape one-dimensionally, but the embodiments of the present disclosure are not limited thereto. In addition to the C-shape, it may also include, for example, a box shape, a cross-finger comb shape or other shapes.

[0362] According to one embodiment, an opening portion of a kth trench structure (where k is 1 to n-1) among the first to nth trench structures may be surrounded by a k+1th trench structure.

[0363] Each of the plurality of internal device isolation portions 103 according to an embodiment may include a first trench structure 103 - 1 and a second trench structure 103 - 2 . In one embodiment, the trench structure may be a vertical structure or a mesa formed within the trench.

[0364] The first trench structure 103-1 may be disposed to surround a portion near or around a common electrode connection portion CECP and an auxiliary line connection portion SLCP. The opening portion of the first trench structure 103-1 may be adjacent to the common electrode connection portion CECP. Accordingly, the auxiliary line connection portion SLCP may be surrounded by the first trench structure 103-1. For example, the common electrode connection portion CECP and the auxiliary line connection portion SLCP may be disposed in an inner region of the first trench structure 103-1.

[0365] The second trench structure 103-2 may be disposed around the first trench structure 103-1. The second trench structure 103-2 may surround the opening portion of the first trench structure 103-1. The opening portion of the second trench structure 103-2 may face in a direction opposite to the opening portion of the first trench structure 103-1, so that it faces the closed portion of the first trench structure 103-1.

[0366] According to one embodiment, each of the first trench structure 103-1 and the second trench structure 103-2 may include a first trench pattern (or a first trench pattern structure) 103a, a second trench pattern (or a second trench pattern structure) 103b, and a third trench pattern (or a third trench pattern structure) 103c. The pattern referred to herein includes a structure formed with the pattern or a structure including the formed pattern.

[0367] The first trench pattern 103a can be disposed on the passivation layer 101d in the vicinity of, around, or partially around the pixel trench region of one common electrode connection part CECP and one sub-line connection part SLCP. The first trench pattern 103a can have an arc shape with one side open in a concentric circle shape. For example, the first trench pattern 103a can have a C shape in one dimension, but embodiments of the present disclosure are not limited thereto.

[0368] The first trench pattern 103a can include the same material as the planarization layer 102. For example, the first trench pattern 103a can be formed or implemented by a portion of the planarization layer 102 (or a non-patterned region) that is patterned (or removed) by a patterning process performed on the planarization layer 102 disposed above the passivation layer 101d of the pixel trench region. Accordingly, the first trench pattern 103a can have the same thickness (or thickness height) as the planarization layer 102.

[0369] The first trench pattern 103a according to one embodiment can be implemented in a tilted vertical structure or a positive taper structure. For example, in the first trench pattern 103a, the width of the bottom surface can be wider than that of the top surface, whereby the side surface can be implemented as a tilted structure or a positive taper structure. As an example, the first trench pattern 103a taken along the first direction X can have a cross-sectional structure of a trapezoidal shape with the top edge narrower than the bottom edge.

[0370] The second trench pattern 103b can be disposed on the first trench pattern 103a.

[0371] The second trench pattern 103b according to one embodiment can be formed together with the pixel electrode PE disposed in the pixel. For example, the second trench pattern 103b can be formed together with the second electrode connection pattern ECP2 and can be a vertical isolation element.

[0372] The second trench pattern 103b according to an embodiment can have a width wider than a top surface of the first trench pattern 103a. The second trench pattern 103b can have a width greater than or equal to a lower surface of the first trench pattern 103a. Accordingly, the second trench pattern 103b can include a disconnected tip 103t protruding out of a side surface of the first trench pattern 103a. As an example, both peripheral portions of the second trench pattern 103b can protrude so as to cover or shield the side surface of the first trench pattern 103a, whereby the disconnected tip 103t can be implemented. As an example, a distance between an end of the disconnected tip 103t of the second trench pattern 103b and the side surface of the first trench pattern 103a can be greater than a thickness obtained by adding a thickness of the self-emitting device ED and a thickness of the common electrode CE. As an example, the disconnected tip 103t of the second trench pattern 103b can be formed or implemented using a second over-etching process on the planarization layer 102 using the second trench pattern 103b as a mask. As an example, the disconnected tip 103t of the second trench pattern 103b can be referred to as a second protruding portion. As an example, the second trench pattern 103b can be referred to as a gutter structure or a tip structure material.

[0373] According to an embodiment of the disclosure, a side surface of the first trench pattern 103a can have an undercut structure with respect to the second trench pattern 103b. For example, each of the first trench structure 103-1 and the second trench structure 103-2 can include a boundary portion between the first trench pattern 103a and the second trench pattern 103b or an undercut region disposed at an upper side surface of the first trench pattern 103a. The undercut region between the first trench pattern 103a and the second trench pattern 103b can be a structure material for isolating (or disconnecting) at least a portion of the light emitting device layer EDL. For example, the undercut region between the first trench pattern 103a and the second trench pattern 103b can be formed or implemented by performing an over-etching process on the planarization layer 102. The second trench pattern 103b can protrude out of a side surface of the first trench pattern 103a based on the undercut structure of the first trench pattern 103a, whereby the side surface of the first trench pattern 103a can be covered. Accordingly, the second trench pattern 103b can have a gutter structure with respect to the first trench pattern 103a.

[0374] The third trench pattern 103c can be stacked on the second trench pattern 103b. The third trench pattern 103c can have a width less than or equal to a top surface of the second trench pattern 103b. A side surface of the third trench pattern 103c can be implemented as a tilted structure or a positive taper structure. For example, the first trench pattern 103a taken along a width direction can have a same trapezoidal cross-sectional structure as the second trench pattern 103b.

[0375] According to one embodiment, the third trench pattern 103c may be stacked on the second trench pattern 103b and may include the same material as the bank BK. The third trench pattern 103c may be formed or implemented as a vertical element consisting of a portion of the bank BK (or a non-patterned region) that is not patterned (or removed) by the patterning process performed on the bank BK. The third trench pattern 103c may prevent the second trench pattern 103b from being etched.

[0376] According to one embodiment, during the deposition process, the material layer of the self-luminous device ED disposed on the inner isolation portion 103 can be automatically isolated based on the undercut region (or eaves structure) between the first and second groove patterns 103a, 103b. For example, because the deposited material of the self-luminous device ED is linear, the material layer of the self-luminous device ED is not deposited on the side surfaces of the first groove pattern 103a covered by the second groove pattern 103b. Instead, the material layer of the self-luminous device ED is deposited on the top and side surfaces of the third groove pattern 103c, the side surfaces of the second groove pattern 103b, and the passivation layer 101d near or around the first groove pattern 103a. As a result, the self-luminous device ED can be isolated (or disconnected) in the undercut region between the first and second groove patterns 103a, 103b. Accordingly, during the deposition process, the self-luminous device ED can be automatically isolated (or disconnected) in each of the first and second groove patterns 103a, 103b.

[0377] Thus, the trench pattern 103-1 forms a first isolation structure surrounding the electrode connection pattern. The first isolation structure is located between pixels in two adjacent columns and between pixels in two adjacent rows. The first isolation structure 103-1 includes a first trench pattern 103a and a second trench pattern 103b located on the first trench pattern 103a. A third trench pattern 103c is located on the second trench pattern 103b. Each of the first trench pattern 103a, the second trench pattern 103b, and the third trench pattern 103c comprises the first isolation structure 103-1. The first trench pattern 103a has a first width at the top, and the second trench pattern 103b has a second width at the bottom, which is greater than the first width.

[0378] According to one embodiment, during the execution of the deposition process, the electrode material of the common electrode CE disposed on the inner isolation portion 103 can be automatically isolated (or disconnected) based on the undercut region (or eave structure) between the first trench pattern 103a and the second trench pattern 103b. For example, the electrode material of the common electrode CE can not be deposited on the side surface of the first trench pattern 103a covered by the second trench pattern 103b, and can be deposited on the top surface and the side surface of the third trench pattern 103c, the side surface of the second trench pattern 103b, and the passivation layer 101d near the first trench pattern 103a, thereby can be isolated (or disconnected) in the undercut region between the first trench pattern 103a and the second trench pattern 103b. Accordingly, during the execution of the deposition process, the common electrode CE disposed on the inner isolation portion 103 can be automatically isolated (or disconnected) in each of the first trench structure 103-1 and the second trench structure 103-2.

[0379] The common electrode CE isolated by the inner isolation portion 103 can directly contact the uppermost surface (or surface) of the passivation layer 101d so as to surround the end portion of the self-emissive device ED isolated by the inner isolation portion 103. For example, the common electrode CE isolated by the inner isolation portion 103 can seal the boundary portion between the passivation layer 101d and the end portion of the self-emissive device ED isolated by the inner isolation portion 103, thereby can prevent water from penetrating through the boundary portion between the passivation layer 101d and the end portion of the self-emissive device ED.

[0380] According to another embodiment, the electrode material of the common electrode CE disposed above the inner isolation portion 103 can be formed to be continuous without being isolated or disconnected at the undercut region of the inner isolation portion 103, thereby can be formed to completely surround the self-emissive device ED. For example, the common electrode CE can be inserted into the undercut region between the first trench pattern 103a and the second trench pattern 103b, and can cover the side surface of the first trench pattern 103a, the uppermost surface (or surface) of the passivation layer 101d exposed under the disconnected tip 103t of the second trench pattern 103b, and the self-emissive device ED isolated by the inner isolation portion 103. Accordingly, the common electrode CE can completely surround the self-emissive device ED isolated by the inner isolation portion 103.

[0381] Each of the plurality of internal isolation portions 103 may be surrounded and planarized by an encapsulation layer 106. For example, a first encapsulation layer 106a of the encapsulation layer 106 may be disposed on the common electrode CE so as to surround or cover the common electrode CE. A second encapsulation layer 106b of the encapsulation layer 106 may be disposed on the first encapsulation layer 106a and may provide a flat surface on the first encapsulation layer 106a. Accordingly, the plurality of internal isolation portions 103 and their peripheral areas may be planarized by the second encapsulation layer 106b. The second encapsulation layer 106b may be covered by a third encapsulation layer 106c of the encapsulation layer 106.

[0382] Each of the plurality of inner isolation portions 103 according to one embodiment may further include a labyrinth region 103m disposed between the first to nth trench structures 103-1 to 103-2. For example, each of the plurality of inner isolation portions 103 may further include a labyrinth region 103m disposed between the first and second trench structures 103-1 and 103-2.

[0383] The labyrinth area 103m may be the area between the common electrode CE disposed in the outer area of ​​the inner isolation portion 103 and the line contact area CEc of the common electrode CE disposed in the inner area of ​​the inner isolation portion 103. The labyrinth area includes one or more structures having elements with several turns or corners between the outermost area and the innermost area. Therefore, water or other impurities must flow from the outside of the labyrinth to the center in order to reach the central area. The labyrinth area 103m includes one or more labyrinth walls or structures having both horizontal and vertical structures as well as horizontal and vertical turns and corners. Due to the horizontal and vertical structures, turns, and corners, it is more difficult for water or other impurities to reach the innermost area of ​​the labyrinth area.

[0384] According to one embodiment, the labyrinth region 103m may have an arc shape between the first trench structure 103-1 and the second trench structure 103-2. For example, the labyrinth region 103m may prevent the line contact region CEc of the common electrode CE, which overlaps the common electrode connection portion CECP and the auxiliary line connection portion SLCP, from being isolated into an island shape by each of the first trench structure 103-1 and the second trench structure 103-2 having an arc shape. Accordingly, the labyrinth region 103m may be referred to as a common electrode region, a common electrode bridge region, or a common electrode bridge line.

[0385] According to one embodiment, the labyrinth region 103m may be a local region of the common electrode CE that is not removed between the first trench structure 103-1 and the second trench structure 103-2. Thus, the line contact region CEc of the common electrode CE overlapping each of the common electrode connection portion CECP and the auxiliary line connection portion SLCP is not isolated from the common electrode CE disposed in the outer region of the inner isolation portion 103 in an island shape. Therefore, the line contact region CEc of the common electrode CE overlapping each of the common electrode connection portion CECP and the auxiliary line connection portion SLCP can remain continuous through the labyrinth region 103m without being disconnected from the common electrode CE disposed in the outer region of the inner isolation portion 103. Accordingly, the pixel common voltage supplied to the pixel common voltage line CVL can be supplied to the common electrode CE disposed in the outer region of the inner isolation portion 103 through the first electrode connection pattern ECP1, the second electrode connection pattern ECP2, the line contact region CEc of the common electrode CE, and the labyrinth region 103m.

[0386] According to one embodiment, each of the plurality of internal isolation portions 103 can prevent or delay (or prolong) the internal penetration of water (or moisture) through the common electrode connection portion CECP and / or the auxiliary line connection portion SLCP, thereby preventing or minimizing the reliability degradation of the self-luminous device ED caused by the internal penetration of water (or moisture). For example, water that penetrates into the light-emitting device layer EDL above each of the common electrode connection portion CECP and / or the auxiliary line connection portion SLCP may travel (or penetrate) toward the light-emitting area EA through the shortest water penetration path MPP1. In this case, since the self-luminous device ED disposed in the shortest water penetration path MPP1 is isolated by each of the first trench structure 103-1 and the second trench structure 103-2, the water that travels toward the light-emitting area EA through the shortest water penetration path MPP1 is blocked by each of the first trench structure 103-1 and the second trench structure 103-2. Water that penetrates into the light-emitting device layer EDL above each of the common electrode connection parts CECP and / or the auxiliary line connection parts SLCP will bypass the shortest water permeability path MPP1 and move (or penetrate) toward the light-emitting area EA through the water permeation delay path MPP2 including the maze area 103m. Therefore, the water permeation time and the water permeation path reaching the light-emitting area EA can be delayed or extended by the length of the water permeation delay path MPP2.

[0387] Accordingly, each of the plurality of internal isolation portions 103 can maximize the water penetration time and water penetration path of the light emitting device layer EDL penetrating over each of the common electrode connection portion CECP and / or the auxiliary line connection portion SLCP, whereby a reliability reduction of the self-luminous device caused by water can be minimized, and a lifespan of the self-luminous device can be prolonged.

[0388] As described above, in the light emitting display apparatus according to one embodiment of the present disclosure, water penetration occurring at the common electrode connection portion CECP can be blocked or delayed by the internal isolation portion 103 disposed in the vicinity or around the common electrode connection portion CECP electrically connected with the common electrode CE and the pixel common voltage line CVL in the display area AA. Also, in the light emitting display apparatus according to one embodiment of the present disclosure, the dam 104 and the external isolation portion 105 can be disposed in the peripheral portion of the first substrate 100 (or the outermost pixel), whereby a reliability reduction of the self-luminous device ED caused by lateral penetration of water can be prevented, and an air bezel structure having no bezel area or having a zero bezel can be implemented.

[0389] Figure 14 FIG. 1 is a diagram illustrating a multi-screen display apparatus according to one embodiment of the present disclosure, Figure 15 is a cross-sectional view taken along Figure 14 the line IV-IV' shown in FIG. 1. Figure 14 and 15 illustrates a multi-screen display apparatus implemented by splicing Figures 1-13 light emitting display apparatuses according to another embodiment of the present disclosure.

[0390] Referring to Figure 14 and 15 , the multi-screen display apparatus (or the spliced light emitting display apparatus) according to one embodiment of the present disclosure can include a plurality of display devices DM1 to DM4.

[0391] The plurality of display devices DM1 to DM4 can each display a separate image or can display one divided image. Each of the plurality of display devices DM1 to DM4 can include a light emitting display apparatus according to one embodiment of the present disclosure shown in Figures 1 to 13 thereby omitting or briefly giving a repetitive description thereof.

[0392] Multiple display devices DM1 to DM4 can be spliced ​​on a single splicing frame so that their side surfaces contact each other. For example, multiple display devices DM1 to DM4 can be laid out in an N×M format, thereby realizing a multi-screen display device with a large screen. As an example, N is a positive integer of 1 or greater, and M is a positive integer of 2 or greater, but the embodiments of the present disclosure are not limited thereto. For example, N is a positive integer of 2 or greater, and M is a positive integer of 1 or greater.

[0393] Each of the plurality of display devices DM1 to DM4 does not include a frame area (or non-display area) surrounding the entire display area AA where an image is displayed, but may have an air frame structure where the display area AA is surrounded by air. For example, in each of the plurality of display devices DM1 to DM4, the entire first surface of the first substrate 100 may be implemented as the display area AA.

[0394] According to this embodiment, in each of the plurality of display devices DM1 to DM4, the second interval D2 between the center portion CP of the outermost pixel Po and the outermost outer surface of the first substrate 100 can be implemented to be half or less of the first interval D1 (or pixel pitch) between adjacent pixels. Accordingly, in two adjacent display devices DM1 to DM4 that are bonded (or in contact) with each other at the side surfaces along the first direction X and the second direction Y based on the lateral bonding method, the interval "D2+D2" between adjacent outermost pixel areas PAo can be equal to or less than the first interval D1 between the two adjacent pixels. Figure 15 , in the first and third display devices DM1 and DM3 that are joined (or in contact) with each other at the side surfaces along the second direction Y, the interval "D2+D2" between the central portion CP of the outermost pixel Po of the first display device DM1 and the central portion CP of the outermost pixel Po of the third display device DM3 may be equal to or less than the first interval D1 (or pixel pitch) between two adjacent pixels set in each of the first display device DM1 and the third display device DM3.

[0395] Therefore, the interval "D2+D2" between the center portions CP of the outermost pixels Po of two adjacent display devices DM1 to DM4 that are joined (or in contact) with each other at the side surfaces along the first direction X and the second direction Y can be equal to or less than the first interval D1 set between two adjacent pixels in each of the display devices DM1 to DM4. As a result, no seam or boundary portion exists between the two adjacent display devices DM1 to DM4, and no dark area caused by the boundary portion provided between the display devices DM1 to DM4 exists. As a result, the images displayed on the multi-screen display device in which the multiple display devices DM1, DM2, DM3, and DM4 are tiled in an N×M format can be displayed continuously without a sense of interruption (or discontinuity) at the boundary portions between the multiple display devices DM1, DM2, DM3, and DM4.

[0396] exist Figure 14 and 15 , multiple display devices DM1 to DM4 are spliced ​​into a 2×2 form, but the embodiments of the present disclosure are not limited thereto, and multiple display devices DM1 to DM4 may be spliced ​​into an x×1 form, a 1×y form, or an x×y form. As an example, in the x×1 form, x may be a natural number greater than or equal to 2, in the 1×y form, y may be a natural number greater than or equal to 2, and in the x×y form, x and y may be natural numbers greater than or equal to 2 and may be equal to or different from each other. For example, in the x×y form, x may be a natural number greater than or equal to 2 and may be equal to y, or x and y may be natural numbers greater than or equal to 2, and y may be greater than or equal to x.

[0397] As described above, when the display area AA of the multiple display devices DM1 to DM4 is one screen and displays one image, the multi-screen display device according to one embodiment of the present disclosure can display an image that is uninterrupted and continuous at the boundary portion between the multiple display devices DM1 to DM4, thereby enhancing the sense of immersion of the viewer who watches the image displayed by the multi-screen display device.

[0398] Hereinafter, a light-emitting display device according to an embodiment of the present disclosure and a multi-screen display device including the light-emitting display device will be described.

[0399] According to one embodiment of the present disclosure, a light-emitting display device may include: a display portion on a first substrate, comprising a plurality of pixels arranged along a first direction and a second direction different from the first direction; a circuit layer, comprising a pixel common voltage line parallel to the second direction and arranged between the plurality of pixels along the first direction; a light-emitting device layer, comprising a self-luminous device arranged on the circuit layer of the display portion and a common electrode arranged on the self-luminous device; a common electrode connecting portion, electrically coupling the pixel common voltage line to the common electrode; and an internal isolation portion, surrounding the common electrode connecting portion and isolating the self-luminous device near the common electrode connecting portion.

[0400] According to some embodiments of the present disclosure, the internal isolation portion may include first to n-th trench structures (where n is a natural number of 2 or greater) surrounding the common electrode connection portion.

[0401] According to some embodiments of the present disclosure, the internal isolation portion may include first to nth groove structures (where n is a natural number of 2 or greater) surrounding the common electrode connection portion, and each of the first to nth groove structures may include an arc shape arranged in a concentric circle shape and including an opening portion on one side.

[0402] According to some embodiments of the present disclosure, the inner isolation portion may further include a labyrinth region formed between the first to nth trench structures.

[0403] According to some embodiments of the present disclosure, the common electrode disposed in the inner region of the inner isolation portion may be electrically connected to the common electrode disposed in the outer region of the inner isolation portion via the common electrode disposed in the labyrinth region.

[0404] According to some embodiments of the present disclosure, an opening portion of a kth trench structure (where k is 1 to n-1) among the first to nth trench structures may be surrounded by a k+1th trench structure.

[0405] According to some embodiments of the present invention, an opening portion of the kth trench structure (where k is 1 to n-1) and an opening portion of the k+1th trench structure among the first to nth trench structures may face different directions.

[0406] According to some embodiments of the disclosure, each of the first to nth trench structures can include a first trench pattern disposed above the circuit layer, a second trench pattern disposed above the first trench pattern to have a eave structure with respect to the first trench pattern, and a third trench pattern disposed above the second trench pattern, the self-emissive device disposed above the inner isolation portion can be isolated by the eave structure of the second trench pattern. Accordingly, the eave serves as a vertical and horizontal labyrinth structure. The turn around the eave is vertically upward and outward in a horizontal direction.

[0407] According to some embodiments of the disclosure, the light emitting display apparatus can further include a planarization layer disposed between the circuit layer and the light emitting device layer, the light emitting device layer can further include a pixel electrode disposed on the planarization layer of each of the plurality of pixels, the first trench pattern can include a same material as a material of the planarization layer, and the second trench pattern can include a same material as a material of the pixel electrode.

[0408] According to some embodiments of the disclosure, the light emitting display apparatus can further include a bank disposed above the planarization layer and a peripheral portion of the pixel electrode of each of the plurality of pixels, and the third trench pattern can include a same material as a material of the bank.

[0409] According to some embodiments of the disclosure, the circuit layer can further include an interlayer insulating layer and a passivation layer disposed above the pixel common voltage line, the common electrode connection portion can include a first electrode connection pattern disposed between the interlayer insulating layer and the passivation layer and electrically connected to the pixel common voltage line, a second electrode connection pattern disposed on the passivation layer and electrically connected to the first electrode connection pattern, and a connection trench including an undercut region formed by removing the passivation layer between an end portion of the second electrode connection pattern and the first electrode connection pattern, and the common electrode can be electrically connected to a side surface and a bottom surface of the end portion of the second electrode connection pattern.

[0410] According to some embodiments of the disclosure, an end portion of the second electrode connection pattern can have a eave structure with respect to the connection trench, and the common electrode can be electrically connected to the first electrode connection pattern under the undercut region or the eave structure.

[0411] According to some embodiments of the present disclosure, the light-emitting display device may further include a planarization layer arranged between the circuit layer and the light-emitting device layer, the light-emitting device layer may further include a pixel electrode arranged on the planarization layer of each pixel in the plurality of pixels, the common voltage connection portion may further include a groove formed by removing a portion of the planarization layer to expose the passivation layer, and the second electrode connection pattern may be arranged on the planarization layer and include the same material as that of the pixel electrode.

[0412] According to some embodiments of the present disclosure, the light-emitting display device may further include an auxiliary voltage line arranged in the circuit layer and parallel to the pixel common voltage line, a line connection pattern electrically connecting the pixel common voltage line and the auxiliary voltage line, and an auxiliary line connection portion electrically connecting the auxiliary voltage line to the common electrode, and the internal isolation portion may additionally surround the auxiliary line connection portion and may additionally isolate the self-luminous device near or around the auxiliary line connection portion.

[0413] According to some embodiments of the present disclosure, the internal isolation portion may include first to nth groove structures (where n is a natural number of 2 or greater) surrounding the common electrode connection portion and the auxiliary line connection portion, and a maze area located between the first to nth groove structures.

[0414] According to some embodiments of the present disclosure, each of the first to nth trench structures may include an arc shape arranged in a concentric circle shape and including an opening portion on one side.

[0415] According to some embodiments of the present disclosure, each of the first to nth groove structures may include a first groove pattern arranged above the circuit layer, a second groove pattern arranged above the first groove pattern to have an eaves structure relative to the first groove pattern, and a third groove pattern arranged above the second groove pattern, and the self-luminous device arranged above the internal isolation portion can be isolated by the eaves structure of the second groove pattern.

[0416] According to some embodiments of the present disclosure, the light-emitting display device may further include a dam arranged on the outer portion of the first substrate; an external isolation portion arranged near or around the dam, the external isolation portion isolating the self-luminous device arranged on the external isolation portion; and an encapsulation layer arranged above the light-emitting device layer, the encapsulation layer including an organic encapsulation layer arranged on the encapsulation area surrounded by the dam.

[0417] According to some embodiments of the present invention, the external isolation portion may include a plurality of isolation structures, each of the plurality of isolation structures may include a lower structure arranged in the circuit layer, an eaves structure arranged on the lower structure, and an upper structure arranged on the eaves structure, wherein the self-luminous device arranged on the external isolation portion is isolated by the eaves structure.

[0418] According to some embodiments of the present disclosure, the light-emitting display device may further include: a first pad portion configured to include a plurality of first pads arranged on a peripheral portion of the first substrate; a second substrate configured to include a second pad portion, the second pad portion including a plurality of second pads overlapping with each of the plurality of first pads; a coupling member arranged between the first substrate and the second substrate; and a wiring portion arranged on a side surface of each of the first substrate and the second substrate, the wiring portion including a plurality of wirings connecting the plurality of first pads to the plurality of second pads in a one-to-one relationship.

[0419] According to some embodiments of the present disclosure, a multi-screen display device may include a plurality of display devices arranged along at least one of a first direction and a second direction different from the first direction, each of the plurality of display devices may include a light-emitting display device, and the light-emitting display device may include: a plurality of pixels arranged along the first direction and the second direction above a first substrate; a circuit layer, including a pixel common voltage line parallel to the second direction and arranged between the plurality of pixels along the first direction; a light-emitting device layer, including a self-luminous device arranged on the circuit layer and a common electrode arranged on the self-luminous device; a common electrode connecting portion, electrically coupling the pixel common voltage line to the common electrode; and an internal isolation portion, surrounding the common electrode connecting portion and isolating the self-luminous device arranged on the common electrode connecting portion.

[0420] According to some embodiments of the present disclosure, in a first display device and a second display device adjacent along the first direction and / or the second direction, the distance between the center part of the outermost pixel of the first display device and the center part of the outermost pixel of the second display device may be less than or equal to the pixel pitch, which may be the distance between the center parts of pixels adjacent along the first direction and the second direction.

[0421] According to some embodiments of the present disclosure, a display device may include: a substrate on which a plurality of pixels are formed, the pixels being arranged in adjacent rows and adjacent columns; a plurality of pixel driving voltage lines located between pixels of two adjacent columns; a plurality of electrode connection patterns coupled to the respective pixel driving voltage lines between pixels of two adjacent columns and pixels of two adjacent rows; and a first isolation structure surrounding the electrode connection pattern, the first isolation element being located between pixels of two adjacent columns and pixels of two adjacent rows, the first isolation structure may include a first vertical element and a second vertical element located on the first vertical element.

[0422] According to some embodiments of the present disclosure, a top area of ​​the first vertical element may have a first width, and a bottom area of ​​the second vertical element may have a second width greater than the first width.

[0423] According to some embodiments of the present disclosure, the display device may further include an eaves structure located between the first vertical element and the second vertical element.

[0424] According to some embodiments of the present disclosure, the display device may further include a second isolation structure surrounding the first isolation structure, the second isolation structure being a circular element having an opening adjacent to a wall portion of the first isolation structure.

[0425] According to some embodiments of the present disclosure, the opening of the first isolation structure may be opposite to the opening of the second isolation structure.

[0426] According to some embodiments of the present disclosure, a multi-screen display device may include a first display device and a second display device adjacent to each other, each of the first display device and the second display device includes a display device, and the display device may include: a substrate, on which a plurality of pixels are formed, and the pixels are arranged in adjacent rows and adjacent columns; a plurality of pixel driving power lines, located between the pixels of two adjacent columns; a plurality of electrode connection patterns, coupled to each pixel driving power line between the pixels of two adjacent columns and the pixels of two adjacent rows; and a first isolation structure, surrounding the electrode connection pattern, the first isolation element is located between the pixels of two adjacent columns and the pixels of two adjacent rows, and the first isolation structure may include a first vertical element and a second vertical element located on the first vertical element.

[0427] According to some embodiments of the present disclosure, the distance between the center parts of the outermost pixels of the first display device and the center parts of the outermost pixels of the second display device is less than or equal to the pixel pitch, which is the distance between the center parts of two adjacent pixels in the first display device or the second display device.

[0428] The light-emitting display device according to one embodiment of the present disclosure can be applied to all electronic devices including a display panel. For example, the display device according to one embodiment of the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic organizers, electronic books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers (PCs), laptop PCs, notebook computers, workstations, navigation devices, car navigation devices, car display devices, car devices, theater devices, theater display devices, TVs, wallpaper display devices, signage devices, game consoles, notebook computers, monitors, cameras, camcorders, home appliances, etc.

[0429] Without departing from the spirit or scope of the present invention, various modifications and changes can be made in the present invention, which will be apparent to those skilled in the art. Therefore, the present invention is intended to cover modifications and changes to the present invention that fall within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display device, comprising: a plurality of pixels arranged over a first substrate along a first direction and a second direction different from the first direction; a circuit layer, the circuit layer including a pixel common voltage line parallel to the second direction and arranged between the plurality of pixels along the first direction; a light-emitting device layer, the light-emitting device layer comprising a self-luminous device disposed on the circuit layer and a common electrode disposed on the self-luminous device; a common electrode connecting portion, the common electrode connecting portion electrically coupling the pixel common voltage line to the common electrode; as well as an internal isolation portion surrounding the common electrode connection portion and isolating the self-luminous device provided on the internal isolation portion, wherein the inner isolation portion includes a first trench structure to an nth trench structure surrounding the common electrode connection portion, wherein n is a natural number of 2 or greater, wherein one side of the first trench structure to each of the n-th trench structures includes an opening portion, The opening portion of the kth trench structure from the first trench structure to the nth trench structure and the opening portion of the k+1th trench structure face different directions, where k is 1 to n-1. 2 . The light emitting display device of claim 1 , wherein the inner isolation portion further comprises a labyrinth region formed between the first trench structure to the nth trench structure. 3 . The light emitting display device of claim 2 , wherein the common electrode disposed in the inner region of the inner isolation portion is electrically connected to the common electrode disposed in the outer region of the inner isolation portion via the common electrode disposed in the labyrinth region. 4 . The light emitting display device of claim 1 , wherein the opening portion of the kth trench structure among the first to nth trench structures is surrounded by a k+1th trench structure, where k is 1 to n−1.

5. The light-emitting display device according to claim 1, wherein each of the first trench structure to the nth trench structure comprises: a first groove pattern provided on the circuit layer; a second groove pattern provided on the first groove pattern to have an eaves structure relative to the first groove pattern; as well as a third groove pattern disposed on the second groove pattern, The self-luminous device disposed on the inner isolation portion is isolated by the eaves structure of the second groove pattern.

6. The light emitting display device according to claim 5, further comprising a planarization layer provided between the circuit layer and the light emitting device layer, wherein the light emitting device layer further comprises a pixel electrode disposed on the planarization layer, wherein the first groove pattern comprises the same material as that of the planarization layer, The second groove pattern comprises the same material as that of the pixel electrode.

7. The light emitting display device according to claim 6, further comprising a bank provided on the planarization layer and at a peripheral portion of the pixel electrode, The third trench pattern comprises the same material as that of the bank.

8. The light-emitting display device according to claim 1, The circuit layer further includes an interlayer insulating layer disposed on the pixel common voltage line and a passivation layer disposed on the interlayer insulating layer. The common electrode connecting portion includes: a first electrode connection pattern disposed between the interlayer insulating layer and the passivation layer and electrically connected to the pixel common voltage line; a second electrode connection pattern disposed on the passivation layer and electrically connected to the first electrode connection pattern; as well as a connection trench including an undercut region formed by removing the passivation layer between an end portion of the second electrode connection pattern and the first electrode connection pattern; wherein the common electrode is electrically connected to side surfaces and a bottom surface of an end portion of the second electrode connection pattern.

9. The light-emitting display device according to claim 8, wherein the end portion of the second electrode connection pattern has an eaves structure relative to the connection groove, The common electrode is electrically connected to the first electrode connection pattern below the eaves structure.

10. The light emitting display device according to claim 8, further comprising a planarization layer provided between the circuit layer and the light emitting device layer, wherein the light emitting device layer further comprises a pixel electrode disposed on the planarization layer, wherein the common electrode connection portion further comprises a groove formed by removing a portion of the planarization layer to expose the passivation layer, The second electrode connection pattern is disposed on the exposed passivation layer and the planarization layer and comprises the same material as that of the pixel electrode.

11. The light-emitting display device according to claim 1 , further comprising: An auxiliary voltage line provided in the circuit layer and parallel to the pixel common voltage line, a line connection pattern electrically connecting the pixel common voltage line and the auxiliary voltage line; as well as electrically connecting the auxiliary voltage line to the auxiliary line connection portion of the common electrode, The inner isolation portion additionally surrounds the auxiliary line connection portion.

12. The light-emitting display device according to claim 1, further comprising: a dam disposed on a peripheral portion of the first substrate; as well as An encapsulation layer is disposed on the light-emitting device layer, wherein the encapsulation layer includes an organic encapsulation layer disposed on an encapsulation region surrounded by the dam.

13. The light-emitting display device according to claim 12, further comprising: an outer isolation portion provided on the outer peripheral portion of the first substrate, the outer isolation portion isolating the self-luminous device provided on the outer isolation portion, The outer isolation portion includes a plurality of isolation structures, and the dam is disposed between the plurality of isolation structures.

14. The light emitting display device according to claim 13, wherein each of the plurality of isolation structures comprises: a lower structure disposed in the circuit layer; an eaves structure provided on the lower structure; as well as a superstructure provided on the eaves structure, The self-luminous device disposed on the external isolation portion is isolated by the eaves structure. 15 . The light emitting display device of claim 14 , wherein the eaves structure comprises a metal layer electrically connected to the pixel common voltage line.

16. The light emitting display device according to claim 1, further comprising: a first pad portion including a plurality of first pads provided at a peripheral portion of the first substrate; a second substrate including a second pad portion including a plurality of second pads overlapping the plurality of first pads; a coupling member disposed between the first substrate and the second substrate; as well as A wiring portion is provided on one side surface of each of the first substrate and the second substrate, the wiring portion including a plurality of wirings connecting the plurality of first pads to the plurality of second pads.

17. A multi-screen display device, comprising: a first display device and a second display device adjacent to each other, Each of the first display device and the second display device comprises the light-emitting display apparatus according to any one of claims 1 to 16.

18. The multi-screen display device of claim 17, wherein a distance between a center portion of an outermost pixel of the first display device and a center portion of an outermost pixel of the second display device is less than or equal to a pixel pitch, The pixel pitch is a distance between center portions of two adjacent pixels in the first display device or the second display device.

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