A detection circuit for driving a parallel resistance

Abstract

This invention discloses a detection circuit for driving a parallel resistor, comprising: an operational amplifier, an external parallel resistor R, MOSFETs M1, M2, M3, M4, M5, M6, M7, M8, and M9, resistors Rz1, Rz2, Rz3, and Rz4, and a logic circuit group. This invention uses the operational amplifier to form a clamping circuit, applying a fixed voltage to the external parallel resistor R of the drive pin, thereby generating current information inversely proportional to the external parallel resistor R. Current comparison is then performed, with the reference current also derived from the operational amplifier's clamping loop. The reference current is determined by the clamping circuit and internal resistors. The identifiable driving range of the external parallel resistor R can be set via internal resistors Ra, Rb, and Rc. Due to the series connection of resistor Rz1, a zero point that follows the change of the DRV terminal pole can be generated, thereby compensating for the influence of this pole on the loop.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a detection circuit for driving a parallel resistor. Background Technology

[0002] Chips typically have externally programmable parameters, allowing circuit parameters to be set based on the external parallel resistance of the driver pin. The external parallel resistance of the driver is only detected during the startup phase, and the detection is performed when the driver is not yet at a high level.

[0003] Method 1: The traditional method involves applying a current to an external resistor through an internal circuit to detect its resistance. For example... Figure 1 As shown. The external parallel resistor of the DRV pin is resistor R. The internal circuit outputs a current of I amperes. The voltage at the DRV terminal, VDRV = I*R volts. The comparator compares the DRV terminal voltage with a series of reference voltages to determine the resistance range of the external parallel resistor R. Initially, switch s1 controls the comparison of VDRV and Vref1. When the value of the parallel resistor R exceeds the first resistance range, the logic module controls the switch to switch, s1 opens, s2 closes, and VDRV is compared with Vref2. When the value of the parallel resistor R exceeds the second resistance range, the logic module continues to control the switch to switch, and VDRV is compared with Vref3. The three range boundaries divide the resistance detection range into four categories, and finally outputs a 2-bit detection result Out<1:0>, which is then sent to other circuits.

[0004] Figure 1 The method described above has a simple circuit structure and is easy to implement. However, a drawback is that when the external parallel resistor is large, the DRV terminal voltage will be too high, which could lead to the power transistor turning on. If the power transistor turns on, the detection will fail. In applications, accidental power transistor activation can have serious consequences.

[0005] Method 2: Figure 2This is another circuit structure for detecting the driving parallel resistor. Resistor R is the external parallel resistor for driving. Operational amplifiers AMP and M1 make the voltage at the DRV pin equal to the reference voltage Vref. M2, M3, M4, and M5 form a current mirror, mirroring the current IR across resistor R, where IR = Vref / R. IB1 is the current source bias. M6, M7 and M8, M9 and M10, M11 and M12, and M13 form a current mirror with a mirror ratio of a:b:c:1. This ratio is closely related to the range of the driving external parallel resistor; assuming a>b>c>1. Branches M3, M6, and M7 perform current comparisons. When the current IR is greater than a*IB1, the voltage at point A is pulled high, and the logic circuit latches this state. Similarly, when the current IR is greater than b*IB1, the voltage at point B is pulled high; when the current IR is greater than c*IB1, the voltage at point C is pulled high. By comparing the currents in multiple branches, the current IR of resistor R can be locked within a certain range. This determines the range of resistor R.

[0006] This method is a relatively common detection method, with a simple circuit and easy implementation. However, it is necessary to consider the mismatch of the current mirror, the offset voltage of the operational amplifier, and the application scenario. Currently, MOS power transistors and energy-saving GaN power transistors are used as power transistors. The DRV driver is used to drive the power transistor, which introduces parasitic capacitances of varying magnitudes into the DRV pins, ranging from picofarads (pF) to nanofarads (nF), placing higher demands on the stability of the loop constructed by the operational amplifier. (Figure) Summary of the Invention

[0007] To address the aforementioned problems, this invention provides a detection circuit for driving a parallel resistor.

[0008] To achieve the above objectives, the present invention provides the following solution:

[0009] A detection circuit for driving a parallel resistor includes: an operational amplifier, an external parallel resistor R, MOSFETs M1, M2, M3, M4, M5, M6, M7, M8, and M9, resistors Rz1, Rz2, Rz3, and Rz4, and a logic circuit group.

[0010] The inverting input terminal of the operational amplifier is connected to the drain of the MOS transistor M9, and the output terminal of the operational amplifier is connected to the gates of the MOS transistors M1, M6, M7, and M8, respectively; the source of the MOS transistor M9 is grounded.

[0011] The source of MOSFET M1 is connected to ground via series with resistor Rz1 and external parallel resistor R; the drain of MOSFET M1 is connected to the drain and gate of MOSFET M2; the source of MOSFET M6 is connected to ground via series with resistor Rz2 and resistor Ra; the source of MOSFET M7 is connected to ground via series with resistor Rz3 and resistor Rb; the source of MOSFET M8 is connected to ground via series with resistor Rz4 and resistor Rc; the drain of MOSFET M6 is connected to the drain of MOSFET M3; the drain of MOSFET M7 is connected to the drain of MOSFET M4; and the drain of MOSFET M8 is connected to the drain of MOSFET M5.

[0012] The drains of MOS transistors M6, M7, and M8 are all connected to the logic circuit group.

[0013] The gate of MOS transistor M2 is also connected to the gates of MOS transistor M3, MOS transistor M4, and MOS transistor M5, respectively; the sources of MOS transistor M2, MOS transistor M3, MOS transistor M4, and MOS transistor M5 are all connected to a power supply.

[0014] A first switch K1 is provided between the resistor Rz1 and the external parallel resistor R; the external parallel resistor R is connected in parallel with the power transistor parasitic capacitance Cg.

[0015] Optionally, the drain of the MOS transistor M6 is also connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded; the capacitor C1 is connected in parallel with a second switch K2.

[0016] Optionally, the drain of the MOSFET M7 is also connected to one end of the capacitor C2, and the other end of the capacitor C2 is grounded; a third switch K3 is connected in parallel with the capacitor C1.

[0017] Optionally, the drain of the MOS transistor M8 is also connected to one end of the capacitor C3, and the other end of the capacitor C4 is grounded; a fourth switch K4 is connected in parallel with the capacitor C4.

[0018] Optionally, the output terminal of the operational amplifier is also connected to one end of capacitor C4, and the other end of capacitor C4 is grounded.

[0019] Optionally, the logic circuit group includes a first logic circuit, a second logic circuit, and a third logic circuit; the first logic circuit, the second logic circuit, and the third logic circuit each include an AND gate, a follower, and an RS flip-flop; the output of the AND gate is connected to the input of the follower, and the output of the follower is connected to the S terminal of the RS flip-flop; the drain of the MOS transistor M6 is connected to the first input of the AND gate in the first logic circuit; the drain of the MOS transistor M7 is connected to the first input of the AND gate in the second logic circuit; and the drain of the MOS transistor M8 is connected to the first input of the AND gate in the third logic circuit.

[0020] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0021] This invention uses an operational amplifier to construct a clamping circuit, applying a fixed voltage to the external parallel resistor R of the drive pin, thereby generating current information inversely proportional to the external parallel resistor R. Current comparison is then performed, with the reference current also derived from the op-amp's clamping loop. The reference current is determined by the clamping circuit and internal resistors, and the identifiable drive external parallel resistor R level can be set via internal resistors Ra, Rb, and Rc. Due to the series connection of resistor Rz1, a zero point that follows the DRV terminal pole change is generated, thus compensating for the pole's influence on the loop. Compared to traditional methods, this invention provides a more stable loop, and this detection method can be used in power transistor applications with a wide range of parasitic capacitances. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a circuit structure for detecting and driving parallel resistors in the prior art;

[0024] Figure 2 This is another circuit structure for detecting the parallel resistor in the driving circuit in the prior art;

[0025] Figure 3 A circuit diagram of the detection circuit for driving parallel resistors provided by the present invention;

[0026] Figure 4 This is a schematic diagram of a logic circuit;

[0027] Figure 5 This is a timing diagram of each control signal. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The purpose of this invention is to optimize the loop structure based on the traditional structure, making the circuit structure more widely applicable, suitable for driving both power MOS transistors and GaN power transistors. It also appropriately reduces the error caused by current mirror adaptation, improving identification accuracy.

[0030] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] like Figure 3 As shown, the detection circuit for driving parallel resistors provided by the present invention includes: an operational amplifier AMP, an external parallel resistor R, MOSFETs M1, M2, M3, M4, M5, M6, M7, M8, and M9, resistors Rz1, Rz2, Rz3, and Rz4, and a logic circuit group.

[0032] The inverting input terminal of the operational amplifier is connected to the drain of the MOS transistor M9, and the output terminal of the operational amplifier is connected to the gates of the MOS transistors M1, M6, M7, and M8, respectively; the source of the MOS transistor M9 is grounded.

[0033] The source of MOSFET M1 is connected to ground via series with resistor Rz1 and external parallel resistor R; the drain of MOSFET M1 is connected to the drain and gate of MOSFET M2, respectively; the source of MOSFET M6 is connected to ground via series with resistor Rz2 and resistor Ra; the source of MOSFET M7 is connected to ground via series with resistor Rz3 and resistor Rb; the source of MOSFET M8 is connected to ground via series with resistor Rz4 and resistor Rc; the drain of MOSFET M6 is connected to the drain of MOSFET M3; the drain of MOSFET M7 is connected to the drain of MOSFET M4; and the drain of MOSFET M8 is connected to the drain of MOSFET M5.

[0034] The drains of MOS transistors M6, M7, and M8 are all connected to the logic circuit group.

[0035] The gate of the MOS transistor M2 is also connected to the gates of the MOS transistor M3, the MOS transistor M4, and the MOS transistor M5 respectively; the sources of the MOS transistor M2, the MOS transistor M3, the MOS transistor M4, and the MOS transistor M5 are all connected to a power supply.

[0036] A first switch K1 is provided between the resistor Rz1 and the external parallel resistor R; the external parallel resistor R is connected in parallel with the parasitic capacitance Cg of the power transistor.

[0037] Wherein, the drain of the MOS transistor M6 is also connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded; the capacitor C1 is connected in parallel with a second switch K2.

[0038] Wherein, the drain of the MOS transistor M7 is also connected to one end of the capacitor C2, and the other end of the capacitor C2 is grounded; the capacitor C1 is connected in parallel with a third switch K3.

[0039] Wherein, the drain of the MOS transistor M8 is also connected to one end of the capacitor C3, and the other end of the capacitor C4 is grounded; the capacitor C4 is connected in parallel with a fourth switch K4.

[0040] Wherein, the output end of the operational amplifier is also connected to one end of the capacitor C4, and the other end of the capacitor C4 is grounded.

[0041] Wherein, the logic circuit group includes a first logic circuit, a second logic circuit, and a third logic circuit; the first logic circuit, the second logic circuit, and the third logic circuit all include an AND gate, a follower, and an RS flip-flop; the output end of the AND gate is connected to the input end of the follower, and the output end of the follower is connected to the S end of the RS flip-flop; the drain of the MOS transistor M6 is connected to the first input end of the AND gate in the first logic circuit; the drain of the MOS transistor M7 is connected to the first input end of the AND gate in the second logic circuit; the drain of the MOS transistor M8 is connected to the first input end of the AND gate in the third logic circuit.

[0042] The working principle of the present invention is as follows:

[0043] The output end of the operational amplifier is connected in parallel with MOS transistors M6, M7, and M8 which are the same as the MOS transistor M1. The source ends of the MOS transistors M6, M7, and M8 are respectively connected to resistors Ra, Rb, and Rc. These three resistors are the resistance values of the four gear dividing lines. Assume that the resistance value Ra < Rb < Rc. Similarly, the MOS transistors M3, M4, and M5 mirror the current of the MOS transistor M2. Points A, B, and C represent the comparison results of the currents in the three branches where the MOS transistors M3, M4, and M5 are located.

[0044] When driving an external parallel resistor for detection, there are several ranges. Depending on the number of range boundaries, the current branch in the internal detection circuit's current comparison circuit will change accordingly. For example, if the detection resistor only has two range boundaries, then... Figure 3 This eliminates the need for the current comparison branch formed by M8 and Rc. If the sensing resistor has five range settings, then... Figure 3 This allows for the addition of two more current comparison branches.

[0045] Logic circuits such as Figure 4 As shown, MOSFET M1, operational amplifier, second switch K2, third switch, fourth switch, and the R terminal of the RS flip-flop are all driven by the signal DET_DRV; the first switch K1 is also driven by the signal DET_DRV. For a period of time after UVLO exits (greater than 4 milliseconds), the DRV terminal does not emit a waveform. During this period, the DET_DRV signal controls the detection circuit connected to the DRV terminal for detection. DIS_DET is used to set the initial state and terminate detection, and the SH signal controls the sampling of the current comparison results at points A, B, and C. When the external parallel resistor R is less than the resistor Ra, point A is charged with current; when the external parallel resistor R is less than the resistor Rb, point B is charged with current; and when the external parallel resistor R is less than the resistor Rc, point C is charged with current. The DET signal controls the logic circuit to monitor the voltages of A, B, and C during detection and latches the monitoring data. The output of the detection circuit is the signal Out<1:3>, which is then output to other circuits for further processing. In addition, the UVLO signal can be replaced with other signals indicating system startup but not DRV signaling. The timing duration of the timing module TIMER_4ms can be replaced with other durations, and the delay of the rising and falling edges can also be replaced with other values.

[0046] like Figure 5 The control timing shown includes the control methods represented by each control timing signal. In application, the detection function is started by setting DIS_FUN to low level. After the circuit is powered on, the UVLO signal goes low, the DIS_DET signal first initializes the circuit, and the DET_DRV control switch K1 closes, connecting the detection circuit to the DRV pin to detect the magnitude of the parallel resistor R outside the DRV.

[0047] During the undervoltage latch-up process at startup, the DIS_DET signal is high. After exiting UVLO, DET_DRV is high, and the detection circuit remains connected to the DRV terminal, establishing its operating point. After the UVLO signal goes low, the timer TIMER_4ms begins counting. After 4ms, the timing module output signal t_4ms goes high. After 30ns, the control signal SH, which samples the current comparison status of points A, B, and C, goes high for 300ns. During this 300ns period, the SH signal controls the logic circuit to monitor the voltages of A, B, and C during the detection period. When the external parallel resistor R is less than the resistor Ra, point A is charged high; when the external parallel resistor R is less than the resistor Rb, point B is charged high; and when the external parallel resistor R is less than the resistor Rc, point C is charged high. SH goes low after 300ns, and the DET_DRV signal goes low after 60ns, meaning the detection circuit is disconnected from the DRV terminal. In this way, the detection action is completed within a few milliseconds after power-on, the detection result is latched, and then output to the circuit logic for setting other circuit parameters.

[0048] This invention has changed Figure 2 In the comparison current generation method, the operational amplifier output is connected in parallel with MOSFETs M6, M7, and M8, which are identical to MOSFET M1. The source voltages S6, S7, and S8 of MOSFETs M6, M7, and M8 are regulated by the loop and the current of MOSFET M1. Since the difference in bias current of the branches containing MOSFETs M3, M4, and M5 is on the order of μA, the source currents of MOSFETs M3, M4, and M5 can be approximated as equal. Therefore, when the resistance R = Ra, the upper and lower currents of the comparison branch at point A are approximately equal. Similarly, when the resistance R = Rb, the upper and lower currents of the comparison branch at point B are approximately equal; when the resistance R = Rc, the upper and lower currents of the comparison branch at point C are approximately equal.

[0049] This invention and Figure 2 The detection methods are similar, both converting resistance values ​​into current IR, comparing the obtained current IR with a preset range threshold reference current, and then processing the data through logic circuits to set relevant circuit parameters, thereby achieving external programmable functionality. The difference lies in the method of generating the preset range threshold reference current. Figure 2 The reference current of this invention is generated by the gate voltages of MOSFETs M6, M7, and M8, which are controlled by a loop, and the bias resistors Ra, Rb, and Rc that determine the range. This operational amplifier forms a clamping loop and drives the reference current for current comparison.

[0050] In the detection circuit for driving the parallel resistor provided by this invention, the output terminal of the operational amplifier adopts a common-source, common-gate structure, and capacitor C4 is used to stabilize the loop, increasing the parasitic capacitance at the output terminal of the operational amplifier. The biggest difference between this invention and traditional detection methods is that the resistors Rz1-Rz4 are connected in series into the circuit. When DET_DRV is high, switch K1 is closed, and the detection circuit is connected to the DRV terminal. The parasitic equivalent capacitance Cg, the external parallel resistor R, and the series resistance Rz1 of the circuit form a pole wp = 1 / RCg and a zero wz = 1 / Req*Cg, where Req = R||Rz1. When taking values, Rz1-Rz4 are set to the same order of magnitude as the external parallel resistor R, so that the resulting zero and the pole at the DRV terminal are always in close positions on the frequency spectrum. Regardless of how the size of the parasitic capacitance Cg of the power transistor changes, that is, how the position of the pole at the DRV terminal changes, the zero can follow the change, compensating for the gain change and phase margin caused by the pole.

[0051] In the loop, although the poles at the DRV pin vary over a large range, Figure 3 The circuit structure shown also ensures that the output of the operational amplifier is stably at the dominant pole, rather than like... Figure 2 In the case of a power MOSFET, when the pole of the DRV pin is connected to a power MOSFET, the pole will increase to exceed the pole of the operational amplifier output and become the dominant pole.

[0052] This invention can drive both power MOSFETs and GaN power transistors. The advantages of this are:

[0053] (1) No additional current bias circuit is required, and the detection of the external parallel resistor of the drive can be realized;

[0054] (2) The reference current of the current comparison circuit does not use a mirror current source to reduce the current mirror error;

[0055] (3) The reference current of the current comparison circuit can be generated by resistor matching to reduce the error caused by resistor mismatch;

[0056] (4) Improved loop stability, enabling it to drive both power MOS and GaN power transistors;

[0057] (5) The deviation direction of the detection circuit error is consistent, which improves the reliability of the detection results.

[0058] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0059] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A detection circuit for driving a parallel resistor, characterized in that, include: Operational amplifier, external parallel resistor R, MOSFETs M1, M2, M3, M4, M5, M6, M7, M8, M9, resistors Rz1, Rz2, Rz3, Rz4, and logic circuit group. The inverting input terminal of the operational amplifier is connected to the drain of the MOS transistor M9, and the output terminal of the operational amplifier is connected to the gates of the MOS transistors M1, M6, M7, and M8, respectively; the source of the MOS transistor M9 is grounded. The source of MOSFET M1 is connected to ground via series with resistor Rz1 and external parallel resistor R; the drain of MOSFET M1 is connected to the drain and gate of MOSFET M2; the source of MOSFET M6 is connected to ground via series with resistor Rz2 and resistor Ra; the source of MOSFET M7 is connected to ground via series with resistor Rz3 and resistor Rb; the source of MOSFET M8 is connected to ground via series with resistor Rz4 and resistor Rc; the drain of MOSFET M6 is connected to the drain of MOSFET M3; the drain of MOSFET M7 is connected to the drain of MOSFET M4; and the drain of MOSFET M8 is connected to the drain of MOSFET M5. The drains of MOS transistors M6, M7, and M8 are all connected to the logic circuit group. The gate of MOS transistor M2 is also connected to the gates of MOS transistor M3, MOS transistor M4, and MOS transistor M5, respectively; the sources of MOS transistor M2, MOS transistor M3, MOS transistor M4, and MOS transistor M5 are all connected to a power supply. A first switch K1 is provided between the resistor Rz1 and the external parallel resistor R; the external parallel resistor R is connected in parallel with the power transistor parasitic capacitance Cg.

2. The detection circuit for driving parallel resistors according to claim 1, characterized in that, The drain of the MOS transistor M6 is also connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded; the capacitor C1 is connected in parallel with the second switch K2.

3. The detection circuit for driving parallel resistors according to claim 1, characterized in that, The drain of the MOS transistor M7 is also connected to one end of the capacitor C2, and the other end of the capacitor C2 is grounded; a third switch K3 is connected in parallel with the capacitor C2.

4. The detection circuit for driving parallel resistors according to claim 1, characterized in that, The drain of the MOS transistor M8 is also connected to one end of the capacitor C3, and the other end of the capacitor C3 is grounded; a fourth switch K4 is connected in parallel with the capacitor C3.

5. The detection circuit for driving parallel resistors according to claim 1, characterized in that, The output terminal of the operational amplifier is also connected to one end of capacitor C4, and the other end of capacitor C4 is grounded.

6. The detection circuit for driving parallel resistors according to claim 1, characterized in that, The logic circuit group includes a first logic circuit, a second logic circuit, and a third logic circuit; each of the first, second, and third logic circuits includes an AND gate, a follower, and an RS flip-flop; the output of the AND gate is connected to the input of the follower, and the output of the follower is connected to the S terminal of the RS flip-flop; the drain of the MOS transistor M6 is connected to the first input of the AND gate in the first logic circuit; the drain of the MOS transistor M7 is connected to the first input of the AND gate in the second logic circuit; and the drain of the MOS transistor M8 is connected to the first input of the AND gate in the third logic circuit.

Images