Modeling method and computing system of subcircuit model of semiconductor device

Abstract

The present invention discloses a modeling method and a computing system for a subcircuit model of a semiconductor device, the modeling method comprising: establishing a black box model, the black box model comprising a plurality of interfaces, and a diode being arranged between any two adjacent interfaces of the plurality of interfaces; connecting the black box model to a standard BSIM4 model to generate a subcircuit model; and using the subcircuit model to characterize the breakdown effect and / or punch-through effect of the semiconductor device. The subcircuit model constructed by the present invention not only has the convergence, compatibility and faster simulation speed of the BSIM4 model, but also includes a black box model capable of characterizing the breakdown effect and punch-through effect of the device, and can improve the modeling speed and modeling accuracy of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a modeling method and a computing system for a subcircuit model of a semiconductor device. Background Art

[0002] The working voltage of a chip is usually an important condition for distinguishing chip applications, and the device's breakdown voltage and punch-through voltage are the limit determination conditions for the chip's working voltage. Therefore, in circuit design, whether the device model contains the breakdown effect and punch-through effect is very important. Among them, the device model containing the breakdown effect and punch-through effect can help circuit designers quickly locate and solve problems in the early design process.

[0003] Currently, CMOS (Complementary Metal Oxide Semiconductor) and LDMOS (Lateral Double-Diffused MOSFET) are usually modeled with BSIM4 as the core. The BSIM4 model includes diodes from the drain to the body and from the source to the body of the transistor device. When the breakdown effect of the diode is needed to characterize the breakdown effect of MOS, this part of the diode can meet part of the requirements of CMOS and LDMOS transistor devices.

[0004] BSIM (Berkeley Short-channel IGFET Model) is the most widely used transistor device model in the industry. Based on the two-dimensional analysis of the slowly varying channel approximation and threshold voltage, it focuses on characterizing the DC characteristics of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), such as narrow channel effect, short channel effect, drain-induced barrier lowering effect, and body effect, and has a certain predictive ability for MOSFET characteristics of different sizes. However, the existing BSIM4 model 10 can only meet the two breakdown effects of the transistor from the drain end to the body end, and from the source end to the body end, such as Figure 1b As shown. Figure 2aThe NMOS transistor 120 with DNW (deep-nwell) isolation region shown in the figure also needs to satisfy the breakdown effect from PW (pwell, P-type well region) 104 to DNW102 and the breakdown effect from PSUB (P-Substrate, P-type substrate) 101 to DNW102, but these two breakdown effects cannot be characterized by the BSIM4 model. Figure 3a The LDMOS device 130 shown also needs to satisfy the breakdown effect of these two parts, and also needs to satisfy the punch-through effect of PW / DNW / PSUB.

[0005] If the two breakdown effects of PW to DNW and PSUB to DNW and the punch-through effect of PW / DNW / PSUB mentioned above cannot be reflected in the circuit design, many problems that cannot be quickly solved will arise in the early circuit design. The problems can only be located during chip testing after tape-out, which will lengthen the chip design process and delay progress.

[0006] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the invention

[0007] In order to solve the above technical problems, the present invention provides a modeling method and a computing system for a sub-circuit model of a semiconductor device. The sub-circuit model constructed based on the modeling method can have the convergence, compatibility and faster simulation speed of the BSIM4 model, while also including a black box model that can characterize the breakdown effect and punch-through effect of the device, thereby improving the modeling speed and modeling accuracy of the semiconductor device.

[0008] According to a first aspect of the present invention, a modeling method for a subcircuit model of a semiconductor device is provided, comprising: establishing a black box model, wherein the black box model comprises a plurality of interfaces, and a diode is provided between any two adjacent interfaces of the plurality of interfaces;

[0009] Connecting the black box model to the standard model to generate a sub-circuit model; and

[0010] The sub-circuit model is used to characterize the breakdown effect and / or punch-through effect of the semiconductor device.

[0011] Optionally, the standard model is a standard BSIM4 model.

[0012] Optionally, the semiconductor device is a transistor provided with deep N-well isolation;

[0013] The steps to build a black box model include:

[0014] Establishing a first interface, a second interface and a third interface of the black box model;

[0015] A first diode is provided to be connected between the first interface and the second interface, and a second diode is provided to be connected between the second interface and the third interface;

[0016] A corresponding connection relationship is set between the first interface, the second interface and the third interface and the body terminal, the deep N-well isolation terminal and the P-type substrate terminal of the semiconductor device.

[0017] Optionally, the first diode is used to characterize the breakdown effect from the deep N-well isolation end to the body end of the semiconductor device, and the second diode is used to characterize the breakdown effect from the deep N-well isolation end to the P-type substrate end of the semiconductor device.

[0018] Optionally, both the first diode and the second diode are unidirectional diodes.

[0019] Optionally, the semiconductor device is a lateral double diffused transistor;

[0020] The steps to build a black box model include:

[0021] Establishing a fourth interface, a fifth interface and a sixth interface of the black box model;

[0022] A third diode is provided to be connected between the fourth interface and the fifth interface, and a fourth diode is provided to be connected between the fifth interface and the sixth interface;

[0023] A corresponding connection relationship is set between the fourth interface, the fifth interface and the sixth interface and the drain terminal, the P-type substrate terminal and the body terminal of the semiconductor device.

[0024] Optionally, the third diode is used to characterize a breakdown effect from the drain end to the P-type substrate end of the semiconductor device, and the fourth diode is used to characterize a punch-through effect from the body end to the P-type substrate end of the semiconductor device.

[0025] Optionally, the third diode is a unidirectional diode, and the fourth diode is a bidirectional TVS diode.

[0026] Optionally, using the sub-circuit model to characterize the breakdown effect and / or punch-through effect of the semiconductor device includes:

[0027] Calculating a test voltage according to a voltage region where the semiconductor device is located in the chip;

[0028] The black box model is called, the calculated test voltage is applied to the corresponding interface of the black box model, and the breakdown effect and / or punch-through effect simulation of the semiconductor device is started to obtain an IV simulation curve.

[0029] Optionally, it also includes:

[0030] The placement position of the semiconductor device in the chip is adjusted, and the black box model is called to realize the simulation of the breakdown effect and / or punch-through effect of the semiconductor device in different voltage regions, and obtain IV simulation curves corresponding to different voltage regions.

[0031] Optionally, it also includes:

[0032] The placement position of the semiconductor device in the chip is adjusted, and the black box model is called to realize the simulation of the breakdown effect and / or punch-through effect of the semiconductor device in different voltage regions, and obtain IV simulation curves corresponding to different voltage regions.

[0033] According to a second aspect of the present invention, there is provided a computing system, which comprises: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the modeling method of the sub-circuit model of the semiconductor device as described above.

[0034] The beneficial effects of the present invention include at least: the present invention constructs a black box model through a diode and multiple interfaces, and connects the black box model with a standard model such as a standard BSIM4 model to merge into a sub-circuit model, so that the sub-circuit model finally constructed not only has the convergence, compatibility and faster simulation speed of the BSIM4 model, but also can characterize the breakdown effect and punch-through effect in the semiconductor device that cannot be characterized by the standard BSIM4 model based on the black box model, thereby improving the sub-circuit model's characterization function for various breakdown effects and punch-through effects in the semiconductor device.

[0035] On the other hand, when using the black box model to characterize the breakdown effect and punch-through effect of semiconductor devices, it is only necessary to calculate the corresponding test voltage according to the placement of the semiconductor device in the chip and call the black box model for simulation, which improves the modeling speed of semiconductor devices. And because there is no need to set too many diodes in the sub-circuit model to achieve the characterization of the breakdown effect and punch-through effect of semiconductor devices in different voltage regions of the chip, the complexity and error rate of the modeling work are reduced, and the modeling accuracy is improved. It also avoids circuit designers from placing too many diodes on the line, reducing the complexity of the line.

[0036] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1a A schematic diagram of a cross-sectional structure of an NMOS transistor provided according to an embodiment of the present invention is shown;

[0038] Figure 1bShow Figure 1a A simple structural diagram of the equivalent circuit of the subcircuit model of the NMOS transistor in FIG.

[0039] Figure 2a A schematic cross-sectional structure diagram of an NMOS transistor with a DNW isolation region provided according to an embodiment of the present invention is shown;

[0040] Figure 2b Show Figure 2a A simple structural schematic diagram of an equivalent circuit of a subcircuit model of an NMOS transistor with a DNW isolation region;

[0041] Figure 3a A schematic diagram of the cross-sectional structure of a lateral double diffused transistor provided according to an embodiment of the present invention is shown;

[0042] Figure 3b Show Figure 3a A simple structural diagram of the equivalent circuit of the subcircuit model of the lateral double diffused transistor in FIG.

[0043] Figure 4 A structural diagram of a sub-circuit model of a semiconductor device provided according to an embodiment of the present invention is shown;

[0044] Figure 5 A simple structural schematic diagram showing an equivalent circuit of a sub-circuit model of a semiconductor device provided according to a first embodiment of the present invention;

[0045] Figure 6 A simple structural schematic diagram showing an equivalent circuit of a sub-circuit model of a semiconductor device provided according to a second embodiment of the present invention;

[0046] Figure 7 A schematic flow chart showing a method for modeling a sub-circuit model of a semiconductor device provided in accordance with an embodiment of the present invention;

[0047] Figure 8 A schematic diagram of the structure of a computing system provided according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0048] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0049] like Figure 1aAs shown, the transistor 110 includes a P-type substrate 101, a P-type well region 104 formed in the P-type substrate 101 and located at the top, and a source terminal, a drain terminal and a body terminal respectively located in the P-type well region 104, the source terminal and the drain terminal are both N-type doped regions, and the body terminal is a P-type doped region. An oxide layer 112 and a polysilicon layer 121 are also formed on the surface of the P-type well region 104. Optionally, the transistor 110 is, for example, an NMOS transistor.

[0050] like Figure 1b As shown, the BSIM4 model 10 is usually used to characterize the breakdown effect of the transistor 110. The BSIM4 model 10 includes an equivalent diode Ddb1 connected between the drain terminal (drain) and the body terminal (body) of the transistor 110 and an equivalent diode Dsb1 connected between the source terminal (source) and the body terminal (body) of the transistor 110. Among them, the cathode of the equivalent diode Ddb1 is connected to the drain terminal of the transistor 110, and the anode of the equivalent diode Ddb1 is connected to the body terminal of the transistor 110. The BSIM4 model 10 can use the breakdown effect of the equivalent diode Ddb1 to equivalently characterize the breakdown effect from the drain terminal to the body terminal of the transistor 110. The cathode of the equivalent diode Dsb1 is connected to the source terminal of the transistor 110, and the anode of the equivalent diode Dsb1 is connected to the body terminal of the transistor 110. The BSIM4 model 10 can use the breakdown effect of the equivalent diode Dsb1 to equivalently characterize the breakdown effect from the source terminal to the body terminal of the transistor 110.

[0051] like Figure 2a As shown, transistor 120 includes: a P-type substrate 101, a P-type well region 104 and an N-type well region 105 formed in the P-type substrate 101 and located at the top, a deep N-well isolation region 102 located between the P-type substrate 101 and the P-type well region 104 and the N-type well region 105, and a source terminal, a drain terminal and a body terminal of an NMOS device respectively located in the P-type well region 104, wherein the source terminal and the drain terminal are both N-type doped regions, and the body terminal is a P-type doped region. An oxide layer 112 and a polysilicon layer 121 are also formed on the surface of the P-type well region 104. Optionally, transistor 120 is, for example, an NMOS transistor with a DNW isolation region.

[0052] like Figure 2b As shown, when the breakdown effect of transistor 120 needs to be characterized, in addition to using Figure 1b In addition to the BSIM4 model 10 shown to characterize the breakdown effect from the drain end to the body end and the breakdown effect from the source end to the body end of the transistor 120, the breakdown effect from the deep N-well isolation end (DN) to the body end and the breakdown effect from the deep N-well isolation end to the P-type substrate end (PSUB) of the transistor 120 also require additional diodes such as the first diode D1 and the second diode D2 to characterize them respectively. Among them, the first diode D1 and the second diode D2 are both unidirectional diodes.

[0053] like Figure 3a As shown, the transistor 130 includes: a substrate 201, a P-type well region 202 formed in the semiconductor substrate 201 and located at the top, an N-type well region 203, an N-type drift region 204 formed on the upper part of the semiconductor substrate 201, a body terminal and a source terminal of the transistor 130 located in the P-type well region 202, and a drain terminal of the transistor 130 in the N-type well region 203, the source terminal and the drain terminal are both N-type doped regions, and the body terminal is a P-type doped region. A field oxide layer 231 and a gate oxide layer 241 are also formed on the surface of the N-type drift region 204, and a polysilicon layer 251 is also formed on the gate oxide layer 241 and the field oxide layer 231. The polysilicon layer 251 is used to form the gate of the LDMOS. In this embodiment, the gate oxide layer 241 includes a portion covering the P-type well region 202 and a portion covering the drift region 204. The polysilicon layer 251 covers the upper surface of the gate oxide layer 241 and part of the upper surface of the field oxide layer 231, which can effectively reduce the surface peak electric field of the N-type drift region 204 below the polysilicon layer 251, thereby improving the breakdown voltage. Optionally, the transistor 130 is, for example, an NLDMOS transistor.

[0054] like Figure 3b As shown, when the breakdown effect of transistor 130 needs to be characterized, in addition to using Figure 1b In addition to the BSIM4 model 10 shown to characterize the breakdown effect from the drain end to the body end and the breakdown effect from the source end to the body end of the transistor 130, the breakdown effect from the drain end to the P-type substrate end and the punch-through effect from the body end to the P-type substrate end of the transistor 130 also require additional diodes such as a third diode D3 and a fourth diode D4 to characterize them respectively. Among them, the third diode D3 is a unidirectional diode, and the fourth diode D4 is a bidirectional TVS diode.

[0055] In the actual application of NMOS transistors and NLDMOS transistors with DNW isolation regions, a typical usage is to place transistors in different voltage regions TUB of the chip, but different voltage regions will have different breakdown voltages due to different design rules. This part of the breakdown voltage mainly occurs between the deep N-well isolation region and the P-type substrate of the semiconductor device. At the same time, since the breakdown voltage and punch-through voltage of different types of transistor devices are different, based on the considerations of simplifying the modeling work and reducing the error rate, the present invention uses a black box model to uniformly characterize the breakdown effect and / or punch-through effect in the semiconductor device that cannot be characterized by the BSIM4 model, that is, Figure 2b or Figure 3b The additional diodes required in the package are packaged into a black box model (such as Figure 5 and Figure 6As shown), this can reduce the complexity and error rate of modeling work and improve the speed and accuracy of semiconductor device modeling.

[0056] Specifically, refer to Figure 4 The present invention discloses a sub-circuit model 100 for characterizing a breakdown effect and / or a punch-through effect of a semiconductor device. The sub-circuit model 100 of the semiconductor device includes: a standard model 10 and a black box model 20 connected to the standard model 10.

[0057] Standard model 10 can be referenced Figure 1b It is understood that it is mainly based on the equivalent diode Ddb1 connected between the drain and body of the semiconductor device and the equivalent diode Dsb1 connected between the source and body of the semiconductor device to respectively equivalently characterize the breakdown effect from the drain to the body and the breakdown effect from the source to the body of the semiconductor device. And illustratively, the standard BSIM4 model is used as the standard model 10 in this embodiment.

[0058] Optionally, the semiconductor device in the present invention may be a transistor with a deep N-well isolation region (eg, NMOS transistor 120 or PMOS transistor), or a lateral double diffused transistor LDMOS (eg, NLDMOS transistor 130 or PLDMOS transistor).

[0059] The black box model 20 has a plurality of interfaces, each of which is connected to a port of a semiconductor device, and a diode is connected between any two adjacent interfaces of the plurality of interfaces. The black box model 20 characterizes the breakdown effect and / or punch-through effect between the corresponding interfaces based on the diode. Among them, the plurality of interfaces of the black box model 20 receive a test voltage to implement the test of the breakdown effect and / or punch-through effect of the semiconductor device. And when located in different voltage regions of the chip, the voltage values ​​of the test voltages received by the plurality of interfaces of the black box model 20 are different.

[0060] For different types of semiconductor devices, the present invention can define the established black box model 20 according to the type of semiconductor device to be characterized, i.e., the target semiconductor device (including the definition of multiple interfaces of the black box model 20 and the definition of diodes in the black box model 20), and then by applying corresponding test voltages to the interfaces after the black box model 20 is defined, the diodes connected between the multiple interfaces in the black box model 20 can be used to characterize the breakdown effect and / or punch-through effect in the target semiconductor device that cannot be characterized by the standard model 10. In other words, the black box model 20 of the present invention can achieve the characterization of the breakdown effect and punch-through effect of multiple different types of semiconductor devices based on limited diodes, and the modeling work is simple.

[0061] In the first embodiment of the present invention, reference Figure 5, taking the semiconductor device as a transistor 120 (referred to as transistor 120) provided with deep N-well isolation as an example. At this time, the black box model 20 for characterizing the breakdown effect of the transistor 120 provided with deep N-well isolation includes: a first interface, a second interface, a third interface, a first diode D1 connected between the first interface and the second interface, and a second diode D2 connected between the second interface and the third interface.

[0062] Exemplarily, the definition of the black box model 20 in this embodiment of the present invention includes: defining that the first interface of the black box model 20 is connected to the body terminal of the semiconductor device, or defining the first interface of the black box model 20 as the body terminal of the semiconductor device; defining that the second interface of the black box model 20 is connected to the deep N-well isolation terminal of the semiconductor device, or defining the second interface of the black box model 20 as the deep N-well isolation terminal of the semiconductor device; defining that the third interface of the black box model 20 is connected to the P-type substrate terminal of the semiconductor device, or defining the third interface of the black box model 20 as the P-type substrate terminal of the semiconductor device; defining the initial value of the breakdown voltage from the deep N-well isolation terminal to the body terminal of the transistor 120, and the initial value of the breakdown voltage from the deep N-well isolation terminal to the P-type substrate terminal; defining the area and perimeter parameters of the first diode D1, and defining the area and perimeter parameters of the second diode D2; defining other conventional parameters of the first diode D1 and the second diode D2. Furthermore, by defining multiple interfaces of the black box model 20, as well as the device parameters of each diode in the black box model 20, the corresponding initial value of the breakdown voltage, and the corresponding end-to-end breakdown effect in the represented transistor 120, in the process of modeling the transistor 120, it is only necessary to call the above-defined black box model 20 of the transistor 120 to quickly and accurately complete the breakdown effect of the transistor 120, and even the characterization of the current and capacitance.

[0063] Exemplarily, in this embodiment, the present invention includes: setting the voltage region (referred to as tub) where the transistor 120 is placed in the chip, for example, tub=5v represents that the transistor 120 is placed in the 5V region of the chip, and tub=100v represents that the transistor 120 is placed in the 100V region of the chip; setting the device parameters of the transistor 120, including respectively setting the channel width and channel length of the transistor 120; and calculating the breakdown voltage bv according to the proportionality coefficient (a) between different voltage regions and the corresponding breakdown voltage and the set voltage region tub, wherein the calculation formula of the breakdown voltage bv is bv=a*tub, for example, if tub=10v, a=1.5, then bv=15v. It can be understood that different voltage regions correspond to different breakdown voltages from the P-type substrate end to the deep N-well isolation end, and when calling the black box model 20, it is only necessary to write the calculated breakdown voltage value into the black box model 20 according to the voltage region where the transistor 120 is located in the chip.

[0064] Furthermore, by applying a corresponding test voltage between the first interface and the second interface of the black box model 20, the first diode D1 can be used to characterize the breakdown effect from the deep N-well isolation end to the body end of the semiconductor device, and by applying a corresponding test voltage between the second interface and the third interface of the black box model 20, the second diode D2 can be used to characterize the breakdown effect from the deep N-well isolation end to the P-type substrate end of the semiconductor device.

[0065] In the second embodiment of the present invention, reference Figure 6 , taking the semiconductor device as a lateral double diffused transistor 130 (abbreviated as transistor 130) as an example. At this time, the black box model 20 used to characterize the breakdown effect and the punch-through effect of the lateral double diffused transistor 130 includes: a fourth interface, a fifth interface, a sixth interface, a third diode D3 connected between the fourth interface and the fifth interface, and a fourth diode D4 connected between the fifth interface and the sixth interface.

[0066] Exemplarily, the definition of the black box model 20 in this embodiment of the present invention includes: defining that the fourth interface of the black box model 20 is connected to the drain terminal of the semiconductor device, or defining the fourth interface of the black box model 20 as the drain terminal of the semiconductor device; defining that the fifth interface of the black box model 20 is connected to the P-type substrate terminal of the semiconductor device, or defining the fifth interface of the black box model 20 as the P-type substrate terminal of the semiconductor device; defining that the sixth interface of the black box model 20 is connected to the body terminal of the semiconductor device, or defining the sixth interface of the black box model 20 as the body terminal of the semiconductor device; defining the initial value of the breakdown voltage from the drain terminal to the body terminal of the transistor 130, the initial value of the breakdown voltage from the drain terminal to the P-type substrate terminal, and the initial value of the punch-through voltage from the body terminal to the P-type substrate terminal of the transistor 130; defining the area and perimeter parameters of the third diode D3, defining the area and perimeter parameters of the fourth diode D4; defining other conventional parameters of the third diode D3 and the fourth diode D4. Furthermore, by defining multiple interfaces of the black box model 20, as well as the device parameters of each diode in the black box model 20, the corresponding initial value of the breakdown voltage, the initial value of the punch-through voltage, and the corresponding end-to-end breakdown effect and / or punch-through effect in the represented transistor 130, in the process of modeling the transistor 130, it is only necessary to call the black box model 20 of the transistor 130 defined above to quickly and accurately complete the characterization of the breakdown effect and the punch-through effect of the transistor 130.

[0067] Exemplarily, in this embodiment, the present invention includes: setting the voltage region where the transistor 130 is placed in the chip, for example, tub=5v represents that the transistor 130 is placed in the 5V region of the chip, and tub=100v represents that the transistor 130 is placed in the 100V region of the chip; setting the device parameters of the transistor 130, including setting the channel width and channel length of the transistor 130 respectively; and calculating the breakdown voltage bv according to the proportional coefficient (a) between different voltage regions and the corresponding breakdown voltage and the set voltage region tub, wherein the calculation formula of the breakdown voltage bv is bv=a*tub, for example, if tub=10v, a=1.5, then bv=15v. It can be understood that different voltage regions correspond to different breakdown voltages from the P-type substrate end to the deep N-well isolation end, and when calling the black box model 20, it is only necessary to write the calculated breakdown voltage value into the black box model 20 according to the voltage region where the transistor 130 is located in the chip.

[0068] Furthermore, by applying a corresponding test voltage between the fourth interface and the fifth interface of the black box model 20, the third diode D3 can be used to characterize the breakdown effect from the drain end to the P-type substrate end of the semiconductor device, and by applying a corresponding test voltage between the fifth interface and the sixth interface of the black box model 20, the fourth diode D4 can be used to characterize the punch-through effect from the body end to the P-type substrate end of the semiconductor device.

[0069] Furthermore, the present invention also discloses a modeling method of a sub-circuit model of a semiconductor device, which is used to establish Figures 4 to 6 The sub-circuit model 100 shown in FIG. Figure 7 , the modeling method comprises the following steps:

[0070] In step S1, a black box model is established.

[0071] The black box model established by the present invention includes multiple interfaces, and a diode is provided between any two adjacent interfaces of the multiple interfaces. Furthermore, when the established black box model is used to characterize the breakdown effect and punch-through effect of a semiconductor device, it is only necessary to define multiple interfaces of the black box model to establish a connection relationship between the interfaces and the corresponding ports of the semiconductor device, and the black box model can be used to characterize the breakdown effect and / or punch-through effect between the corresponding ends of the semiconductor device based on the diodes therein.

[0072] Furthermore, the black box model established in the present invention includes two categories, wherein the first category of black box models corresponds to Figure 5The black box model 20 shown in the figure can be applied to the transistor 120 with deep N-well isolation, and its establishment steps include: establishing the first interface, the second interface and the third interface of the black box model; setting a first diode connected between the first interface and the second interface, and setting a second diode connected between the second interface and the third interface; setting the corresponding connection relationship between the first interface, the second interface and the third interface and the body end, the deep N-well isolation end and the P-type substrate end of the semiconductor device. Among them, the first diode and the second diode are both unidirectional diodes. And the first diode is used to characterize the breakdown effect from the deep N-well isolation end to the body end of the semiconductor device, and the second diode is used to characterize the breakdown effect from the deep N-well isolation end to the P-type substrate end of the semiconductor device.

[0073] The second type of black box model corresponds to Figure 6 The black box model 20 shown in the figure can be applied to the lateral double diffused transistor 130, and its establishment steps include: establishing the fourth interface, the fifth interface and the sixth interface of the black box model; setting a third diode connected between the fourth interface and the fifth interface, and setting a fourth diode connected between the fifth interface and the sixth interface; setting the corresponding connection relationship between the fourth interface, the fifth interface and the sixth interface and the drain end, the P-type substrate end and the body end of the semiconductor device. Among them, the third diode is a unidirectional diode, and the fourth diode is a bidirectional TVS diode. And the third diode is used to characterize the breakdown effect from the drain end to the P-type substrate end of the semiconductor device, and the fourth diode is used to characterize the punch-through effect from the body end to the P-type substrate end of the semiconductor device.

[0074] In step S2, the black box model is connected to the standard model to generate a sub-circuit model.

[0075] The black box model established in step S1 is connected and merged with a standard model, such as a standard BSIM4 model, to generate a sub-circuit model in an embodiment of the present invention.

[0076] In step S3, a sub-circuit model is used to characterize a breakdown effect and / or a punch-through effect of a semiconductor device.

[0077] In this embodiment, step S3 further includes: calculating the test voltage according to the voltage region where the semiconductor device is located in the chip; calling the black box model, applying the calculated test voltage to the corresponding interface of the black box model, and starting the breakdown effect and / or punch-through effect simulation of the semiconductor device to obtain an IV simulation curve.

[0078] Furthermore, after adjusting the placement position of the semiconductor device in the chip (i.e., the voltage region where the semiconductor device is located in the chip), the black box model is called again. The breakdown effect and / or punch-through effect simulation of the semiconductor device in different voltage regions can be realized without placing too many diodes in the circuit, and the IV simulation curves corresponding to different voltage regions can be obtained.

[0079] It should be noted that the drawings of the present invention only illustrate various types of N-channel MOS transistors, but the sub-circuit model and modeling method disclosed in the present invention are also applicable to P-channel MOS transistors corresponding to various types of N-channel MOS transistors (for example, PMOS transistors with deep N-well isolation corresponding to NMOS transistors with deep N-well isolation, PLDMOS transistors corresponding to NLDMOS transistors, etc.).

[0080] Furthermore, the present invention also discloses a computing system 200 for modeling a sub-circuit model of a semiconductor device, such as Figure 8 As shown, it includes a memory 220, a processor 210, and a program stored in the memory 220 and executable on the processor 210. When the program is executed by the processor 210, each process of each embodiment of the modeling method of the sub-circuit model of the semiconductor device described above can be implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0081] In summary, the present invention constructs a black box model through diodes and multiple interfaces, and connects the black box model with the standard BSIM4 model, so that the sub-circuit model finally constructed not only has the convergence, compatibility and faster simulation speed of the BSIM4 model, but also can characterize the breakdown effect and punch-through effect in the device that cannot be characterized by the standard BSIM4 model based on the black box model, thereby improving the characterization function of the sub-circuit model for various breakdown effects and punch-through effects in semiconductor devices.

[0082] On the other hand, when using the black box model to characterize the breakdown effect and punch-through effect of semiconductor devices, it is only necessary to calculate the corresponding test voltage according to the placement of the semiconductor device in the chip and call the black box model for simulation, which improves the modeling speed of semiconductor devices. And because there is no need to set too many diodes in the device model to achieve the characterization of the breakdown effect and punch-through effect of semiconductor devices in different voltage regions of the chip, the complexity and error rate of the modeling work are reduced, and the accuracy of the modeling is improved.

[0083] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. A method for modeling a subcircuit model of a semiconductor device, wherein: include: Establishing a black box model, wherein the black box model includes a plurality of interfaces, and a diode is provided between any two adjacent interfaces among the plurality of interfaces; Connecting the black box model to a standard model to generate a subcircuit model, wherein the standard model is a standard BSIM4 model; as well as The sub-circuit model is used to characterize the breakdown effect and / or punch-through effect of the semiconductor device, including: Defining a plurality of interfaces of the established black box model according to the type of semiconductor device to be characterized, and defining a diode in the black box model; A corresponding test voltage is applied to the interface after the black box model is defined, and a breakdown effect and / or punch-through effect in the semiconductor device that cannot be characterized by the standard model is characterized by using diodes arranged between multiple interfaces in the black box model. The breakdown effects in the semiconductor device that cannot be characterized by the standard model include: the breakdown effect from the deep N-well isolation end to the body end of the semiconductor device and the breakdown effect from the deep N-well isolation end to the P-type substrate end of the semiconductor device, or the breakdown effect from the drain end to the P-type substrate end of the semiconductor device; The punch-through effect in the semiconductor device that cannot be characterized by the standard model includes: a punch-through effect from the body end to the P-type substrate end of the semiconductor device.

2. The modeling method according to claim 1, wherein: The semiconductor device is a transistor provided with deep N-well isolation; The steps to build a black box model include: Establishing a first interface, a second interface and a third interface of the black box model; A first diode is provided to be connected between the first interface and the second interface, and a second diode is provided to be connected between the second interface and the third interface; A corresponding connection relationship is set between the first interface, the second interface and the third interface and the body terminal, the deep N-well isolation terminal and the P-type substrate terminal of the semiconductor device.

3. The modeling method according to claim 2, wherein: The first diode is used to characterize the breakdown effect from the deep N-well isolation end to the body end of the semiconductor device, and the second diode is used to characterize the breakdown effect from the deep N-well isolation end to the P-type substrate end of the semiconductor device.

4. The modeling method according to claim 3, wherein: The first diode and the second diode are both unidirectional diodes.

5. The modeling method according to claim 1, wherein: The semiconductor device is a lateral double diffused transistor; The steps to build a black box model include: Establishing a fourth interface, a fifth interface and a sixth interface of the black box model; A third diode is provided to be connected between the fourth interface and the fifth interface, and a fourth diode is provided to be connected between the fifth interface and the sixth interface; A corresponding connection relationship is set between the fourth interface, the fifth interface and the sixth interface and the drain terminal, the P-type substrate terminal and the body terminal of the semiconductor device.

6. The modeling method according to claim 5, wherein: The third diode is used to characterize the breakdown effect from the drain end to the P-type substrate end of the semiconductor device, and the fourth diode is used to characterize the punch-through effect from the body end to the P-type substrate end of the semiconductor device.

7. The modeling method according to claim 6, wherein: The third diode is a unidirectional diode, and the fourth diode is a bidirectional TVS diode.

8. The modeling method according to claim 1, wherein: Characterizing the breakdown effect and / or punch-through effect of a semiconductor device using the sub-circuit model includes: Calculating a test voltage according to a voltage region where the semiconductor device is located in the chip; The black box model is called, the calculated test voltage is applied to the corresponding interface of the black box model, and the breakdown effect and / or punch-through effect simulation of the semiconductor device is started to obtain an IV simulation curve.

9. The modeling method according to claim 8, wherein: Also includes: The placement position of the semiconductor device in the chip is adjusted, and the black box model is called to realize the simulation of the breakdown effect and / or punch-through effect of the semiconductor device in different voltage regions, and obtain IV simulation curves corresponding to different voltage regions.

10. A computing system, wherein: include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program implements the steps of the method according to any one of claims 1 to 9 when executed by the processor.

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