Flash memory controller and method for accessing flash memory module

Abstract

The present invention discloses a flash memory controller and a method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes multiple blocks, each block includes multiple pages, and the method includes the following steps: sending a read command to the flash memory module to request data on at least one memory unit; receiving multi-bit information of multiple memory cells of the at least one memory unit from the flash memory module; and analyzing the multi-bit information of the multiple memory cells to obtain a critical voltage distribution of the multiple memory cells for determining a decoding procedure. In general, the flash memory module of the present invention can output multi-bit information of each memory cell to the flash memory controller in response to the read command, and the multi-bit information of each memory cell can indicate the critical voltage or state of the memory cell. Therefore, the reading efficiency can be greatly improved.

Description

[0001] This application is a divisional application of the Chinese invention application with the application date of July 17, 2019, application number 201910647337.4, and invention name “Flash memory controller and method for accessing flash memory module”. Technical Field

[0002] The present invention relates to access control of flash memory, and in particular to a method for managing access to a flash memory module, a related flash memory controller, and an electronic device. Background Art

[0003] With the continuous advancement of memory technology in recent years, various portable and non-portable memory devices (e.g., memory cards compliant with the SD / MMC, CF, MS, XD, and UFS standards; solid-state drives (SSDs); and embedded memory devices compliant with the UFS and EMMC specifications) have been widely implemented in numerous applications. Consequently, access control of the memory in these devices has become a hot topic.

[0004] As for the commonly used NAND flash memory, it can mainly include two categories of flash memory: single-level cell (SLC) and multi-level cell (MLC). In single-level cell flash memory, each transistor used as a memory cell has only two charge values, which are used to represent the logical value 0 and the logical value 1 respectively. In addition, the storage capacity of each transistor used as a memory cell in multi-level cell flash memory is fully utilized. It is driven by a higher voltage to record at least two bits of information (such as 00, 01, 11, 10) in a transistor through different levels of voltage. In theory, the recording density of multi-level cell flash memory can reach at least twice the recording density of single-level cell flash memory. This is very good news for the NAND flash memory industry, which has encountered bottlenecks in its development.

[0005] Compared to single-level cell flash memory, multi-level cell flash memory is cheaper and offers greater capacity within a limited space. Therefore, multi-level cell flash memory has quickly become the mainstream memory device on the market. However, problems caused by the instability of multi-level cell flash memory have also emerged. To ensure that access control to the flash memory in memory devices complies with relevant regulations, flash memory controllers typically have some management mechanisms to properly manage data access.

[0006] According to the existing technology, memory devices with the above management mechanisms still have shortcomings. For example, when triple level cells (TLC) are used in memory devices, there will be problems such as increased bit error rate. Although traditional sensing schemes for reading data from triple level cell flash memory have been proposed to try to solve these problems, they do not work on memory devices with quadruple level cell (QLC) flash memory. In particular, traditional sensing schemes are not good for the high-level storage potential per memory cell in quadruple level cell flash memory. Therefore, a novel method and related architecture are needed to enhance overall performance without side effects or with less side effects. Summary of the Invention

[0007] An object of the present invention is to disclose a method for performing access management on a memory device, which can efficiently obtain sufficient information for decoding operation even in a high-density storage arrangement to solve the above-mentioned problem.

[0008] One embodiment of the present invention discloses a flash memory controller, wherein the flash memory controller is coupled to a flash memory module, the flash memory module including at least one flash memory chip, each flash memory chip including multiple blocks, each block including multiple pages, and the flash memory controller includes a memory, a microprocessor, and a control logic circuit. The memory is used to store a program code, and the microprocessor is used to execute the program code to access the flash memory module through the control logic circuit. During operation of the flash memory controller, after the microprocessor sends a read command to the flash memory module to request data from at least one memory unit, the control logic circuit receives multi-bit information from multiple memory cells of the at least one memory unit from the flash memory module, and the control logic circuit analyzes the multi-bit information of the multiple memory cells to obtain a threshold voltage distribution of the multiple memory cells for determining a decoding process.

[0009] Another embodiment of the present invention discloses a method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes multiple blocks, each block includes multiple pages, and the method includes the following steps: sending a read command to the flash memory module to request data on at least one memory unit; receiving multi-bit information of multiple memory cells of the at least one memory unit from the flash memory module; and analyzing the multi-bit information of the multiple memory cells to obtain a threshold voltage distribution of the multiple memory cells for determining a decoding procedure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0011] Figure 2 FIG. 1 is a schematic diagram of a three-dimensional NAND flash memory according to an embodiment of the present invention.

[0012] Figure 3 An embodiment of the present invention is shown Figure 2 Some local structures of the three-dimensional NAND flash memory are shown.

[0013] Figure 4 An embodiment of the present invention is shown Figure 2 Some implementation details of one memory cell among a plurality of memory cells of a three-dimensional NAND flash memory are shown.

[0014] Figure 5 FIG. 1 is a schematic diagram illustrating multiple states (programmed states) of a memory cell in a fourth-level cell block according to an embodiment of the present invention.

[0015] Figure 6 FIG. 1 is a schematic diagram of a flash memory chip according to an embodiment of the present invention.

[0016] Figure 7 FIG. 1 is a schematic diagram of a sense amplifier according to a first embodiment of the present invention.

[0017] Figure 8 According to an embodiment of the present invention Figure 7 Figure 1 shows the timing diagram of some signals of the sense amplifier.

[0018] Figure 9 FIG. 4 is a schematic diagram of a counter and a mapping circuit according to an embodiment of the present invention.

[0019] Figure 10 FIG. 1 is a diagram illustrating states S0 - S15 and corresponding most significant bits and least significant bits according to an embodiment of the present invention.

[0020] Figure 11 FIG. 1 is a timing diagram of transmitting a read command and the most significant bit / least significant bit according to an embodiment of the present invention.

[0021] Figure 12 The flowchart of a method for accessing a flash memory module according to one embodiment of the present invention is shown.

[0022] Figure 13 FIG. 4 is a histogram of multiple states of multiple memory cells according to an embodiment of the present invention.

[0023] Figure 14The flowchart of a method for accessing a flash memory module according to another embodiment of the present invention is shown.

[0024] Figure 15 FIG. 1 is a timing diagram of transmitting a read command and the most significant bit / least significant bit according to an embodiment of the present invention.

[0025] Figure 16 FIG. 4 is a schematic diagram showing valley values of a histogram according to an embodiment of the present invention.

[0026] Figure 17 FIG. 1 is a schematic diagram showing the distribution of threshold voltages of a plurality of memory cells according to an embodiment of the present invention.

[0027] Figure 18 FIG. 1 is a schematic diagram of a sense amplifier according to a second embodiment of the present invention.

[0028] Figure 19 According to an embodiment of the present invention Figure 18 Figure 1 shows the timing diagram of some signals of the sense amplifier.

[0029] The description of the accompanying drawings is as follows:

[0030] 10 Electronic devices

[0031] 50 Main unit

[0032] 52 processors

[0033] 54 Power supply circuit

[0034] 100 Memory Device

[0035] 110 Memory Controller

[0036] 112 microprocessors

[0037] 112C Program Code

[0038] 112M read-only memory

[0039] 114 Control Logic Circuit

[0040] 132 Encoder

[0041] 134 Decoder

[0042] 136 Randomizer

[0043] 138 Derandomizer

[0044] 116 Random Access Memory

[0045] 118 transmission interface circuit

[0046] 120 Flash Memory Module

[0047] 122-1, 122-2, …, 122-N flash memory chips

[0048] 1200,1202,1204,1206,1208,

[0049] 1210,1212,1214,1216,

[0050] 1400,1402,1404,1406,1408,

[0051] 1410,1412,1414,1416,1418,

[0052] 1420,1422,1424,1426,1428, steps

[0053] M(1,1,1),M(2,1,1),…,M(Nx,

[0054] 1,1),

[0055] M(1,2,1),…,M(Nx,2,1),…,

[0056] M(1,Ny,1),…,M(Nx,Ny,1),

[0057] M(1,1,2),M(2,1,2),…,M(Nx,

[0058] 1,2),

[0059] M(1,2,2),…,M(Nx,2,2),…,

[0060] M(1,Ny,2),…,M(Nx,Ny,

[0061] 2),…,

[0062] M(1,1,Nz),…,M(Nx,1,Nz),

[0063] M(1,2,Nz),…,M(Nx,2,

[0064] Nz),…,

[0065] M(1,Ny,Nz),…,M(Nx,Ny,Nz),

[0066] M(nx,ny,nz) memory cells

[0067] MBLS(1,1),…,MBLS(Nx,1),

[0068] MBLS(1,2),…,MBLS(Nx,

[0069] 2),…,

[0070] MBLS(1,Ny),…,MBLS(Nx, upper selection circuit

[0071] Ny)

[0072] MSLS(1,1),…,MSLS(Nx,1),

[0073] MSLS(1,2),…,MSLS(Nx,

[0074] 2),…,

[0075] MSLS(1,Ny),…,MSLS(Nx,Ny) bottom selection circuit

[0076] BL(1),…,BL(Nx) bit lines

[0077] WL(1,1),WL(2,1),…,WL(Ny,

[0078] 1),

[0079] WL(1,2),WL(2,2),…,WL(Ny,

[0080] 2),…,

[0081] WL(1,Nz),WL(2,Nz),…,word lines

[0082] WL(Ny,Nz)

[0083] BLS(1),BLS(2),…,BLS(Ny) upper selection line

[0084] SLS(1),SLS(2),…,SLS(Ny) lower selection line

[0085] SL(1),SL(2),…,SL(Ny) source lines

[0086] PS2D(1),PS2D(2),…,PS2D(Ny) circuit modules

[0087] S(1,1),…,S(Nx,1),

[0088] S(1,2),…,S(Nx,2),…,

[0089] S(1,Ny),…,S(Nx,Ny) secondary circuit modules

[0090] Mch rod segment

[0091] Md Upper side of the rod segment

[0092] Ms lower side of the rod segment

[0093] Mfg first tubular local structure

[0094] Mcg Second tubular local structure

[0095] VR1, VR2, VR3, VR4, VR5,

[0096] VR6, VR7, VR8, VR9, VR10,

[0097] VR11, VR12, VR13, VR14, read voltage

[0098] VR15

[0099] S0,S1,S2,S3,S4,S5,S6,S7,

[0100] S8,S9,S10,S11,S12,S13,S14,Status

[0101] S15

[0102] 600 flash memory chips

[0103] 610,620 memory array

[0104] 612,614,622,624 Sense Amplifiers

[0105] 632,634 Peripheral Circuits

[0106] 700,1800 Sense Amplifier

[0107] 710,1810 Operational Amplifier

[0108] 712,1812 Voltage Source

[0109] 714 Control Circuit

[0110] 716 Counter

[0111] 910 Mapping Circuit

[0112] 1814 Digital-to-Analog Converter

[0113] Vout output signal

[0114] Vsen, Vpre, VBL voltage

[0115] VR read voltage

[0116] CNT count value

[0117] CBL parasitic capacitance

[0118] SW1 switch

[0119] I_cell current

[0120] T0, T1, T2 time

[0121] CNT_EN, DAC_EN enable signal

[0122] VH1, VH13 symbols

[0123] SS1,SS17,SS33,SS49,SS65,

[0124] SS81,

[0125] SS97,SS113,SS129,SS145,

[0126] SS167.SS177,

[0127] SS193,SS209,SS225,SS241, Status

[0128] SS257 DETAILED DESCRIPTION

[0129] Figure 1FIG1 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention. The electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors), collectively referred to as a processor 52, and may also include a power supply circuit 54 coupled to the processor 52. The processor 52 may be used to control the operation of the host device 50, while the power supply circuit 54 may be used to provide power to the processor 52 and the memory device 100, and output one or more driving voltages to the memory device 100. The memory device 100 may provide storage space for the host device 50 and obtain the one or more driving voltages from the host device 50 as power for the memory device 100. Examples of the host device 50 include, but are not limited to, multifunctional mobile phones, tablet computers, and personal computers such as desktop computers and laptop computers. Examples of memory device 100 include (but are not limited to): solid state drives (SSDs) and various types of embedded memory devices, such as those compliant with the Peripheral Component Interconnect Express (PCIe) standard. According to this embodiment, memory device 100 may include a flash memory controller 110 and may also include a flash memory module 120. Flash memory controller 110 is used to control the operation of memory device 100 and access flash memory module 120, which is used to store information. Flash memory module 120 may include at least one flash memory chip, such as multiple flash memory chips 122-1, 122-2, ..., and 122-N, where "N" may represent a positive integer greater than one.

[0130] like Figure 1As shown, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage unit such as a read-only memory (ROM) 112M, a control logic circuit 114, a random access memory (RAM) 116, and a transmission interface circuit 118, wherein these components may be coupled to each other via a bus. The RAM 116 may be implemented as a static random access memory (SRAM), but the present invention is not limited thereto. The RAM 116 may be used to provide internal storage space for the flash memory controller 110. For example, the RAM 116 may be used as a buffer memory to buffer data. In addition, the ROM 112M of this embodiment is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120. Please note that in some examples, the program code 112C may be stored in the RAM 116 or any other form of memory. In addition, the control logic circuit 114 can be used to control the flash memory module 120 and may include an encoder 132, a decoder 134, a randomizer 136, a de-randomizer 138, and other circuits. The transmission interface circuit 118 can comply with a specific communication standard (such as the Serial Advanced Technology Attachment (SATA) standard, the Peripheral Component Interconnect (PCI) standard, the Peripheral Component Interconnect Express standard, the Universal Flash Storage (UFS) standard, etc.) and can communicate according to the specific communication standard, for example, for the memory device 100 to communicate with the host device 50, wherein the host device 50 may include a corresponding transmission interface circuit that complies with the specific communication standard to enable the host device 50 to communicate with the memory device 100.

[0131] In this embodiment, the host device 50 can send a host command and a corresponding logical address to the flash memory controller 110 to access the memory device 100. The flash memory controller 110 receives the host command and the logical address and translates the host command into a memory operation command (hereinafter referred to as an operation command). The operation command is then used to control the flash memory module 120 to read, write, or program memory cells (e.g., data pages) at certain physical addresses in the flash memory module 120, where the physical addresses correspond to the logical addresses. When the memory controller 110 performs an erase operation on any flash memory chip 122-n among the flash memory chips 122-1, 122-2, ..., and 122-N (where "n" can represent any integer in the range [1, N]), at least one block among a plurality of blocks of the flash memory chip 122-n is erased. Each of the plurality of blocks may include a plurality of pages (e.g., data pages), and an access operation (e.g., read or write) may be performed on one or more pages.

[0132] Figure 2 A schematic diagram of a three-dimensional (3D) NAND flash memory according to an embodiment of the present invention. For example, any memory component in at least one of the flash memory chips 122-1, 122-2, ... and 122-N may be based on Figure 2 The present invention is implemented with a three-dimensional NAND flash memory as shown, but the present invention is not limited thereto.

[0133] According to this embodiment, the three-dimensional NAND flash memory may include a plurality of memory cells arranged in a three-dimensional structure, such as (Nx*Ny*Nz) memory cells {{M(1,1,1),…,M(Nx,1,1)}, {M(1,2,1),…,M(Nx,2,1)},…,{M(1,Ny,1),…,M(Nx,Ny,1)}}, {{M(1,1,2),…,M(Nx,1 ,2)},{M(1,2,2),…,M(Nx,2,2)},…,{M(1,Ny,2),…,M(Nx,Ny,2)}},…,and{{M(1,1,Nz),…,M(Nx,1,Nz)},{M(1,2,Nz),…,M(Nx,2,Nz)},…,{M(1,Ny,Nz),…,M(Nx,Ny,Nz)}}, and may further include a plurality of selector circuits for selection control, such as an upper layer (upper) arranged above the Nz layer. The (Nx*Ny) upper selector circuits {MBLS(1,1),…,MBLS(Nx,1)}, {MBLS(1,2),…,MBLS(Nx,2)},…and {MBLS(1,Ny),…,MBLS(Nx,Ny)} of the Nz layer, and the (Nx*Ny) lower selector circuits {MSLS(1,1),…,MSLS(Nx,1)}, {MSLS(1,2),…,MSLS(Nx,2)},…and {MSLS(1,Ny),…,MSLS(Nx,Ny)} of a lower layer arranged below the Nz layer. In addition, the three-dimensional NAND flash memory may include multiple bit lines and multiple word lines for access control, such as Nx bit lines BL(1), ..., and BL(Nx) arranged in a top layer above the upper layer, and (Ny*Nz) word lines {WL(1,1), WL(2,1), ..., WL(Ny,1)}, {WL(1,2), WL(2,2), ..., WL(Ny,2)}, ..., and {WL(1,Nz), WL(2,Nz), ..., WL(Ny,Nz)} arranged in the Nz layer respectively.In addition, the three-dimensional NAND flash memory may include a plurality of selection lines for selection control, such as Ny upper selection lines BLS(1), BLS(2), ... and BLS(Ny) arranged in the upper layer, and Ny lower selection lines SLS(1), SLS(2), ... and SLS(Ny) arranged in the lower layer, and may also include a plurality of source lines for providing a plurality of reference levels, such as Ny source lines SL(1), SL(2), ... and SL(Ny) arranged in a bottom layer below the lower layer.

[0134] like Figure 2As shown, the three-dimensional NAND flash memory can be divided into Ny circuit modules PS2D(1), PS2D(2), ... and PS2D(Ny) distributed along the Y axis. For ease of understanding, the circuit modules PS2D(1), PS2D(2), ... and PS2D(Ny) may have certain electrical characteristics similar to those of a planar NAND flash memory (whose memory cells are arranged in a single layer), and therefore may be respectively regarded as multiple virtual two-dimensional (pseudo-2D) circuit modules, but the present invention is not limited to this. In addition, any circuit module PS2D(ny) among the circuit modules PS2D(1), PS2D(2), ... and PS2D(Ny) may include Nx secondary circuit modules S(1,ny), ... and S(Nx,ny), where "ny" may represent any integer in the interval [1,Ny]. For example, circuit module PS2D(1) may include Nx secondary circuit modules S(1,1), ... and S(Nx,1), circuit module PS2D(2) may include Nx secondary circuit modules S(1,2), ... and S(Nx,2), ..., and circuit module PS2D(Ny) may include Nx secondary circuit modules S(1,Ny), ... and S(Nx,Ny). In circuit module PS2D(ny), any of the secondary circuit modules S(1,ny), ..., and S(Nx,ny) may include Nz memory cells M(nx,ny,1), M(nx,ny,2), ..., and M(nx,ny,Nz), and may include a set of selector circuits corresponding to the memory cells M(nx,ny,1), M(nx,ny,2), ..., and M(nx,ny,Nz), such as an upper selector circuit MBLS(nx,ny) and a lower selector circuit MSLS(nx,ny), where "nx" may represent any integer in the interval [1,Nx]. The upper selector circuit MBLS(nx,ny), the lower selector circuit MSLS(nx,ny), and the memory cells M(nx,ny,1), M(nx,ny,2), ..., and M(nx,ny,Nz) may be implemented using transistors. For example, the upper selector circuit and the lower selector circuit MSLS(nx,ny) can be implemented by ordinary transistors without any floating gates, and any memory cell M(nx,ny,nz) among the memory cells M(nx,ny,1), M(nx,ny,2), ... and M(nx,ny,Nz) can be implemented by a floating gate transistor, where "nz" can represent any integer in the interval [1,Nz], but the present invention is not limited to this.In addition, the upper selector circuits MBLS(1,ny), ... and MBLS(Nx,ny) in the circuit module PS2D(ny) can be selected according to the selection signal on the corresponding selection line BLS(ny), and the lower selector circuits MSLS(1,ny), ... and MSLS(Nx,ny) in the circuit module PS2D(ny) can be selected according to the selection signal on the corresponding selection line SLS(ny).

[0135] Figure 3 An embodiment of the present invention is shown Figure 2 The three-dimensional NAND flash memory can be designed to have a plurality of rod-shaped local structures such as Figure 3 The rod-shaped local structures shown in FIG. 3 and the rod-shaped local structures can be arranged to pass through the secondary circuit modules {S(1,1),…,S(Nx,1)}, {S(1,2),…,S(Nx,2)}, … and {S(1,Ny),…,S(Nx,Ny)}. For ease of understanding, the rod-shaped local structures can be regarded as Figure 2 The channels of transistors associated with the secondary circuit blocks {S(1,1), ..., S(Nx,1)}, {S(1,2), ..., S(Nx,2)}, ..., and {S(1,Ny), ..., S(Nx,Ny)} in the illustrated architecture include channels of ordinary transistors used to implement the upper selector circuit MBLS(nx,ny) and the lower selector circuit MSLS(nx,ny), as well as channels of floating gate transistors used to implement the memory cells M(nx,ny,nz). According to some embodiments, the number of the plurality of rod-shaped local structures may be equal to the total number (Nx*Ny) of the secondary circuit blocks {S(1,1), ..., S(Nx,1)}, {S(1,2), ..., S(Nx,2)}, ..., and {S(1,Ny), ..., S(Nx,Ny)}, but the present invention is not limited thereto. For example, the arrangement of the plurality of memory cells may be varied, and the number of the plurality of rod-shaped local structures may be changed accordingly.

[0136] In addition, the three-dimensional NAND flash memory can be designed to have a plurality of pipe-shaped partial structures, and the plurality of pipe-shaped partial structures can be arranged to encircle the plurality of rod-shaped partial structures to form the respective components of the secondary circuit modules {S(1,1), ..., S(Nx,1)}, {S(1,2), ..., S(Nx,2)}, ... and {S(1,Ny), ..., S(Nx,Ny)}, in particular to form Figure 2The control gates and floating gates of the memory cells and the gates of the selector circuits in the illustrated architecture are shown. Memory cells {{M(1,1,1),M(2,1,1),…},{M(1,1,2),M(2,1,2),…},…} and word lines {WL(1,1),WL(1,2),…} are shown in FIG. Figure 3 In, and Figure 3 The tubular partial structure shown may indicate that some additional partial structures surround each of the plurality of rod-shaped partial structures, wherein the details of these additional partial structures will be further described in subsequent embodiments.

[0137] Figure 4 An embodiment of the present invention is shown Figure 2 Some implementation details of one of the plurality of memory cells of the three-dimensional NAND flash memory shown. Figure 4 As shown, the memory cell M(nx,ny,nz) may include a portion of one of the plurality of rod-shaped local structures, such as a rod segment Mch of the rod-shaped local structure corresponding to the secondary circuit module S(nx,ny), and may also include certain tubular local structures having the same axis of symmetry. For example, the upper side Md and lower side Ms of the rod segment Mch may serve as the drain and source of a floating gate transistor implementing the memory cell M(nx,ny,nx), and a first tubular local structure Mfg and a second tubular local structure Mcg of the tubular local structures may serve as the floating gate and control gate of the floating gate transistor. Other tubular local structures, such as the tubular local structure between the rod segment Mch and the first tubular local structure Mfg and the tubular local structure between the first tubular local structure Mfg and the second tubular local structure Mcg, may be implemented from one or more insulating materials.

[0138] According to some embodiments, Figure 2 Any of the plurality of selector circuits in the illustrated architecture may be modified by Figure 4 The structure shown in FIG. For example, the upper side Md and lower side Ms of the rod segment Mch can serve as the drain and source of a common transistor used to implement the selector circuit, while the second tubular partial structure Mcg among the tubular partial structures can serve as the gate of the common transistor, wherein the first tubular partial structure Mfg should be removed from the one or more insulating materials. Therefore, there is only one tubular partial structure between the rod segment Mch and the second tubular partial structure Mcg, but the present invention is not limited to this.

[0139] In the flash memory module 120, when a block of any of the flash memory chips 122-1 to 122-N functions as a single-level cell block, each of the multiple physical pages in the block corresponds to a logical page, i.e., each of the multiple memory cells in the page is configured to store only one bit, where one physical page may include all transistors controlled by a word line (e.g., memory cells M(1,1,Nz) to M(Nx,1,Nz) corresponding to word line WL(1,Nz) form a physical page). When a block of any of the flash memory chips 122-1 to 122-N functions as a multi-level cell block, each of the multiple physical pages in the block corresponds to two logical pages, i.e., each of the multiple memory cells in the page is configured to store two bits. When a block of any of the flash memory chips 122-1 to 122-N functions as a triple-level cell block, each of the multiple physical pages in the block corresponds to three logical pages, i.e., each of the multiple memory cells in the page is configured to store three bits. When a block of any of the flash memory chips 122 - 1 ˜ 122 -N serves as a four-level cell block, each of the physical pages in the block corresponds to four logical pages, ie, each of the memory cells of the page is configured to store four bits.

[0140] Figure 5 FIG. 1 is a schematic diagram of multiple states (programmed states) of a memory cell in the fourth-order cell block according to an embodiment of the present invention. Figure 5 As shown in FIG, each memory cell can have sixteen states, and each state represents a different combination of four bits (named as top bit, upper bit, middle bit and lower bit). Figure 5In the embodiment shown, when the memory cell is programmed to have state S0, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 1, 1); when the memory cell is programmed to have state S1, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 1, 0); when the memory cell is programmed to have state S2, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 0, 1, 0); when the memory cell is programmed to have state S3, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 0, 0 ,0); when the memory cell is programmed to have state S4, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1,0,0,1); when the memory cell is programmed to have state S5, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,0,1); when the memory cell is programmed to have state S6, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,0,0); when the memory cell is programmed to have state S7, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,1,0); When the memory cell is programmed to have state S8, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 1, 0); when the memory cell is programmed to have state S9, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 0, 0); when the memory cell is programmed to have state S10, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 0, 0); when the memory cell is programmed to have state S11, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 0, 1); The memory cell is programmed to have state S12, and the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 0, 1); when the memory cell is programmed to have state S13, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 1, 1); when the memory cell is programmed to have state S14, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 0, 1, 1); and when the memory cell is programmed to have state S15, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 0, 1, 1).

[0141] In the prior art, when the top bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply four read voltages VR5, VR10, VR12, and VR15 to read the memory cell. If the memory cell is conductive when the read voltage VR5 is applied, the top bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR5 is applied and the memory cell is conductive when the read voltage VR10 is applied, the top bit is determined to be "0"; if the memory cell is non-conductive when the read voltage VR10 is applied and the memory cell is conductive when the read voltage VR12 is applied, the top bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR12 is applied and the memory cell is conductive when the read voltage VR15 is applied, the top bit is determined to be "0"; and if the memory cell is non-conductive when the read voltage VR15 is applied, the top bit is determined to be "1." When the flash memory controller 110 needs to read the upper bit, the flash memory controller 110 can control the flash memory module 120 to apply three read voltages VR2, VR8, and VR14 to read the memory cell. If the memory cell is conductive when the read voltage VR2 is applied, the upper bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR2 is applied and the memory cell is conductive when the read voltage VR8 is applied, the upper bit is determined to be "0"; if the memory cell is non-conductive when the read voltage VR8 is applied and the memory cell is conductive when the read voltage VR14 is applied, the upper bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR14 is applied, the upper bit is determined to be "0". When the flash memory controller 110 needs to read the middle bit, the flash memory controller 110 can control the flash memory module 120 to apply four read voltages VR3, VR7, VR9, and VR13 to read the memory cell. If the memory cell is conductive when the read voltage VR3 is applied, the middle bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR3 is applied and the memory cell is conductive when the read voltage VR7 is applied, the middle bit is determined to be "0"; if the memory cell is non-conductive when the read voltage VR7 is applied and the memory cell is conductive when the read voltage VR9 is applied, the middle bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR9 is applied and the memory cell is conductive when the read voltage VR13 is applied, the middle bit is determined to be "0"; and if the memory cell is non-conductive when the read voltage VR13 is applied, the middle bit is determined to be "1".When the lower bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply four read voltages VR1, VR4, VR6, and VR11 to read the memory cell. If the memory cell is conductive when the read voltage VR1 is applied, the lower bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR1 is applied and the memory cell is conductive when the read voltage VR4 is applied, the lower bit is determined to be "0"; if the memory cell is non-conductive when the read voltage VR4 is applied and the memory cell is conductive when the read voltage VR6 is applied, the lower bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR6 is applied and the memory cell is conductive when the read voltage VR11 is applied, the lower bit is determined to be "0"; and if the memory cell is non-conductive when the read voltage VR11 is applied, the lower bit is determined to be "1".

[0142] It should be noted that Figure 5 The gray code shown is for illustrative purposes only and is not intended to limit the present invention. Any suitable gray code can be used in the memory device 100, and the read voltages used to determine the top bit, upper bit, middle bit, and lower bit can be changed accordingly.

[0143] The bit read from the memory cell using a portion of read voltages VR1-VR15 can be considered a sign bit. The sign bits obtained from multiple memory cells (e.g., four thousand (4K) memory cells) are processed by the derandomizer 138 and error correction is performed by the decoder 134 to generate decoded data. However, since the state intervals of the memory cells in the multi-level cell block are very small, these states may have significant variation due to read disturb, program disturb, or data retention issues that occur in the flash memory module 120, and the error correction operation may fail. To address this issue, the prior art applies additional read voltages to read the memory cells to obtain multiple soft bits to increase the success rate of the error correction operation. For example, if the decoder 134 is unable to decode the sign bits obtained from the memory cells, the flash memory controller 110 may control the flash memory module 120 to use additional read voltages to re-read the memory cells to obtain a first set of soft bits, and the decoder 134 may use a low-density parity-check code (LDPC) method to decode the sign bits using the first set of soft bits. For example, if the flash memory controller 110 attempts to read the top page of the block (i.e., the top bits of the memory cells), the flash memory controller 110 may control the flash memory module 120 to use additional read voltages (VR5-Δ), (VR10-Δ), (VR12-Δ), and (VR15-Δ) to obtain the first set of soft bits. If the decoder 134 still cannot decode, the flash memory controller 110 can control the flash memory module 120 to use additional read voltages (VR5+Δ), (VR10+Δ), (VR12+Δ), and (VR15+Δ) to re-read the multiple memory cells to obtain a second set of soft bits, and the decoder 134 can use the low-density parity-check code method to decode the multiple sign bits using the first set of soft bits and the second set of soft bits, etc.

[0144] Given the above, if flash memory controller 110 needs to read data from a fourth-level cell block in flash memory module 120, flash memory controller 110 may read the multiple memory cells and decode the data multiple times to obtain soft bits to successfully decode the data. Each time flash memory controller 110 reads the multiple memory cells, it must send a read command to flash memory module 120, and flash memory module 120 requires a read busy time to read the sign bit or soft bits. Therefore, the conventional read mechanism for high-density storage (such as a fourth-level cell block using 3D NAND flash memory technology) is not very efficient.

[0145] To solve the above problems, embodiments of the present invention disclose a reading mechanism and a decoding method to efficiently access the flash memory module 120 .

[0146] Figure 6 is a schematic diagram of a flash memory chip 600 according to an embodiment of the present invention, wherein the flash memory chip 600 may be Figure 1 Any one of the flash memory chips 122-1 to 122-N shown. Figure 6 As shown, the flash memory chip 600 includes two memory arrays 610 and 620, sense amplifiers 612, 614, 622 and 624, and peripheral circuits 632 and 634, wherein the memory arrays 610 and 620 include Figure 2 Memory cells, sense amplifiers 612 , 614 , 622 , and 624 are shown for reading data from memory arrays 610 and 620 , and peripheral circuits 632 and 634 include pads, associated control circuits, and other interface circuits.

[0147] Figure 7 FIG. 1 is a schematic diagram of a sense amplifier 700 according to a first embodiment of the present invention. Figure 7 In the embodiment, the sense amplifier 700 includes an operational amplifier 710, a voltage source 712, a control circuit 714, a counter 716 and a switch SW1. Figure 1 The memory cell M(1,1,Nz) corresponding to the bit line BL(1) and the word line WL(1,Nz) is shown. When the memory cell M(1,1,Nz) is to be read, the control circuit 714 is used to generate a read voltage VR to Figure 1 The memory cell M(1,1,Nz) is shown, while the upper selector circuit MBLS(1,1) and other memory cells M(1,1,1) to M(1,1,(Nz-1)) are controlled to be turned on.

[0148] For reference Figure 7 as well as Figure 8 , Figure 8The following is a timing diagram of some signals of the sense amplifier 700 according to one embodiment of the present invention. During the operation of the sense amplifier 700, the read voltage VR is initially equal to zero (i.e., the memory cell M(1,1,Nz) is disabled). The switch SW1 is controlled to connect the bit line BL(1) to the voltage source 712, and the voltage source 712 begins to charge the parasitic capacitor CBL so that the voltage VBL at one terminal of the parasitic capacitor CBL is equal to the voltage Vpre provided by the voltage source 712 at time T0. Then, at time T1, the switch SW1 is controlled to connect the bit line BL(1) to the negative terminal of the operational amplifier 710, and the control circuit 714 begins to generate a ramp signal serving as the read voltage VR to the word line WL(1,Nz) to control the memory cell M(1,1,Nz). The control circuit 714 also generates an enable signal CNT_EN to enable the counter 716 to start operating and provide an incremented count value CNT when the output signal Vout becomes high. For example, assuming that the memory cell M(1,1,Nz) stores data corresponding to state S8 (whose threshold voltage is approximately 3V), when the read voltage VR starts to increase from 0V to 3V, the read voltage VR is not high enough to enable the memory cell M(1,1,Nz), and the voltage VBL remains at the voltage Vpre. Since the voltage VBL / Vpre is greater than the reference voltage Vsen on the positive terminal of the operational amplifier 710, the output signal Vout generated by the operational amplifier 710 is equal to "0". When the read voltage VR is greater than the threshold voltage of the memory cell M(1,1,Nz) at time T2, the memory cell M(1,1,Nz) is enabled to generate a current I_cell to discharge the parasitic capacitance CBL, and the voltage VBL decreases. When the voltage VBL decreases and becomes lower than the reference voltage Vsen, the output signal Vout becomes "1" to trigger the counter 716 to output the current count value CNT. Figure 8 In the illustrated embodiment, if the memory cell M(1,1,Nz) stores data corresponding to the state S8, the count value CNT is approximately "28".

[0149] exist Figure 7 as well as Figure 8In the illustrated embodiment, because the slope, discharge time, and circuit delay of the read voltage VR are known, the count value CNT output by the counter 716 can accurately represent the threshold voltage of the memory cell M(1,1,Nz). Furthermore, if the counter 716 is a high-resolution counter, such as an 8-bit counter (i.e., the counter 716 operates at a higher frequency), the count value CNT can represent the sign bit and soft bit of the memory cell M(1,1,Nz). Therefore, compared to the prior art, which uses multiple read operations to obtain the sign bit and soft bit, the embodiment of the present invention can obtain the sign bit and soft bit with a single read instruction, significantly improving read efficiency. Furthermore, because the count value CNT output by the counter 716 can represent the threshold voltage of the memory cell M(1,1,Nz), the state of the memory cell M(1,1,Nz) can be determined. Therefore, the count value CNT carries far more information than the sign bit obtained in the prior art (i.e., the sign bit in the prior art cannot accurately indicate the state of the memory cell M(1,1,Nz)). Specifically, if the top bit of memory cell M(1,1,Nz) is to be read, the conventional flash memory module uses read voltages VR5, VR10, VR12, and VR15 to read memory cell M(1,1,Nz), while the flash memory module only sends the top bit to the flash memory controller. For example, if the conventional flash memory module outputs the top bit "1" (i.e., the sign bit) to the flash memory controller, the flash memory controller only knows that memory cell M(1,1,Nz) has one of the states S0-S4, S10-S11, and S15, but the flash memory controller cannot accurately determine which state memory cell M(1,1,Nz) is in.

[0150] It should be noted that although Figure 8 While the ramp signal is shown as serving as the read voltage VR, the present invention is not limited thereto. In other embodiments, the control circuit 714 can apply read voltages VR having different voltage levels to the memory cells M(1, 1, Nz) (i.e., the read voltages VR having different voltage levels can be considered as multiple read voltages). Each voltage level of the read voltage VR corresponds to a count value CNT. The read voltage VR can have any other suitable design. In one embodiment, the number of voltage levels of the read voltage VR (or the number of read voltages) is equal to or greater than the number of states of the memory cells M(1, 1, Nz).

[0151] In one embodiment, the sense amplifier 700 further includes Figure 9Mapping circuit 910 is shown. Mapping circuit 910 is used to convert the count value into eight bits of information indicating the threshold voltage or state of memory cell M(1,1,Nz), where four bits are the most significant bits (MSBs) and the remaining four bits are the least significant bits (LSBs). For example, a count value of "1" is mapped to eight bits of information (0,0,0,0,0,0,0,0), a count value of "2" is mapped to eight bits of information (0,0,0,0,0,0,0,1), a count value of "3" is mapped to eight bits of information (0,0,0,0,0,0,1,0), ..., a count value of "255" is mapped to eight bits of information (1,1,1,1,1,1,1,0), and a count value of "256" is mapped to eight bits of information (1,1,1,1,1,1,1,1). Figure 10 Schematic diagram of states S0 to S15 and corresponding most significant bits and least significant bits according to an embodiment of the present invention. Figure 10 In the illustrated embodiment, the most significant bits are used to indicate the state of memory cell M(1,1,Nz), i.e., the most significant bits (0,0,0,0) represent state S0, the most significant bits (0,0,0,1) represent state S1, the most significant bits (0,0,1,0) represent state S2, ..., the most significant bits (1,1,1,0) represent state S14, and the most significant bits (1,1,1,1) represent state S15. Furthermore, the range defined by the most significant bits is further divided into sixteen sub-ranges represented by the least significant bits, and the least significant bits can function as the soft bits described above.

[0152] In one embodiment, the flash memory module 120 can transmit the most significant bit and the least significant bit to the flash memory controller 110 in response to a read command when only one read command is received. Figure 11If the flash memory controller 110 wishes to read data from a page (e.g., a logical page), the flash memory controller 110 transmits a read command to the flash memory module 120, and the flash memory module 120 uses the aforementioned mechanism to read the memory cells of the page to generate the most significant bit and the least significant bit for each memory cell. Assuming that the page includes four sectors / chunks and each sector / chunk is an encoding / decoding unit, the flash memory module 120 can sequentially transmit the most significant bit of each memory cell in a first sector / chunk, the most significant bit of each memory cell in a second sector / chunk, the most significant bit of each memory cell in a third sector / chunk, and the most significant bit of each memory cell in a fourth sector / chunk to the flash memory controller 110 for subsequent de-randomization and decoding operations. After the MSBs of all memory cells in the page are transmitted to the flash memory controller 110, the flash memory module 120 begins to sequentially transmit the LSBs of each memory cell in the first sector / block, the LSBs of each memory cell in the second sector / block, the LSBs of each memory cell in the third sector / block, and the LSBs of each memory cell in the fourth sector / block to the flash memory controller 110 for subsequent de-randomization and decoding operations.

[0153] In the above embodiment, if the decoder 134 of the flash memory controller 110 can successfully decode the data using only the most significant bits of the plurality of memory cells of the page, the least significant bits of the plurality of memory cells may not be used for the decoding operation, or the flash memory controller 110 may notify the flash memory module 120 to stop transmitting the least significant bits.

[0154] In one embodiment, although the flash memory module 120 obtains the most significant bits and the least significant bits of the multiple memory cells in response to a read command from the flash memory controller 110, the flash memory module 120 does not automatically transmit the least significant bits of the multiple memory cells to the flash memory controller 110 until the flash memory controller 110 requests the least significant bits of the multiple memory cells (for example, when the flash memory controller 110 requests the least significant bits of the multiple memory cells, the flash memory module 120 transmits the least significant bits of the multiple memory cells to the flash memory controller 110).

[0155] Figure 12FIG1 is a flow chart of a method for accessing a flash memory module 120 according to an embodiment of the present invention. In step 1200, the process starts and the host device 50 and the memory device 100 are powered on. In step 1202, the flash memory controller 110 sends a read command to the flash memory module 120 and requests a page of data. In step 1204, the flash memory module 120 receives the read command and uses Figures 7 to 10 The read mechanism shown is used to read all memory cells of the page and obtain the most significant bit and the least significant bit of each memory cell. Assuming that the page has multiple blocks and each block is an encoding / decoding unit such as the encoding / decoding unit described above, the flash memory module 120 sequentially transmits the most significant bit of each memory cell in a first block, the most significant bit of each memory cell in a second block, ..., and the most significant bit of each memory cell in a final block to the flash memory controller 110. In step 1206, while sequentially receiving data from the flash memory module 120, the flash memory controller 110 determines whether the multiple numbers of multiple states of a portion of the memory cells are balanced or unbalanced to generate a determination result. If the determination result indicates that the multiple numbers of the multiple states of the portion of the memory cells are balanced, the process proceeds to step 1208. If the determination result indicates that the multiple numbers of the multiple states of the portion of the memory cells are unbalanced, the process proceeds to step 1210.

[0156] Specifically, since the most significant bit transmitted from the flash memory module 120 can be regarded as the state of the memory cell, the flash memory controller 110 can accumulate the number of states S0 to S15 during the process of sequentially receiving the most significant bits of the multiple memory cells. Ideally, since the data programmed into the flash memory module 120 is processed by the randomizer 136, the number of states S0 to S15 should be close to each other. For example, if the flash memory controller 110 receives the most significant bits of sixteen thousand (16K) memory cells from the flash memory module 120, the number of each of the states S0 to S15 of the sixteen thousand memory cells should be approximately "1000". If the difference between the numbers of these states is within a defined range, the numbers of these states are judged to be balanced; and if the difference between the numbers of these states is not within the defined range, the numbers of these states are judged to be unbalanced. For example, the flash memory controller 110 may establish Figure 13 The histogram shown in . Figure 13 As shown, ideally, states S0-S15 have similar numbers, and if the page encounters problems such as data retention or read disturbance, the multiple memory cells will have threshold value offset problems. Figure 13In the example shown, state S15 is shifted to other states such as S12 to S14 , so the sense amplifier (eg, sense amplifier 700 ) does not sense state S15 from any memory cell. This threshold shift phenomenon results in an unbalanced number of states.

[0157] If the flash memory controller 110 determines that the number of states of the memory cells of the portion are balanced, the process proceeds to step 1208 and the decoder 134 decodes the data using the most significant bits of the memory cells belonging to a group (i.e., hard decoding). If the flash memory controller 110 determines that the number of states of the memory cells of the portion are unbalanced, the process proceeds to step 1210 and the flash memory controller 110 sends a signal to trigger the flash memory module 120 to transmit the least significant bits of the memory cells. After reading the least significant bits of the memory cells from the flash memory module 120, in step 1214, the decoder 134 decodes the data using the most significant bits and the least significant bits of the memory cells belonging to a group (i.e., soft decoding).

[0158] In step 1212, it is determined whether the decoder 134 successfully decodes the data. If the decoder 134 successfully decodes the data, the process proceeds to step 1216 to end the read operation or start the next read operation. If the decoder 134 cannot decode the data, the process proceeds to step S1210 to send the signal to trigger the flash memory module 120 to send the least significant bits of the plurality of memory cells.

[0159] exist Figure 12 In the flowchart shown, if the multiple numbers of the multiple states of the portion of memory cells are determined to be balanced, the flash memory controller 110 can directly perform a hard decoding operation on the most significant bits of the plurality of memory cells, and the least significant bits of the plurality of memory cells temporarily stored in the flash memory module 120 will only be transmitted to the flash memory controller 110 if the hard decoding operation fails. Therefore, the present invention can avoid unnecessary data transmission, thereby saving bandwidth and power. Furthermore, if the multiple numbers of the multiple states of the portion of memory cells are determined to be unbalanced, the flash memory controller 110 can directly perform a soft decoding operation on the most significant bits and least significant bits of the plurality of memory cells without first performing the hard decoding operation, thereby avoiding wasting power and time on hard decoding operations with a high failure rate.

[0160] It should be noted that the details of the above-mentioned hard decoding operation and soft decoding operation are well known to those skilled in the art, and the detailed steps of the above-mentioned hard decoding operation and soft decoding operation are not the subject of the present invention and will not be described in detail.

[0161] Figure 14 FIG1 is a flow chart of a method for accessing a flash memory module 120 according to another embodiment of the present invention. In step 1400, the process starts and the host device 50 and the memory device 100 are powered on. In step 1402, the flash memory controller 110 sends a read command to the flash memory module 120 and requests a page of data. In step 1404, the flash memory module 120 receives the read command and uses Figures 7 to 10 The read mechanism shown is used to read all memory cells of the page and obtain multiple bits of information of each memory cell (such as the most significant bit and the least significant bit of each memory cell). Assuming that the page has multiple blocks and each block is an encoding / decoding unit such as the encoding / decoding unit mentioned above, refer to Figure 15 The flash memory module 120 sequentially transmits the most significant bit and the least significant bit of each memory cell in a first block, the most significant bit and the least significant bit of each memory cell in a second block, ..., and the most significant bit and the least significant bit of each memory cell in a last block to the flash memory controller 110. Upon receiving these blocks from the flash memory module 120, the control logic circuit 114 begins to construct a distribution of states S0-S15 (e.g., SS1-SS256) in step 1406. Figure 16 , which shows the state construction according to an embodiment of the present invention. Figure 16 In the embodiment shown, the horizontal axis shows sub-states SS1 to SS256 (or Figure 10 , wherein each of sub-states SS1-SS256 corresponds to one of a plurality of combinations of four most significant bits and four least significant bits, and sub-states SS1-SS16 belong to state S0, sub-states SS17-SS32 belong to state S1, sub-states SS33-SS48 belong to state S2, ..., and sub-states SS241-SS256 belong to state S15, and the vertical axis shows the number of each of sub-states SS1-SS256. After the number of sub-states SS1-SS256 is accumulated and the number of most significant bits and least significant bits of the plurality of memory cells received in a memory unit (e.g., a page) increases, a plurality of peaks and valleys gradually appear.

[0162] In step 1408, after the plurality of peaks and valleys occur (note that only a portion of the chunks may be received or all of the chunks may be received), the control logic circuit 114 determines a plurality of valley heights of the plurality of valleys, wherein the valley height (e.g., any of the plurality of valley heights described above) is the number of one of the plurality of combinations of the four most significant bits and the four least significant bits in the received data (e.g., Figure 16Symbols VH1 and VH13 are shown. Symbol VH1 can be mapped to a sub-state, such as SS17. The threshold voltage distribution of the plurality of memory cells can be plotted based on the number of sub-states, where the plurality of valleys represent relatively low-numbered sub-states, such as SS17 or SS18, and the plurality of peaks represent relatively high-numbered sub-states, such as SS209. In step 1410, control logic circuit 114 determines whether any of the plurality of valley heights is greater than a threshold value TH. If none of the plurality of valley heights is greater than the threshold value TH, the process proceeds to step 1412; otherwise, the process proceeds to step 1416.

[0163] In step 1412, the control logic circuit 114 de-maps the most significant bits of the received memory cells to obtain the corresponding sign bits. Figure 5 Taking the top bit as an example, if the four most significant bits indicate that the memory cell has one of states S0-S4, S10-S11, and S15, a sign bit of "1" is output as a demapping result. If the four most significant bits indicate that the memory cell has one of states S5-S9 and S12-S14, a sign bit of "0" is output as a demapping result. After determining the sign bits of the memory cells of a block, the decoder 134 decodes the data using the sign bits of the memory cells of the block (i.e., hard decoding). In step 1414, it is determined whether the decoder 134 successfully decoded the data. If the decoder 134 successfully decoded the data, the process proceeds to step 1428 to end the read operation or start the next read operation. If the decoder 134 cannot decode the data, the process proceeds to step 1416.

[0164] In step 1416 , the decoder 134 uses a log-likelihood ratio (LLR) table to obtain a log-likelihood ratio value for each of the eight bits of information of the plurality of memory cells (ie, the four most significant bits and the four least significant bits of each memory cell).

[0165] In step 1418, the decoder 134 decodes the data using the multiple log-likelihood ratio values corresponding to the multiple memory cells belonging to the group of blocks (i.e., soft decoding). In step 1420, it is determined whether the decoder 134 successfully decoded the data. If the decoder 134 successfully decoded the data, the process proceeds to step 1426. If the decoder 134 was unable to decode the data, the process proceeds to step 1422.

[0166] In step 1422, it can be determined whether a decoding cycle number has reached a maximum decoding cycle number Tmax. If this decoding cycle number has reached the maximum decoding cycle number Tmax, the process enters step 1428 to end the reading operation or start the next reading operation; if this decoding cycle number has not reached the maximum decoding cycle number Tmax, the process enters step 1424.

[0167] In step 1424, the decoder 134 updates the multiple log-likelihood ratio values according to the received eight-bit information of the multiple memory cells. In particular, the decoder 134 can update the multiple log-likelihood ratio values according to the eight-bit information of the multiple memory cells corresponding to the adjacent blocks that have been successfully decoded. Figure 5 Taking the Gray code shown as an example, the updated log-likelihood ratio values for the top bit, upper bit, middle bit, and lower bit can be obtained by the following calculation.

[0168]

[0169]

[0170]

[0171]

[0172] “P1” is the probability value of the logical value “1”, “P0” is the probability value of the logical value “0”, PV s (R i ) is s=0-15 (i.e., sixteen states) and i=0-255 (i.e., 8 bits of information and 256 sub-states).

[0173] In detail, Figure 17 According to an embodiment of the present invention, the threshold voltage distribution is shown, wherein the threshold voltage distribution is from Figure 16 The graph shown is obtained (e.g., an envelope similar to a histogram). Figure 16 as well as Figure 17 In the illustrated embodiment, since state S15 is shifted to other states such as S12-S14, the state boundaries of states S11-S15 need to be adjusted, and multiple log-likelihood ratio values are updated for the new probability values of these states. Furthermore, since those skilled in the art already understand how to use these multiple log-likelihood ratio values in the soft decoding process and log-likelihood ratio calculation, and the present embodiment focuses on establishing the threshold voltage distribution and updating the log-likelihood ratio table during the decoding process, the detailed log-likelihood ratio calculation is not further described here.

[0174] After the multiple log-likelihood ratio values are updated in step 1424, the process returns to step 1418, and the decoder 134 decodes the data by using the updated log-likelihood ratio values, and the loop from steps 1418 to 1424 continues until the decoding operation is successful or the number of decoding cycles reaches the maximum number of decoding cycles Tmax.

[0175] In step 1426, the decoder 134 updates the log-likelihood ratio table according to the received eight-bit information of the plurality of memory cells. In particular, the decoder 134 can update the plurality of log-likelihood ratio values according to the eight-bit information of the plurality of memory cells corresponding to the successfully decoded current block and / or adjacent blocks. The plurality of log-likelihood ratio values in the log-likelihood ratio table can be updated according to Figure 17 The threshold voltage distribution is updated as shown, and the updated log-likelihood ratio table can be used to decode the next chunk in step 1416 .

[0176] In the embodiments shown in Figures 14-17, if the determination result is that none of the valley heights is greater than the threshold value TH, the flash memory controller 10 can directly perform a hard decoding operation on the sign bits of the multiple memory cells. If the determination result is that any of the valley heights is greater than the threshold value TH, the flash memory controller 110 can directly perform a soft decoding operation on the most significant bit and the least significant bit of the multiple memory cells without first performing a hard decoding operation, thereby avoiding wasting power and time on hard decoding operations with a higher failure rate. In addition, because the eight bits of information obtained from the flash memory module 120 can be used to establish the threshold voltage distribution of the multiple memory cells, the multiple log-likelihood ratio values can be updated based on the threshold voltage distribution when the decoder 134 decodes the block, and the log-likelihood ratio table can be updated during the decoding process for use by the next block (possibly on the same page). Therefore, the decoding success rate during the decoding process can be significantly improved. It should be noted that since the flash memory module in the prior art only sends the sign bit and the soft bit to the flash memory controller, and the threshold voltage distribution cannot be established by using only the sign bit and the soft bit, the prior art cannot establish the threshold voltage distribution or identify the valley value of the distribution during the decoding process.

[0177] Figure 18 FIG. 1 is a schematic diagram of a sense amplifier 1800 according to a second embodiment of the present invention. Figure 18 In the embodiment, the sense amplifier 1800 includes an operational amplifier 1810, a voltage source 1812, a digital-to-analog converter 1814, and a switch SW1. Figure 1The memory cell M(1,1,Nz) corresponding to the bit line BL(1) and the word line WL(1,Nz) is shown. When the memory cell M(1,1,Nz) is to be read, the analog-to-digital converter 1814 is used to generate a read voltage VR to Figure 1 The memory cell M(1,1,Nz) is shown, while the other memory cells M(1,1,1) to M(1,1,(Nz-1)) are controlled to be turned on.

[0178] For reference Figure 18 as well as Figure 19 , Figure 19 The following is a timing diagram of certain signals of the sense amplifier 1800 according to an embodiment of the present invention. During the operation of the sense amplifier 1800, the digital-to-analog converter 1814 is initially disabled and the read voltage VR is initially equal to zero (i.e., the memory cell M(1,1,Nz) is disabled). The switch SW1 is controlled to connect the bit line BL(1) to the voltage source 1812, and the voltage source 1812 begins to charge the parasitic capacitor CBL so that the voltage VBL at one terminal of the parasitic capacitor CBL is equal to the voltage Vpre provided by the voltage source 1812 at time T0. Then, at time T1, the switch SW1 is controlled to connect the bit line BL(1) to the negative terminal of the operational amplifier 1810, and the digital-to-analog converter 1814 begins to generate a ramp signal serving as the read voltage VR to the word line WL(1,Nz) according to an enable signal DAC_EN to control the memory cell M(1,1,Nz). For example, assuming that memory cell M(1,1,Nz) stores data corresponding to state S8 (its threshold voltage is approximately 3V), when read voltage VR begins to increase from 0V to 3V, read voltage VR is not high enough to enable memory cell M(1,1,Nz). Voltage VBL remains at voltage Vpre. Since voltage VBL / Vpre is greater than reference voltage Vsen at the positive terminal of operational amplifier 1810, output signal Vout generated by operational amplifier 1810 is equal to "0." When read voltage VR exceeds the threshold voltage of memory cell M(1,1,Nz) at time T2, memory cell M(1,1,Nz) is enabled to generate a current I_cell to discharge parasitic capacitance CBL, causing voltage VBL to decrease. When voltage VBL decreases and becomes lower than reference voltage Vsen, output signal Vout becomes "1," triggering digital-to-analog converter 1814 to output a digital value corresponding to the current read voltage VR.

[0179] It should be noted that although Figure 19While the ramp signal is shown as serving as the read voltage VR, the present invention is not limited thereto. In other embodiments, the digital-to-analog converter 1814 can apply read voltages VR having different voltage levels to the memory cells M(1, 1, Nz) (i.e., the read voltages VR having different voltage levels can be considered as multiple read voltages). The read voltage VR can have any other suitable design. In one embodiment, the number of voltage levels (or the number of read voltages) of the read voltage VR is equal to or greater than the number of states of the memory cells M(1, 1, Nz).

[0180] exist Figure 18 and Figure 19 In the embodiment shown, the digital value output by the digital-to-analog converter 1814 can represent the threshold voltage of the memory cell M(1,1,Nz) (i.e., the analog voltage corresponding to the digital value output by the digital-to-analog converter 1814 is very close to the threshold voltage of the memory cell M(1,1,Nz)), so the digital value can be effectively used in subsequent decoding operations. In addition, assuming that the digital-to-analog converter 1814 is an 8-bit digital-to-analog converter, the digital value can have Figure 10 The four most significant bits and four least significant bits are shown, and the flash memory module 120 can directly transmit the digital value (i.e., multiple most significant bits and multiple least significant bits) to the flash memory controller 110 using a read command. The timing diagram of transmitting the read command and the multiple most significant bits / least significant bits can be referred to Figure 11 In addition, due to circuit delay and discharge time, the digital value output by the digital-to-analog converter 1814 may be slightly adjusted so that the adjusted digital value is closer to the threshold voltage of the memory cell M(1,1,Nz).

[0181] The above embodiment uses a quadratic cell block as an example. However, the above reading mechanism can also be applied to quadratic cell blocks, multi-level cell blocks, and single-level cell blocks. Those skilled in the art will understand how to use the above steps to read memory cells in quadratic cell blocks, multi-level cell blocks, and single-level cell blocks. Further details are not detailed here.

[0182] In summary, in the flash memory controller and flash memory module of the present invention, the flash memory module can output multi-bit information of each memory cell to the flash memory controller in response to a read instruction, and the multi-bit information of each memory cell can indicate the critical voltage or state of the memory cell. Therefore, the reading efficiency can be greatly improved. In addition, in the decoding operation of the flash memory controller, the decoder can determine whether the multiple numbers of the multiple states are balanced or unbalanced, or whether the height of a valley of the critical voltage distribution is greater than a critical value, so as to adopt different decoding mechanisms to improve decoding efficiency. In addition, since the critical voltage distribution can be established in the decoding process, the multiple log-likelihood ratio values and / or the log-likelihood ratio table can be updated to increase the success rate of the decoder.

[0183] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A flash memory controller, wherein the flash memory controller is coupled to a flash memory module, the flash memory module including at least one flash memory chip, each flash memory chip including a plurality of blocks, each block including a plurality of pages, the flash memory controller being characterized by comprising: a memory for storing a program code; as well as a microprocessor, configured to execute the program code to access the flash memory module through a control logic circuit; After the microprocessor sends a read instruction to the flash memory module to request data on at least one memory unit, the control logic circuit receives multi-bit information of multiple memory cells of the at least one memory unit from the flash memory module, wherein each memory cell of the at least one memory unit is used to store multiple bits, each memory cell has multiple states, the multiple states are used to indicate different combinations of the multiple bits, each state is divided into multiple sub-states, and the multi-bit information of each memory cell is used to indicate which sub-state the memory cell has; and the control logic circuit analyzes the multi-bit information of the multiple memory cells to obtain a critical voltage distribution of the multiple memory cells for determining whether a decoder in the control logic circuit adopts a first decoding method or a second decoding method for decoding.

2. The flash memory controller according to claim 1, wherein: The control logic circuit analyzes the multi-bit information of the memory cells to obtain a plurality of valley heights of the threshold voltage distribution of the memory cells for determining whether the decoder in the control logic circuit adopts the first decoding method or the second decoding method for decoding.

3. The flash memory controller according to claim 2, wherein: The first decoding method is a hard decoding method, and the second decoding method is a soft decoding method.

4. A method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, the method comprising: Sending a read command to the flash memory module to request data on at least one memory cell; receiving, from the flash memory module, multi-bit information of a plurality of memory cells of the at least one memory unit, wherein each memory cell of the at least one memory unit is used to store a plurality of bits, each memory cell has a plurality of states, the plurality of states are used to indicate different combinations of the plurality of bits, each state is divided into a plurality of sub-states, and the multi-bit information of each memory cell is used to indicate which sub-state the memory cell has; and The multi-bit information of the memory cells is analyzed to obtain a threshold voltage distribution of the memory cells for determining whether a decoder adopts a first decoding method or a second decoding method for decoding.

5. The method according to claim 4, wherein The step of analyzing the multi-bit information of the plurality of memory cells to obtain a plurality of valley heights of the threshold voltage distribution of the plurality of memory cells for determining whether the decoder adopts the first decoding method or the second decoding method for decoding includes: The multi-bit information of the plurality of memory cells is analyzed to obtain a plurality of valley heights of the threshold voltage distribution of the plurality of memory cells for determining whether the decoder adopts the first decoding method or the second decoding method for decoding.

6. The method according to claim 4, wherein The first decoding method is a hard decoding method, and the second decoding method is a soft decoding method.

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