Anti-backflow interface circuit

Abstract

The present invention provides an anti-backflow interface circuit, including a power supply module, an anti-backflow logic generation module, a gate tracking module, an output driver transistor and a chip working circuit. After the chip enters the power saving mode, the anti-backflow logic generation module transmits a logic high level to the gate tracking module; after receiving the logic high level, the gate tracking module outputs a first high level to the control end of the output driver transistor; after receiving the first high level, the control end of the output driver transistor disconnects the current channel between the power supply module and the chip working circuit. The anti-backflow function is realized, the chip is prevented from being woken up by mistake, the stability of the chip working state is ensured, and the safety and service life of the chip power supply are improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to an interface circuit for preventing backflow. Background Art

[0002] When the chip is in a low-power mode, such as when the chip enters sleep mode or power saving mode, the voltage at the IO end of the general-purpose input / output (GPIO) power supply is 0. At this time, if the GPIO peripheral interface is still equipped with an IO interface with power, due to the potential difference between the periphery and the interior of the GPIO, the voltage or current of the peripheral IO interface will flow back from the GPIO to the chip power supply, thereby waking up the chip by mistake.

[0003] The Chinese patent with publication number CN 205213119 U discloses an infrared lamp driving circuit that can be used for iris recognition fill light and distance sensing, which includes an application processor of a mobile terminal, a first power management chip for cooperating with the iris recognition module of the mobile terminal, a second power management chip for cooperating with the distance sensing module of the mobile terminal, a power supply unit, and an infrared lamp; the enable terminals of the first and second power management chips are connected to the GPIO interface of the application processor; the voltage of the first and second power management chips is connected to the power supply unit; the voltage output terminals of the first and second power management chips are connected to the infrared lamp; and the voltage output terminal of the second power management chip is connected to an anti-backflow circuit. The utility model adopts a diode or a transistor plus a pull-down resistor to achieve anti-backflow, but the anti-backflow is only used to protect the first power management chip that outputs a small current, and does not have the function of anti-backflow protection for the chip in the dormant state.

[0004] Therefore, it is necessary to provide an interface circuit for preventing backflow to solve the above problems in the prior art. Summary of the invention

[0005] The purpose of the present invention is to provide an anti-backflow interface circuit to solve the problem of backflow occurring in a chip in a low power consumption mode.

[0006] To achieve the above-mentioned purpose, the anti-backflow interface circuit of the present invention includes a power supply module, an anti-backflow logic generation module, a gate tracking module, an output driver transistor and a chip working circuit, wherein the power supply module is connected to the anti-backflow logic generation module and the gate tracking module, the anti-backflow logic generation module is connected to the gate tracking module, the source of the output driver transistor is connected to the power supply module, the drain of the output driver transistor is connected to the chip working circuit, and the control end of the output driver transistor is connected to the output end of the gate tracking module;

[0007] After the chip enters the power saving mode, the anti-backflow logic generation module transmits a logic high level to the gate tracking module;

[0008] After receiving the logic high level, the gate tracking module outputs a first high level to the control terminal of the output driver transistor;

[0009] After receiving the first high level, the control end of the output driver transistor disconnects the current channel between the power supply module and the chip working circuit.

[0010] The beneficial effects of the anti-backflow interface circuit of the present invention are:

[0011] After the chip enters the power saving mode, the anti-backflow logic generation module transmits a logic high level to the gate tracking module, and after the gate tracking module receives the logic high level, it outputs a first high level to the control end of the output driver transistor, and after the output driver transistor receives the first high level, it disconnects the current channel between the power supply module and the chip working circuit, thereby achieving the disconnection of the current channel between the power supply module and the chip working circuit after the chip enters the power saving mode, thereby avoiding the backflow of the voltage or current of the GPIO power supply, realizing the anti-backflow function of the universal input and output interface, avoiding the chip from being woken up by mistake, ensuring the stability of the chip working state, and improving the safety and service life of the chip power supply.

[0012] Optionally, the power supply module includes a battery, an IO power supply and an external power supply, the battery is connected to the IO power supply, the IO power supply is connected to the source of the output driver stage transistor, and the external power supply is connected to the drain of the output driver stage transistor through a backflow terminal;

[0013] The anti-backflow logic generation module includes a first PMOS tube and a first NMOS tube, the source of the first PMOS tube is connected to the gate tracking module and the backflow end, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the gate of the first PMOS tube is connected to the gate of the first NMOS tube and the IO power supply, and the source of the first NMOS tube is grounded;

[0014] When the chip enters the power saving mode, the IO power supply output voltage is 0, the external power supply generates the logic high level and transmits the logic high level to the source of the first PMOS tube through the backflow terminal.

[0015] Optionally, the anti-backflow interface circuit further includes a second NMOS tube, the gate of the second NMOS tube is connected to the drain of the first PMOS tube, the drain of the second NMOS tube is connected to the chip working circuit, and the source of the second NMOS tube is grounded;

[0016] When the chip enters the power saving mode, the IO power supply output voltage is 0, the source and drain of the first PMOS tube are turned on, and the drain of the first PMOS tube outputs a second high level to the gate of the second NMOS tube;

[0017] After the gate of the second NMOS tube receives the second high level, the source and drain are turned on and the current is output to the ground. Its beneficial effect is that when the chip enters the power saving mode, the IO power supply output voltage is 0, the source and drain of the first PMOS tube are turned on, and the drain of the first PMOS tube outputs the second high level to the gate of the second NMOS tube, and after the gate of the second NMOS tube receives the second high level, the source and drain are turned on and the current is output to the ground, thereby avoiding the backflow of current, thereby further realizing the anti-backflow function of the circuit.

[0018] Optionally, the gate tracking module includes a second PMOS tube, the source of the second PMOS tube is connected to the source of the first PMOS tube to receive the logic high level, the gate of the second PMOS tube is connected to the IO power supply, and the drain of the second PMOS tube is connected to the control end of the output driver stage transistor.

[0019] Optionally, when the chip enters the power saving mode, the IO power supply output voltage is 0, the source and drain of the second PMOS tube are turned on, so that the drain of the second PMOS tube outputs the first high level to the control end of the output driver transistor;

[0020] After the control end of the output driver transistor receives the first high level, the source and drain are disconnected, thereby disconnecting the current channel between the power supply module and the chip working circuit. Its beneficial effect is that after the chip enters the power saving mode, the IO power supply output voltage is 0, so that the source and drain of the second PMOS tube are turned on, and the drain of the second PMOS tube outputs the first high level to the control end of the output driver transistor, so that the source and drain of the output driver transistor are disconnected, thereby disconnecting the current channel between the power supply module and the chip working circuit, and realizing the anti-backflow function.

[0021] Optionally, the anti-backflow interface circuit further includes a third NMOS tube, the gate of the third NMOS tube is connected to the drain of the second NMOS tube, the drain of the third NMOS tube is connected to the drain of the output driver stage transistor, and the source of the third NMOS tube is grounded;

[0022] The source and substrate of the second NMOS tube are short-circuited, and the source and substrate of the third NMOS tube are short-circuited.

[0023] Optionally, the substrate of the first PMOS tube, the substrate of the second PMOS tube and the substrate of the output driver transistor are all connected to the battery. Its beneficial effect is that the substrate of the conventional driver PMOS tube is connected to the source, and when the source is floating and the level of the external power supply is high, a backflow phenomenon will occur. However, the substrate of the output driver transistor of the present invention is connected to the battery, and when the chip enters the power saving mode, the voltage will not flow back to the substrate of the output driver transistor. Compared with the conventional anti-backflow circuit, the design of the present invention greatly simplifies the design complexity and reduces the area requirement of the chip.

[0024] Optionally, the anti-backflow interface circuit also includes an electrostatic discharge protection module, and the electrostatic discharge protection module includes a battery electrostatic discharge unit and an IO power supply electrostatic discharge unit, the battery electrostatic discharge unit is connected to the battery, and the IO power supply electrostatic discharge unit is connected to the IO power supply.

[0025] Optionally, the chip working circuit includes a switch and a plurality of first inverters and a plurality of second inverters, the plurality of first inverters are connected in series in sequence, and an output end of one of the first inverters is connected to a first end of the switch, a second end of the switch is connected to a control end of the output driving stage transistor, and a first end of the switch is connected to the IO power supply;

[0026] A plurality of the second inverters are connected in series in sequence, and an output end of one of the second inverters is connected to a drain of the second NMOS tube and a gate of the third NMOS tube;

[0027] The drain of the second PMOS tube is connected to the second end of the switch.

[0028] Optionally, the first end of the switch is connected to the gate of the first PMOS tube and the gate of the first NMOS tube;

[0029] When the chip enters the power saving mode, the first PMOS tube and the first NMOS tube generate a switch control signal to disconnect the switch. Its beneficial effect is that the switch is disconnected by generating a switch control signal through the gate of the first PMOS tube and the first NMOS tube, thereby preventing the gate tracking module from pulling up the control terminal of the output driver stage transistor and causing the gate high level to continue to flow back to the previous stage, blocking the backflow path, thereby further realizing the backflow prevention and enhancing the backflow prevention effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A structural block diagram of an interface circuit for preventing backflow according to an embodiment of the present invention;

[0031] Figure 2 The circuit diagram of the interface circuit for preventing backflow according to an embodiment of the present invention is shown in FIG. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0033] In view of the problems existing in the prior art, an embodiment of the present invention provides an interface circuit for preventing backflow. Figure 1 The figure is a structural block diagram of an interface circuit for preventing backflow according to an embodiment of the present invention.

[0034] Reference Figure 1 The anti-backflow interface circuit of the present invention comprises a power supply module 3, an anti-backflow logic generation module 1, a gate tracking module 2, an output driver transistor 4 and a chip working circuit 5, wherein the power supply module 3 is connected to the anti-backflow logic generation module 1 and the gate tracking module 2 respectively, the anti-backflow logic generation module 1 is connected to the gate tracking module 2, the source of the output driver transistor 4 is connected to the power supply module 3, the drain of the output driver transistor 4 is connected to the chip working circuit 5, and the control end of the output driver transistor 4 is connected to the output end of the gate tracking module 2;

[0035] The anti-backflow logic generation module 1 is used to generate a logic high level after the chip enters the power saving mode, and transmit the logic high level to the gate tracking module 2;

[0036] After receiving the logic high level, the gate tracking module 2 outputs a first high level to the control terminal of the output driving stage transistor 4;

[0037] After receiving the first high level, the control end of the output driving stage transistor 4 disconnects the current channel between the power supply module 3 and the chip working circuit 5 .

[0038] The advantage of the anti-backflow interface circuit of the present invention is that: the logic high level is transmitted to the gate tracking module 2 through the anti-backflow logic generation module 1 after the chip enters the power saving mode, and the gate tracking module 2 outputs the first high level to the control end of the output driver transistor 4 after receiving the logic high level, and the output driver transistor 4 disconnects the current channel between the power supply module 3 and the chip working circuit 5 after receiving the first high level, thereby realizing that after the chip enters the power saving mode, the current channel between the power supply module 3 and the chip working circuit is disconnected, thereby avoiding the backflow of the voltage or current of the GPIO power supply, realizing the anti-backflow function of the universal input and output interface, avoiding the chip from being woken up by mistake, ensuring the stability of the chip working state, and improving the safety and service life of the chip power supply.

[0039] In some embodiments, the output driver stage transistor 4 is a PMOS transistor, and the control end of the output driver stage transistor 4 refers to the gate of the PMOS transistor.

[0040] In some embodiments, the anti-backflow interface circuit of the present invention can not only be used for GPIO anti-backflow, but also be compatible with the segment code LCD liquid crystal screen interface, that is, it can be used for anti-backflow of the segment code LCD liquid crystal screen interface, and has high compatibility.

[0041] Figure 2 The circuit diagram of the interface circuit for preventing backflow according to an embodiment of the present invention is shown in FIG.

[0042] As an optional embodiment of the present invention, refer to Figure 1 and Figure 2 , the power supply module 3 includes a battery 31, an IO power supply 32 and an external power supply 33, the battery 31 is connected to the IO power supply 32; the IO power supply 32 is connected to the source of the output driver transistor 4, and the external power supply 33 is connected to the drain of the output driver transistor 4 through the reverse end PAD;

[0043] The anti-backflow logic generation module 1 includes a first PMOS tube 11 and a first NMOS tube 12, the source of the first PMOS tube 11 is connected to the gate tracking module 2 and the external power supply 33, the drain of the first PMOS tube 11 is connected to the drain of the first NMOS tube 12, the gate of the first PMOS tube 11 is connected to the gate of the first NMOS tube 12 and the IO power supply 32, and the source of the first NMOS tube 12 is grounded;

[0044] When the chip enters the power saving mode, the output voltage of the IO power supply 32 is 0, the external power supply 33 generates the logic high level and transmits the logic high level to the source of the first PMOS tube 11 through the backflow terminal PAD. The advantage is that when the chip enters the power saving mode, the output voltage of the IO power supply 32 is 0, the external power supply 33 generates the logic high level and transmits it to the source of the first PMOS tube 11, thereby realizing accurate judgment of the working state of the power saving mode of the chip.

[0045] As an optional embodiment of the present invention, refer to Figure 1 and Figure 2 , the anti-backflow interface circuit also includes a second NMOS tube 7, the gate of the second NMOS tube 7 is connected to the drain of the first PMOS tube 11, the drain of the second NMOS tube 7 is connected to the chip working circuit 5, and the source of the second NMOS tube 7 is grounded;

[0046] When the chip enters the power saving mode, the output voltage of the IO power supply 32 is 0, the source and drain of the first PMOS tube 11 are turned on, and the drain of the first PMOS tube 11 outputs a second high level to the gate of the second NMOS tube 7;

[0047] After the gate of the second NMOS tube 7 receives the second high level, the source and drain of the second NMOS tube 7 are turned on and output current to the ground. Its advantage is that when the chip enters the power saving mode, the output voltage of the IO power supply 32 is 0, the source and drain of the first PMOS tube 11 are turned on, and the drain of the first PMOS tube 11 outputs the second high level to the gate of the second NMOS tube 7, and after the gate of the second NMOS tube 7 receives the second high level, the source and drain of the second NMOS tube 7 are turned on and output current to the ground, thereby avoiding the backflow of current, thereby further realizing the anti-backflow function of the circuit.

[0048] As an optional embodiment of the present invention, refer to Figure 1 and Figure 2 The gate tracking module 2 includes a second PMOS tube 21, the source of the second PMOS tube 21 is connected to the source of the first PMOS tube 11 to receive the logic high level, the gate of the second PMOS tube 21 is connected to the IO power supply 32, and the drain of the second PMOS tube 21 is connected to the control end of the output driving stage transistor 4.

[0049] As an optional implementation of the present invention, when the chip enters the power saving mode, the output voltage of the IO power supply 32 is 0, the source and drain of the second PMOS tube 21 are turned on, so that the drain of the second PMOS tube 21 outputs the first high level to the control end of the output driver transistor 4;

[0050] After the control end of the output driver transistor 4 receives the first high level, the source and drain of the output driver transistor 4 are disconnected, thereby disconnecting the current channel between the power supply module 3 and the chip working circuit 5. Its advantage is that after the chip enters the power saving mode, the output voltage of the IO power supply 32 is 0, so that the source and drain of the second PMOS tube 21 are turned on, and the drain of the second PMOS tube 21 outputs the first high level to the control end of the output driver transistor 4, so that the source and drain of the output driver transistor 4 are disconnected, thereby disconnecting the current channel between the power supply module 3 and the chip working circuit 5, and realizing the anti-backflow function.

[0051] As an optional embodiment of the present invention, refer to Figure 1 and Figure 2 , the anti-backflow interface circuit also includes a third NMOS tube 8, the gate of the third NMOS tube 8 is connected to the drain of the second NMOS tube 7, the drain of the third NMOS tube 8 is connected to the drain of the output driving stage transistor 4, and the source of the third NMOS tube 8 is grounded;

[0052] The source and substrate of the second NMOS transistor 7 are short-circuited, and the source and substrate of the third NMOS transistor 8 are short-circuited.

[0053] As an optional embodiment of the present invention, refer to Figure 1 and Figure 2 The substrate of the first PMOS tube 11 , the substrate of the second PMOS tube 21 and the substrate of the output driving stage transistor 4 are all connected to the battery 31 .

[0054] In the conventional driver-stage PMOS tube, the substrate is connected to the source. When the source of the driver-stage PMOS tube is floating and the level of the external power supply is high, that is, the level of the external power supply is higher than the internal level of the chip, a backflow phenomenon will occur. However, the substrate of the output driver-stage transistor 4 of the present invention is connected to the battery 31. When the chip enters the power saving mode, the backflow voltage will not flow back to the substrate of the output driver-stage transistor 4. Compared with the conventional anti-backflow circuit, the design of the present invention greatly simplifies the design complexity and reduces the area requirement of the chip.

[0055] As an optional embodiment of the present invention, refer to Figure 2The anti-backflow interface circuit also includes an electrostatic discharge protection module 6, which includes a battery electrostatic discharge unit 61 and an IO power supply electrostatic discharge unit 62. The battery electrostatic discharge unit 61 is connected to the battery 31, and the IO power supply electrostatic discharge unit 62 is connected to the IO power supply 32.

[0056] It can be explained that the electrostatic discharge (ESD) protection module ensures rail-to-rail ESD protection of the GPIO port. Since the electrostatic discharge protection module 6 is a conventional technology in the art, it will not be described in detail here.

[0057] As an optional embodiment of the present invention, refer to Figure 1 and Figure 2 , the chip working circuit 5 includes a switch 51, a plurality of first inverters 52 and a plurality of second inverters 53, the plurality of first inverters 52 are connected in series in sequence, and the output end of one of the first inverters 52 is connected to the first end of the switch 51, the second end of the switch 51 is connected to the control end of the output driving stage transistor 4, and the first end of the switch 51 is connected to the IO power supply 32;

[0058] A plurality of the second inverters 53 are connected in series in sequence, and an output end of one of the second inverters 53 is connected to the drain of the second NMOS transistor 7 and the gate of the third NMOS transistor 8;

[0059] The drain of the second PMOS tube 21 is connected to the second end of the switch 51 .

[0060] As an optional implementation of the present invention, the first end of the switch 51 is connected to the gate of the first PMOS transistor 11 and the gate of the first NMOS transistor 12;

[0061] When the chip enters the power saving mode, the first PMOS transistor 11 and the first NMOS transistor 12 generate a switch control signal to disconnect the switch 51. This prevents the gate tracking module 2 from pulling up the control terminal of the output driver transistor, which causes the gate high level to continue to flow back to the chip working circuit 5 of the previous stage, thereby blocking the backflow path, thereby further realizing the backflow prevention and enhancing the backflow prevention effect.

[0062] In some embodiments, the working process of the anti-backflow interface circuit of the present invention includes:

[0063] (1) When the chip is in a normal working state, the GPIO works normally, and the VDDIO voltage output by the IO power supply 32 is greater than 0. In some specific examples, the VDDIO voltage is 1.8V or 3V. At this time, the external power supply 33 is floating. At this time, the gate levels of the first PMOS tube 11 and the second PMOS tube 21 are high. Therefore, at this time, the source and drain of the first PMOS tube 11 and the source and drain of the second PMOS tube 21 are all in the off state, and the drain of the first PMOS tube 11 outputs a low level. Since the gate of the second NMOS tube 7 receives the low level output by the drain of the first PMOS tube 11, the source and drain of the second NMOS tube 7 are disconnected at this time.

[0064] The second PMOS tube 21 is turned off, and the drain is floating; the switch 51 is closed, and the control end of the output driver transistor 4 receives the signal sent by the first inverter 52, so that the chip works normally;

[0065] (2) When the chip enters the power saving mode (PSM), the voltage VDDIO of the IO power supply 32 is 0, and the anti-backflow logic generation module 1 determines that the current chip state is a state that requires anti-backflow. Since the voltage VDDIO of the IO power supply 32 is 0 at this time, the gate level of the first PMOS tube 11 and the gate level of the second PMOS tube 21 are both low levels. At this time, the source and drain of the first PMOS tube 11 are turned on, and the source and drain of the second PMOS tube 21 are turned on;

[0066] At the same time, the external power supply 33 outputs a logic high level to the source of the first PMOS tube 11 and the source of the second PMOS tube 21 through the backflow terminal PAD, wherein the logic high level is less than the battery 31 voltage VBAT, that is, at this time, the level of the backflow terminal PAD is a high level less than the battery 31 voltage; the source and drain of the second PMOS tube 21 are turned on, and after the source of the second PMOS tube 21 receives the logic high level, the drain of the second PMOS tube 21 outputs the first high level to the control end of the output driver transistor 4, so that the source and drain of the output driver transistor 4 are disconnected, thereby disconnecting the current channel between the power supply module 3 and the chip working circuit 5, thereby disconnecting the backflow channel, avoiding the occurrence of backflow, and realizing the anti-backflow function of the chip;

[0067] At the same time, after the source and drain of the first PMOS tube 11 are turned on, the drain of the first PMOS tube 11 outputs the second high level from the drain to the gate of the second NMOS tube 7, so that the source and drain of the second NMOS tube 7 are turned on, thereby outputting the current output by the second inverter 53 to the ground, preventing the backflow of current;

[0068] At the same time, since the second NMOS tube 7 outputs the current output by the second inverter 53 to the ground, the gate level of the third NMOS tube 8 is low at this time, and the source and drain of the third NMOS tube 8 are disconnected, thereby preventing the external power supply 33 from leaking to GND through the NMOS tube 8, further realizing backflow prevention; wherein GND is the ground terminal;

[0069] At the same time, the first PMOS tube 11 and the first NMOS tube 12 generate a switch control signal to disconnect the switch 51, thereby preventing the gate tracking module 2 from pulling up the control end of the output driver stage transistor 4, thereby preventing the gate high level from continuing to flow back to the previous chip working circuit 5, blocking the backflow path, and further achieving backflow prevention.

[0070] In summary, the anti-backflow interface circuit of the present invention can realize the first-level anti-backflow by controlling the output driver-level transistor 4 to enter the cut-off state and disconnecting the power supply module 3 from the chip working circuit 5 after the chip enters the low-power state; it can also realize the second-level anti-backflow by controlling the switch 51 to be disconnected and disconnecting the first inverter 52 from the control end of the output driver-level transistor 4; it can also realize the third-level anti-backflow by controlling the second NMOS tube 7 to be turned on and conducting the output current of the second inverter 53 to the ground; it can also realize the fourth-level anti-backflow by controlling the third NMOS tube 8 to be in the cut-off state to avoid the current output by the external power supply 33 from leaking to GND through the NMOS tube 8; therefore, the anti-backflow interface circuit of the present invention can perform multi-level anti-backflow after the chip enters the low-power state, which greatly enhances the stability of anti-backflow and greatly reduces the possibility of false wake-up of the chip.

[0071] To verify the effect of the present invention, the inventors also conducted a test on the anti-backflow interface circuit of the present invention:

[0072] During the experiment, the chip was put into a low power consumption state, at which time the GPIO IO power supply 32 voltage VDDIO was 0, and the GPIO logic high level PAD was any value less than the battery 31 voltage VBAT; after testing, the GPIO anti-backflow function was turned on, and the chip was not woken up by mistake.

[0073] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. An interface circuit for preventing backflow, characterized in that: It includes a power supply module, an anti-backflow logic generation module, a gate tracking module, an output driver transistor and a chip working circuit, wherein the power supply module is connected to the anti-backflow logic generation module and the gate tracking module respectively, the anti-backflow logic generation module is connected to the gate tracking module, the source of the output driver transistor is connected to the power supply module, the drain of the output driver transistor is connected to the chip working circuit, and the control end of the output driver transistor is connected to the output end of the gate tracking module; after the chip enters the power saving mode, the anti-backflow logic generation module transmits a logic high level to the gate tracking module; After receiving the logic high level, the gate tracking module outputs a first high level to the control terminal of the output driver transistor; After receiving the first high level, the control end of the output driver transistor disconnects the current channel between the power supply module and the chip working circuit; The power supply module includes a battery, an IO power supply and an external power supply, the battery is connected to the IO power supply, the IO power supply is connected to the source of the output driver transistor, and the external power supply is connected to the drain of the output driver transistor through a backflow terminal; The anti-backflow logic generation module includes a first PMOS tube and a first NMOS tube, the source of the first PMOS tube is connected to the gate tracking module and the backflow end, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the gate of the first PMOS tube is connected to the gate of the first NMOS tube and the IO power supply, and the source of the first NMOS tube is grounded; When the chip enters the power saving mode, the IO power supply output voltage is 0, the external power supply generates the logic high level and transmits the logic high level to the source of the first PMOS tube through the backflow terminal; Wherein, it also includes a second NMOS tube, the gate of the second NMOS tube is connected to the drain of the first PMOS tube, the drain of the second NMOS tube is connected to the chip working circuit, and the source of the second NMOS tube is grounded; When the chip enters the power saving mode, the IO power supply output voltage is 0, the source and drain of the first PMOS tube are turned on, and the drain of the first PMOS tube outputs a second high level to the gate of the second NMOS tube; After the gate of the second NMOS tube receives the second high level, the source of the second NMOS tube and the drain of the second NMOS tube are turned on and output current to the ground.

2. The anti-backflow interface circuit according to claim 1, characterized in that: The gate tracking module includes a second PMOS tube, the source of the second PMOS tube is connected to the source of the first PMOS tube to receive the logic high level, the gate of the second PMOS tube is connected to the IO power supply, and the drain of the second PMOS tube is connected to the control end of the output driving stage transistor.

3. The anti-backflow interface circuit according to claim 2, characterized in that: When the chip enters the power saving mode, the IO power supply output voltage is 0, the source and drain of the second PMOS tube are turned on, so that the drain of the second PMOS tube outputs the first high level to the control end of the output driver transistor; After the control end of the output driver transistor receives the first high level, the source and drain of the output driver transistor are disconnected, thereby disconnecting the current channel between the power supply module and the chip working circuit.

4. The anti-backflow interface circuit according to claim 2, characterized in that: It also includes a third NMOS tube, wherein the gate of the third NMOS tube is connected to the drain of the second NMOS tube, the drain of the third NMOS tube is connected to the drain of the output driver stage transistor, and the source of the third NMOS tube is grounded; The source and substrate of the second NMOS tube are short-circuited, and the source and substrate of the third NMOS tube are short-circuited.

5. The anti-backflow interface circuit according to claim 2, characterized in that: The substrate of the first PMOS tube, the substrate of the second PMOS tube and the substrate of the output driving stage transistor are all connected to the battery.

6. The anti-backflow interface circuit according to claim 5, characterized in that: It also includes an electrostatic discharge protection module, which includes a battery electrostatic discharge unit and an IO power supply electrostatic discharge unit. The battery electrostatic discharge unit is connected to the battery, and the IO power supply electrostatic discharge unit is connected to the IO power supply.

7. The anti-backflow interface circuit according to claim 4, characterized in that: The chip working circuit includes a switch and a plurality of first inverters and a plurality of second inverters, wherein the plurality of first inverters are connected in series in sequence, and an output end of one of the first inverters is connected to a first end of the switch, a second end of the switch is connected to a control end of the output driving stage transistor, and a first end of the switch is connected to the IO power supply; A plurality of the second inverters are connected in series in sequence, and an output end of one of the second inverters is connected to a drain of the second NMOS tube and a gate of the third NMOS tube; The drain of the second PMOS tube is connected to the second end of the switch.

8. The anti-backflow interface circuit according to claim 7, characterized in that: The first end of the switch is connected to the gate of the first PMOS tube and the gate of the first NMOS tube; When the chip enters the power saving mode, the first PMOS transistor and the first NMOS transistor generate a switch control signal to disconnect the switch.

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