Calibration method for capacitance array mismatch

Abstract

The application discloses a calibration method for capacitor array mismatch. By adjusting the value of the adjustable reference voltage of the capacitor connected to at least one bit, the value of the adjustable reference voltage is locked when the actual output voltage is equal to the rated output voltage under the corresponding condition, and correct conversion voltage can be obtained even if there is error in the capacitor of some bits in the capacitor array, so that the capacitor array is calibrated.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and more specifically, to a calibration method for capacitor array mismatch. Background Technology

[0002] Currently, the most widely used analog-to-digital converters (ADCs) are based on capacitor arrays as their main structure. However, during the integrated circuit manufacturing process, there will be matching problems between capacitors. Especially for applications with limited wafer area, the unit capacitance is becoming smaller and smaller, which makes the capacitor matching even worse. Capacitor mismatch error has a great impact on ADC performance, so it is necessary to calibrate it.

[0003] One type of existing self-calibration technique uses a separate calibration capacitor array to measure the error of each capacitor and store the error in a register. In actual operation, the calibration capacitor array converts the error into an analog quantity and subtracts this error in the analog domain. This method requires an additional capacitor array for measuring and subtracting the error voltage, increasing the chip area and limiting its widespread use.

[0004] Another type of existing calibration technology calibrates capacitance values ​​(or weights) using different algorithms, either analog or digital. These are all calibrations of the capacitors themselves. Furthermore, analog calibration of capacitor mismatch requires additional capacitor arrays; digital calibration typically requires extra computation time to calculate the final result, and the conversion result cannot be output in real time in an analog-to-digital converter. Summary of the Invention

[0005] In view of this, the present invention provides a new calibration method for capacitor array mismatch, which does not calibrate the capacitors in the capacitor array themselves, but achieves the purpose of calibrating the capacitor array by changing the reference voltage.

[0006] This invention provides a calibration method for capacitor array mismatch, applied in an analog-to-digital converter, wherein the capacitor array comprises at least two capacitors, characterized in that it includes:

[0007] The reference voltage of the capacitor at least one bit is configured as an adjustable reference voltage, and the reference voltage of the capacitors in the remaining bits is configured as a predetermined reference voltage.

[0008] By adjusting the value of each of the adjustable reference voltages individually, the deviation of the capacitors at each bit corresponding to the adjustable reference voltage is compensated, thereby enabling the capacitor array to output an accurate conversion voltage.

[0009] Preferably, the amount of charge switched by the capacitor array is adjusted by adjusting the value of each of the adjustable reference voltages, thereby compensating for the deviation of the capacitance at each bit corresponding to the adjustable reference voltage.

[0010] Preferably, the ratio of the value of each adjustable reference voltage to the predetermined reference voltage is consistent with the ratio of the corresponding rated capacitance ratio factor to the actual capacitance ratio factor, wherein the capacitance ratio factor is the ratio of the capacitance at one bit corresponding to the adjustable reference voltage to the total capacitance of the capacitor array.

[0011] Preferably, when the analog-to-digital converter is in the charge redistribution stage, the voltage value of each of the adjustable reference voltages is adjusted so that the capacitor on one bit corresponding to the adjustable reference voltage is connected to the adjustable reference voltage, and the capacitors on other bits are connected to the predetermined reference voltage. The actual output voltage is equal to the rated output voltage.

[0012] Preferably, each of the rated output voltages is obtained based on the difference between the product of a corresponding rated capacitance ratio factor and the predetermined reference voltage and the input voltage, wherein the rated capacitance ratio factor is the ratio of the rated capacitance of the capacitor at one position corresponding to the adjustable reference voltage to the rated capacitance of the total capacitance of the capacitor array.

[0013] Preferably, the predetermined reference voltage is a fixed voltage.

[0014] Preferably, the adjustable reference voltage is obtained by dividing the predetermined reference voltage using an adjustable voltage divider circuit.

[0015] Preferably, the adjustable voltage divider circuit consists of two resistors connected in series, and the adjustable reference voltage is output at the common connection terminal of the two resistors. At least one of the two resistors is an adjustable resistor, and the voltage value of the adjustable reference voltage that meets the requirements is obtained by adjusting the resistance value of the at least one adjustable resistor.

[0016] This invention aims to provide a new calibration method for capacitor array mismatch. By adjusting the values ​​of adjustable reference voltages connected to different capacitors, the value of the adjustable reference voltage is locked when the actual output voltage equals the rated output voltage under the corresponding conditions. This method can still obtain the correct conversion voltage even if there are errors in some capacitors in the capacitor array, which is equivalent to calibrating the capacitor array. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a proportional capacitor array;

[0019] Figure 2 This is a schematic diagram of a capacitor array according to Embodiment 1 of the present invention;

[0020] Figure 3 This is a schematic diagram of a capacitor array according to Embodiment 2 of the present invention;

[0021] Figure 4 This is a schematic diagram of a capacitor array according to Embodiment 3 of the present invention. Detailed Implementation

[0022] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0023] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0024] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0025] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0026] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0027] Figure 1 This is a schematic diagram of a proportional capacitor array. (Example) Figure 1 As shown, the capacitor array 10 consists of capacitors C1, C2, ... C N-2 C N-1 C N The capacitor array 10 is composed of capacitors connected in parallel, where N is a natural number greater than or equal to 2. The base plate of the capacitor array 10 is connected to a predetermined reference voltage V through a set of switching switches. REFP Input voltage V IN Or reference ground voltage V GND The top plate is connected to the reference ground voltage V via a switch S0. GND Preferably, the switch array consists of single-pole three-throw switches S1, S2, ... S1. N-2 S N-1 S N The circuit consists of a switch array where each switch corresponds one-to-one with a capacitor in the capacitor array 10. An output voltage V is generated on the top plate of the capacitor array 10. TOP .

[0028] For example, in an analog-to-digital converter (ADC) application, the output of capacitor array 10 is connected to one input of a comparator, and the other input of the comparator is connected to the common-mode voltage V. CM The output of the comparator is connected to the input of the successive approximation (SAR) logic circuit. Then, the SAR logic circuit implements logic control of the switch array in the capacitor array 10 based on the output signal of the comparator.

[0029] A capacitor-type DAC (digital-to-analog converter) utilizes the principle of charge conservation to obtain the desired output voltage V based on the redistribution of charge before and after sampling. TOP However, the output voltage V TOP The accuracy depends strictly on the matching between the capacitors in the capacitor array. The basic working principle of capacitor array 10 will be analyzed below:

[0030] During the sampling phase: Switch S0 is closed, and switches S1 to S... N Connected to input voltage V IN At this point, the charge Q stored in the top plate of capacitor array 10 is... TOP for:

[0031] Q TOP =(0-V IN )*C Total =(-VIN )*C Total

[0032] in,

[0033]

[0034] During the holding phase: Switch S0 is open, if S1 to S N Connected to reference ground voltage V GND According to the law of charge conservation, the output voltage V on the top plate of capacitor array 10 at this time is... TOP for:

[0035]

[0036] During the charge redistribution stage: different output voltages V can be obtained by changing the voltage on the base plate of capacitor array 10. TOP If the capacitance C at the m-th bit (between 1 and N) is... m Switch S on the base plate m Received the predetermined reference voltage V REFP From the above, we can conclude:

[0037] (V TOP_m -V REFP )*C m +V TOP_m *(C Total -C m )=Q TOP

[0038] =(-V IN )*C Total

[0039] V TOP_m *C Total =(-V IN )*C Total +V REFP *C m

[0040] Therefore, the output voltage V of the top plate of capacitor array 10 TOP_m for:

[0041]

[0042] As can be seen from the above formula, in order to obtain the accurate top plate voltage, the capacitance C at the m-th position... m and total capacitance C Total The capacitance ratio W between m This plays a crucial role; the matching between capacitors directly affects the voltage output from the top plate of capacitor array 10. Here, the capacitance proportionality coefficient W... m for:

[0043]

[0044] If there is a capacitor mismatch, if the capacitor proportional coefficient becomes W′ m This will cause the voltage on the top plate of capacitor array 10 to become:

[0045] V TOP_m =-V IN +W′ m V REFP

[0046] The output voltage V of capacitor array 10 is not accurate. TOP Alright.

[0047] In summary, the fundamental principle of a capacitor-type DAC is charge redistribution. That is, the charge remains constant throughout the entire ADC conversion cycle, and each bit switching is essentially a process of charge redistribution. Therefore, if there is a mismatch between the capacitors, it will affect the amount of redistributed charge. Based on this problem, this invention proposes a method of changing the reference voltage to adjust the amount of charge switching in the capacitor array. In this way, even if there is a mismatch between the capacitors, the capacitor array can ultimately generate the correct conversion voltage.

[0048] The calibration method for capacitor array mismatch proposed in this invention includes: configuring the reference voltage of at least one capacitor as an adjustable reference voltage, and configuring the reference voltage of the capacitors in the remaining bits as a predetermined reference voltage; by adjusting the value of each of the adjustable reference voltages respectively, the deviation of the capacitors in each bit corresponding to the adjustable reference voltage is compensated, thereby enabling the capacitor array to finally output an accurate conversion voltage. Here, the predetermined reference voltage is a fixed voltage.

[0049] Specifically, the amount of charge switched by the capacitor array is adjusted by adjusting the value of the reference voltage of the capacitor at least one bit configured as the adjustable reference voltage, thereby calibrating the capacitor at the bit corresponding to the adjustable reference voltage.

[0050] Figure 2 This is a schematic diagram of a capacitor array according to an embodiment of the present invention. Figure 2 As shown, capacitor array 20 also consists of capacitors C1, C2, ... C N-2 C N-1 C N The capacitor array 20 is composed of capacitors connected in parallel, where N is a natural number greater than or equal to 2. The top plate of the capacitor array 20 is connected to the reference ground voltage V through a switch S0. GND The difference is that the capacitors C1, C2, ... C in capacitor array 20N-2 C N-1 The base plate is connected to a predetermined reference voltage V via a set of switching arrays. REFP Input voltage V IN Or reference ground voltage V GND Preferably, the switch array consists of single-pole three-throw switches S1, S2, ... S1. N-2 S N-1 The switch array consists of a switch array and a capacitor array 20, each corresponding to one of the switches. The capacitors C in the capacitor array 20 are... N The base plate is controlled by switch S N Adjustable reference voltage V connected to the adjustable reference voltage output REFP_N Input voltage V IN Or reference ground voltage V GND An output voltage V is generated on the top plate of the capacitor array 20. TOP .

[0051] It should be noted that, in this embodiment of the invention, only the capacitor C at the Nth position is selected. N The reference voltage of the capacitor is configured as an adjustable reference voltage, while the reference voltage of the capacitors on the other bits is configured as a fixed predetermined reference voltage V. REFP In other implementations, depending on the calibration accuracy requirements, the capacitor reference voltages on multiple bits can be configured as adjustable reference voltages.

[0052] The basic working principle of capacitor array 20 is analyzed below:

[0053] During the sampling phase: Switch S0 is closed, and switches S1 to S... N Connected to input voltage V IN At this point, the charge Q stored in the top plate of capacitor array 20 is... TOP for:

[0054] Q TOP =(0-V IN )*C Total =(-V IN )*C Total

[0055] in,

[0056]

[0057] In traditional capacitor arrays, mismatched capacitors will cause the final output voltage V to change during the charge redistribution phase. TOP This is not the voltage value we want. As shown in the formula above, capacitor mismatch will cause the actual capacitance proportionality coefficient W′ to change. m Not equal to the rated capacitance ratio W m And in Figure 2In the capacitor array 20 shown, during the charge redistribution phase, the capacitor C... N Base plate switch S N The received reference level is no longer the predetermined reference voltage V. REFP Instead, it is related to capacitor C. N The corresponding adjustable reference voltage V REFP_N At this time, the output voltage V on the top plate of capacitor array 20 is... TOP_N Represented as:

[0058] V TOP_N =-V IN +W′ N *V REFP_N

[0059] Its rated value is:

[0060] V TOP_N =-V IN +W N *V REFP

[0061] Here, the actual capacitance proportionality coefficient W′ N For capacitor C N With total capacitance C Total The ratio of the actual capacitance value to the rated capacitance proportionality coefficient W. N For capacitor C N With total capacitance C Total The ratio of the rated capacitance value,

[0062]

[0063] Therefore, in this embodiment of the invention, it is necessary to make the output voltage V TOP_N Equal to the corresponding rated output voltage, as long as W′ N *V REFP_N =W N *V REFP That's it. Therefore, simply adjust the adjustable reference voltage V. REFP_N The voltage values ​​should satisfy the following relationship:

[0064]

[0065] This allows for the calibration of the capacitor C at the Nth position. N The purpose.

[0066] Therefore, it can be concluded that if the capacitor C at the m-th position is... m Connected to its corresponding adjustable reference voltage V REFP_m If above, then only V needs to be adjusted. REFP_m The value satisfies:

[0067]

[0068] Even if each adjustable reference voltage V REFP_m The value and the predetermined reference voltage V REFP The ratio of the capacitance to the corresponding rated capacitance proportionality coefficient W m And the actual capacitance ratio W′ m If the ratios are consistent, the capacitance C at the m-th position can be effectively calibrated. m The purpose, in practical operation, is to make the actual output voltage V TOP_m The output voltage is equal to the rated voltage, as shown in the following formula, which is to say, it is considered to be related to the capacitance C at the m-th position. m The corresponding adjustable reference voltage V REFP_m The values ​​have been adjusted.

[0069] V TOPm =-V IN +W m *V REFP

[0070]

[0071] Taking binary as an example, the capacitance C1 in the first bit (e.g., the most significant bit) and the total capacitance C Total If the capacitance ratio is 1 / 2, then W1 = 1 / 2. Adjust the adjustable reference voltage V. REFP_1 The value of makes At that time, the adjustable reference voltage V can be locked. REFP_1 The value; the capacitance C2 in the second bit (e.g., the most significant bit) and the total capacitance C. Total If the capacitance ratio is 1 / 4, then W2 = 1 / 4. Adjust the adjustable reference voltage V. REFP_2 The value of makes At that time, the adjustable reference voltage V can be locked. REFP_2 The value, and so on.

[0072] Therefore, when the analog-to-digital converter is in the charge redistribution phase, each adjustable reference voltage V is adjusted separately. REFP_m The voltage value is such that the capacitor C at the bit corresponding to the adjustable reference voltage is... m Connected to the adjustable reference voltage V REFP_m And the capacitors at other positions are connected to a predetermined reference voltage V. REFP The actual output voltage V at that time TOP_m This equals the rated output voltage. This allows for calibration of capacitor mismatch at the corresponding bit. Here, the rated output voltage is based on a rated proportionality coefficient W. m and the predetermined reference voltage V REFP The product of the input voltage VIN The difference between them is obtained, where the rated proportionality coefficient W m To match the adjustable reference voltage V REFP_m The corresponding capacitor C m The total capacitance C of the capacitor array Total The ratio of the rated capacitance value.

[0073] Wherein, reference voltage V REFP_m This can be achieved in several ways, a relatively simple one being by using an adjustable resistor to perform voltage division adjustment, such as... Figure 3 The diagram shown is a schematic diagram of the capacitor array 20 according to Embodiment 2 of the present invention.

[0074] refer to Figure 3 The adjustable reference voltage is achieved by adjusting the predetermined reference voltage V. REFP This voltage is obtained by using an adjustable voltage divider circuit. Preferably, the adjustable voltage divider circuit includes a resistor voltage divider circuit consisting of two resistors R1 and R2 connected in series, outputting an adjustable reference voltage V at the common connection terminal of the two resistors. REFP_m In this embodiment, m = N, where at least one of the two resistors R1 and R2 is an adjustable resistor. By adjusting the resistance value of the at least one adjustable resistor and comparing the current output voltage with the rated output voltage, the process continues until the adjusted output voltage equals the rated output voltage. The resulting adjustable reference voltage is the voltage value that meets the requirements, i.e., the required reference voltage V. REFP_m Here, taking resistor R1 as an adjustable resistor as an example, it can be understood that resistor R2, or both resistors R1 and R2, can also form the aforementioned adjustable voltage divider circuit.

[0075] It should also be noted that the adjustable voltage divider circuit is not limited to... Figure 3 The resistor divider circuit shown is within the range of possible adjustable voltage dividers, including any other known or unknown circuit configurations that can achieve an adjustable output voltage.

[0076] Figure 4 This is a schematic diagram of the capacitor array 30 according to Embodiment 3 of the present invention. The difference between this array and Embodiments 1 and 2 is that the reference voltage of the capacitors on multiple bits is configured as an adjustable reference voltage V. REFP_m The reference voltage for the capacitors in the remaining positions is configured to a predetermined reference voltage V. REFP . Figure 4 In the capacitor array 30 shown, the capacitor C in the capacitor array 30 N The base plate is controlled by switch S N Connected to adjustable reference voltage V REFP_N Capacitor C N-1 The base plate is controlled by switch SN-1 Connected to adjustable reference voltage V REFP_N-1 Capacitor C N-2 The base plate is controlled by switch S N-2 Connected to adjustable reference voltage V REFP_N-2 The purpose of this design is to resolve the mismatch between different capacitors, allowing capacitors at different positions to be connected to different reference voltage values. The voltage value of each adjustable reference voltage is adjusted sequentially, so that the capacitor C at the corresponding position of the adjustable reference voltage... m Connected to adjustable reference voltage V REFP_m And the capacitors at other positions are connected to a predetermined reference voltage V. REFP The actual output voltage V at that time TOP_m When the output voltage equals the rated voltage, the corresponding reference voltage value is locked, thereby calibrating the capacitor array and obtaining the required conversion voltage. When the capacitor array 30 is calibrated to an ideal state, because the capacitors at each position are calibrated sequentially, the voltage values ​​of the adjustable reference voltage outputs corresponding to the capacitors at the multiple positions may be the same or different.

[0077] In summary, the present invention aims to provide a new calibration method for capacitor array mismatch. By adjusting the value of the adjustable reference voltage connected to different capacitors, the value of the adjustable reference voltage is locked when the actual output voltage is equal to the rated output voltage under the corresponding conditions. This method can still obtain the correct conversion voltage even if there are errors in some capacitors in the capacitor array, which is equivalent to calibrating the capacitor array.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A calibration method for capacitor array mismatch, applied in an analog-to-digital converter, wherein the capacitor array comprises at least two capacitors, characterized in that, include: The reference voltage of the capacitor at least one bit is configured as an adjustable reference voltage, while the reference voltage of the capacitors in the remaining bits is configured as a predetermined reference voltage of a fixed value. By adjusting the value of each adjustable reference voltage, the capacitor at the corresponding bit is connected to the adjustable reference voltage, and the capacitors at other bits are connected to the predetermined reference voltage. This compensates for the capacitance deviation of the capacitor at each bit corresponding to the adjustable reference voltage, thereby locking the corresponding reference voltage value when the actual output voltage of the capacitor array is equal to the rated output voltage during the charge redistribution phase.

2. The calibration method for capacitor array mismatch according to claim 1, characterized in that, By adjusting the value of each of the adjustable reference voltages individually, the amount of charge switched by the capacitor array is adjusted, thereby compensating for the deviation of the capacitance at each bit corresponding to the adjustable reference voltage.

3. The calibration method for capacitor array mismatch according to claim 1, characterized in that, The ratio of each adjustable reference voltage value to the predetermined reference voltage is consistent with the ratio of the corresponding rated capacitance ratio factor to the actual capacitance ratio factor, wherein the capacitance ratio factor is the ratio of the capacitance at a position corresponding to the adjustable reference voltage to the total capacitance of the capacitor array.

4. The calibration method for capacitor array mismatch according to claim 1, characterized in that, Each of the rated output voltages is obtained based on the difference between the product of a corresponding rated capacitance ratio factor and the predetermined reference voltage and the input voltage, wherein the rated capacitance ratio factor is the ratio of the rated capacitance of the capacitor at one position corresponding to the adjustable reference voltage to the rated capacitance of the total capacitance of the capacitor array.

5. The calibration method for capacitor array mismatch according to claim 1, characterized in that, The predetermined reference voltage is a fixed voltage.

6. The calibration method for capacitor array mismatch according to claim 1, characterized in that, The adjustable reference voltage is obtained by dividing the predetermined reference voltage using an adjustable voltage divider circuit.

7. The calibration method for capacitor array mismatch according to claim 6, characterized in that, The adjustable voltage divider circuit consists of two resistors connected in series. The adjustable reference voltage is output at the common connection terminal of the two resistors. At least one of the two resistors is an adjustable resistor. By adjusting the resistance value of the at least one adjustable resistor, the required voltage value of the adjustable reference voltage can be obtained.

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