Processor, apparatus for protecting the processor, and method for protecting the processor

Abstract

A processor, an apparatus for protecting the processor, and a method for protecting the processor are disclosed. The apparatus includes an input interface and a protection circuit. The input interface is configured to monitor a plurality of program instructions processed by the processor, at least one program instruction including at least one error detection bit. The protection circuit is configured to use the error detection bit to detect an error in program code and to initiate a response action in response to detecting the error.

Description

Technical Field

[0001] This invention relates to microprocessors, and more particularly to a method and system for in-band error detection in microprocessor circuits. Background Technology

[0002] Fault injection attacks are a series of techniques used to access, analyze, or extract information from secure electronic circuits such as encrypted circuits. Fault injection attacks typically involve causing a circuit or a portion thereof to change its logical state and behavior, helping attackers to see through the circuit or the information it stores. For example, fault injection attacks can be launched by physically touching signal lines, applying high-power lasers or electromagnetic pulses, or creating waveform interference at power supplies or other external interfaces. Various techniques for detecting and / or mitigating fault injection attacks are existing technologies. Summary of the Invention

[0003] One embodiment described herein provides an apparatus for protecting a processor. The apparatus includes an input interface and a protection circuit. The input interface is configured to monitor a plurality of program instructions processed by the processor, at least one of the program instructions including at least one error detection bit. The protection circuit is configured to use the error detection bit to detect an error in program code and to initiate a response action in response to the detection of the error.

[0004] In some embodiments, when detecting the error, the protection circuit is configured to detect a fault injection attack. In one embodiment, the at least one error detection bit is inserted into a plurality of reserved bit positions in the at least one program instruction; and the protection circuit is configured to remove the error detection bit from the reserved bit positions. In another embodiment, the at least one error detection bit is inserted into a plurality of substantially reserved positions in the at least one program instruction, and the plurality of substantially reserved positions do not affect the execution of the program instruction; and the protection circuit is configured to remove the error detection bit from the substantially reserved bit positions.

[0005] In another embodiment, in at least one jump instruction, the at least one error detection bit is inserted in at least one bit position, the at least one bit position being (i) designated to represent a jump offset, but (ii) configured not to be executed by the processor. In another embodiment, the at least one error detection bit is inserted in at least one special program instruction, the special program instruction being added to the program code for error detection; and the protection circuit is configured to recognize the special program instruction and extract the error detection bit from the special program instruction.

[0006] In one disclosed embodiment, the protection circuit is configured to store a definition of the position of the error detection bit in the program instructions and to extract the error detection bit from the program instructions according to the definition. In an exemplary embodiment, a given set of at least one error detection bit is calculated by at least a portion of a given program instruction and inserted into the given program instruction.

[0007] In some embodiments, a given set of at least one error detection bit is calculated from a plurality of select bits in the program code; and the at least one select bit and the at least one error detection bit in the set are located in different program instructions. In one embodiment, the plurality of select bits are limited to a segment of the program code that includes a deterministic code stream. In an exemplary embodiment, the plurality of select bits are limited to a segment of the program code that does not traverse the jump instruction or multiple jump destination instructions.

[0008] In some embodiments, the device further includes an insertion circuit configured to insert the at least one error detection at the at least one program instruction provided to the processor for processing.

[0009] According to an embodiment of the present invention, a processor is further provided, comprising: an instruction pipeline and a protection circuit. The instruction pipeline is configured to extract and execute program code, the program code comprising a plurality of program instructions, at least one of the plurality of program instructions comprising at least one error detection bit. The protection circuit is configured to at least monitor the error detection bit in the program instructions, and use the error detection code to detect an error in the program code, and initiate a response action in response to detecting the error.

[0010] According to embodiments of the present invention, a method for protecting a processor is also provided. The method includes monitoring a plurality of program instructions processed by the processor, at least one of the program instructions including at least one error detection bit. The error detection bit is used to detect an error in the program code; and a response action is initiated in response to the detection of the error.

[0011] The present invention will be more fully understood after the following description of the embodiments and accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a structural diagram illustrating a processor according to one embodiment of the present invention.

[0013] Figure 2 This is a flowchart illustrating a method for protecting a processor according to one embodiment of the present invention.

[0014] Symbol explanation:

[0015] 20: Processor

[0016] 24: Command Pipeline

[0017] 28: Protection Circuit

[0018] 32: Memory

[0019] 36: Extraction Unit

[0020] 40: Decoding Unit

[0021] 44: Execution Unit

[0022] 48: Insertion circuit

[0023] 50: Interface

[0024] 52: Comparison Table

[0025] 56: Logic (EDC Inspection Circuit)

[0026] 60, 64, 68, 72, 76, 80, 84: Steps Detailed Implementation

[0027] The embodiments of the invention described herein provide a method and apparatus for protecting a processor from bit errors in program instructions. For example, fault injection attacks can cause errors in program instructions, attempting to malfunction the processor and extract sensitive information. However, in general, the techniques disclosed herein can protect the processor from errors caused by any malicious or unintentional mechanisms. In this document, the term "processor" refers to various types of processors, such as central processing units (CPUs), microcontroller units (MCUs), embedded controllers, processing cores, etc.

[0028] Processors typically include an instruction pipeline, configured to fetch instructions from memory and execute those instructions. Each program instruction is fetched from a specific Instruction Set Architecture (ISA), described by a set of bits, and stored in memory. Each bit defines the instruction's operand and may define at least one operand. It is understandable that a bit error in any bit of the instruction will result in unpredictable and highly undesirable outcomes.

[0029] Some embodiments of the present invention provide protection circuitry to protect the processor from bit errors. The protection circuitry monitors at least one error detection bit, which is inserted into at least one program instruction. When an error is detected in the program code using the error detection bit, the protection circuitry initiates appropriate response behavior.

[0030] In some embodiments, the protection circuitry is integrated into the processor. In alternative embodiments, the protection circuitry is located externally to the processor. In some embodiments, error detection bits are pre-inserted into program instructions by a compiler or post-processor, so that the program code stored in memory already contains the error detection bits. In alternative embodiments, the error detection bits are inserted into program instructions at runtime. For example, a dedicated insertion circuit can insert the error detection bits into program instructions fetched from memory and provided to the processor.

[0031] In some embodiments, error detection bits are inserted into existing bit positions within the instruction without requiring editing of the specific ISA in the processing and without expanding the instruction size (width). This feature is important, for example, for maintaining processor instruction throughput and backward compatibility with legacy processors. Various techniques for reusing existing bit positions for error detection bits are described herein.

[0032] In some embodiments, error detection is applied independently for each instruction. In such embodiments, the error detection bit instruction for a specific instruction is computed on (some or all) bits of the same instruction. In other embodiments, error detection is applied across boundaries between instructions, for example, across an entire section of code. In some embodiments, additional commands are added to the code for error detection.

[0033] The embodiments described herein are primarily concerned with parity checking, but other suitable error detection mechanisms may be used in alternative embodiments. For the sake of brevity, the error detection bits will hereinafter also be referred to as the Error-Detection Code (EDC) bits.

[0034] The technology disclosed herein will provide an effective and cost-efficient means to protect the processor from bit errors in program instructions.

[0035] System Description

[0036] Figure 1 This is a structural diagram illustrating a processor 20 according to one embodiment of the present invention. Figure 1In one embodiment, the processor 20 includes: an instruction pipeline 24 for fetching and executing program code; a memory 32 for storing program code; and a protection circuit 28 for preventing bit errors that may occur in the program code.

[0037] Instruction pipeline 24 comprises multiple pipeline stages. In this example, instruction pipeline 24 includes a fetch unit 36, a decode unit 40, and at least one execution unit 44. The fetch unit 36 ​​fetches program instructions from memory 22. The decode unit 40 decodes the fetched instructions. The execution unit 44 executes the decoded instructions. For example, the execution unit 44 may include at least one load-store unit (LSU), an arithmetic logic unit (ALU), a shunt unit, or other suitable execution unit.

[0038] Protection circuit 28 uses error detection bits (also known as EDC bits) to detect bit errors in the program code, wherein the EDC bits are inserted into at least one predetermined bit position in the program instructions. In this document, the terms "bit error in program code" and "bit error in code instruction" refer to errors maliciously or unintentionally caused in the program after the program code has been provided to the system or processor (in other words, after the original program code has been stored in memory 32). In other words, in the technology disclosed herein, the original program code provided to the system or processor (in other words, the program code originally stored in memory 32) can prevent maliciously generated errors.

[0039] The examples described below primarily concern parity checking. When using parity checking, each parity bit is calculated from a predetermined set of program instructions. If the number of "1"s in the set is odd, the parity bit is set to "1"; if the number of "1"s in the set is even, the parity bit is set to "0". Parity checking can be used to detect multiple error bits, for example, implemented using Hamming codes. Other error detection mechanisms, such as CRC (Cyclical Redundancy Check), hashing, SHA (Secure Hash Algorithm), multi-bit parity checking, or other suitable mechanisms, can also be used to implement the techniques disclosed herein.

[0040] In some embodiments, the program code stored in memory 32 already includes an EDC bit. For example, the EDC bit can be inserted by a compiler or by a post-processor that processes compiled program code. In other embodiments, the program code stored in memory 32 does not include an EDC bit, and processor 20 further includes an EDC insertion circuit 48 to insert the EDC bit into the program code during runtime. In one embodiment, the EDC bit is connected in series between memory 32 and instruction pipeline 24, and is inserted into at least one program instruction fetched from memory by fetch unit 36.

[0041] exist Figure 1 In this embodiment, the protection circuit uses interface 50 to receive program instructions via instruction pipeline 24. Protection circuit 28 conventionally stores definitions of the EDC mechanism, for example, (i) the definition of the location of the EDC bit in the program instructions, and (ii) the definition of the location of the relevant bits used to calculate the EDC bit. Protection circuit 28 uses these definitions to identify whether the value of the EDC bit indicates at least one bit error in the program code.

[0042] In this example, the EDC mechanism defines at most one EDC bit for each program instruction. When a program instruction contains an EDC bit, the EDC bit is calculated from the other bits of the instruction, or from a predefined portion of the instruction, as a parity check. In this example, protection circuit 28 includes a look-up table (LUT) 52 that illustrates the EDC mechanism. For each instruction monitored through interface 50, look-up table 52 produces two outputs: (i) an "EDC present" bit, indicating whether the instruction contains an EDC bit, and (ii) an "EDC location" bit, indicating the location of the EDC bit. In alternative embodiments, look-up table 52 may include other suitable structures and outputs to support other types of EDC mechanisms. Further alternatively, the EDC mechanism may also be defined and stored using other suitable circuitry or data structures without the need for a look-up table.

[0043] Protection circuit 28 also includes logic 56 (also known as EDC check logic) to verify whether the EDC bit indicates any bit error in the program code. In this example, logic 56 receives program instructions monitored by interface 50 as input. For each instruction, logic 56 receives an "EDC present" bit and an "EDC position" bit generated by lookup table 52. For a given instruction, if the relevant "EDC present" bit is "1", logic 56 calculates the parity (odd / even) of the appropriate bits in the instruction and compares it with the value of the bit at the "EDC position". If the calculated parity (odd / even) of the appropriate bits in the instruction does not match the value of the bit at the "EDC position", logic 56 concludes that a bit error has occurred in the instruction and initiates appropriate response behavior.

[0044] In various embodiments, logic 56 can initiate a wide variety of response behaviors. For example, logic 56 can issue a warning indicating that a fault injection attack may be underway. Additionally, logic 56 can selectively disable the processor or a portion thereof, erase data from the processor, or initiate other appropriate actions.

[0045] As shown in the figure, the "EDC location" bit is also provided to instruction pipeline 24 (typically to decoding unit 40). In some embodiments, elements of instruction pipeline 24 (e.g., decoding unit 40) need to know the location of the EDC bit in the instruction in order to ignore it. This will be described in detail later. In some embodiments, logic 56 also receives a "JUMP" input to indicate that the currently monitored instruction is a jump instruction or a jump destination instruction (a "target" or "landing" instruction made by a JUMP). In some embodiments, logic 56 further receives an "EXCEPTION" input to indicate that an exception has occurred in the processor. The "JUMP" input is used to mark the boundary between independent programs, where the EDC bit will be checked independently. The "EXCEPTION" input is used to temporarily disable or pause error detection checks. These will also be described in further detail later.

[0046] Figure 1 The configuration of the processor 20 and protection circuit 28 shown is illustrative for the purpose of making the concept clearer. Other suitable configurations may be used in alternative embodiments.

[0047] For example, in Figure 1 In this embodiment, memory 32 is part of the processor. In an alternative embodiment, memory 32 may also be located outside the processor and / or accessed via a suitable instruction cache.

[0048] As another example Figure 1The protection circuit 28 is an integrated part of the processor 20. Alternatively, the protection circuit 28 can also be located externally to the processor. Similarly, the EDC insertion circuit 48 (if used) can also be located externally to the processor. Therefore, by coupling external circuitry, the technology disclosed herein is suitable for use with existing general-purpose processors.

[0049] In another example, although in Figure 1 In this embodiment, instructions are provided to the protection circuit 28 from the output of the fetch circuit 36, but the disclosed technology is not limited to this configuration. In alternative embodiments, the interface 50 can transmit instructions to the protection circuit from other suitable locations in the instruction pipeline 24. For example, the interface 50 can transmit instructions to the protection circuit from the output of the decoding unit 40, or even from the output of the execution unit 44. In one embodiment, if the instruction is fetched from the later part of the pipeline, the protection circuit 28 needs to reconstruct the original format of the instruction (the format of the instruction stored in memory 32) after fetching so that the EDC bits correspond to the bits of other instructions. In one alternative embodiment, the compiler or post-processor can insert the EDC bits into the program at the sampling point of the interface 50 while considering the structure of the instruction. When using this technique, care must be taken to ensure that the instruction pipeline 24 does not discard those EDC bits before they arrive at the interface 50.

[0050] Furthermore, for clarity, the structure of instruction pipeline 24 has been highly simplified. Real-world processors can contain much more complex instruction pipelines. Additionally, the techniques disclosed herein are not limited to use with pipelined processors, but can also be used with processors containing other suitable microarchitectures. Generally, for the purpose of understanding the techniques disclosed herein, non-mandatory components have been omitted for simplicity.

[0051] In various embodiments, any circuit disclosed herein may be implemented using suitable hardware or firmware, such as using at least one separate component, at least one application-specific integrated circuit (ASIC), and / or at least one field-programmable gate array (FPGA).

[0052] In some embodiments, the protected processor may include a general-purpose processor programmed in software to perform the functions described herein. For example, the software may be downloaded to the processor electronically via a network; alternatively, it may be provided by means of non-transitory tangible media, such as magnetic storage, optical storage, or electronic storage.

[0053] Figure 2This is a flowchart illustrating a method for protecting a security processor 20 according to one embodiment of the present invention. The method begins with an extraction step 60, in which extraction unit 36 ​​extracts at least one instruction from memory 32. The extracted instruction is provided to decoding unit 40 and protection circuit 28. The method flow then splits into two parallel branches.

[0054] In decoding step 64, decoding unit 40 decodes the retrieved instructions. In execution step 68, execution unit 44 executes the instructions and returns to step 60 to retrieve the next instruction from memory.

[0055] In identification step 72, protection circuit 28 identifies which program instructions among these instructions contain EDC bits and the location of the EDC bits. In extraction step 76, protection circuit 28 extracts the EDC bits from the instructions. In EDC check step 80, protection circuit 28 checks whether the value of the EDC bits indicates any bit error in the program instructions.

[0056] If the EDC bit does not indicate any error (“EDC passed”), the process flow returns to step 60. Conversely, if the EDC bit indicates an error (“EDC failed”), then at action triggering step 84, protection circuit 28 initiates response behavior.

[0057] Figure 2 The flowchart shown is illustrative and is drawn solely for ease of understanding of the concept. In alternative embodiments, other suitable flowcharts may be used.

[0058] For example, processor 20 can support a "safe" operating mode that enables EDC insertion and checking, and a "normal" operating mode that disables EDC insertion and checking. These modes can be configured on a per-program address range basis.

[0059] EDC bit position

[0060] In various embodiments, the EDC mechanism used by the protection circuit 28 may also be different from each other. For example, the location of the EDC bit in the code and throughout the code may also be different from each other.

[0061] In some embodiments, at least one EDC bit is inserted (by the compiler, post-processor, or insertion circuit 48) into a "reserved" bit position as defined by the processor's ISA. The bit values ​​in the "reserved" positions are ignored by the instruction pipeline 24, so editing these bit values ​​does not affect program execution.

[0062] In some embodiments, at least one EDC bit is inserted (by the compiler, post-processor, or insertion circuit 48) into a "substantially reserved" bit location. Herein, the term "substantially reserved bit location" refers to a bit location that is not defined and reserved in the processor's ISA, but is ignored by the instruction pipeline 24 without affecting program execution. One type of unrestricted substantially reserved bit location is an address bit that is outside the address range that the processor can execute. For example, consider a case where the instruction structure specifies an n-bit address, but the address space used in the program code is only n-1 bits. In this case, even if the nth bit is not defined as "reserved" in the ISA, the nth bit can still be safely used as an EDC bit.

[0063] As another example, some ISAs support multiple jump instructions, and the maximum size of these jump instructions differs from each other (the size of the jump bias). This feature helps reduce the instruction size when executing small-biased jumps. In some embodiments, the compiler or post-processor is configured to use jump commands, and the jump location or bias is defined by the instruction operands (as long as it is not defined in a register) with a bias larger than actually needed, so that at least one most-significant bit (MSB) of the bias value can be used as the EDC bit. In these embodiments, the processor should also be aware of these specifications, so that instruction pipeline 24 (e.g., a shunt execution unit) ignores the EDC bit.

[0064] For example, consider an ISA that supports two types of jump instructions: a "normal" jump allowing a jump bias of up to ±24 bits, and a "nearby" jump allowing a jump bias of up to ±16 bits. In one embodiment, the compiler or post-processor is configured to (i) always allow a jump bias of up to ±16 bits, but (ii) always allow the "normal" jump instruction type. This configuration leaves the remaining 8 MSBs of the jump bias unused and effectively reserved as EDC bits (for example, for insertion by the compiler, post-processor, or insertion circuit 48).

[0065] Alternatively, the compiler or post-processor can be configured with various other instructions to generate substantially unused bit locations for EDC. Additionally, the compiler or post-processor can generally be configured to favor redundant instructions. This feature creates more substantially unused bits that can be used for EDC. These preferences can be enabled, disabled, or configured to suit a trade-off between safety and efficiency.

[0066] In some embodiments, the compiler or post-processor adds at least one dedicated program instruction to the program code for use with EDC and inserts the EDC into these instructions. For example, the compiler or post-processor may generate NOP instructions at periodic intervals in the program code. The protection circuit 28 in these embodiments is configured to identify the dedicated instructions and extract the EDC bit from them. For example, the dedicated instruction may contain a No-operation (NOP) command, which is ignored by the processor as defined by ISA instructions, but typically reserves some space for reserved bits, or substantially reserved bits.

[0067] Alternatively, instructions can be configured as "substantially NOP" or "NOP-like" through coordination between the protection circuit 28 and the compiler or post-processor. For example, a processor register can be configured to be unused in the actual program code. The compiler or post-processor can generate instructions for this register at periodic intervals in the program code and insert EDC bits into these instructions. The protection circuit 28 in these embodiments is configured to recognize instructions related to the registers discussed and extract EDC bits from these instructions. Various coordination mechanisms can be used to use dedicated commands for EDC without affecting normal program execution.

[0068] When using "NOP" or "NOP-like" instructions, a hybrid mechanism can also be used, causing the compiler or post-processor to generate "NOP" or "NOP-like" instructions (e.g., at periodic intervals) without inserting the EDC bit. At runtime, the insertion circuit 48 inserts the EDC bit into at least one "NOP" or "NOP-like" instruction generated by the compiler or post-processor.

[0069] The above mechanism is chosen merely as an example. In alternative embodiments, other suitable bit positions can also be used as EDC bits.

[0070] Program overlay via EDC mechanism

[0071] In various embodiments, the EDC mechanisms used by the protection circuit 28 may also be different from each other. For example, the parts of the EDC protection program may also be different from each other.

[0072] For example, in some embodiments, the EDC mechanism is an "internal instruction," meaning that an EDC bit inserted within a given instruction is calculated (and thus protected) by at least one other bit of the same program instruction. For instance, the EDC bit can be calculated (by the compiler, post-processor, or insertion circuit 48) by all other bits in the instruction, or by a predetermined portion of the instruction, for parity checking. In other embodiments, the EDC mechanism spans instruction boundaries; in this sense, a given EDC bit can be calculated (and thus protected) by multiple bits from multiple program instructions.

[0073] In some embodiments, the EDC mechanism can protect an entire code segment, or at least the vast majority of the code. Consider the following example: in one embodiment, the code is divided into multiple segments, and within each segment, a set of at least one EDC bit is inserted (by the compiler, post-processor, or insertion circuit 48). Each set of at least one EDC bit is calculated (and thus protected) by the entire code segment.

[0074] It is understood that for the above mechanism to function properly, each protected program segment should contain a deterministic code flow (in other words, non-data-dependent or otherwise variable or unpredictable). In this document, the term "program segment containing a deterministic code flow" means that the execution of any program segment within the same program segment always follows the same order. The order discussed refers to the instructions used for EDC checks to achieve the purpose of protecting the circuitry. For example, if an EDC check is performed at the output of the extraction unit, it allows the processing pipeline to decode and execute instructions out of order. On the other hand, if extraction is not performed in order, the instructions must be reordered (e.g., through the protection circuitry) before EDC calculation and checking.

[0075] In an exemplary embodiment, this requirement is met by defining each segment as a segment between consecutive jump instructions and / or jump destination instructions. A "jump destination" instruction is the instruction to which a jump instruction in the program code jumps. In other words, at least one EDC bit in each group is calculated (and thus protected) by a program segment that does not traverse any jump or jump destination instructions. In this document, the term "not traversed" does not include the first and last instructions of the segment, as these are typically jump or jump destination instructions.

[0076] In one embodiment, conditional branch instructions, unconditional jump instructions, and return instructions are all treated as jump instructions, with the aim of dividing the program into multiple segments. When segmented in this way, each protected program segment will not traverse any jump or jump destination instructions.

[0077] In some embodiments, at least one EDC bit of any group is calculated (and thus protected) by a separate procedure segment that begins not prior to (but possibly after) the previous hop or hop destination instruction. The separate procedure segment ends not later than (but possibly prior to) the next hop or hop destination instruction.

[0078] To take jump destinations into account, in some embodiments, the compiler (or post-processor) analyzes and annotates various possible jump destination instructions. In various embodiments, various techniques can be used to identify jump destination instructions.

[0079] In one embodiment, a policy can be defined such that the compiler or post-processor guarantees that all jump instructions will jump to a specific type of instruction that is inserted into the program for this purpose (in other words, all jump destination instructions belong to a specific and identifiable type). When using this contract, any jump instruction and the specific type of instruction can be used as instruction boundaries. For example, the policy could instruct all jump destination instructions to be NOP instructions, or instructions that operate on a specific register. As another example, the policy could also instruct the compiler or post-processor to allow jumping only to a subset of addresses (e.g., addresses with N LSBs == 0). "LSB" is an abbreviation for "Least Significant Bit." Alternatively, jump destination instructions can be defined using any suitable contract. Generally, defining redundant jump destination instructions is permissible because this definition rarely results in good program segments being divided into smaller sections. Conversely, the lack of a truly effective jump destination instruction for segmentation is problematic.

[0080] Alternatively, as long as each program segment contains a deterministic bitstream, it can also be divided into multiple segments in other ways.

[0081] In one embodiment, at least one EDC bit from a set is inserted (e.g., by a compiler, post-processor, or insertion circuit 48) into each jump instruction and jump destination instruction, and is calculated (and thus protected) by the entire program segment, starting from the previous jump or jump destination. This mechanism protects the vast majority of the program code.

[0082] In one embodiment, at least one EDC bit from a set is inserted (e.g., by a compiler, post-processor, or insertion circuit 48) into at least one instruction containing a deterministic code stream (e.g., anywhere between consecutive jump instructions or jump destination instructions). The EDC bits within a given segment are calculated (and thus protected) by a plurality of select bits within the program segment, which may include bits in the instruction that appear earlier than the EDC bit and / or later than the EDC bit.

[0083] In another embodiment, a given instruction (e.g., a jump or jump destination instruction that is distributed and adjacent between two program segments) contains two types of EDC bits. The first type of EDC bit is calculated by the instruction itself (and is therefore protected). The second type of EDC bit is calculated by the program segment preceding the jump / jump destination instruction (and is therefore protected).

[0084] In the above embodiments, the protection circuit 28 can use the "JUMP" input of logic 56 (hereinafter also referred to as "EDC check circuit 56") to indicate the starting position of the protected program segment. In these embodiments, the EDC check circuit 56 resets and begins the calculation of each EDC indicated in the "JUMP" input.

[0085] Another possible cause of nondeterministic bitstream is the occurrence of exception handling within processor 20. Therefore, in some embodiments, protection circuit 28 specifies the EDC check circuit 56 in each exception handling step. Figure 1 The EDC check circuit receives the "EXCEPTION" input and exits the exception handling procedure and returns in each exception handling. When the "EXCEPTION" input is indicated, the EDC check circuit suspends the current EDC calculation and pauses error checking until the beginning of the next program segment contains a deterministic bitstream (e.g., until the next "JUMP" input is indicated).

[0086] In some embodiments, when processor 20 is interrupted, protection circuit 28 can record the EDC check status (“CONTEXT”) in the main program. Once the interrupted program finishes execution and the flow returns to execute the main program, protection circuit 28 restarts the EDC check from the point of interruption and stores the recorded status (“CONTEXT”).

[0087] It should be understood that the above embodiments are for illustrative purposes only, and the present invention is not limited to the specific illustrations and descriptions above. Rather, the scope of the present invention includes combinations and sub-combinations of the above features, as well as modifications and variations not disclosed in the prior art that would be apparent to those skilled in the art upon reading the foregoing description. Documents incorporated herein by reference are to be considered part of this application; unless the terms defined in such documents conflict with the express or implied definitions in this application, only the definitions in this specification shall apply.

Claims

1. An apparatus for protecting a processor, the apparatus comprising: The apparatus comprises: an input interface configured to monitor a plurality of program instructions processed by the processor, wherein at least one program instruction of the plurality of program instructions comprises at least one error detection bit; and a protection circuit configured to use the error detection bit to detect an error in a program code and initiate a response action in response to detecting the error; wherein the at least one error detection bit is inserted in at least one bit position designated to represent a jump offset in at least one jump instruction, and the at least one bit position is not executed by the processor, the jump offset having a number of bits greater than actually required by the processor to allow a jump offset; wherein at least one most significant bit of the number of bits is the at least one bit position.

2. The apparatus of claim 1, wherein: wherein the protection circuit is configured to detect a fault injection attack when detecting the error.

3. The apparatus of claim 1, wherein: wherein the at least one error detection bit is inserted in a plurality of reserved bit positions in the at least one program instruction; wherein the protection circuit is configured to extract the error detection bit from the reserved bit positions.

4. The apparatus of claim 1, wherein: wherein, the at least one error detection bit is inserted in a plurality of substantially reserved bit positions in the at least one program instruction, and the plurality of substantially reserved bit positions do not affect execution of the program instruction; wherein the protection circuit is configured to extract the error detection bit from the substantially reserved bit positions.

5. The apparatus of claim 1, wherein: wherein the at least one error detection bit is inserted in at least one special program instruction added to the program code for error detection; wherein the protection circuit is configured to recognize the special program instruction and extract the error detection bit from the special program instruction.

6. The apparatus of claim 1, wherein: wherein the protection circuit is configured to save a definition of positions of the error detection bits in the program instructions, and extract the error detection bits from program instructions according to the definition.

7. The apparatus of claim 1, wherein: wherein a given set of the at least one error detection bit is computed from at least a portion of a given program instruction and inserted in the given program instruction.

8. The apparatus of claim 1, wherein: wherein, a given set of the at least one error detection bit is computed from a plurality of selected bits in the program code; wherein at least one selected bit and the at least one error detection bit in the set are in different program instructions.

9. The apparatus of claim 8, wherein: wherein the plurality of selected bits are confined in a section of the program code comprising a deterministic code stream.

10. The apparatus of claim 8, wherein: wherein, The multiple select bits are confined within a section of the program code that does not traverse the jump instruction or multiple jump destination instructions.

11. The apparatus of claim 1, wherein, Also included are: An insertion circuit configured to insert the at least one error detection bit in the at least one program instruction, the program instruction being provided to the processor for processing.

12. A processor, comprising: Included are: An instruction pipeline configured to fetch and execute a program code, the program code including multiple program instructions, at least one program instruction of the multiple program instructions including at least one error detection bit; And A protection circuit configured to monitor at least the error detection bit among the program instructions, and use the error detection code to detect an error in the program code, and initiate a response action in response to detecting the error; Wherein, in at least one jump instruction, the at least one error detection bit is inserted in at least one bit position designated to represent a jump offset, and the at least one bit position is not executed by the processor, the jump offset having a number of bits greater than actually required by the processor to allow a jump offset; Wherein, at least one most significant bit of the number of bits is the at least one bit position.

13. A method for protecting a processor, the method comprising: The method includes: Monitoring multiple program instructions processed by the processor, at least one program instruction of the multiple program instructions including at least one error detection bit; Using the error detection bit to detect an error in a program code; and Initiating a response action in response to detecting the error; Wherein, in at least one jump instruction, the at least one error detection bit is inserted in at least one bit position designated to represent a jump offset, and the at least one bit position is not executed by the processor, the jump offset having a number of bits greater than actually required by the processor to allow a jump offset; Wherein, at least one most significant bit of the number of bits is the at least one bit position.

14. The method of claim 13, wherein: wherein Detecting the error includes detecting a fault injection attack.

15. The method of claim 13, wherein: wherein The at least one error detection bit is inserted in a reserved bit position in the at least one program instruction; Wherein, monitoring the program instructions includes extracting the error detection bit from the reserved bit position.

16. The method of claim 13, wherein: wherein The at least one error detection bit is inserted in a substantial reserved bit position in the at least one program instruction, and the substantial reserved bit position does not affect execution of the program instruction; Wherein, monitoring the program instructions includes extracting the error detection bit from the substantial reserved bit position.

17. The method of claim 13, wherein: wherein, The at least one error detection bit is inserted in at least one special program instruction, the special program instruction being added to the program code for error detection; Wherein, monitoring the program instructions includes identifying the special program instruction, and extracting the error detection bit from the special program instruction.

18. The method of claim 13, wherein: wherein, monitoring the program instructions includes saving a definition of a location of the error detection bits among the program instructions, and extracting the error detection bits from the program instructions according to the definition.

19. The method of claim 13, wherein: wherein a given set of the at least one error detection bit is computed from at least a portion of a given program instruction and inserted in the given program instruction.

20. The method of claim 13, wherein: wherein, a given set of the at least one error detection bit is computed from a plurality of selected bits in the program code; wherein at least one selected bit and the at least one error detection bit in the set are in different program instructions.

21. The method of claim 20, wherein: wherein, the plurality of selected bits are confined to a section of the program code that includes a deterministic code stream.

22. The method of claim 20, wherein: wherein, the plurality of selected bits are confined to a section of the program code that does not traverse the jump instruction or a plurality of jump destination instructions.

23. The method of claim 13, wherein, further comprising: inserting the at least one error detection bit in the at least one program instruction, the program instruction being provided to the processor for processing.

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