Planarization method

Abstract

This invention discloses a planarization method, comprising the following steps: A substrate is provided. The substrate includes a first region and a second region. A material layer is formed on the substrate. The top surface of the material layer in the first region is lower than the top surface of the material layer in the second region. A patterned photoresist layer is formed on the material layer in the first region. The patterned photoresist layer exposes the top surface of the material layer in the second region. The top surface of the patterned photoresist layer is higher than the top surface of the material layer in the second region. A first etching process is performed on the patterned photoresist layer such that the top surface of the patterned photoresist layer and the top surface of the material layer in the second region have substantially the same height. A second etching process is performed on the patterned photoresist layer and the material layer. In the second etching process, the etching rate of the patterned photoresist layer and the etching rate of the material layer are substantially the same.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor manufacturing process, and more particularly to a planarization method. BACKGROUND

[0002] In a semiconductor manufacturing process, height difference between different device regions can be caused by etching loading effect or different pattern density. Currently, a planarization method commonly used is chemical mechanical polishing. However, even if planarization is performed by a chemical mechanical polishing manufacturing process, due to the influence of polishing loading effect, there will still be a certain degree of height difference between different device regions, which will affect product performance or yield. SUMMARY

[0003] The present invention provides a planarization method which can effectively reduce the height difference between different device regions.

[0004] The present invention provides a planarization method, comprising the following steps. A substrate is provided. The substrate comprises a first region and a second region. A material layer is formed on the substrate. The top surface of the material layer in the first region is lower than the top surface of the material layer in the second region. A patterned photoresist layer is formed on the material layer in the first region. The patterned photoresist layer exposes the top surface of the material layer in the second region. The top surface of the patterned photoresist layer is higher than the top surface of the material layer in the second region. A first etching manufacturing process is performed on the patterned photoresist layer, so that the top surface of the patterned photoresist layer and the top surface of the material layer in the second region have substantially the same height. A second etching manufacturing process is performed on the patterned photoresist layer and the material layer. In the second etching manufacturing process, the etching rate of the patterned photoresist layer and the etching rate of the material layer are substantially the same.

[0005] According to an embodiment of the present invention, in the above planarization method, in the first etching manufacturing process, the etching rate of the patterned photoresist layer can be greater than the etching rate of the material layer.

[0006] According to an embodiment of the present invention, in the above planarization method, the first etching manufacturing process can be a dry etching manufacturing process.

[0007] According to an embodiment of the present invention, in the above planarization method, the gas used in the first etching manufacturing process can include oxygen (O2), sulfur dioxide (SO2), nitrogen (N2), hydrogen (H2), carbon monoxide (CO), carbon dioxide (CO2), or a combination thereof.

[0008] According to an embodiment of the present invention, in the above planarization method, after the second etching manufacturing process is performed, the overall structure height of the first region and the overall structure height of the second region can be substantially the same.

[0009] According to an embodiment of the present application, in the planarization method, the second etching process can be a dry etching process.

[0010] According to an embodiment of the present application, in the planarization method, the second etching process can be a dry etching process.

[0011] According to an embodiment of the present application, in the planarization method, the second etching process can be a non-selective etching process.

[0012] According to an embodiment of the present application, in the planarization method, the gas used in the second etching process can include carbon fluoride (CF4). x F y ).

[0013] According to an embodiment of the present application, in the planarization method, the first region and the second region can be one and the other of a central region and a peripheral region.

[0014] According to an embodiment of the present application, in the planarization method, the central region can be a memory cell region, and the peripheral region can be a peripheral circuit region.

[0015] According to an embodiment of the present application, in the planarization method, before the material layer is formed, the following steps can be further included. A buried word line structure is formed in a substrate of the memory cell region. A bit line structure is formed on the substrate at one side of the buried word line structure. A first hard mask layer is formed on the bit line structure. A first cap layer is formed on the first hard mask layer.

[0016] According to an embodiment of the present application, in the planarization method, before the material layer is formed, the following steps can be further included. A buried word line structure is formed in a substrate of the memory cell region. A bit line structure is formed on the substrate at one side of the buried word line structure. A first hard mask layer is formed on the bit line structure. A first cap layer is formed on the first hard mask layer.

[0017] According to an embodiment of the present application, in the planarization method, before the material layer is formed, the following steps can be further included. A buried word line structure is formed in a substrate of the memory cell region. A bit line structure is formed on the substrate at one side of the buried word line structure. A first hard mask layer is formed on the bit line structure. A first cap layer is formed on the first hard mask layer.

[0018] According to an embodiment of the present application, in the planarization method, the second hard mask layer can be removed by the second etching process.

[0019] According to an embodiment of the present application, in the planarization method, before the material layer is formed, the following steps can be further included. A transistor is formed on a substrate of the peripheral circuit region. The transistor can include a gate and a dielectric layer. The gate is located on the substrate of the memory cell region. The dielectric layer is located between the gate and the substrate. A second hard mask layer is formed on the gate. A second cap layer is formed on the second hard mask layer.

[0020] In one embodiment according to the present application, the top surface of the second cap layer is higher than the top surface of the first cap layer.

[0021] In one embodiment according to the present application, the material layer covers the first cap layer and the second cap layer.

[0022] In one embodiment according to the present application, the planarization method further comprises a second etching process performed on the first cap layer, the second cap layer, the first hard mask layer, and the second hard mask layer.

[0023] In one embodiment according to the present application, the etching rate of the patterned photoresist layer, the etching rate of the material layer, the etching rate of the first cap layer, the etching rate of the second cap layer, the etching rate of the first hard mask layer, and the etching rate of the second hard mask layer are substantially the same in the second etching process.

[0024] Based on the above, in the planarization method according to the present application, the top surface of the patterned photoresist layer and the top surface of the material layer in the second region have substantially the same height after the first etching process. In addition, the etching rate of the patterned photoresist layer and the etching rate of the material layer are substantially the same in the second etching process. Therefore, the planarization method according to the present application can effectively reduce the height difference between the first region and the second region, and thus improve the product performance and / or yield.

[0025] In order to make the features and advantages of the present application more apparent, specific embodiments will be described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figures 1A-1E A cross-sectional view of a planarization process according to one embodiment of the present application;

[0027] Figure 1F A cross-sectional view after removing some of the contact holes in Figure 1E

[0028] SYMBOL DESCRIPTION

[0029] 100: substrate

[0030] 102: isolation structure

[0031] 104: buried wordline structure

[0032] 106: buried wordline

[0033] 108, 138, 146, 148, 150: dielectric layer

[0034] 110: barrier layer​

[0035] 112, 122, 124, 126, 154: top cap layer

[0036] 114: bit line structure

[0037] 116, 128: contact hole

[0038] 118: wire

[0039] 120, 132, 144: hard mask layer

[0040] 130: liner

[0041] 134: transistor

[0042] 136: gate

[0043] 140, 142: conductor layer

[0044] 152: spacer

[0045] 156: material layer

[0046] 158: patterned photoresist layer

[0047] E1: first etch fabrication process

[0048] E2: second etch fabrication process

[0049] H1, H2: overall structure height

[0050] R1: first region

[0051] R2: second region

[0052] TS1 ~ TS7: top surface DETAILED DESCRIPTION

[0053] Figures 1A-1E A cross-sectional view of a planarization flow according to an embodiment of the present application. Figure 1F A cross-sectional view after removing part of the contact holes in Figure 1E A cross-sectional view after removing part of the contact holes in

[0054] Please refer to Figure 1AA substrate 100 is provided. The substrate 100 includes a first region Rl and a second region R2. The first region Rl and the second region R2 can be one and the other of a central region and an edge region, respectively. In some embodiments, the central region and the edge region can be located at the center and the edge of a chip, respectively. In the present embodiment, the first region Rl is exemplified by the central region, and the second region R2 is exemplified by the edge region, but the present application is not limited thereto. In other embodiments, the first region Rl can be the edge region, and the second region R2 can be the central region. In the present embodiment, the central region can be a memory cell region, and the edge region can be a peripheral circuit region, but the present application is not limited thereto. For example, the first region Rl can be a memory cell region to form memory cells (e.g., dynamic random access memory cells (DRAM cells)), and the second region R2 can be a peripheral circuit region to form transistors as logic elements. The substrate 100 is, for example, a semiconductor substrate such as a silicon substrate. Further, an isolation structure 102 can be formed in the substrate 100. The isolation structure 102 can be a single-layer structure or a multi-layer structure. The isolation structure 102 is, for example, a shallow trench isolation (STI). The material of the isolation structure 102 is, for example, silicon oxide.

[0055] A buried word line structure 104 can be formed in the substrate 100 of the first region Rl (e.g., the memory cell region). The buried word line structure 104 can include a buried word line 106 and a dielectric layer 108. The buried word line 106 is located in the substrate 100. The material of the buried word line 106 is, for example, tungsten (W), aluminum (Al), or copper (Cu). The dielectric layer 108 is located between the buried word line 106 and the substrate 100. The material of the dielectric layer 108 is, for example, silicon oxide. Further, the buried word line structure 104 can also include a barrier layer 110. The barrier layer 110 is located between the buried word line 106 and the dielectric layer 108. The material of the barrier layer 110 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. Further, a cap layer 112 can be formed on the buried word line structure 104. The material of the cap layer 112 is, for example, silicon nitride. Further, desired doped regions (not shown) can be formed in the substrate 100 of the first region Rl according to product requirements.

[0056] A bit line structure 114 can be formed on the substrate 100 at one side of the buried word line structure 104. The bit line structure 114 can include a contact window 116 and a conductive line 118. The contact window 116 is located on the substrate 100. The contact window 116 can be used as a bit line contact window. The material of the contact window 116 is, for example, a conductor material such as doped polysilicon. The conductive line 118 is located on the contact window 116. The conductive line 118 can be used as a bit line. The material of the conductive line 118 is, for example, tungsten, aluminum, or copper. In addition, a hard mask layer 120 can be formed on the bit line structure 114. The material of the hard mask layer 120 is, for example, silicon nitride. Further, a cap layer 122 can be formed on the hard mask layer 120. The cap layer 122 can be a single layer structure or a multi-layer structure. In the present embodiment, the cap layer 122 is taken as an example of a multi-layer structure, but the present application is not limited thereto. For example, the cap layer 122 can include a cap layer 124 and a cap layer 126. The cap layer 124 is located on the hard mask layer 120. The material of the cap layer 124 is, for example, silicon oxide. The cap layer 126 is located on the cap layer 124. The material of the cap layer 126 is, for example, silicon oxide.

[0057] A contact window 128 can be formed on the substrate 100 at the other side of the buried word line structure 104. The contact window 128 can be used as a storage node contact window. The material of the contact window 128 is, for example, a conductor material such as doped polysilicon. In addition, a liner layer 130 can be formed between the contact window 128 and the bit line structure 114. The liner layer 130 can be located between the contact window 128 and the conductive line 118. The material of the liner layer 130 is, for example, a dielectric material such as silicon nitride. Further, a hard mask layer 132 can be formed on the contact window 128. The material of the hard mask layer 132 is, for example, silicon nitride.

[0058] A transistor 134 can be formed on the substrate 100 in the second region R2. The transistor 134 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), but the present application is not limited thereto. The transistor 134 can include a gate 136 and a dielectric layer 138. The gate 136 is located on the substrate 100. The gate 136 can be a single layer structure or a multi-layer structure. In the present embodiment, the gate 136 is taken as an example of a multi-layer structure, but the present application is not limited thereto. For example, the gate 136 can include a conductor layer 140 and a conductor layer 142. The conductor layer 140 is located on the substrate 100. The material of the conductor layer 140 is, for example, doped polysilicon. The conductor layer 142 is located on the conductor layer 140. The material of the conductor layer 142 is, for example, tungsten, aluminum, or copper. The dielectric layer 138 is located between the gate 136 and the substrate 100. The material of the dielectric layer 138 is, for example, silicon oxide. The transistor 134 can further include a component such as a doped region (not shown) in the substrate 100.

[0059] A hard mask layer 144 can be formed on the gate 136. The material of the hard mask layer 144 is, for example, silicon nitride. A dielectric layer 146 can be formed on both sides of the gate 136. The dielectric layer 146 can be a single layer structure or a multi-layer structure. In this embodiment, the dielectric layer 146 is taken as an example of a multi-layer structure, but the present application is not limited thereto. For example, the dielectric layer 146 can include a dielectric layer 148 and a dielectric layer 150. The dielectric layer 148 can be located on the dielectric layer 138. The material of the dielectric layer 148 is, for example, silicon oxide. The dielectric layer 150 is located on the dielectric layer 148. The material of the dielectric layer 150 is, for example, silicon oxide. A spacer 152 can be formed between the dielectric layer 146 and the gate 136. The material of the spacer 152 is, for example, silicon nitride. A cap layer 154 can be formed on the hard mask layer 144. Due to the influence of etching loading effect, the top surface TS2 of the cap layer 154 can be higher than the top surface TS1 of the cap layer 122. The material of the cap layer 154 is, for example, silicon oxide.

[0060] Referring to Figure 1B A material layer 156 is formed on the substrate 100. For example, the material layer 156 can cover the cap layer 122 and the cap layer 154. The top surface TS3 of the material layer 156 in the first region R1 is lower than the top surface TS4 of the material layer 156 in the second region R2. In some embodiments, the reason why the top surface TS3 of the material layer 156 in the first region R1 is lower than the top surface TS4 of the material layer 156 in the second region R2 is that it is affected by the topography on the substrate 100. In this embodiment, the material layer 156 can be a dielectric layer, but the present application is not limited thereto. For example, the material of the material layer 156 is, for example, a dielectric material such as silicon nitride. The formation method of the material layer 156 is, for example, chemical vapor deposition.

[0061] Referring to Figure 1C A patterned photoresist layer 158 is formed on the material layer 156 in the first region R1. The patterned photoresist layer 158 exposes the top surface TS4 of the material layer 156 in the second region R2. The top surface TS5 of the patterned photoresist layer 158 is higher than the top surface TS4 of the material layer 156 in the second region R2. The patterned photoresist layer 158 can be formed by a photolithography process.

[0062] Referring to Figure 1DA first etching process E1 is performed on the patterned photoresist layer 158 to make the top surface TS5 of the patterned photoresist layer 158 and the top surface TS4 of the material layer 156 in the second region R2 substantially the same height. The term "substantially" as used herein refers to the existence of "acceptable error values," which are also within the scope of this invention. In the first etching process E1, the etching rate of the patterned photoresist layer 158 may be greater than the etching rate of the material layer 156. In some embodiments, when the height of the patterned photoresist layer 158 is reduced by removing a portion of the patterned photoresist layer 158 through the first etching process E1, the first etching process E1 hardly damages the material layer 156. The first etching process E1 may be a dry etching process. The gas used in the first etching process E1 may include oxygen, sulfur dioxide, nitrogen, hydrogen, carbon monoxide, carbon dioxide, or combinations thereof.

[0063] Please refer to Figure 1E A second etching process E2 is performed on the patterned photoresist layer 158 and the material layer 156. In the second etching process E2, the etching rate of the patterned photoresist layer 158 is substantially the same as that of the material layer 156. Therefore, after a period of time, the second etching process E2 can be removed. Figure 1D The patterned photoresist layer 158 and a portion of the material layer 156 are incorporated, and the material layer 156 in the first region R1 and the material layer 156 in the second region R2 may have substantially the same height, thus achieving planarization. The second etching process E2 may be a dry etching process. The gas used in the second etching process E2 may include fluorinated carbon, such as carbon tetrafluoride.

[0064] In some embodiments, a second etching process E2 can be performed on the cap layer 122, the cap layer 154, the hard mask layer 120, the hard mask layer 144, the hard mask layer 132, the liner layer 130, the contact 128, the dielectric layer 150 and the spacer 152. In the present embodiments, the patterned photoresist layer 158, the material layer 156, the cap layer 122, the cap layer 154, the hard mask layer 120, the hard mask layer 144, the hard mask layer 132, the liner layer 130, the contact 128, the dielectric layer 150 and the spacer 152 can be removed by the second etching process E2, but the present application is not limited thereto. In some embodiments, the second etching process E2 can be a non-selective etching process, which means that the etching rates of all the film layers to be etched are substantially the same. In the second etching process E2 using a non-selective etching process, the etching rate of the patterned photoresist layer 158, the etching rate of the material layer 156, the etching rate of the cap layer 122, the etching rate of the cap layer 154, the etching rate of the hard mask layer 120, the etching rate of the hard mask layer 144, the etching rate of the hard mask layer 132, the etching rate of the liner layer 130, the etching rate of the contact 128, the etching rate of the dielectric layer 150 and the etching rate of the spacer 152 can be substantially the same. In addition, after the second etching process E2 is performed, the overall structure height H1 of the first region R1 and the overall structure height H2 of the second region R2 can be substantially the same, thereby achieving the effect of planarization.

[0065] In addition, in the case that the first region R1 is a dynamic random access memory cell region, the subsequent steps for completing the dynamic random access memory cells (such as the step of forming a capacitor electrically connected to the contact 128, etc.) are well known to those skilled in the art, and the description thereof is omitted herein.

[0066] Based on the above embodiments, in the above planarization method, the top surface TS5 of the patterned photoresist layer 158 and the top surface TS4 of the material layer 156 of the second region R2 can have substantially the same height by the first etching process E1. In addition, in the second etching process E2, the etching rate of the patterned photoresist layer 158 and the etching rate of the material layer 156 are substantially the same. Therefore, the above planarization method of the above embodiments can effectively reduce the height difference between the first region R1 and the second region R2, thereby improving the product performance and / or yield.

[0067] For example, when the planarization method of Figures 1B-1E is applied to the semiconductor structure of Figure 1A , in the first region R1 of Figure 1EIn this context, the top surface TS6 of the contact window 128 near the center of the first region R1 and the top surface TS7 of the contact window 128 near the edge of the first region R1 (i.e., near the second region R2) can have substantially the same height. Therefore, as Figure 1F As shown, after the etching process (e.g., dry etching process) to remove part of the contact window 128, the top surface TS6 of the contact window 128 near the center of the first region R1 and the top surface TS7 of the contact window 128 near the edge of the first region R1 can still have substantially the same height. This avoids the problem of uneven height of the contact window 128, thereby improving product performance and / or yield. Furthermore, when the first etching process E1, the second etching process E2, and the etching process for removing part of the contact window 128 are all dry etching processes, the above etching processes can be performed on the same etching machine. Therefore, defects caused by particulate contamination during wafer transfer between different machines can be prevented, and costs can be reduced.

[0068] Furthermore, although the planarization method described in the above embodiments is applied to... Figure 1A The invention is illustrated using a semiconductor structure as an example, but is not limited thereto. In other embodiments, the planarization method described above can be applied to other semiconductor structures.

[0069] In summary, in the planarization method of the above embodiments, the height difference between different component areas can be reduced by the first etching process and the second etching process, thereby improving product performance and / or yield.

[0070] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A planarization method, comprising: providing a substrate, wherein the substrate comprises a first region and a second region; forming a material layer on the substrate, wherein a top surface of the material layer in the first region is lower than a top surface of the material layer in the second region; forming a patterned photoresist layer on the material layer in the first region, wherein the patterned photoresist layer exposes a top surface of the material layer in the second region, and a top surface of the patterned photoresist layer is higher than the top surface of the material layer in the second region; performing a first etching process on the patterned photoresist layer to remove a portion of the patterned photoresist layer such that a thinned top surface of the patterned photoresist layer is substantially the same height as the top surface of the material layer in the second region, wherein an etch rate of the patterned photoresist layer is greater than an etch rate of the material layer during the first etching process; and performing a second etching process on the thinned patterned photoresist layer and the material layer, wherein the etch rate of the thinned patterned photoresist layer is substantially the same as the etch rate of the material layer during the second etching process.

2. The planarization method of claim 1, wherein the etch rate of the patterned photoresist layer is greater than the etch rate of the material layer during the first etching process.

3. The planarization method of claim 1, wherein the first etching process comprises a dry etching process.

4. The planarization method of claim 1, wherein a gas used in the first etching process comprises oxygen, sulfur dioxide, nitrogen, hydrogen, carbon monoxide, carbon dioxide, or a combination thereof.

5. The planarization method of claim 1, wherein a total structure height of the first region is substantially the same as a total structure height of the second region after performing the second etching process.

6. The planarization method of claim 1, wherein the thinned patterned photoresist layer is removed by the second etching process.

7. The planarization method of claim 1, wherein the second etching process comprises a dry etching process.

8. The planarization method of claim 1, wherein the second etching process comprises a non-selective etching process.

9. The planarization method of claim 1, wherein a gas used in the second etching process comprises carbon fluoride.

10. The planarization method of claim 1, wherein the first region and the second region are one of a central region and an edge region, respectively.

11. The planarization method of claim 10, wherein the central region comprises a memory cell region, and the edge region comprises a peripheral circuit region.

12. The planarization method of claim 11, further comprising, prior to forming the material layer, the steps of: forming a buried wordline structure in the substrate in the memory cell region; forming a bitline structure on the substrate on a side of the buried wordline structure; forming a first hardmask layer on the bitline structure; and ​ ​ forming a first top cap layer over the first hard mask layer.

13. The planarization method of claim 12, further comprising: forming a contact window in the substrate on another side of the buried bitline structure prior to forming the material layer.

14. The planarization method of claim 13, further comprising: forming a second hard mask layer over the contact window prior to forming the material layer.

15. The planarization method of claim 14, wherein the second hard mask layer is removed by the second etching fabrication process.

16. The planarization method of claim 12, further comprising, prior to forming the material layer, the steps of: forming a transistor in the substrate in the peripheral circuit region, wherein the transistor comprises: a gate over the substrate; and a dielectric layer between the gate and the substrate; forming a second hard mask layer over the gate; and forming a second top cap layer over the second hard mask layer.

17. The planarization method of claim 16, wherein a top surface of the second top cap layer is higher than a top surface of the first top cap layer.

18. The planarization method of claim 16, wherein the material layer covers the first top cap layer and the second top cap layer.

19. The planarization method of claim 16, further comprising subjecting the first top cap layer, the second top cap layer, the first hard mask layer, and the second hard mask layer to the second etching fabrication process.

20. The planarization method of claim 19, wherein an etch rate of the thinned patterned photoresist layer, an etch rate of the material layer, an etch rate of the first top cap layer, an etch rate of the second top cap layer, an etch rate of the first hard mask layer, and an etch rate of the second hard mask layer are substantially the same in the second etching fabrication process. ​

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