An N-sided GaN-based p- and n-channel device integrated structure and its manufacturing method

Abstract

The present invention discloses an integrated structure of an N-face GaN-based p-channel and n-channel device and a preparation method thereof, including: providing a first substrate and growing an epitaxial structure; removing the p-GaN layer in a first preset area and etching a first groove in a second preset area; depositing a SiN layer on the surface of the p-GaN layer; bonding a second substrate on the surface of the SiN layer, flipping the sample and etching away the first substrate and the GaN buffer layer; etching an electrically isolated area, an n-channel device active area and a p-channel device active area; fabricating source and drain electrodes of the n-channel device and the p-channel device; etching the GaN layer of the n-channel device to form a second groove and depositing Al2O3; removing the Al2O3 outside the n-channel device and fabricating gate electrodes of the n-channel device and the p-channel device; growing a SiN protection layer, and leading out electrodes after photolithographing an opening area of a metal interconnection layer. The present invention can improve the carrier mobility of the channel, and further improve the electrical characteristics of the p-channel device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to an N-face GaN-based p-channel and n-channel device integrated structure and a preparation method thereof. Background Art

[0002] As a wide-bandgap semiconductor, GaN has excellent material quality factors, making it the first choice for next-generation high-efficiency power devices and power electronic devices. For traditional power devices, their external driving is mainly realized by a driving circuit made of silicon materials. The interconnection between different materials will introduce additional parasitic effects, affecting the device working efficiency, and at the same time may cause the device to turn on incorrectly, etc. Therefore, the research and development of GaN-based driving circuits are needed. Currently, HEMT devices based on Ga-face GaN-based materials are still in the mainstream. When preparing p-channel devices from Ga-face GaN, the GaN / AlGaN heterojunction has its polarization characteristics, resulting in a two-dimensional hole gas channel on the GaN side. The channel closer to the gate will cause a larger off-state current in the device. Therefore, it is necessary to deposit an insulating medium (such as Al2O3) under the gate to reduce the off-state current. However, the deposited insulating layer will introduce problems such as fixed charges and interface charges with the material, introducing Coulomb scattering, thereby affecting the carrier mobility of p-channel devices and degrading the device characteristics. Summary of the Invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides an N-face GaN-based p-channel and n-channel device integrated structure and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0004] In a first aspect, the present invention provides a preparation method for an N-face GaN-based p-channel and n-channel device integrated structure, including:

[0005] Providing a first substrate, and growing an epitaxial structure on the surface of the first substrate, the epitaxial structure including a GaN buffer layer, a GaN layer, an AlGaN barrier layer, and a p-GaN layer sequentially grown on the surface of the first substrate, the epitaxial structure including a first preset region and a second preset region;

[0006] Removing the p-GaN layer in the first preset region by etching, and etching the surface of the p-GaN layer on the side away from the AlGaN barrier layer in the second preset region to form a first groove;

[0007] Depositing and forming a SiN layer on the surface of the p-GaN layer on the side away from the AlGaN barrier layer, and at least part of the SiN layer is in contact with the surface of the GaN layer on the side away from the GaN buffer layer;

[0008] A second substrate is bonded to the surface of the SiN layer on the side away from the first substrate. After flipping the sample in a direction perpendicular to the plane of the first substrate, the first substrate and the GaN buffer layer are etched away.

[0009] At least a part of the GaN layer, the AlGaN barrier layer, the p-GaN layer, and the SiN layer on the side of the second preset region close to the first preset region are etched to form an electrically isolated region, and an n-channel device active region and a p-channel device active region respectively located on both sides of the electrically isolated region.

[0010] After fabricating a first source electrode and a first drain electrode on the surface of the GaN layer of the n-channel device on the side away from the AlGaN barrier layer, the GaN layer and at least a part of the AlGaN barrier layer of the p-channel device are etched, and a second source electrode and a second drain electrode are fabricated on the side of the p-GaN layer away from the second substrate.

[0011] The surface of the GaN layer of the n-channel device on the side away from the AlGaN barrier layer is etched to form a second groove, and Al2O3 is deposited on the surfaces of the n-channel device and the p-channel device on the side away from the second substrate.

[0012] The Al2O3 covering the area outside the n-channel device is etched away, and a third groove is etched on the surface of the AlGaN barrier layer of the p-channel device on the side away from the second substrate, and then a first gate electrode of the n-channel device and a second gate electrode of the p-channel device are fabricated.

[0013] A SiN protective layer is grown on the surfaces of the n-channel device and the p-channel device on the side away from the second substrate. After lithographically opening the metal interconnection layer region on the SiN protective layer, the first source electrode, the first drain electrode, the first gate electrode, the second source electrode, the second drain electrode, and the second gate electrode are led out, and the first drain electrode is electrically connected to the second drain electrode to obtain the N-face GaN-based p-channel and n-channel device integrated structure.

[0014] In an embodiment of the present invention, before the step of bonding and forming the second substrate on the surface of the SiN layer on the side away from the first substrate, the following steps are further included:

[0015] The surface of the SiN layer on the side away from the first substrate is polished by a chemical mechanical polishing process.

[0016] In an embodiment of the present invention, the step of etching away the first substrate and the GaN buffer layer after flipping the sample in a direction perpendicular to the plane of the first substrate includes:

[0017] After flipping the sample in a direction perpendicular to the plane of the first substrate, etch away the first substrate under the conditions that the upper electrode power is 250 - 350 W, the lower electrode power is 20 - 40 W, the pressure is 5 mTorr, and the SF6 flow rate is 50 sccm.

[0018] Under the conditions that the upper electrode power is 40 - 60 W, the lower electrode power is 20 - 30 W, the pressure is 5 mTorr, the Cl2 flow rate is 8 sccm, and the BCl3 flow rate is 20 sccm, etch away the GaN buffer layer.

[0019] In an embodiment of the present invention, the second preset region includes a sub-region close to the first preset region;

[0020] The step of etching at least a part of the GaN layer, AlGaN barrier layer, p-GaN layer, and SiN layer on the side of the second preset region close to the first preset region to form an electrically isolated region, and an n-channel device active region and a p-channel device active region located on both sides of the electrically isolated region respectively, includes:

[0021] Apply and spin-coat photoresist on the sample;

[0022] Put the sample into a lithography machine, expose the photoresist in the sub-region, and put the exposed sample into a developer to remove the photoresist in the sub-region;

[0023] Use inductively coupled plasma ICP process to etch the GaN layer, AlGaN barrier layer, and p-GaN layer in the sub-region in sequence to achieve mesa isolation of the active region, and form an electrically isolated region, and an n-channel device active region and a p-channel device active region located on both sides of the electrically isolated region respectively.

[0024] In an embodiment of the present invention, the step of etching the surface of the GaN layer on the side of the n-channel device away from the AlGaN barrier layer to form a second groove, and depositing Al2O3 on the surface of the n-channel device and the p-channel device away from the second substrate, includes:

[0025] Under the conditions that the upper electrode power is 15 - 25 W, the lower electrode power is 3 - 5 W, the pressure is 5 mTorr, the Cl2 flow rate is 4 sccm, and the BCl3 flow rate is 10 sccm, etch the surface of the GaN layer on the side of the n-channel device away from the AlGaN barrier layer to form a second groove;

[0026] Use atomic layer deposition ALD technology to deposit Al2O3 with a thickness of 20 nm on the surface of the n-channel device and the p-channel device away from the second substrate.

[0027] In one embodiment of the present invention, the second groove includes a first surface parallel to the first substrate;

[0028] Wherein, along the direction perpendicular to the plane where the first substrate is located, the distance between the first surface and the AlGaN barrier layer is 10 nm.

[0029] In one embodiment of the present invention, the step of etching to remove the Al2O3 covering outside the n-channel device and etching to form a third groove on the surface of the AlGaN barrier layer of the p-channel device away from the second substrate, and then fabricating the first gate electrode of the n-channel device and the second gate electrode of the p-channel device includes:

[0030] Under the conditions of an upper electrode power of 100 - 200 W, a lower electrode power of 30 - 40 W, a pressure of 10 mTorr, and a CF4 flow rate of 45 sccm, etch to remove the Al2O3 covering outside the n-channel device, exposing the AlGaN barrier layer, the second source electrode, the second drain electrode in the p-channel device, and the first source electrode and the first drain electrode in the n-channel device;

[0031] Under the conditions of an upper electrode power of 15 - 25 W, a lower electrode power of 3 - 5 W, a pressure of 5 mTorr, a Cl2 flow rate of 4 sccm, and a BCl3 flow rate of 10 sccm, etch to form a third groove on the surface of the AlGaN barrier layer of the p-channel device away from the second substrate;

[0032] Fabricate the first gate electrode of the n-channel device and the second gate electrode of the p-channel device.

[0033] In one embodiment of the present invention, along the direction perpendicular to the plane where the first substrate is located, the orthographic projection of the first groove coincides with the orthographic projection of the third groove.

[0034] In a second aspect, the present invention further provides an N-face GaN-based p-n channel device integrated structure, which is obtained by the preparation method of the N-face GaN-based p-n channel device integrated structure described in the first aspect above.

[0035] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0036] The present invention provides an integrated structure of N-face GaN-based p- and n-channel devices and a preparation method thereof. Since an N-face AlGaN / GaN heterojunction is used to prepare the p-channel device, and there is an AlGaN barrier layer on the upper layer of the GaN channel, which can play a role in blocking the gate leakage current, the insulating medium such as Al2O3 between the gate metal and the p-GaN channel can be omitted during the preparation process. Furthermore, problems such as the fixed charges introduced by the deposited insulating layer and the interface charges between the materials are avoided, improving the mobility of the p-channel device. In addition, the GaN-based n-channel device prepared from the N-face GaN-based material has more advantages in high frequency compared with the Ga-face n-channel device. Therefore, the preparation of an N-face n-channel enhancement device using a recessed MIS structure also has good characteristics. The integration of the N-face enhancement n-channel device and the p-channel device enables the realization of a GaN-based complementary logic structure.

[0037] The following will further elaborate on the present invention in detail with reference to the drawings and embodiments. Description of the Drawings

[0038] Figure 1 is a flowchart of a preparation method of an integrated structure of N-face GaN-based p- and n-channel devices provided by an embodiment of the present invention;

[0039] Figure 2 is a schematic diagram of a preparation method of an integrated structure of N-face GaN-based p- and n-channel devices provided by an embodiment of the present invention;

[0040] Figure 3 is another schematic diagram of a preparation method of an integrated structure of N-face GaN-based p- and n-channel devices provided by an embodiment of the present invention;

[0041] Figure 4 is another schematic diagram of a preparation method of an integrated structure of N-face GaN-based p- and n-channel devices provided by an embodiment of the present invention;

[0042] Figure 5 is another schematic diagram of a preparation method of an integrated structure of N-face GaN-based p- and n-channel devices provided by an embodiment of the present invention;

[0043] Figure 6 is another schematic diagram of a preparation method of an integrated structure of N-face GaN-based p- and n-channel devices provided by an embodiment of the present invention;

[0044] Figure 7 is another schematic diagram of a preparation method of an integrated structure of N-face GaN-based p- and n-channel devices provided by an embodiment of the present invention;

[0045] Figure 8 is another schematic diagram of a preparation method of an integrated structure of N-face GaN-based p- and n-channel devices provided by an embodiment of the present invention;

[0046] Figure 9 It is another schematic diagram of the preparation method of the N-face GaN-based p- and n-channel device integrated structure provided by the embodiments of the present invention;

[0047] Figure 10 It is another schematic diagram of the preparation method of the N-face GaN-based p- and n-channel device integrated structure provided by the embodiments of the present invention;

[0048] Figure 11 It is another schematic diagram of the preparation method of the N-face GaN-based p- and n-channel device integrated structure provided by the embodiments of the present invention;

[0049] Figure 12 It is another schematic diagram of the preparation method of the N-face GaN-based p- and n-channel device integrated structure provided by the embodiments of the present invention;

[0050] Figure 13 It is another schematic diagram of the preparation method of the N-face GaN-based p- and n-channel device integrated structure provided by the embodiments of the present invention;

[0051] Figure 14 It is another schematic diagram of the preparation method of the N-face GaN-based p- and n-channel device integrated structure provided by the embodiments of the present invention;

[0052] Figure 15 It is another schematic diagram of the preparation method of the N-face GaN-based p- and n-channel device integrated structure provided by the embodiments of the present invention. Detailed implementation manners

[0053] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0054] Figure 1 It is a flowchart of the preparation method of the N-face GaN-based p- and n-channel device integrated structure provided by the embodiments of the present invention, Figures 2 - 15 It is a schematic diagram of the preparation method of the N-face GaN-based p- and n-channel device integrated structure provided by the embodiments of the present invention. Please refer to Figures 1 - 15 , the embodiments of the present invention provide a preparation method of an N-face GaN-based p- and n-channel device integrated structure, including:

[0055] S1. Provide a first substrate, and grow an epitaxial structure on the surface of the first substrate. The epitaxial structure includes a GaN buffer layer, a GaN layer, an AlGaN barrier layer, and a p-GaN layer that are sequentially grown on the surface of the first substrate. The epitaxial structure includes a first preset region and a second preset region;

[0056] S2. Remove the p-GaN layer within the first preset region by etching, and etch the surface of the p-GaN layer on the side away from the AlGaN barrier layer within the second preset region to form a first groove 10;

[0057] S3. Deposit an SiN layer on the surface of the p-GaN layer on the side away from the AlGaN barrier layer, and at least part of the SiN layer is in contact with the surface of the GaN layer on the side away from the GaN buffer layer;

[0058] S4. Bond a second substrate on the surface of the SiN layer on the side away from the first substrate, and after flipping the sample in the direction perpendicular to the plane where the first substrate is located, etch away the first substrate and the GaN buffer layer;

[0059] S5. Etch at least part of the GaN layer, AlGaN barrier layer, p-GaN layer, and SiN layer in the second preset region near the first preset region to form an electrically isolated region, and an n-channel device active region and a p-channel device active region located on both sides of the electrically isolated region respectively;

[0060] S6. After fabricating a first source electrode and a first drain electrode on the surface of the GaN layer on the side away from the AlGaN barrier layer in the n-channel device, etch the GaN layer and at least part of the AlGaN barrier layer of the p-channel device, and fabricate a second source electrode and a second drain electrode on the side of the p-GaN layer away from the second substrate;

[0061] S7. Etch the surface of the GaN layer on the side away from the AlGaN barrier layer in the n-channel device to form a second groove 20, and deposit Al2O3 on the surface of the n-channel device and the p-channel device on the side away from the second substrate;

[0062] S8. Etch away the Al2O3 covering outside the n-channel device, and after etching a third groove 40 on the surface of the AlGaN barrier layer of the p-channel device on the side away from the second substrate, fabricate a first gate electrode G1 for the n-channel device and a second gate electrode G2 for the p-channel device;

[0063] S9. Grow an SiN protective layer on the surface of the n-channel device and the p-channel device on the side away from the second substrate, and after lithographically opening a metal interconnection layer region on the SiN protective layer, lead out the first source electrode, the first drain electrode, the first gate electrode G1, the second source electrode, the second drain electrode, and the second gate electrode G2, and electrically connect the first drain electrode D1 and the second drain electrode D2 to obtain an N-face GaN-based p- and n-channel device integrated structure.

[0064] In this embodiment, the first substrate may be a Si substrate, and an epitaxial structure is grown on the surface of the first substrate by using the MOCVD (Metal-organic Chemical Vapor Deposition) method. Optionally, in Figure 2 From the perspective shown, the epitaxial structure from bottom to top is a GaN buffer layer, a GaN layer, an AlGaN barrier layer, and a p-GaN layer in sequence.

[0065] Specifically, in step S2, the sample is baked at 200 °C for 5 minutes, and then placed on a spin coater. EPI621 photoresist is dropped on the surface of the first substrate of the sample. When spin coating, the glue can be spun at a speed of 500 rpm / min for 5 seconds first, and then spun at a speed of 3500 rpm / min for 40 seconds, and then baked at 90 °C for 60 seconds; then, the sample is exposed, developed, rinsed with ultrapure water, and dried with nitrogen. Further, under the conditions of an upper electrode power of 40 - 60 W, a lower electrode power of 10 - 20 W, a pressure of 5 mTorr, and a Cl2 / BCl3 flow rate of 8 / 20 sccm, the surface of the p-GaN layer on the side away from the AlGaN barrier layer is etched using chlorine-based ICP to form a first groove 10 in the second preset region; optionally, along the direction perpendicular to the plane where the first substrate is located, the remaining thickness of the p-GaN layer at the first groove 10 is about 10 - 30 nm.

[0066] It should be noted that in this embodiment, the p-GaN layer in the first preset region is also removed by photolithography and etching processes, and the etching conditions are the same as those for etching the first groove 10 above, so details are not repeated here.

[0067] In step S3, using the plasma-enhanced chemical vapor deposition PECVD process, SiN is deposited on the surface of the p-GaN layer on the side away from the AlGaN barrier layer. As Figure 4 shown, the SiN layer fills the first groove 10, and within the range of the first preset region, the SiN layer contacts the surface of the GaN layer on the side away from the GaN buffer layer. Further, a second substrate is bonded to the surface of the SiN layer away from the first substrate, and then the sample is flipped along the direction perpendicular to the plane where the first substrate is located, that is, Figure 5 from the perspective shown, the sample is flipped up and down, and then the first substrate and the GaN buffer layer are etched away in sequence.

[0068] Please continue to refer to Figure 7 , in the above step S5, the position in the second preset region close to the first preset region is etched to form an electrical isolation region. Then Figure 7 the right part of the electrical isolation region in Figures 8 - 9As shown, the source and drain electrodes of the n-channel device and the p-channel device are fabricated respectively. The first source electrode and the first drain electrode of the n-channel device are oppositely disposed on one surface of the GaN layer away from the AlGaN barrier layer, and the second source electrode and the second drain electrode of the p-channel device are oppositely disposed on one side of the p-GaN layer away from the second substrate.

[0069] Please refer to Figures 10 - 13 , after the source and drain electrodes of the n- and p-channel devices are fabricated, the surface of the GaN layer on the side of the n-channel device away from the AlGaN barrier layer is subjected to groove etching to obtain the second groove 20. Then, aluminum oxide 30 is deposited on the surfaces of the n-channel device and the p-channel device. Next, the aluminum oxide 30 on the surface of the GaN layer on the side of the n-channel device away from the AlGaN barrier layer is retained, the aluminum oxide 30 in other regions is etched away, and the third groove 40 is etched on the surface of the AlGaN barrier layer on the side of the p-channel device away from the second substrate, thereby obtaining the gate groove of the p-channel device.

[0070] Furthermore, as Figures 14 - 15 shown, the gate electrodes of the n- and p-channel devices are fabricated simultaneously, and then the SiN protective layer is grown. After photolithographing the opening area of the metal interconnection layer on the SiN protective layer, each electrode is led out, and the first drain electrode D1 is electrically connected to the second drain electrode D2, thereby obtaining the N-face GaN-based p- and n-channel device integrated structure.

[0071] It should be understood that since the N-face GaN-based HFET p-channel device has an AlGaN layer, the insulating medium such as Al2O3 between the gate metal and the p-GaN channel can be omitted in the manufacturing process, so that problems such as fixed charges introduced by the deposited insulating layer and interface charges between materials can be avoided, thereby improving the mobility of the p-channel device. At the same time, the n-channel enhancement-mode device with a groove MIS structure fabricated on the N-face also has good characteristics. The integration of the enhancement-mode n-channel device and the p-channel device enables the realization of a complementary logic structure.

[0072] Optionally, before the step of bonding and forming the second substrate on the surface of the SiN layer away from the first substrate, it further includes:

[0073] Polishing the surface of the SiN layer away from the first substrate by a chemical mechanical polishing process.

[0074] In this embodiment, before bonding the second substrate, the upper surface of the SiN layer away is polished by a chemical mechanical polishing process first. This design method can make the surface of the SiN layer in contact with the second substrate smoother, thereby avoiding unstable bonding between the second substrate and the SiN layer and preventing the second substrate from falling off due to unstable bonding when the sample is flipped later.

[0075] Please continue to refer to Figure 6, in step S4 above, after flipping the sample in a direction perpendicular to the plane of the first substrate, the steps of etching away the first substrate and the GaN buffer layer include:

[0076] S401. After flipping the sample in a direction perpendicular to the plane of the first substrate, under the conditions of an upper electrode power of 250 - 350 W, a lower electrode power of 20 - 40 W, a pressure of 5 mTorr, and an SF6 flow rate of 50 sccm, etch away the first substrate;

[0077] S402. Under the conditions of an upper electrode power of 40 - 60 W, a lower electrode power of 20 - 30 W, a pressure of 5 mTorr, a Cl2 flow rate of 8 sccm, and a BCl3 flow rate of 20 sccm, etch away the GaN buffer layer.

[0078] Please refer to Figures 5 - 7 , the second preset region includes a sub-region close to the first preset region;

[0079] In step S5 above, the steps of etching at least a part of the GaN layer, AlGaN barrier layer, p-GaN layer, and SiN layer on the side close to the first preset region in the second preset region to form an electrically isolated region, and an n-channel device active region and a p-channel device active region located on both sides of the electrically isolated region respectively, include:

[0080] S501. Apply and spin the photoresist on the sample;

[0081] S502. Place the sample in a lithography machine, expose the photoresist in the sub-region, and then place the exposed sample in a developer to remove the photoresist in the sub-region;

[0082] S503. Use inductively coupled plasma (ICP) process to etch the GaN layer, AlGaN barrier layer, and p-GaN layer in the sub-region in sequence to achieve mesa isolation of the active region, and form an electrically isolated region, and an n-channel device active region and a p-channel device active region located on both sides of the electrically isolated region respectively.

[0083] Specifically, first bake the sample on a hot plate at 200 °C, apply and spin the photoresist, then bake the sample on a hot plate at 90 °C, where the spin speed for spinning the photoresist can be 3500 revolutions per minute; then, after placing the sample in a lithography machine to expose the photoresist in the sub-region, place the exposed sample in a developer to remove the photoresist in the electrically isolated region, and rinse it with ultrapure water and dry it with nitrogen.

[0084] Further, the sub-region after lithography is etched. First, the GaN layer, AlGaN barrier layer, p-GaN layer, and SiN layer in the sub-region are etched in sequence using the ICP process to achieve mesa isolation of the active region; then, the sample is successively placed in acetone solution, stripping solution, acetone solution, and ethanol solution for cleaning to remove the photoresist outside the electrically isolated region; finally, the sample is rinsed with ultrapure water and dried with nitrogen gas.

[0085] Please continue to refer to Figures 8 - 10 , after fabricating the first source electrode and the first drain electrode on the surface of the GaN layer far from the AlGaN barrier layer in the n-channel device, etching the GaN layer and at least part of the AlGaN barrier layer of the p-channel device, and fabricating the second source electrode and the second drain electrode on the side of the p-GaN layer far from the second substrate, the steps include:

[0086] S601. Lithograph the first source electrode region and the first drain electrode region:

[0087] First, place the sample on a hot plate at 200 °C for baking, apply and spin-coat the stripping glue on the GaN layer. Optionally, spin-coat the glue at a speed of 2000 rpm for 40 s, and the spin-coating thickness is 0.35 μm, then bake the sample on the hot plate again; then, apply and spin-coat the EPI621 photoresist on the stripping glue, spin-coat the glue at a speed of 5000 rpm for 30 s, and the spin-coating thickness is 0.77 μm, and then bake it with the hot plate; place the sample with the glue applied and spin-coated into a lithography machine, and expose the photoresist in the first source electrode region and the first drain electrode region; finally, place the exposed sample in a developer solution to remove the photoresist and stripping glue in the first source electrode region and the first drain electrode region, rinse it with ultrapure water, and dry it with nitrogen gas.

[0088] S602. Evaporate the first source electrode S1 and the first drain electrode D1:

[0089] First, place the sample with the lithography patterns of the first source electrode and the first drain electrode into an α-plasma plasma asher for treatment, and then place the sample into an electron beam evaporation station. Wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6After reaching Torr, ohmic metal is evaporated on the GaN cap layer within the first source electrode region and the first drain electrode region, as well as on the photoresist outside the first source electrode region and the first drain electrode region. The ohmic metal can be a metal stack structure composed of four layers of metals, Ti / Al / Ni / Au, from bottom to top in sequence; then, the sample after the evaporation of the ohmic metal is subjected to lift-off to remove the ohmic metal, photoresist, and lift-off glue outside the first source electrode region and the first drain electrode region, and is rinsed with ultrapure water and dried with nitrogen; finally, the sample is placed in a rapid annealing furnace for annealing treatment to form the first source electrode S1 and the first drain electrode D1; optionally, the annealing atmosphere is N2, the annealing temperature is 800 - 860 °C, and the annealing time is 30 - 60 s.

[0090] S603. Etch the GaN layer of the p-channel device:

[0091] After baking the sample on a hot plate at 200 °C, spin coating and spinning of the photoresist are carried out, and the spinning speed is 3500 rpm, and the sample is baked on a hot plate at 90 °C; then, the sample is placed in a lithography machine to expose the photoresist in a partial area of the p-channel device, and the sample after exposure is placed in a developer to remove the photoresist within the electrically isolated region, and it is rinsed with ultrapure water and dried with nitrogen; then, the GaN layer of the developed region is etched successively until the AlGaN layer by using ICP process. The etching conditions can be: the power of the upper electrode is 15 - 25 W, the power of the lower electrode is 3 - 5 W, the pressure is 5 mTorr, the flow rate of Cl2 is 4 sccm, and the flow rate of BCl3 is 10 sccm; the sample is successively placed in acetone solution, stripping solution, acetone solution, and ethanol solution for cleaning to remove the photoresist outside the electrically isolated region, and finally the sample is rinsed with ultrapure water and dried with nitrogen.

[0092] S604. Etch at least a part of the AlGaN barrier layer of the p-channel device:

[0093] First, bake the sample on a hot plate at 200 °C; then, apply and spin coat the photoresist, with a spin coating speed of 3500 rpm, and bake the sample on a hot plate at 90 °C; next, place the sample in a lithography machine to expose the photoresist in the source and drain partial regions of the p-channel device, then place the exposed sample in a developer to remove the photoresist in the electrically isolated region, and rinse it with ultrapure water and dry it with nitrogen. Further, use the ICP process to etch the AlGaN layer in the developed region until the p-GaN layer, with an etching depth of approximately 20 nm. The etching conditions can be: upper electrode power 15 - 25 W, lower electrode power 3 - 5 W, pressure 5 mTorr, Cl2 flow rate 4 sccm, BCl3 flow rate 10 sccm; after that, place the sample in acetone solution, stripping solution, acetone solution, and ethanol solution in sequence for cleaning to remove the photoresist outside the electrically isolated region, and then rinse the sample with ultrapure water and dry it with nitrogen.

[0094] S605. Lithograph the second source electrode region and the second drain electrode region:

[0095] First, bake the sample on a hot plate at 200 °C, apply and spin coat the stripping resist on the sample. Optionally, spin coat at a speed of 2000 rpm for 40 s with a spin coating thickness of 0.35 μm, and then bake the sample on a 200 °C hot plate for 5 min; then, apply and spin coat the EPI621 photoresist on the stripping resist, spin coat at a speed of 5000 rpm for 30 s with a spin coating thickness of 0.77 μm, and then bake on a 900 °C hot plate for 1 min; place the sample after applying and spin coating in a lithography machine to expose the photoresist in the second source electrode region and the second drain electrode region; place the exposed sample in a developer to remove the photoresist and the stripping resist in the second source electrode region and the second drain electrode region, and rinse it with ultrapure water and dry it with nitrogen.

[0096] S606. Evaporate the second source electrode S2 and the second drain electrode D2:

[0097] First, place the sample with the second source electrode lithography pattern and the second drain electrode lithography pattern in an α - plasma plasma asher for treatment, and then place the sample in an electron beam evaporation station. Wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6After Torr, ohmic metal is evaporated on the GaN cap layer in the second source electrode region and the second drain electrode region, as well as on the photoresist outside the second source electrode region and the second drain electrode region. The ohmic metal can be a metal stack structure composed of four layers of metals, namely Ti / Al / Ni / Au, from bottom to top in sequence; then, the sample after the evaporation of the ohmic metal is subjected to lift-off to remove the ohmic metal, the photoresist and the lift-off glue outside the second source electrode region and the second drain electrode region, and is rinsed with ultrapure water and dried with nitrogen; finally, the sample is placed in a rapid annealing furnace for annealing treatment to form the second source electrode S2 and the second drain electrode D2; exemplarily, the annealing atmosphere is O2, the annealing temperature is 500 - 550 °C, and the annealing time is 5 - 10 min.

[0098] In the above step S7, the step of etching the surface of the GaN layer on the side of the n-channel device away from the AlGaN barrier layer to form the second groove 20 and depositing Al2O3 on the surface of the n-channel device and the p-channel device on the side away from the second substrate includes:

[0099] Under the conditions of an upper electrode power of 15 - 25 W, a lower electrode power of 3 - 5 W, a pressure of 5 mTorr, a Cl2 flow rate of 4 sccm, and a Bl3 flow rate of 10 sccm, the surface of the GaN layer on the side of the n-channel device away from the AlGaN barrier layer is etched to form the second groove 20;

[0100] Using atomic layer deposition (ALD) technology, Al2O3 with a thickness of 20 nm is deposited on the surface of the n-channel device and the p-channel device on the side away from the second substrate.

[0101] In this embodiment, the second groove 20 includes a first surface parallel to the first substrate; wherein, along the direction perpendicular to the plane where the first substrate is located, the distance between the first surface and the AlGaN barrier layer is 10 nm; that is to say, the GaN layer in the n-channel device is etched until about 10 nm remains.

[0102] Optionally, in the above step S8, after etching away the Al2O3 covering outside the n-channel device and etching to form a third groove 40 on the surface of the AlGaN barrier layer of the p-channel device on the side away from the second substrate, the step of fabricating the first gate electrode G1 of the n-channel device and the second gate electrode G2 of the p-channel device includes:

[0103] Under the conditions of an upper electrode power of 100 - 200 W, a lower electrode power of 30 - 40 W, a pressure of 10 mTorr, and a CF4 flow rate of 45 sccm, the Al2O3 covering outside the n-channel device is etched away to expose the AlGaN barrier layer, the second source electrode S2, the second drain electrode D2 in the p-channel device, and the first source electrode S1 and the first drain electrode D1 in the n-channel device;

[0104] Under the conditions that the power of the upper electrode is 15 - 25 W, the power of the lower electrode is 3 - 5 W, the pressure is 5 mTorr, the flow rate of Cl2 is 4 sccm, and the flow rate of BCl3 is 10 sccm, a third groove 40 is etched and formed on the surface of the AlGaN barrier layer of the p-channel device on the side far from the second substrate;

[0105] Fabricate the first gate electrode G1 of the n-channel device and the second gate electrode G2 of the p-channel device.

[0106] Optionally, along the direction perpendicular to the plane where the first substrate is located, the orthographic projection of the first groove 10 coincides with the orthographic projection of the third groove 40. It should be understood that if the first groove 10 and the third groove 40 are not aligned, it will cause the fabricated device to malfunction in turn-off due to the relatively thick p-GaN layer corresponding to the second gate electrode, and the device will not have normal characteristics.

[0107] In this embodiment, the first gate electrode G1 of the n-channel device and the second gate electrode G2 of the p-channel device can be fabricated simultaneously. Since their fabrication processes are the same, only the first gate electrode G1 will be taken as an example for illustration. Specifically, after the sample with the photolithography pattern of the first gate electrode G1 is put into an α-plasma plasma asher for bottom film treatment, the sample is placed in an electron beam evaporation chamber. When the vacuum degree of the reaction chamber of the electron beam evaporation chamber reaches 2×10 -6 Torr, gate metal is evaporated on the photoresist inside and outside the first gate electrode region. This gate metal can be a metal stack structure composed of two layers of metals, Ni and Au, from bottom to top in sequence; then, the sample after the gate metal evaporation is stripped to remove the gate metal, photoresist and stripping glue outside the first gate electrode region; finally, the sample is rinsed with ultrapure water and dried with nitrogen.

[0108] In the above step S9, the step of growing the SiN protective layer on the surface of the n-channel device and the p-channel device on the side far from the second substrate includes:

[0109] Using NH3 and SiH4 as reaction gases, under the conditions that the temperature of the second substrate is 250 °C, the pressure of the reaction chamber is 600 mTorr, and the RF power is 20 - 25 W, a SiN protective layer with a thickness of 200 nm is grown by PECVD process.

[0110] Optionally, after the growth of the SiN protective layer is completed, the steps of lithographing the opening area of the metal interconnection layer on the SiN protective layer and then leading out the first source electrode S1, the first drain electrode D1, the first gate electrode G1, the second source electrode S2, the second drain electrode D2 and the second gate electrode G2, and electrically connecting the first drain electrode D1 and the second drain electrode D2 to obtain the N-face GaN-based p, n-channel device integrated structure include:

[0111] Open the photolithographic electrode. Specifically, first bake the sample on a hot plate at 200 °C, then apply and spin coat the photoresist. In this embodiment, EPI621 photoresist can be selectively used, and the spin coating speed is 3500 revolutions per minute. After that, bake the sample on a hot plate at 90 °C. Then, place the sample in a lithography machine to expose the photoresist in the metal interconnection layer opening area, and put the exposed sample into a developer to remove the photoresist in the interconnection opening area, and rinse it with ultrapure water and dry it with nitrogen.

[0112] After photolithography, use CF4 and O2 as reaction gases, and perform ICP etching under the conditions of a reaction chamber pressure of 10 mTorr, an upper electrode RF power of 80 - 100 W, and a lower electrode RF power of 10 - 20 W to remove the 200 nm thick SiN protective layer in the interconnection opening area.

[0113] Further, photolithograph the metal interconnection layer area on the SiN protective layer. First, bake the sample after etching the metal interconnection layer opening on a hot plate at 200 °C, then apply and spin coat the stripping resist on the first source electrode, second source electrode, first drain electrode, second drain electrode in the metal interconnection layer opening area and the unetched SiN protective layer, and bake the sample on a hot plate at 200 °C, where the spin coating thickness is 0.35 μm. Then, apply and spin coat the photoresist on the stripping resist, and bake the sample on a hot plate at 90 °C, and the spin coating thickness can be 0.77 μm. Place the sample after applying and spin coating into a lithography machine to expose the photoresist in the metal interconnection area. After that, put the exposed sample into a developer to remove the photoresist and stripping resist in the metal interconnection layer area, and rinse it with ultrapure water and dry it with nitrogen.

[0114] Next, evaporate the metal interconnection. In this embodiment, first place the sample with the metal interconnection photolithographic pattern into an α - plasma plasma asher for bottom film treatment, then put the sample into an electron beam evaporation chamber. After the vacuum degree of the reaction chamber of the electron beam evaporation chamber reaches 2×10 -6 Torr, evaporate the interconnection metal on the electrodes in the interconnection metal area, the SiN protective layer, and the photoresist outside the metal interconnection area. Then, strip the sample after evaporating the interconnection metal to remove the interconnection metal, photoresist, and stripping resist outside the metal interconnection layer area. The above interconnection metal can be a metal stack structure composed of two layers of metals, Ti and Au, from bottom to top. Finally, strip the sample after evaporating the interconnection metal to remove the interconnection metal, photoresist, and stripping resist outside the metal interconnection layer area, rinse the sample with ultrapure water and dry it with nitrogen to obtain the fabricated N - face GaN - based p - and n - channel device integrated structure.

[0115] As Figure 15As shown in the figure, an embodiment of the present invention further provides an integrated structure of N-face GaN-based p- and n-channel devices, which is obtained by the preparation method of the above-mentioned integrated structure of N-face GaN-based p- and n-channel devices.

[0116] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0117] The present invention provides an integrated structure of N-face GaN-based p- and n-channel devices and a preparation method thereof. Since an N-face AlGaN / GaN heterojunction is used to prepare the p-channel device, the AlGaN barrier layer existing in the upper layer of the GaN channel can play a role in blocking the gate leakage current. Therefore, the insulating medium between the gate metal and the p-GaN channel, such as Al2O3, can be omitted during the preparation process, thereby avoiding problems such as fixed charges introduced by the deposited insulating layer and interface charges between the materials, and improving the mobility of the p-channel device. In addition, the GaN-based n-channel device prepared from the N-face GaN-based material has more advantages in terms of high frequency compared with the Ga-face n-channel device. Therefore, the n-channel enhancement device with a groove MIS structure prepared on the N-face also has good characteristics. The integration of the N-face enhancement n-channel device and the p-channel device also enables the realization of the GaN-based complementary logic structure.

[0118] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0119] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0120] In the present invention, unless otherwise clearly specified or limited, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0121] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0122] Although the present application has been described in conjunction with various embodiments herein, however, in the process of implementing the claimed present application, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure content, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality of situations. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0123] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A preparation method of an integrated structure of an N-sided GaN-based p-channel and n-channel device, characterized in that, Including: Providing a first substrate, and growing an epitaxial structure on the surface of the first substrate, the epitaxial structure including a GaN buffer layer, a GaN layer, an AlGaN barrier layer, and a p-GaN layer that are sequentially grown on the surface of the first substrate, the epitaxial structure including a first preset region and a second preset region; Removing the p-GaN layer in the first preset region by etching, and etching the surface of the p-GaN layer on the side away from the AlGaN barrier layer in the second preset region to form a first groove; Depositing an SiN layer on the surface of the p-GaN layer on the side away from the AlGaN barrier layer, and at least part of the SiN layer is in contact with the surface of the GaN layer on the side away from the GaN buffer layer; Bonding a second substrate on the surface of the SiN layer on the side away from the first substrate, and after flipping the sample in a direction perpendicular to the plane where the first substrate is located, etching away the first substrate and the GaN buffer layer; Etching at least part of the GaN layer, AlGaN barrier layer, p-GaN layer, and SiN layer in the second preset region close to the first preset region to form an electrically isolated region, and an n-channel device active region and a p-channel device active region located on both sides of the electrically isolated region respectively; After fabricating a first source electrode and a first drain electrode on the surface of the GaN layer of the n-channel device on the side away from the AlGaN barrier layer, etching the GaN layer and at least part of the AlGaN barrier layer of the p-channel device, and fabricating a second source electrode and a second drain electrode on the side of the p-GaN layer away from the second substrate; Etching the surface of the GaN layer of the n-channel device on the side away from the AlGaN barrier layer to form a second groove, and depositing Al2O3 on the surface of the n-channel device and the p-channel device on the side away from the second substrate; Etching away the Al2O3 covering outside the n-channel device, and etching to form a third groove on the surface of the AlGaN barrier layer of the p-channel device on the side away from the second substrate, and then fabricating a first gate electrode of the n-channel device and a second gate electrode of the p-channel device; Growing an SiN protective layer on the surface of the n-channel device and the p-channel device on the side away from the second substrate, and after photolithographing the opening area of the metal interconnection layer on the SiN protective layer, leading out the first source electrode, the first drain electrode, the first gate electrode, the second source electrode, the second drain electrode, and the second gate electrode, and electrically connecting the first drain electrode and the second drain electrode to obtain the N-face GaN-based p, n-channel device integrated structure.

2. The manufacturing method of the N-sided GaN-based p- and n-channel device integrated structure according to claim 1, wherein Before the step of bonding a second substrate on the surface of the SiN layer on the side away from the first substrate, it further includes: Polishing the surface of the SiN layer on the side away from the first substrate by using a chemical mechanical polishing process.

3. The preparation method of the N-sided GaN-based p- and n-channel device integrated structure according to claim 1, characterized in that The step of etching away the first substrate and the GaN buffer layer after flipping the sample in a direction perpendicular to the plane where the first substrate is located includes: After flipping the sample in a direction perpendicular to the plane where the first substrate is located, etching away the first substrate under the conditions that the upper electrode power is 250 - 350 W, the lower electrode power is 20 - 40 W, the pressure is 5 mTorr, and the SF6 flow rate is 50 sccm; Under the conditions that the upper electrode power is 40 - 60 W, the lower electrode power is 20 - 30 W, the pressure is 5 mTorr, the Cl2 flow rate is 8 sccm, and the BCl3 flow rate is 20 sccm, the GaN buffer layer is etched away.

4. The manufacturing method of the N-face GaN-based p- and n-channel device integrated structure according to claim 1, characterized in that The second preset region includes a sub-region close to the first preset region; The step of etching at least a part of the GaN layer, the AlGaN barrier layer, the p-GaN layer, and the SiN layer on the side of the second preset region close to the first preset region to form an electrically isolated region, and an n-channel device active region and a p-channel device active region respectively located on both sides of the electrically isolated region includes: Coating and spinning photoresist on the sample; Placing the sample in a lithography machine, exposing the photoresist in the sub-region, and placing the exposed sample in a developer to remove the photoresist in the sub-region; Using inductively coupled plasma (ICP) process to etch the GaN layer, the AlGaN barrier layer, and the p-GaN layer in the sub-region in sequence to achieve mesa isolation of the active region, forming an electrically isolated region, and an n-channel device active region and a p-channel device active region respectively located on both sides of the electrically isolated region.

5. The preparation method of the N-sided GaN-based p- and n-channel device integrated structure according to claim 1, characterized in that, The step of etching the surface of the GaN layer on the side of the n-channel device away from the AlGaN barrier layer to form a second groove, and depositing Al2O3 on the surface of the n-channel device and the p-channel device on the side away from the second substrate includes: Under the conditions that the upper electrode power is 15 - 25 W, the lower electrode power is 3 - 5 W, the pressure is 5 mTorr, the Cl2 flow rate is 4 sccm, and the Bl3 flow rate is 10 sccm, etching the surface of the GaN layer on the side of the n-channel device away from the AlGaN barrier layer to form a second groove; Using atomic layer deposition (ALD) technology to deposit Al2O3 with a thickness of 20 nm on the surface of the n-channel device and the p-channel device on the side away from the second substrate.

6. The preparation method of the N-face GaN-based p- and n-channel device integrated structure according to claim 5, characterized in that, The second groove includes a first surface parallel to the first substrate; Wherein, along the direction perpendicular to the plane where the first substrate is located, the distance between the first surface and the AlGaN barrier layer is 10 nm.

7. The preparation method of the N-face GaN-based p- and n-channel device integrated structure according to claim 1, characterized in that, The step of etching away the Al2O3 covering outside the n-channel device, and etching a third groove on the surface of the AlGaN barrier layer of the p-channel device on the side away from the second substrate, and then fabricating a first gate electrode of the n-channel device and a second gate electrode of the p-channel device includes: Under the conditions that the upper electrode power is 100 - 200 W, the lower electrode power is 30 - 40 W, the pressure is 10 mTorr, and the CF4 flow rate is 45 sccm, etching away the Al2O3 covering outside the n-channel device to expose the AlGaN barrier layer, the second source electrode, the second drain electrode in the p-channel device, and the first source electrode and the first drain electrode in the n-channel device; Under the conditions that the power of the upper electrode is 15 - 25 W, the power of the lower electrode is 3 - 5 W, the pressure is 5 mTorr, the flow rate of Cl2 is 4 sccm, and the flow rate of BCl3 is 10 sccm, a third groove is etched and formed on the surface of the AlGaN barrier layer of the p-channel device on the side far from the second substrate; Fabricate the first gate electrode of the n-channel device and the second gate electrode of the p-channel device.

8. The preparation method of the N-face GaN-based p and n-channel device integrated structure according to claim 7, characterized in that, Along the direction perpendicular to the plane where the first substrate is located, the orthographic projection of the first groove coincides with the orthographic projection of the third groove.

9. An N-face GaN-based p- and n-channel device integrated structure, characterized in that, Prepared by the method for preparing an N-face GaN-based p, n-channel device integrated structure according to any one of claims 1 - 8.

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