An ESD protection circuit

Abstract

The application provides an ESD protection circuit, belonging to the technical field of static discharge protection design of integrated circuit chip, comprising: a transient detection circuit, comprising: a first PMOS tube, a first NMOS tube and a second NMOS tube connected with the first PMOS tube, a first voltage dividing element connected with the gate of the first PMOS tube, a first capacitor connected in series with the first voltage dividing element, a second capacitor connected with the source of the first NMOS tube, and a current mirror circuit connected with the second capacitor; a static detection circuit, used for determining whether to conduct according to the relationship between the ESD voltage and the trigger voltage; and a discharge circuit, used for discharging the ESD current. The application solves the defects of the chip internal circuit insecurity caused by the latch-up, false trigger phenomenon or slow reaction to the ESD event of the ESD protection circuit in the prior art, realizes the combination of the transient detection and the static detection, effectively avoids the latch-up and the false trigger phenomenon, and ensures that the reaction speed to the ESD event is fast enough, thereby ensuring the safety of the chip internal circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit chip electrostatic discharge protection design, and particularly relates to an ESD protection circuit. BACKGROUND

[0002] The electrostatic discharge (ESD) protection design of an integrated circuit chip is a focus and difficulty of the reliability design in the semiconductor industry, and with the progress of semiconductor technology, the ESD protection window under an advanced process is narrowed, which brings great challenges to the on-chip ESD protection design. The full-chip ESD protection design strategy requires that low-resistance discharge paths can be provided for different impact modes between different chip pins, and the power clamp ESD protection circuit is a key module to realize this function. Therefore, the effective power clamp ESD protection circuit design is the key to the success of the full-chip ESD protection strategy.

[0003] The traditional power clamp ESD protection circuit adopts a transient trigger module to quickly trigger a discharge transistor, and the discharge transistor is a field effect transistor with large current discharge capacity. This scheme has the characteristics of fast discharge under an ESD event, and can effectively avoid the overvoltage event on the power line to cause internal device failure. However, because there are also many noise pulses with the same transient characteristics as the ESD event on the chip power line, how to prevent the occurrence of the latch-up and false trigger phenomenon is a design difficulty of this type of protection circuit.

[0004] Of course, there are also power clamp ESD protection circuits with direct current trigger mode in the industry. This type of protection circuit relies on the overvoltage phenomenon on the power line to trigger the discharge transistor. The protection circuit relying on voltage amplitude discrimination has the characteristics of being insensitive to transient noise, but the slow response speed under the ESD event is a major shortcoming of this scheme. SUMMARY

[0005] The present application provides an ESD protection circuit to solve the defects of the chip internal circuit insecurity caused by the latch-up, false trigger phenomenon, or slow response to the ESD event of the ESD protection circuit in the prior art, realizes the combination of transient detection and static detection, effectively avoids the occurrence of latch-up and false trigger phenomenon, and ensures that the response speed to the ESD event is fast enough, thereby ensuring the safety of the chip internal circuit.

[0006] The present application also provides an ESD protection circuit, comprising:

[0007] The transient detection circuit comprises a first PMOS, a first NMOS connected with the first PMOS, a second NMOS connected with the first PMOS, a first voltage dividing element connected with the gate of the first PMOS, a first capacitor connected in series with the first voltage dividing element, a second capacitor connected with the source of the first NMOS, and a current mirror circuit connected with the second capacitor;

[0008] The static detection circuit is connected with the transient detection circuit, and is configured to determine whether to be turned on according to the relationship between the ESD voltage and a set trigger voltage when the first PMOS is turned on.

[0009] The discharge circuit is connected with the static detection circuit, and is configured to be turned on when the static detection circuit is turned on, so as to discharge the ESD current.

[0010] According to the ESD protection circuit, the source of the first PMOS is connected with the power pin of the ESD protection circuit, the gate of the first PMOS is connected with one end of the first voltage dividing element and the first capacitor, the drain of the first NMOS and the gate of the second NMOS respectively, the drain of the first PMOS is connected with the drain of the second NMOS.

[0011] The other end of the first voltage dividing element is connected with the power pin of the ESD protection circuit.

[0012] One end of the first capacitor which is not connected with the first voltage dividing element and the source of the second NMOS are grounded.

[0013] According to the ESD protection circuit, the current mirror circuit comprises a third NMOS and a fourth NMOS, the gate of the third NMOS is connected with the gate of the fourth NMOS.

[0014] The gate and the drain of the third NMOS and the gate of the fourth NMOS are connected with one end of the second capacitor which is not connected with the source of the first NMOS, the drain of the fourth NMOS is connected with one end of the second capacitor which is connected with the source of the first NMOS, and the sources of the third NMOS and the fourth NMOS are grounded.

[0015] According to the ESD protection circuit, the static detection circuit comprises a second PMOS, a fifth NMOS, a second voltage dividing element, a third voltage dividing element and a voltage limiting element.

[0016] The second PMOS transistor is connected with the second voltage dividing element, the voltage limiting element and the third voltage dividing element respectively; the fifth NMOS transistor is connected with the first NMOS transistor and the voltage limiting element respectively; and the third voltage dividing element is connected with the discharge circuit.

[0017] According to the ESD protection circuit, the gate of the second PMOS transistor is connected with the first end of the second voltage dividing element and the first end of the voltage limiting element respectively; the drain of the second PMOS transistor is connected with the first end of the third voltage dividing element; the gate of the fifth NMOS transistor is connected with the gate of the first NMOS transistor; the drain of the fifth NMOS transistor is connected with the second end of the voltage limiting element; the source of the second PMOS transistor and the second end of the second voltage dividing element are connected with the power supply pin of the ESD protection circuit; and the source of the fifth NMOS transistor and the second end of the third voltage dividing element are grounded.

[0018] According to the ESD protection circuit, the voltage limiting element is a diode; the anode of the diode is connected with the gate of the second PMOS transistor and the second end of the second voltage dividing element; and the cathode of the diode is connected with the drain of the fifth NMOS transistor.

[0019] According to the ESD protection circuit, the diode is one and / or a plurality of diodes connected in series; and the number of the diodes determines the size of the trigger voltage.

[0020] According to the ESD protection circuit, the width-length ratio of the fourth NMOS transistor is greater than the width-length ratio of the third NMOS transistor; and the ratio of the width-length ratio of the fourth NMOS transistor to the width-length ratio of the third NMOS transistor determines the duration of the ESD current discharge.

[0021] According to the ESD protection circuit, the first voltage dividing element, the second voltage dividing element and the third voltage dividing element are all resistors.

[0022] According to the ESD protection circuit, the discharge circuit comprises a discharge transistor.

[0023] The gate of the discharge transistor is connected with the drain of the second PMOS transistor and the first end of the third voltage dividing element; the drain of the discharge transistor is connected with the power supply pin of the ESD protection circuit; and the source of the discharge transistor is grounded.

[0024] The ESD protection circuit provided by the application detects whether the pulse on the power line of the integrated circuit chip has the transient characteristic of ESD impact through a transient detection circuit, and the static detection circuit determines whether overvoltage occurs on the power line, i.e. whether the ESD voltage reaches the trigger voltage, according to the amplitude of the pulse on the power line in the case that the transient detection circuit detects a transient ESD event, and if overvoltage occurs, the discharge circuit is turned on, i.e. the discharge circuit is turned on only when the transient detection circuit and the static detection circuit both meet the detection condition of the ESD event, to complete the discharge of the static charge and ensure the safety of the internal circuit of the chip.

[0025] The transient response time of the whole ESD protection circuit can be adjusted through the setting of the current mirror circuit in the transient detection circuit, so as to be applicable to different ESD events and protection scenes and have strong flexibility. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the application or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0027] Figure 1 is a structural schematic diagram of an ESD protection circuit provided by the application;

[0028] Figure 2 is a test diagram of the ESD protection circuit shown in Figure 1 Fig. 1, in which a direct current leakage test is performed on the power pin VDD end;

[0029] Figure 3 is a test result schematic diagram of the clamping voltage changing with time in the ESD protection circuit shown in Figure 1 Fig. 1, in which 5V-1us EOS excitation is applied to the power pin VDD end;

[0030] Figure 4 is a test result schematic diagram of the clamping voltage changing with time in the ESD protection circuit shown in Figure 1 Fig. 1 under 1kv-HBM event. DETAILED DESCRIPTION

[0031] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0032] It should be noted that the full-chip ESD protection design strategy requires that low-resistance discharge paths can be provided for different impact modes between different chip pins, and the power clamp ESD protection circuit is a key module for realizing this function. The traditional power clamp ESD protection circuit generally includes two kinds, one is to use a transient trigger module to quickly trigger a discharge transistor, and the other is a power clamp ESD protection circuit using a direct-current trigger mode. Among them, the scheme of using a transient trigger module to quickly trigger a discharge transistor has the characteristics of fast discharge under an ESD event, that is, it can effectively avoid overvoltage events causing internal device failure on the power line. However, because there are also many noise pulses with the same transient characteristics as ESD events on the chip power line, latch-up and false trigger phenomena are prone to occur; and the power clamp ESD protection circuit using a direct-current trigger mode triggers the discharge transistor by relying on the overvoltage phenomenon on the power line. This way can avoid latch-up and false trigger phenomena, and is not sensitive to transient noise, but the response speed under an ESD event is not fast enough.

[0033] It can be seen that the existing ESD protection circuit cannot completely and effectively protect the safety of the internal circuit of the chip.

[0034] In view of the above problems, the present application provides a power clamp ESD protection circuit combining transient triggering and direct-current triggering, that is, a transient detection circuit is used to detect whether the pulse on the power line of the integrated circuit chip has the transient characteristics of ESD impact, and in the case that the transient detection circuit detects a transient ESD event, the static detection circuit determines whether an overvoltage phenomenon occurs on the power line according to the amplitude of the pulse on the power line, and only when the overvoltage phenomenon occurs, the discharge circuit is turned on to complete the discharge of electrostatic charge, effectively ensuring the safety of the internal circuit of the chip.

[0035] In order to make the above objects, features and advantages of the present application more obvious and easy to understand, the following will be combined with Figures 1 to 4 The ESD protection circuit of the present application is described as follows, Figure 1 As shown in the figure, the ESD protection circuit comprises:

[0036] The transient detection circuit 10 comprises a first PMOS transistor Mp1, a first NMOS transistor Mn1 connected to the first PMOS transistor Mp1, a second NMOS transistor Mn2 connected to the first PMOS transistor Mp1, a first voltage dividing element R1 connected to the gate of the first PMOS transistor Mp1, a first capacitor C1 connected in series to the first voltage dividing element R1, a second capacitor C2 connected to the source of the first NMOS transistor Mn1, and a current mirror circuit 11 connected to the second capacitor C2;

[0037] The static detection circuit 20 is connected to the transient detection circuit 10, and is configured to determine whether to be turned on according to the relationship between the ESD voltage and a set trigger voltage when the first PMOS transistor Mp1 is turned on.

[0038] The discharge circuit 30 is connected to the static detection circuit 20, and is configured to be turned on when the static detection circuit 20 is turned on, so as to discharge the ESD current.

[0039] Specifically, when the ESD pulse arrives, the voltage on the first capacitor C1 cannot be changed instantaneously, so that a voltage difference is formed between the gate and the source of the first PMOS transistor Mp1, the first PMOS transistor Mp1 and the first NMOS transistor Mn1 are turned on, the first capacitor C1 and the second capacitor C2 start to charge, and at the same time, the static detection circuit 20 receives the signal that the first PMOS transistor Mp1 is turned on, detects the ESD voltage, i.e., whether the voltage value of the ESD transient pulse applied to the power supply pin VDD of the ESD protection circuit reaches the set trigger voltage, and when the ESD voltage reaches the trigger voltage, i.e., the static detection circuit determines that the amplitude of the pulse on the chip power supply line has overvoltage phenomenon, the discharge circuit is turned on, and then the ESD current is discharged through the discharge circuit when the transient detection circuit detects the transient ESD event and the static detection circuit determines that there is overvoltage phenomenon. After a period of time, the first capacitor C1 and the second capacitor C2 are fully charged, the capacitor charging process is ended, the transient detection circuit part is naturally turned off, and then the discharge transistor is turned off. Therefore, the entire ESD discharge process is completed, thereby effectively ensuring the safety of the internal circuit of the integrated circuit chip.

[0040] It can be understood that the trigger voltage and the maintaining voltage of the power clamp ESD protection circuit are always the focus of the on-chip ESD protection design, because whether the two values fall within the ESD design window of the corresponding process is the key to measure whether the ESD protection strategy is effective. Meanwhile, with the continuous progress of technology, the energy consumption of the chip gradually becomes the focus of attention. After the power clamp ESD protection circuit is triggered, the appropriate transient response time can not only ensure that the ESD current is completely discharged, but also ensure that the additional power loss and the latch effect caused by the long discharge time are avoided. Based on this, in the ESD protection circuit described in the embodiment of the present application, a current mirror circuit is further arranged in the transient detection circuit, and then by adjusting the current mirror circuit, the transient response time of the entire ESD protection circuit can be changed, so that the ESD protection circuit can be applicable to different ESD events and protection scenarios, and has stronger flexibility.

[0041] More specifically, after the first PMOS tube Mp1 and the first NMOS tube Mn1 are turned on, the first capacitor C1 and the second capacitor C2 start to charge, and the connection of the current mirror circuit with the second capacitor C2 makes the charging time of the second capacitor C2 controlled by the current mirror circuit, and the charging time of the second capacitor C2 corresponds to the current discharge time of the discharge circuit. Therefore, by setting the current mirror circuit, the flexible control of the discharge time is realized, the problem of the transient response time of the power clamp circuit under the ESD event is solved, the disadvantages of the large amount of additional power loss caused by the too long transient response time, the long time latch phenomenon of the circuit, the influence on the normal work of the chip, and the damage to the internal circuit caused by the too short transient response time are avoided.

[0042] As an embodiment of the present application, the source of the first PMOS tube Mp1 is connected with the power pin VDD of the ESD protection circuit, the gate of the first PMOS tube Mp1 is connected with one end of the first voltage dividing element R1, the drain of the first NMOS tube Mn1 and the gate of the second NMOS tube Mn2 respectively, the drain of the first PMOS tube Mp1 is connected with the drain of the second NMOS tube Mn2;

[0043] The other end of the first voltage dividing element R1 is connected with the power pin VDD of the ESD protection circuit;

[0044] The end of the first capacitor C1 which is not connected with the first voltage dividing element R1, and the source of the second NMOS tube Mn2 are grounded VSS.

[0045] Specifically, the gate of the PMOS transistor Mp1 is connected with the gate of the NMOS transistor Mn2, the source of the NMOS transistor Mn2 is grounded, the drain of the NMOS transistor Mn2 is connected with the drain of the PMOS transistor Mp1, the source of the PMOS transistor Mp1 is connected with the power supply pin VDD of the ESD protection circuit, the source of the NMOS transistor Mn1 is connected with one end of the second capacitor C2, the drain of the NMOS transistor Mn1 is connected with the gate of the PMOS transistor Mp1, the gate of the NMOS transistor Mn1 is connected with the drain of the PMOS transistor Mp1, one end of the first voltage dividing element R1 is connected with the power supply pin VDD, the other end of the first voltage dividing element R1 is connected with the gate of the PMOS transistor Mp1, one end of the first capacitor C1 is connected with the gate of the PMOS transistor Mp1, the other end of the first capacitor C1 is grounded, one end of the second capacitor C2 is connected with the source of the NMOS transistor Mn1, and the other end of the second capacitor C2 is connected with the current mirror circuit 11.

[0046] As an embodiment of the present application, the current mirror circuit 11 comprises a third NMOS transistor Mn3 and a fourth NMOS transistor Mn4; the gate of the third NMOS transistor Mn3 is connected with the gate of the fourth NMOS transistor Mn4;

[0047] The gate and the drain of the third NMOS transistor Mn3 and the gate of the fourth NMOS transistor Mn4 are connected with one end of the second capacitor C2 which is not connected with the source of the first NMOS transistor Mn1; the drain of the fourth NMOS transistor Mn4 is connected with one end of the second capacitor C2 which is connected with the source of the first NMOS transistor Mn1; the sources of the third NMOS transistor Mn3 and the fourth NMOS transistor Mn4 are grounded VSS.

[0048] Specifically, the current mirror circuit is composed of two NMOS transistors, and the size ratio of the two NMOS transistors directly determines the amplification ratio of the capacitance of the second capacitor C2, and the charging time of the capacitor is proportional to the size of the capacitor and the size of the voltage dividing element, so that the charging time of the second capacitor C2 can be flexibly adjusted by adjusting the width-length ratio of the third NMOS transistor Mn3 and the fourth NMOS transistor Mn4, that is, by dynamically changing the size ratio of the current mirror, the ESD protection circuit presents different transient response times, so as to be applicable to different ESD events and protection scenarios, and has strong flexibility.

[0049] As an embodiment of the present application, the static detection circuit 20 comprises a second PMOS transistor Mp2, a fifth NMOS transistor Mn5, a second voltage dividing element R2, a third voltage dividing element R3 and a voltage limiting element D;

[0050] The second PMOS transistor Mp2 is connected with the second voltage dividing element R2, the voltage limiting element D and the third voltage dividing element R3 respectively; the fifth NMOS transistor Mn5 is connected with the first NMOS transistor Mn1 and the voltage limiting element D respectively; the third voltage dividing element R3 is connected with the discharge circuit 30.

[0051] Specifically, the first PMOS transistor Mp1 is turned on, so that the first NMOS transistor Mn1 and the fifth NMOS transistor Mn5 are turned on, the fifth NMOS transistor Mn5 is turned on, when the ESD voltage reaches the trigger voltage, the voltage limiting element D is turned on, the second voltage dividing element R2 is divided, so that the gate and the source of the second PMOS transistor Mp2 form a voltage difference, the second PMOS transistor Mp2 is turned on, and then the third voltage dividing element R3 is divided, forming a high level, that is, sending a conductive signal to the discharge circuit 30.

[0052] As an embodiment of the present application, the gate of the second PMOS transistor Mp2 is connected with the first end of the second voltage dividing element R2 and the first end of the voltage limiting element D respectively; the drain of the second PMOS transistor Mp2 is connected with the first end of the third voltage dividing element R3; the gate of the fifth NMOS transistor Mn5 is connected with the gate of the first NMOS transistor Mn1; the drain of the fifth NMOS transistor Mn5 is connected with the second end of the voltage limiting element D; the source of the second PMOS transistor Mp2 and the second end of the second voltage dividing element R2 are connected with the power supply pin VDD of the ESD protection circuit; the source of the fifth NMOS transistor Mn5 and the second end of the third voltage dividing element R3 are grounded VSS.

[0053] Specifically, the gate of the PMOS transistor Mp2 is connected with one end of the second voltage dividing element R2, the source of the PMOS transistor Mp2 is connected with the power supply pin VDD of the ESD protection circuit, the drain of the PMOS transistor Mp2 is connected with one end of the third voltage dividing element R3, the drain of the NMOS transistor Mn5 is connected with the voltage limiting element D, the gate of the NMOS transistor Mn5 is connected with the drain of the NMOS transistor Mn2, the source of the NMOS transistor Mn5 is grounded, one end of the resistor R2 is connected with VDD, and the other end is connected with the drain of the NMOS transistor Mn5 in series with the voltage limiting element D, one end of the third voltage dividing element R3 is grounded, and the other end is connected with the drain of the PMOS transistor Mp2.

[0054] As an embodiment of the present application, the voltage limiting element D is a diode; the anode of the diode is connected with the gate of the second PMOS transistor Mp2 and the second end of the second voltage dividing element R2; the cathode of the diode is connected with the drain of the fifth NMOS transistor Mn5.

[0055] Specifically, by using a diode as a voltage limiting element, when the ESD voltage reaches the trigger voltage, the diode is turned on, i.e. the entire static detection circuit is turned on, and the detection of the ESD voltage is realized.

[0056] As an embodiment of the present application, the diode is one and / or a plurality of diodes connected in series; the number of diodes determines the size of the trigger voltage.

[0057] Specifically, for example, two diodes D1 and D2 connected in series are provided, and by connecting the diodes in series between the second voltage dividing element R2 and the drain of the NMOS tube Mn5, the different design windows of the integrated circuit chip are matched by adjusting the number of diodes. Figure 1

[0058] As an embodiment of the present application, the width-length ratio of the fourth NMOS tube Mn4 is greater than the width-length ratio of the third NMOS tube Mn3; the ratio of the width-length ratio of the fourth NMOS tube Mn4 to the width-length ratio of the third NMOS tube Mn3 determines the duration of the ESD current discharge.

[0059] Specifically, for the current mirror circuit composed of the fourth NMOS tube Mn4 and the third NMOS tube Mn3, the capacitance value of the second capacitor C2 is directly determined by the ratio of the width-length ratio of the fourth NMOS tube Mn4 to the width-length ratio of the third NMOS tube Mn3, so that by setting the width-length ratio of the fourth NMOS tube Mn4 to be greater than the width-length ratio of the third NMOS tube Mn3, the capacitance value of the second capacitor C2 is equivalent to being amplified, and the charging time of the second capacitor C2 is prolonged, i.e. the overall discharge time of the ESD protection circuit is increased.

[0060] More specifically, by dynamically adjusting the ratio of the width-length ratio of the fourth NMOS tube Mn4 to the width-length ratio of the third NMOS tube Mn3, the duration of the ESD current discharge is adjusted, which effectively avoids the problems of excessive power loss caused by excessively long transient response time, long-term latch-up of the circuit, and the ESD protection circuit being unable to safely and effectively discharge all ESD current due to excessively short transient response time, which causes damage to the internal circuit of the integrated circuit chip, so that the integrated circuit chip using the ESD protection circuit according to the embodiment of the present application can completely discharge the ESD current when the ESD phenomenon occurs, and will not cause power loss due to excessively long transient response time, effectively protecting the internal circuit of the integrated circuit chip and avoiding energy waste.

[0061] As an embodiment of the present application, the first voltage dividing element R1, the second voltage dividing element R2 and the third voltage dividing element R3 are all resistors.​

[0062] Specifically, by setting the first voltage dividing element R1, the second voltage dividing element R2 and the third voltage dividing element R3 as resistors, good voltage dividing effect can be achieved, and the sensitivity of the ESD protection circuit of the embodiment of the present application can be effectively improved.

[0063] More specifically, the third voltage dividing element R3 can also be set as an NMOS tube.

[0064] As an embodiment of the present application, the discharge circuit 30 comprises a discharge transistor BigFET.

[0065] The gate of the discharge transistor BigFET is connected with the drain of the second PMOS tube Mp2 and the first end of the third voltage dividing element R3; the drain of the discharge transistor BigFET is connected with the power supply pin VDD of the ESD protection circuit; and the source of the discharge transistor BigFET is grounded VSS.

[0066] Specifically, the discharge transistor is an NMOS tube BigFET, the gate of which is connected with the drain of the PMOS tube Mp2, the gate of which is also connected with one end of the third voltage dividing element R3, the source of which is connected with the ground VSS of the ESD protection circuit, and the drain of which is connected with the power supply line VDD of the ESD protection circuit.

[0067] More specifically, after the static detection circuit is turned on, the fifth NMOS tube Mn5 and the voltage limiting element D are both turned on, at this time, due to the voltage division of the second voltage dividing element R2, a voltage difference is formed between the gate and the source of the second PMOS tube Mp2, the second PMOS tube Mp2 is turned on, at this time, the third voltage dividing element R3 divides voltage, a voltage difference is formed between the gate and the source of the discharge transistor BigFET, the discharge transistor BigFET is thus turned on, and the discharge of the ESD current is realized.

[0068] Further, taking the ESD protection circuit shown in FIG. 8 as an example, the specific working process of the ESD protection circuit of the above-mentioned embodiment of the present application when the ESD pulse arrives is as follows: Figure 1

[0069] ​Firstly, the transient detection circuit 10 identifies the fast power-on pulse signal, that is, when the ESD event occurs, the voltage on the first capacitor C1 cannot change instantaneously, so that the first PMOS tube Mp1 gate-source forms a pressure difference, the first PMOS tube Mp1, the first NMOS tube Mn1 and the fifth NMOS tube Mn5 are opened, the power pin VDD of the ESD protection circuit charges the first capacitor C1 and the second capacitor C2, at the same time, the current mirror third NMOS tube Mn3 and fourth NMOS tube Mn4 on the second capacitor C2 path are also opened, which equivalently amplifies the capacitance value of the second capacitor C2, so that the overall discharge time is increased. In this charging process, the above-mentioned tubes are always kept open. The static detection circuit 20 is sensitive to the level size, when the ESD voltage reaches the trigger voltage, the diode D1 and D2 are opened, the second voltage dividing element R2 divides the voltage, so that the second PMOS tube Mp2 gate-source has a pressure difference, the second PMOS tube Mp2 is opened, then the third voltage dividing element R3 divides the voltage, so that the Gate end of the discharge transistor BigFET is set to high level, and finally the discharge transistor BigFET is opened to discharge the ESD current.

[0070] Then, after the time designed by the current mirror circuit composed of the third NMOS tube Mn3 and the fourth NMOS tube Mn4, the first capacitor C1 and the second capacitor C2 are full, the voltage on the first capacitor C1 rises to the power pin VDD of the ESD protection circuit, so that the second NMOS tube Mn2 is opened and the first PMOS tube Mp1 is closed. At this time, the second NMOS tube Mn2 pulls down the gate level of the first NMOS tube Mn1 and the fifth NMOS tube Mn5, so that the two NMOS tubes are closed, and the capacitor charging process is ended, and the vertical path of the second voltage dividing element R2 of the static detection circuit 20 is cut off, so that the second PMOS tube Mp2 is also closed, and then the discharge transistor BigFET is closed, thereby the whole ESD discharge process is closed.

[0071] Next, taking the 28nm integrated circuit process as an example, the normal operating voltage of the power line VDD of the ESD protection circuit is set to 1.8V, the first voltage dividing element R1, the second voltage dividing element R2 and the third voltage dividing element R3 are resistors, and the voltage limiting element D is a series-connected diode.

[0072] Under the constraint of the above-mentioned ESD design window, the ESD protection circuit proposed in the above-mentioned embodiment of the application can well meet the ESD protection requirements under the advanced process by reasonably designing the size of each element in the circuit.

[0073] Specifically, the direct current scanning method is used to observe the leakage current of the ESD protection circuit under normal power supply conditions, and the results are as followsFigure 2 As shown, the ESD protection circuit described in this embodiment of the invention has a very small leakage current at 1.8V, which is less than 10nA, and remains unchanged with the number of diodes. This proves that the ESD protection circuit described in this embodiment of the invention can adapt to different ESD design windows and processes.

[0074] Figure 3 The diagram shows the test results of the clamping voltage changing over time when a 5V-1µs EOS excitation is applied to the VDD power line of the ESD protection circuit. Sample 1, sample 2, and sample 3 are three samples obtained by adjusting the size ratio of the current mirror in the ESD protection circuit; samples 1-3 correspond to a linear increase in the size ratio, respectively. Observation reveals that the three samples exhibit different transient response times under the same EOS excitation: 400ns, 600ns, and 1µs.

[0075] Figure 4 The diagram shows the test results of the clamping voltage changing over time under a 1kV-HBM event. Samples 1-3 are the same as described above. Figure 3 The three corresponding samples also exhibited three transient response times under the 1kv-HBM event: 380ns, 600ns, and 1us.

[0076] In summary, by Figure 2 It is evident that the change in the number of diodes does not affect the leakage current of the ESD protection circuit described in this invention. Therefore, the number of diodes can be flexibly adjusted according to the magnitude of the trigger voltage in the electrostatic protection window required by the process. Specifically, the larger the trigger voltage, the more series diodes are required.

[0077] Depend on Figure 3 and Figure 4 As can be seen, the ESD protection circuit proposed in this embodiment of the invention is a power clamping ESD protection circuit with adjustable transient response time, which can solve the problem of inappropriate transient response time of power clamping circuit under ESD events. The adjustable transient response time ensures that the ESD protection circuit described in this embodiment of the invention can adapt to different ESD events and protection scenarios.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An ESD protection circuit, characterized in that, include: Transient detection circuit, static detection circuit, and discharge circuit; The transient detection circuit includes: a first PMOS transistor, a first NMOS transistor connected to the first PMOS transistor, a second NMOS transistor connected to the first PMOS transistor, a first voltage divider element connected to the gate of the first PMOS transistor, a first capacitor connected in series with the first voltage divider element, a second capacitor connected to the source of the first NMOS transistor, and a current mirror circuit connected to the second capacitor. A static detection circuit, connected to the transient detection circuit, is used to determine whether to turn on the first PMOS transistor based on the relationship between the ESD voltage and the set trigger voltage when the first PMOS transistor is turned on. A discharge circuit, connected to the static detection circuit, is used to conduct when the static detection circuit is turned on, so as to discharge the ESD current. The source of the first PMOS transistor is connected to the power supply pin of the ESD protection circuit. The gate of the first PMOS transistor is connected to one end of the first voltage divider element connected to the first capacitor, the drain of the first NMOS transistor, and the gate of the second NMOS transistor, respectively. The drain of the first PMOS transistor is connected to the drain of the second NMOS transistor. The other end of the first voltage divider element is connected to the power supply pin of the ESD protection circuit. The end of the first capacitor that is not connected to the first voltage divider element, and the source of the second NMOS transistor are grounded; The current mirror circuit includes a third NMOS transistor and a fourth NMOS transistor; the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor. The gate and drain of the third NMOS transistor, and the gate of the fourth NMOS transistor are connected to the end of the second capacitor that is not connected to the source of the first NMOS transistor; the drain of the fourth NMOS transistor is connected to the end of the second capacitor that is connected to the source of the first NMOS transistor; the sources of the third NMOS transistor and the fourth NMOS transistor are grounded.

2. The ESD protection circuit according to claim 1, characterized in that, The static detection circuit includes: a second PMOS transistor, a fifth NMOS transistor, a second voltage divider element, a third voltage divider element, and a voltage limiting element; The second PMOS transistor is connected to the second voltage divider element, the voltage limiting element, and the third voltage divider element, respectively; the fifth NMOS transistor is connected to the first NMOS transistor and the voltage limiting element, respectively; and the third voltage divider element is connected to the discharge circuit.

3. The ESD protection circuit according to claim 2, characterized in that, The gate of the second PMOS transistor is connected to the first terminal of the second voltage divider element and the first terminal of the voltage limiting element, respectively; the drain of the second PMOS transistor is connected to the first terminal of the third voltage divider element; the gate of the fifth NMOS transistor is connected to the gate of the first NMOS transistor; the drain of the fifth NMOS transistor is connected to the second terminal of the voltage limiting element; the source of the second PMOS transistor and the second terminal of the second voltage divider element are connected to the power supply pin of the ESD protection circuit; the source of the fifth NMOS transistor and the second terminal of the third voltage divider element are grounded.

4. The ESD protection circuit according to claim 2, characterized in that, The voltage limiting element is a diode; the anode of the diode is connected to the gate of the second PMOS transistor and the second terminal of the second voltage divider element; the cathode of the diode is connected to the drain of the fifth NMOS transistor.

5. The ESD protection circuit according to claim 4, characterized in that, The diode may be a single diode or multiple diodes connected in series; the number of diodes determines the magnitude of the trigger voltage.

6. The ESD protection circuit according to claim 3, characterized in that, The width-to-length ratio of the fourth NMOS transistor is greater than that of the third NMOS transistor; the ratio of the width-to-length ratio of the fourth NMOS transistor to that of the third NMOS transistor determines the duration of ESD current discharge.

7. The ESD protection circuit according to claim 3, characterized in that, The first voltage divider element, the second voltage divider element, and the third voltage divider element are all resistors.

8. The ESD protection circuit according to claim 3, characterized in that, The discharge circuit includes: a discharge transistor; The gate of the discharge transistor is connected to the drain of the second PMOS transistor and the first terminal of the third voltage divider element; the drain of the discharge transistor is connected to the power supply pin of the ESD protection circuit; and the source of the discharge transistor is grounded.

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