A GaN HEMT and SBD device structure, fabrication method and ring oscillator

Abstract

The application provides a GaN HEMT and SBD device structure, a preparation method and a ring oscillator, and the GaN HEMT and SBD device structure comprises a substrate layer, a nucleation layer, a D-mode HEMT, an E-mode HEMT and an SBD which are sequentially and spaced apart on the side of the nucleation layer away from the substrate layer; wherein the D-mode HEMT, the E-mode HEMT and the SBD each comprise an n-type GaN base layer, an n-type GaN channel layer, an Al 0.23 Ga 0.67 N layer, a Si3N4 field plate layer, an Al2O3 protective layer and a diamond-like film layer which are sequentially and overlaid on the side of the nucleation layer away from the substrate layer; the D-mode HEMT and the E-mode HEMT each further comprise a Si3N4 field plate connected to one side of the corresponding n-type GaN base layer and n-type GaN channel layer; and the SBD further comprises a Schottky diode anode and a Schottky diode cathode which are connected to one side of the corresponding n-type GaN channel layer, Al 0.23 Ga 0.67 N layer, Si3N4 field plate layer and Al2O3 protective layer. In the scheme, by arranging the field plate structure on the surface of gallium nitride, a good protection effect can be formed, the forward conduction resistance is reduced and the reverse breakdown voltage is increased, and the performance of the device is effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and particularly relates to a GaN HEMT and SBD device structure, fabrication method and ring oscillator. Background Technology

[0002] Gallium nitride (GaN) power electronic devices offer lower on-resistance and higher operating frequencies compared to traditional Si power devices, meeting the requirements of electronic devices for high power, high frequency, small size, and high-temperature operation, thus attracting widespread attention. Monolithic integration of the driver circuit with the power electronic device effectively reduces parasitic parameters and is a crucial technique for realizing the low-loss and high-frequency advantages of GaN power electronic devices. GaN digital circuits are typically implemented by monolithically integrating enhancement-mode (E-mode) and depletion-mode (D-mode) GaN devices.

[0003] A ring oscillator is formed by connecting an odd number of inverters end-to-end, utilizing the inherent propagation delay time of gate circuits. This circuit has no steady state. Because in a static state (assuming no oscillation), the input and output of any inverter cannot be stably high or low; they can only be between high and low levels, in an amplified state. The advantage of a ring oscillator is its extremely simple circuit structure and ease of integration. However, due to the extremely short propagation delay time of the gate circuits—tens of nanoseconds for TTL gates and only a couple hundred nanoseconds for CMOS circuits—it is difficult to achieve low oscillation frequencies, and the frequency is not easily adjusted. Furthermore, over a wide temperature range, temperature changes can cause the oscillator's output signal to deviate. Traditional GaN oscillators also suffer from low breakdown voltage and high leakage current. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a GaN HEMT and SBD device structure, fabrication method and ring oscillator, which can reduce forward conduction resistance and increase reverse breakdown voltage, effectively improving the performance of the device.

[0005] To solve the above-mentioned technical problems, the present invention provides a GaN HEMT and SBD (Schottky diode) device structure, comprising:

[0006] Substrate layer;

[0007] A nucleation layer stacked on one side of the substrate layer;

[0008] A D-mode HEMT, an E-mode HEMT, and an SBD are formed on the side of the nucleation layer away from the substrate layer and are arranged sequentially at intervals. An isolation layer is provided between the D-mode HEMT and the E-mode HEMT, and between the E-mode HEMT and the SBD.

[0009] The D-mode HEMT, the E-mode HEMT, and the SBD all include an n-type GaN substrate, an n-type GaN channel layer, and an Al layer sequentially stacked on the side of the nucleation layer facing away from the substrate. 0.23 Ga 0.67 N-layer, Si3N4 field plate layer, Al2O3 protective layer and diamond-like thin film layer;

[0010] Both the D-mode HEMT and the E-mode HEMT further include a Si3N4 field plate connected to one side of the corresponding n-type GaN substrate and n-type GaN channel layer, and connected to the Si3N4 field plate and the corresponding n-type GaN channel layer and Al. 0.23 Ga 0.67 The drain of the N-layer and Si3N4 field plate layer is connected to the corresponding n-type GaN channel layer and Al. 0.23 Ga 0.67 The source of the N-layer, Si3N4 field plate layer, and the corresponding Al 0.23 Ga 0.67 The gate of the N-layer, Si3N4 field plate layer; the gate of the E-mode HEMT and Al 0.23 Ga 0.67 A p+ type GaN layer is set between N layers;

[0011] The SBD also includes connections to the corresponding n-type GaN channel layer and Al. 0.23 Ga 0.67 The Schottky diode anode is located on one side of the N-layer, Si3N4 field plate, and Al2O3 protective layer, and is also located in the Al layer. 0.23 Ga 0.67 Schottky diode cathode consisting of an N-layer, a Si3N4 field plate layer, and an Al2O3 protective layer connected to an n-type GaN channel layer.

[0012] Furthermore, the substrate layer is a double-sided polished n-type highly doped self-supporting GaN substrate with a thickness greater than or equal to 1 μm;

[0013] The nucleation layer comprises AlN and has a thickness of 0.3-0.8 μm;

[0014] The n-type GaN substrate has a thickness of 15-25 μm and a doping concentration of 5 x 10⁻⁶. 15 -10x1015 cm -3 ;

[0015] The n-type GaN channel layer has a thickness of 0.8-1.5 μm and a doping concentration of 1.5 x 10⁻⁶. 18 -2.5x10 18 cm -3 .

[0016] Furthermore, the Al 0.23 Ga 0.67 The thickness of the N layer is 20-40 nm;

[0017] The thickness of the Si3N4 field plate layer is 18-25 nm;

[0018] The thickness of the Al2O3 protective layer is 18-25 nm;

[0019] The thickness of the diamond-like carbon film layer is 8-15 nm;

[0020] The anode thickness of the Schottky diode is 50-80 nm.

[0021] Furthermore, the drain, the gate, the source, and the Schottky diode cathode are all ohmic contact electrodes, including Ti, Al, Ni, or Au;

[0022] The p+ type GaN layer has a thickness of 25-35 nm and a carrier concentration of 1 x 10⁻⁶. 20 -2x10 20 cm -3 .

[0023] Furthermore, an isolation gap is formed between the isolation layer and the Si3N4 field plate, and one end of the source electrode is filled in the isolation gap.

[0024] Furthermore, a method for fabricating GaN HEMT and SBD device structures is provided, comprising the following steps:

[0025] Provide GaN substrates;

[0026] A nucleation layer, a GaN base layer, an n-type GaN channel layer, and an Al layer are sequentially formed on one side of the substrate. 0.23 Ga 0.67 N-layer and p+ type GaN layer;

[0027] Excess material in the p+ type GaN layer was removed by dry etching with Cl2 / SiCl4.

[0028] In Al 0.23 Ga 0.67A 18-25 nm Si3N4 field plate and an 18-25 nm Al2O3 protective layer are sequentially grown on one side of the N layer.

[0029] Photolithography forms the Al2O3 protective layer, Si3N4 field plate layer, and Al 0.23 Ga 0.67 The isolation trench consists of an N-layer, an n-type GaN channel layer, and a GaN base layer;

[0030] A Si3N4 field plate is grown within the isolation channel, and the Si3N4 field plate is photolithographically formed to create isolation gaps and isolation channels;

[0031] An electrode layer is formed on the surface of the device. The electrode layer is then stripped to form the gate, source, drain, and Schottky diode cathode. After the electrodes are formed, the device is annealed.

[0032] Schottky diode anodes are fabricated using photolithography and atomic layer deposition, while excess metal electrodes are removed by photolithography.

[0033] A diamond-like carbon film is formed on the surface of the device, and excess portions of the diamond-like carbon film are removed by photolithography.

[0034] Furthermore, the GaN substrate is a double-sided polished n-type highly doped self-supporting GaN substrate;

[0035] The following layers are sequentially formed on one side of the substrate: a nucleation layer, a GaN base layer, an n-type GaN channel layer, and an Al layer. 0.23 Ga 0.67 N-layers and p+ type GaN layers include:

[0036] Organic chemical vapor deposition (ECV) was used to sequentially grow 0.3–0.8 μm AlN layers and 15–2 μm n-type GaN layers on GaN substrates, with a doping concentration of 5 x 10⁻⁶. 15 -10x10 15 cm -3 ; 0.8-1.5 μm n-type GaN channel layer with a doping concentration of 1.5 x 10⁻⁶ 18 -2.5x10 18 cm -3 ; 20-40nm Al 0.23 Ga 0.67 The concentration of N, heterojunction 2DEG is 0.8 × 10⁻⁶. 13 -1.2×10 13 cm -2 A 25-35nm p+ type GaN layer with a doping concentration of 1x10⁻⁶. 20 -2x10 20 cm -3 .

[0037] Further, the growth of the Si3N4 field plate within the isolation trench includes:

[0038] A 50 nm Si3N4 field plate was grown in an isolation channel using plasma-enhanced chemical vapor deposition or atomic layer deposition.

[0039] Further, the process of forming an electrode layer on the device surface, forming the gate, source, drain, and Schottky diode cathode using a stripping process on the electrode layer, and annealing after electrode formation includes:

[0040] An electrode layer is formed on the device surface by organic chemical vapor deposition. The electrode layer is then stripped to form the gate, source, drain, and Schottky diode cathode. The electrode layer is then annealed at 650°C in an N2 environment.

[0041] Furthermore, a ring oscillator is provided, comprising the GaN HEMT and SBD device structure as described above, wherein the D-mode HEMT and the E-mode HEMT are connected to form an inverter, and the GaN HEMT and SBD device structure comprises 2n+1 cascaded inverters, wherein n=1,2,3…

[0042] Compared with existing technologies, the GaN HEMT and SBD device structures, fabrication methods, and ring oscillators in this invention have the following advantages:

[0043] In this design, by incorporating a field plate structure on the gallium nitride surface, a good protective effect is achieved, reducing forward conduction resistance and increasing reverse breakdown voltage, thus effectively improving device performance. Furthermore, by employing a GaN HEMT and SBD device structure, the ring oscillator circuit exhibits high accuracy over a wide temperature range. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the GaN HEMT and SBD device structures in an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the epitaxial growth process for preparing GaN HEMT and SBD device structures in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the field plate structure process for preparing GaN HEMT and SBD device structures in an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram illustrating the process of preparing electrodes for GaN HEMT and SBD device structures in an embodiment of the present invention;

[0048] Figure 5This is a schematic diagram of the circuit structure of the ring oscillator in an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of the circuit connection of the inverter in an embodiment of the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0051] Example:

[0052] In this embodiment, combined with Figure 1 A GaN HEMT and SBD (Schottky diode) device structure is provided, comprising:

[0053] Substrate layer 7;

[0054] Nucleation layer 13 stacked on one side of substrate layer 7;

[0055] A D-mode HEMT, an E-mode HEMT, and an SBD are formed on the side of the nucleation layer 13 away from the substrate layer 7 and are arranged sequentially at intervals. An isolation layer 14 is provided between the D-mode HEMT and the E-mode HEMT, and between the E-mode HEMT and the SBD.

[0056] Among them, D-mode HEMT, E-mode HEMT and SBD all include an n-type GaN base layer 12, an n-type GaN channel layer 11 and an Al layer sequentially stacked on the side of the nucleation layer 13 facing away from the substrate layer 7. 0.23 Ga 0.67 N layer 3, Si3N4 field plate layer 15, Al2O3 protective layer 9 and diamond-like thin film layer 1;

[0057] Both D-mode HEMT and E-mode HEMT also include a Si3N4 field plate 4 connected to one side of the corresponding n-type GaN substrate 12 and n-type GaN channel layer 11, and connected to the Si3N4 field plate 4 and the corresponding n-type GaN channel layer 11, Al 0.23 Ga 0.67 The drain 2 of the N-layer 3 and the Si3N4 field plate layer 15 is connected to the corresponding n-type GaN channel layer 11 and Al. 0.23 Ga 0.67 The source 2 of N-layer 3, Si3N4 field plate layer 15, and connected to the corresponding Al 0.23 Ga 0.67 Gate 5 of N-layer 3, Si3N4 field plate layer 15; Gate 5 of E-mode HEMT and Al0.23 Ga 0.67 A p+ type GaN layer 8 is set between N layers 3;

[0058] SBD also includes connections to the corresponding n-type GaN channel layer 11 and Al. 0.23 Ga 0.67 The Schottky diode anode 10 is located on one side of the N-layer 3, Si3N4 field plate layer 15, and Al2O3 protective layer 9, and is also located on the Al-layer 9. 0.23 Ga 0.67 The Schottky diode cathode consists of an N-layer 3, a Si3N4 field plate layer 15, and an Al2O3 protective layer 9, connected to an n-type GaN channel layer 11. The Schottky diode cathode is a ring structure surrounding the Schottky diode anode 10.

[0059] In this scheme, by setting a field plate structure on the gallium nitride surface, a good protective effect can be formed, the forward conduction resistance can be reduced and the reverse breakdown voltage can be increased, effectively improving the performance of the device.

[0060] In this embodiment, the substrate 7 is a double-sided polished n-type highly doped self-supporting GaN substrate with a thickness greater than or equal to 1 μm. In some embodiments, the substrate 7 may also be a SiC substrate.

[0061] The nucleation layer 13 comprises AlN and has a thickness of 0.3-0.8 μm. Preferably, in this embodiment, the thickness of the nucleation layer 13 is preferably 0.5 μm.

[0062] The n-type GaN substrate has a thickness of 15-25 μm and a doping concentration of 5 x 10⁻⁶. 15 -10x10 15 cm -3 Preferably, in this embodiment, the n-type GaN substrate 12 is 20 μm thick and the doping concentration is 8 x 10⁻⁶. 15 cm -3 .

[0063] The n-type GaN channel layer has a thickness of 0.8-1.5 μm and a doping concentration of 1.5 x 10⁻⁶. 18 -2.5x10 18 cm -3 Preferably, in this embodiment, the n-type GaN channel layer 11 has a thickness of 1 μm and a doping concentration of 2 x 10⁻⁶. 18 cm -3 .

[0064] Al 0.23 Ga 0.67 The thickness of the N-layer 3 is 20-40 nm, preferably 30 nm.

[0065] The thickness of the Si3N4 field plate 15 is 18-25nm, preferably 20nm.

[0066] The thickness of the Al2O3 protective layer 9 is 18-25 nm, preferably 20 nm.

[0067] The thickness of the diamond-like carbon film layer 1 is 8-15 nm, preferably 10 nm.

[0068] The thickness of the anode 10 of the Schottky diode is 50-80 nm, preferably 60 nm. The anode 10 of the Schottky diode can be made of Ni or Au.

[0069] Drain 2, gate 5, source 2 and Schottky diode cathode are all ohmic contact electrodes, which can be 20nm Ti layer, 200mAl layer, 55nm Ni layer or 45nm Au layer.

[0070] The p+ type GaN layer has a thickness of 25-35 nm and a carrier concentration of 1 x 10⁸. 20 -2x10 20 cm -3 Preferably, the p+ type GaN layer 8 has a thickness of 30 nm and a carrier concentration of 1.5 x 10⁸. 20 cm -3 .

[0071] In this embodiment, an isolation gap is formed between the isolation layer 14 and the Si3N4 field plate 4, and one end of the source electrode 2 is filled in the isolation gap. The thickness of the Si3N4 field plate 4 is 40-70 nm, preferably 50 nm.

[0072] In some embodiments, the Si3N4 material can be changed to materials such as Al2O3 or SiO2.

[0073] Furthermore, combined Figure 2-4 This paper provides a method for fabricating GaN HEMT and SBD device structures, comprising the following steps:

[0074] S1. Provide a GaN substrate; the GaN substrate is a double-sided polished n-type highly doped self-supporting GaN substrate.

[0075] S2. Sequentially forming a nucleation layer 13, a GaN base layer 12, an n-type GaN channel layer 11, and an Al layer on one side of the substrate layer 7. 0.23 Ga 0.67 Three N-layers and eight p+ type GaN layers;

[0076] Specifically, in this embodiment, the step includes: sequentially growing 0.3-0.8 μm AlN, preferably 0.5 μm, and 15-2 μm n-type GaN base layer 12 on a GaN substrate using organic chemical vapor deposition, with a doping concentration of 5 x 10⁻⁶. 15 -10x10 15 cm-3 Preferably, in this embodiment, the n-type GaN substrate 12 is 20 μm thick and the doping concentration is 8 x 10⁻⁶. 15 cm -3 ; 0.8-1.5 μm n-type GaN channel layer with a doping concentration of 1.5 x 10⁻⁶ 18 -2.5x10 18 cm -3 Preferably, in this embodiment, the n-type GaN channel layer 11 has a thickness of 1 μm and a doping concentration of 2 x 10⁻⁶. 18 cm -3 ; 20-40nm Al 0.23 Ga 0.67 N, preferably 30 nm, and the concentration of heterojunction 2DEG is 0.8 × 10⁻⁶. 13 -1.2×10 13 cm -2 ; 25-35nm p+ type GaN layer 8, with a doping concentration of 1x10⁸ 20 -2x10 20 cm -3 Preferably, the p+ type GaN layer 8 has a thickness of 30 nm and a carrier concentration of 1.5 x 10⁸. 20 cm -3 .

[0077] S3. Remove excess material from the p+ type GaN layer 8 using a Cl2 / SiCl4 dry etching method;

[0078] S4, in Al 0.23 Ga 0.67 A 18-25 nm Si3N4 field plate layer 15 and an 18-25 nm Al2O3 protective layer 9 are sequentially grown on one side of the N layer 3. In this embodiment, a 20 nm Si3N4 field plate 4 is grown on the surface of the GaN-based device structure using plasma-enhanced chemical vapor deposition or atomic layer deposition to protect the structure surface.

[0079] S5, Photolithography forms the Al2O3 protective layer 9, Si3N4 field plate layer, Al 0.23 Ga 0.67 The isolation channel consists of N-layer 3, n-type GaN channel layer 11, and GaN base layer 12; to create a barrier layer.

[0080] S6. A Si3N4 field plate 4 is grown in the isolation channel, and the Si3N4 field plate 4 is photolithographically formed to form isolation gaps and isolation channels; specifically, a 50nm Si3N4 field plate 4 is grown in the isolation channel using plasma-enhanced chemical vapor deposition or atomic layer deposition.

[0081] S7. An electrode layer is formed on the device surface. The electrode layer is then stripped to form the gate 5, source 2, drain 2, and Schottky diode cathode. After forming the electrodes, the device is annealed. In this step, an electrode layer is formed on the device surface by organic chemical vapor deposition. The electrode layer is then stripped to form the gate 5, source, drain, and Schottky diode cathode ohmic contact electrodes (such as TI / Al / Ni / Au). The device is then annealed at 650℃ in an N2 environment.

[0082] S8. The Schottky diode anode 10 (Schottky contact electrode, such as Ni / Au) is fabricated by photolithography and atomic layer deposition, and excess metal electrode is removed by photolithography;

[0083] S9. A 20nm diamond-like carbon film is deposited on the device surface by chemical vapor deposition (CVD), and excess parts of the diamond-like carbon film are removed by photolithography.

[0084] Furthermore, combined Figure 5 A ring oscillator is provided, comprising a GaN HEMT and SBD device structure as described above, wherein a D-mode HEMT and an E-mode HEMT are connected to form an inverter, and the GaN HEMT and SBD device structure comprises 2n+1 cascaded inverters, wherein n=1,2,3…

[0085] The circuit structure is as follows: Figure 5 As shown, the circuit is powered by VDD. On the left side, a voltage reference circuit consisting of two GaN SBDs, one D-mode, and two E-mode HEMTs provides VREF to the next stage ring oscillator. The two SBDs (Schottky diodes) provide the negative temperature coefficient voltage (CTAT), while the D-mode and E-mode provide the positive temperature coefficient voltage (PTAT). By canceling out the positive and negative temperature coefficients, extremely low voltage variation can be achieved over a wide temperature range, resulting in a high-precision voltage reference. The ring oscillator consists of 2n+1 (n=1,2,3…) cascaded inverters. Each inverter is composed of one D-mode and one E-mode HEMT, connected as shown in the diagram. Figure 6 As shown, the gate 5 and source of the D-mode are connected to the drain of the E-mode as the output. The drain of the D-mode is connected to the power supply voltage (VDD), the gate 5 of the E-mode is connected to the input, and the source is grounded. The last stage is connected to the input to form a loop, and the final output Vosc is a waveform with a fixed period. In this scheme, the ring oscillator circuit has high accuracy over a wide temperature range.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A GaN HEMT and SBD device structure, characterized in that, include: Substrate layer; A nucleation layer stacked on one side of the substrate layer; A D-mode HEMT, an E-mode HEMT, and an SBD are formed on the side of the nucleation layer away from the substrate layer and are arranged sequentially at intervals. An isolation layer is provided between the D-mode HEMT and the E-mode HEMT, and between the E-mode HEMT and the SBD. The D-mode HEMT, the E-mode HEMT, and the SBD all include an n-type GaN substrate, an n-type GaN channel layer, and an Al layer sequentially stacked on the side of the nucleation layer facing away from the substrate. 0.23 Ga 0.67 N-layer, Si3N4 field plate layer, Al2O3 protective layer and diamond-like thin film layer; Both the D-mode HEMT and the E-mode HEMT further include a Si3N4 field plate connected to one side of the corresponding n-type GaN substrate and n-type GaN channel layer, and connected to the Si3N4 field plate and the corresponding n-type GaN channel layer and Al. 0.23 Ga 0.67 The drain of the N-layer and Si3N4 field plate layer is connected to the corresponding n-type GaN channel layer and Al. 0.23 Ga 0.67 The source of the N-layer, Si3N4 field plate layer, and the corresponding Al 0.23 Ga 0.67 The gate of the N-layer, Si3N4 field plate layer; the gate of the E-mode HEMT and Al 0.23 Ga 0.67 A p+ type GaN layer is set between N layers; The SBD also includes connections to the corresponding n-type GaN channel layer and Al. 0.23 Ga 0.67 The Schottky diode anode is located on one side of the N-layer, Si3N4 field plate, and Al2O3 protective layer, and is also located in the Al layer. 0.23 Ga 0.67 Schottky diode cathode consisting of an N-layer, a Si3N4 field plate layer, and an Al2O3 protective layer connected to an n-type GaN channel layer.

2. The GaN HEMT and SBD device structure according to claim 1, characterized in that, The substrate is a double-sided polished n-type highly doped self-supporting GaN substrate with a thickness greater than or equal to 1 μm; The nucleation layer comprises AlN and has a thickness of 0.3-0.8 μm; The n-type GaN substrate has a thickness of 15-25 μm and a doping concentration of 5 x 10⁻⁶. 15 -10x10 15 cm -3 ; The n-type GaN channel layer has a thickness of 0.8-1.5 μm and a doping concentration of 1.5 x 10⁻⁶. 18 -2.5x10 18 cm -3 .

3. The GaN HEMT and SBD device structure according to claim 2, characterized in that... : The Al 0.23 Ga 0.67 The thickness of the N layer is 20-40 nm; The thickness of the Si3N4 field plate layer is 18-25 nm; The thickness of the Al2O3 protective layer is 18-25 nm; The thickness of the diamond-like carbon film layer is 8-15 nm; The anode thickness of the Schottky diode is 50-80 nm.

4. The GaN HEMT and SBD device structure according to claim 1, characterized in that, The drain, the gate, the source, and the Schottky diode cathode are all ohmic contact electrodes, including Ti, Al, Ni, or Au; The p+ type GaN layer has a thickness of 25-35 nm and a carrier concentration of 1 x 10⁻⁶. 20 -2x10 20 cm -3 .

5. The GaN HEMT and SBD device structure according to any one of claims 1-4, characterized in that, An isolation gap is formed between the isolation layer and the Si3N4 field plate, and one end of the source electrode is filled in the isolation gap.

6. A method for fabricating GaN HEMT and SBD device structures, characterized in that, Includes the following steps: Provide GaN substrates; A nucleation layer, a GaN base layer, an n-type GaN channel layer, and an Al layer are sequentially formed on one side of the GaN substrate. 0.23 Ga 0.67 N-layer and p+ type GaN layer; Excess material in the p+ type GaN layer was removed by dry etching with Cl2 / SiCl4. In Al 0.23 Ga 0.67 A 18-25 nm Si3N4 field plate and an 18-25 nm Al2O3 protective layer are sequentially grown on one side of the N layer. Photolithography forms the Al2O3 protective layer, Si3N4 field plate layer, and Al 0.23 Ga 0.67 The isolation trench consists of an N-layer, an n-type GaN channel layer, and a GaN base layer; A Si3N4 field plate is grown within the isolation channel, and the Si3N4 field plate is photolithographically formed to create isolation gaps and isolation channels; An electrode layer is formed on the surface of the device. The electrode layer is then stripped to form the gate, source, drain, and Schottky diode cathode. After the electrodes are formed, the device is annealed. Schottky diode anodes are fabricated using photolithography and atomic layer deposition, while excess metal electrodes are removed by photolithography. A diamond-like carbon film is formed on the surface of the device, and excess portions of the diamond-like carbon film are removed by photolithography.

7. The fabrication method of GaN HEMT and SBD device structures according to claim 6, characterized in that, The GaN substrate is a double-sided polished n-type highly doped self-supporting GaN substrate; The formation of a nucleation layer, a GaN base layer, an n-type GaN channel layer, and an Al layer is sequentially formed on one side of the GaN substrate. 0.23 Ga 0.67 N-layers and p+ type GaN layers include: Organic chemical vapor deposition (ECV) was used to sequentially grow 0.3–0.8 μm AlN layers and 15–2 μm n-type GaN layers on GaN substrates, with a doping concentration of 5 x 10⁻⁶. 15 -10x10 15 cm -3 ; 0.8-1.5 μm n-type GaN channel layer with a doping concentration of 1.5 x 10⁻⁶ 18 -2.5x10 18 cm -3 ; 20-40nm Al 0.23 Ga 0.67 The concentration of N, heterojunction 2DEG is 0.8 × 10⁻⁶. 13 -1.2×10 13 cm -2 A 25-35nm p+ type GaN layer with a doping concentration of 1x10⁻⁶. 20 -2x10 20 cm -3 .

8. The method for fabricating GaN HEMT and SBD device structures according to claim 7, characterized in that, The process of growing a Si3N4 field plate within the isolation trench includes: A 50 nm Si3N4 field plate was grown in an isolation channel using plasma-enhanced chemical vapor deposition or atomic layer deposition.

9. The method for fabricating GaN HEMT and SBD device structures according to claim 6, characterized in that, The process involves forming an electrode layer on the device surface, using a stripping process to form the gate, source, drain, and Schottky diode cathode on the electrode layer, followed by annealing after electrode formation, including: An electrode layer is formed on the device surface by organic chemical vapor deposition. The electrode layer is then stripped to form the gate, source, drain, and Schottky diode cathode. The electrode layer is then annealed at 650°C in an N2 environment.

10. A ring oscillator, characterized in that, The device includes the GaN HEMT and SBD device structure as described in any one of claims 1-9, wherein the D-mode HEMT and the E-mode HEMT are connected to form an inverter, and the GaN HEMT and SBD device structure includes 2n+1 cascaded inverters, where n=1,2,3…

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