Method for manufacturing a semiconductor package, semiconductor package, and imaging device

Abstract

The present disclosure provides a method for manufacturing a semiconductor package, a semiconductor package, and an imaging device. The method for manufacturing the semiconductor package includes: preparing a substrate having a first connection region and a sensor chip having a second connection region; disposing a first bonding layer including a multi-layer nano low-melting-point metal material having different melting point gradients on the first connection region of the substrate; disposing a second bonding layer including a multi-layer nano low-melting-point metal material having different melting point gradients on the second connection region of the sensor chip; stacking the substrate and the sensor chip on top of each other so that the first bonding layer and the second bonding layer are aligned and pressed against each other to obtain a composite structure; and processing the composite structure at a temperature of 30-180 °C, a pressure of 1-8 Mpa, and ultrasonic waves of 10-30 kHz for a period of time so that the first bonding layer and the second bonding layer form a eutectic crystal.

Description

Technical Field

[0001] Exemplary embodiments of the inventive concept relate to the field of semiconductor packaging, and more particularly, to a method of manufacturing the semiconductor package, a semiconductor package, and an imaging device including the semiconductor package. Background Art

[0002] In recent years, as consumer electronic products tend to be miniaturized, the packaging of semiconductor chips also develops towards miniaturization and microminiaturization. In the field of camera chip packaging, ultra-thin packaging has become a development trend, and how to reduce the packaging thickness of camera chips has become the focus of the industry.

[0003] Currently, the chip packaging for cameras mainly includes chip on board (COB) and flip chip. Figure 1 The top view of a packaging structure formed by bonding a sensor chip to a substrate using the prior art COB packaging method is shown. Figure 2 The side view of a packaging structure formed by bonding a sensor chip to a substrate using the prior art COB packaging method is shown. As Figure 1 and Figure 2 shown, the sensor chip 1 is bonded to the substrate 2 through an adhesive layer, and then the pads 3 of the sensor chip 1 and the pads 4 of the substrate 2 are electrically connected to each other via wires 5 through a wire bonding process. The wires 5 usually may include gold wires. However, due to the wire arc height of the COB package, it will occupy a certain space, which is not conducive to the ultra-thinning of the package. At the same time, there will also be problems such as stray light interference caused by light reflection in the wires.

[0004] Therefore, in order to overcome the deficiencies of the COB process, some high-end camera packages currently adopt the flip chip process. Figure 3 The cross-sectional view of a packaging structure formed by bonding a sensor chip to a substrate using the prior art flip chip packaging method is shown. As Figure 3As shown, first, spherical bumps 5 are fabricated on the pads 3 of the sensor chip 1. Then, through special processes such as thermocompression and ultrasonic waves, the spherical bumps 5 of the sensor chip 1 are aligned with the pads 4 of the substrate 2 and then connected. Finally, a potting process is used to coat insulating glue around the sensor chip 1 for sealing to improve reliability. Since the flip chip process inverts and embeds the chip into the opening window of the substrate, the chip packaging thickness can be significantly reduced, thereby further reducing the overall height of the camera module. However, the flip chip process requires the fabrication of spherical bumps, and the height of the gold balls is usually between 10μm and 50μm. Although the height of the gold balls can be minimized by controlling the process conditions, there is still a certain height of the gold balls. In addition, the flip chip process requires multiple processes such as high temperature, high pressure, and ultrasonic waves, with complex processes, high difficulty, high energy consumption, and high cost.

[0005] The above information disclosed in this background art section is only used to enhance the understanding of the background of the inventive concept. Therefore, the above information may include information that does not form the prior art already known to those skilled in the art in this country. Summary of the Invention

[0006] Exemplary embodiments of the inventive concept disclose a method of manufacturing a semiconductor package that can solve problems such as complex existing packaging processes, high energy consumption, and high costs.

[0007] Exemplary embodiments of the inventive concept disclose a semiconductor package capable of achieving ultra-thin packaging and an imaging device including the semiconductor package.

[0008] In one aspect of the inventive concept, there is provided a method of manufacturing a semiconductor package, the method comprising the steps of: preparing a substrate having a first connection region and a sensor chip having a second connection region; disposing a first bonding layer including a multi-layer nano low melting point metal material having different melting point gradients on the first connection region of the substrate; disposing a second bonding layer including a multi-layer nano low melting point metal material having different melting point gradients on the second connection region of the sensor chip; stacking the substrate and the sensor chip on top of each other so that the first bonding layer and the second bonding layer are aligned and pressed against each other to obtain a composite structure; and processing the composite structure at a temperature of 30 - 180°C, a pressure of 1 - 8 Mpa, and ultrasonic waves of 10 - 30 kHz for a period of time so that the first bonding layer and the second bonding layer form a eutectic.

[0009] Further, the melting point of each layer of the multi-layer nano low melting point metal material may decrease as it is farther away from the first connection region or the second connection region.

[0010] Further, each layer of the multi-layer nano low-melting-point metal material may include one of gold, silver, aluminum, copper, zinc, tin, lead, antimony, bismuth, lithium, indium, magnesium, gallium, cadmium, and their alloys.

[0011] Further, the first bonding layer and the second bonding layer may be composed of different nano low-melting-point metal materials.

[0012] Further, the thickness of each layer of the multi-layer nano low-melting-point metal material may be substantially 10 - 800 nanometers.

[0013] Further, the step of processing the composite structure may include increasing the processing temperature stepwise to reach the final reaction temperature, and may include at least one heat preservation stage before reaching the final reaction temperature.

[0014] On the other hand of the inventive concept, a semiconductor package is provided, which includes: a substrate including a first connection area; a sensor chip including a second connection area; a first bonding layer on the first connection area; and a second bonding layer on the second connection area, wherein the substrate and the sensor chip are bonded to each other by forming a eutectic crystal from the first bonding layer and the second bonding layer, and wherein both the first bonding layer and the second bonding layer include a multi-layer nano low-melting-point metal material having different melting point gradients.

[0015] Further, the melting point of each layer of the multi-layer nano low-melting-point metal material may decrease as it is farther away from the first connection area or the second connection area.

[0016] Further, each layer of the multi-layer nano low-melting-point metal material may include one of gold, silver, aluminum, copper, zinc, tin, lead, antimony, bismuth, lithium, indium, magnesium, gallium, cadmium, and their alloys.

[0017] Further, the substrate may include a first part and a second part both in an inverted L shape, and the first part and the second part are arranged opposite to each other to form an opening window, and the sensor chip is built in the opening window.

[0018] Further, the first connection area may be located on the inner surfaces of the first part and the second part of the substrate, the second connection area may be located on the upper surface of the sensor chip, and the first bonding layer and the second bonding layer are aligned and bonded to each other in the vertical direction.

[0019] Another aspect of the inventive concept provides an imaging device including a camera module including a lens, a filter, and a semiconductor package. The semiconductor package includes: a substrate including a first connection area; a sensor chip including a second connection area; a first bonding layer on the first connection area; and a second bonding layer on the second connection area. Wherein, the substrate and the sensor chip are bonded to each other by forming a eutectic crystal with the first bonding layer and the second bonding layer, and wherein both the first bonding layer and the second bonding layer include a multi-layer nano low-melting-point metal material having different melting point gradients.

[0020] Further, the melting point of each layer of the multi-layer nano low-melting-point metal material may decrease as it is farther away from the first connection area or the second connection area.

[0021] Further, each layer of the multi-layer nano low-melting-point metal material may include one of gold, silver, aluminum, copper, zinc, tin, lead, antimony, bismuth, lithium, indium, magnesium, gallium, cadmium, and their alloys.

[0022] Further, the substrate may include a first part and a second part both in an inverted L shape, and the first part and the second part are arranged opposite to each other to form a window, and the sensor chip is built in the window.

[0023] Further, the substrate may be a circuit board.

[0024] Further, the substrate may be mounted on a circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features and advantages of the inventive concept will become apparent from the following detailed description of exemplary embodiments of the inventive concept in conjunction with the drawings. In the drawings, the same reference numerals will always indicate the same elements.

[0026] Figure 1 A top view showing a package structure formed by bonding a sensor chip to a substrate using the prior art COB packaging method.

[0027] Figure 2 A side view showing a package structure formed by bonding a sensor chip to a substrate using the prior art COB packaging method.

[0028] Figure 3 A cross-sectional view showing a package structure formed by bonding a sensor chip to a substrate using the prior art flip chip packaging method.

[0029] Figure 4 A process flow chart showing a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0030] Figure 5 Shows a temperature curve in a method of manufacturing a semiconductor package according to a first embodiment of the inventive concept.

[0031] Figure 6 Shows a temperature curve in a method of manufacturing a semiconductor package according to a second embodiment of the inventive concept.

[0032] Figure 7 Shows a temperature curve in a method of manufacturing a semiconductor package according to a third embodiment of the inventive concept.

[0033] Figure 8 Shows a schematic diagram of a semiconductor package structure according to a first embodiment of the inventive concept.

[0034] Figure 9 Shows a schematic diagram of a semiconductor package structure according to a second embodiment of the inventive concept.

[0035] Figure 10 Shows a schematic diagram of an imaging device structure according to a first embodiment of the inventive concept.

[0036] Figure 11 Shows a schematic diagram of an imaging device structure according to a second embodiment of the inventive concept. Detailed Description

[0037] Hereinafter, various embodiments of the inventive concept will be described more fully with reference to the accompanying drawings in which some embodiments are shown. However, the inventive concept may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this description will be thorough and complete, and will convey the scope of the inventive concept to those skilled in the art. In the drawings, the dimensions of layers and regions may be exaggerated for clarity.

[0038] For ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element to other elements as shown in the drawings. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as "under" or "below" other elements will then be oriented "above" the other elements. Thus, the term "under" may encompass both an orientation of "above" and "under". The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0039] Hereinafter, reference will be made to Figures 4 to 7 to describe in detail a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0040] Figure 4 A process flowchart showing a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept is shown. As Figure 4 shown, a method of manufacturing a semiconductor package according to a first embodiment of the inventive concept includes: Step S1, preparing a substrate having a first connection area and a sensor chip having a second connection area. In an embodiment, the substrate may be a substrate commonly used in the prior art for manufacturing semiconductor packages. The substrate may include various materials and structures commonly used in the art. In an embodiment, the sensor chip may be any type of image sensor chip commonly used in imaging devices for electronic products in the art. However, the inventive concept is not limited thereto, and the substrate and the sensor chip may also include all variant embodiments and equivalent arrangements covered by the inventive concept.

[0041] Step S2, disposing a first bonding layer including a multi-layer nano low melting point metal material having different melting point gradients on the first connection area of the substrate. Step S3, disposing a second bonding layer including a multi-layer nano low melting point metal material having different melting point gradients on the second connection area of the sensor chip. In an embodiment, steps S2 and S3 are not limited to the order described herein. Steps S2 and S3 may be performed simultaneously in the same process, or step S2 may be performed after step S3. In an embodiment, the first bonding layer and the second bonding layer may be respectively disposed on the first connection area and the second connection area via a coating process. Here, the coating process may be a nano-coating preparation process commonly used in the prior art. The coating process may also be a physical or chemical film-forming process commonly used in the prior art, such as a plasma coating process, a chemical vapor deposition process, or a physical sputtering process.

[0042] In an embodiment, the steps of disposing the first bonding layer and the second bonding layer may include respectively coating a multi-layer nano low melting point metal material having different melting point gradients on the first connection area and the second connection area by using a coating process. The multi-layer nano low melting point metal material may include at least two layers, for example, three layers, four layers or more metal layers. The melting point of each layer may decrease as it is farther away from the first connection area or the second connection area to form a melting point gradient.

[0043] In an embodiment, each layer of the multi-layer nano low-melting-point metal material forming the first bonding layer and the second bonding layer may include one of gold, silver, aluminum, copper, zinc, tin, lead, antimony, bismuth, lithium, indium, magnesium, gallium, cadmium, and their alloys. In an embodiment, the first bonding layer and the second bonding layer may be composed of the same or different nano low-melting-point metal materials. As long as the selected nano metal material can form a melting point gradient that meets the process requirements.

[0044] In an embodiment, the thickness of each layer of the nano low-melting-point metal material may be formed to be approximately 10 - 800 nanometers. The thickness of each layer of the multi-layer nano low-melting-point metal material may be different from each other according to the properties of the metals used and the changes in process conditions, as long as it can ensure that the first bonding layer and the second bonding layer can achieve eutectic fusion at a lower temperature to form a eutectic.

[0045] Step S4, stack the substrate and the sensor chip on top of each other so that the first bonding layer and the second bonding layer are aligned and pressed against each other to obtain a composite structure. Step S5, process the obtained composite structure at a temperature of 30 - 180 °C, a pressure of 1 - 8 Mpa, and ultrasonic waves of 10 - 30 kHz for a period of time so that the first bonding layer and the second bonding layer form a eutectic.

[0046] The method for manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept employs three process conditions, namely temperature, pressure, and ultrasonic treatment. Among them, pressure and ultrasonic treatment are applied from the start of the reaction until the end of the reaction, and the temperature process condition may include gradually increasing the treatment temperature in a stepwise manner to reach the final reaction temperature, and may include at least one heat preservation stage before reaching the final reaction temperature. This will be described in detail below in conjunction with Figure 5 、 Figure 6 and Figure 7 Detailed description.

[0047] Under the process conditions of step S5, the multi-layer nano low-melting-point metal materials of the first bonding layer and the second bonding layer with different melting point gradients undergo eutectic fusion, resulting in a further reduction in the melting point. According to the eutectic reaction principle, the melting point of the eutectic compound can be lower than the melting point of each metal material. At the same time, by utilizing the high activity of the nano material, the reaction temperature is further reduced. The applied pressure and ultrasonic vibration can promote the movement and diffusion of the upper layer metal material molecules downward, which helps to accelerate the reaction process, and ultimately enables the bonding of the sensor chip and the substrate at a temperature of 30 - 180 °C, a pressure of 1 - 8 Mpa, and ultrasonic vibration of 10 - 30 kHz, directly connecting the sensor chip and the substrate.

[0048] After the end of step S5, the temperature, pressure, and ultrasonic treatment can be maintained for a period of time and then cooled. Next, a sealant can be applied to the edge of the area where the sensor chip is bonded to the substrate for sealing, and then the sealant is cured, thus completing the encapsulation of the sensor chip and the substrate.

[0049] Hereinafter, a method for manufacturing a semiconductor package according to the inventive concept will be described in detail with reference to three specific embodiments. Since steps S1 and S4 of the above three embodiments are substantially the same, steps S2, S3, and S5 will be described in detail below.

[0050] Figure 5 A temperature curve diagram in a method for manufacturing a semiconductor package according to a first embodiment of the inventive concept is shown.

[0051] In the first embodiment, a silver, aluminum, magnesium, gallium metal multi-layer nano-gradient coating can be sequentially prepared on the surface of the first connection area of the substrate in step S2 to form a first bonding layer. A gold, silver, tin, indium metal multi-layer nano-gradient coating can be sequentially prepared on the surface of the second connection area of the sensor chip in step S3 to form a second bonding layer. The process for preparing the coating can be various commonly used nano-coating processes or physical or chemical film-forming processes mentioned above. The selected nano-metal materials can have a gradient in which the melting point decreases as the distance from the first connection area or the second connection area increases. However, the "gradient" described here does not mean that the melting point must decrease layer by layer, as long as the melting points of the respective layers of the finally prepared nano-coating generally show a decreasing trend, it falls within the protection scope of the inventive concept.

[0052] In step S5, heating can be carried out according to the temperature curve T1, a pressure of 1 Mpa is applied, and ultrasonic treatment is carried out at 30 kHz. As Figure 5 shown, before reaching the final reaction temperature of 180 °C, the temperature curve T1 includes three heating stages and two holding stages. After the reaction starts, the temperature is raised to 70 °C through the first heating stage and held at 70 °C through the first holding stage. Then, the temperature is raised to 150 °C through the second heating stage and held at 150 °C through the second holding stage. Then, the temperature is raised to the final reaction temperature of 180 °C through the third heating stage. This process feature of stepwise increasing the reaction temperature and experiencing multiple holding stages can promote the diffusion of the molecules of the multi-layer nano-metal materials with different melting point gradients of the first bonding layer and the second bonding layer to the next layer. The multiple holding stages can provide sufficient eutectic bonding reaction time, ensure the smooth progress of the eutectic bonding reaction, improve the quality of the obtained eutectic, and improve the reliability of the semiconductor package.

[0053] After the end of step S5, the final reaction temperature of 180 °C, the applied pressure, and the ultrasonic treatment can be maintained for a period of time and then cooled, which corresponds to Figure 5 the third heat preservation stage and the subsequent cooling stage shown in

[0054] Figure 6 A temperature curve diagram in a method for manufacturing a semiconductor package according to a second embodiment of the inventive concept is shown.

[0055] In the second embodiment, a lithium, bismuth-tin alloy, and gallium metal multi-layer nano-gradient coating can be sequentially prepared on the surface of the first connection area of the substrate in step S2 to form a first bonding layer. A tin, lead-tin alloy, and indium metal multi-layer nano-gradient coating can be sequentially prepared on the surface of the second connection area of the sensor chip in step S3 to form a second bonding layer.

[0056] In step S5, heating can be performed according to temperature curve T2, a pressure of 8 Mpa can be applied, and ultrasonic treatment at 30 kHz can be used. As Figure 6 shown, before reaching the final reaction temperature of 30 °C, temperature curve T2 includes two heating stages and one heat preservation stage. After the reaction starts, the temperature is raised to 25 °C through the first heating stage and the first heat preservation stage is experienced at 25 °C. The temperature is raised to the final reaction temperature of 30 °C through the second heating stage. This process realizes a low-temperature eutectic reaction, can reduce the temperature to room temperature, greatly simplifies the process, significantly saves energy, significantly reduces costs, and at the same time, a semiconductor package with excellent reliability can be obtained.

[0057] After the end of step S5, the final reaction temperature of 30 °C, the applied pressure, and the ultrasonic treatment can be maintained for a period of time and then cooled, which corresponds to Figure 6 the second heat preservation stage and the subsequent cooling stage shown in

[0058] Figure 7 A temperature curve diagram in a method for manufacturing a semiconductor package according to a third embodiment of the inventive concept is shown.

[0059] In the third embodiment, an aluminum, antimony, bismuth-lead alloy, and gallium metal multi-layer nano-gradient coating can be sequentially prepared on the surface of the first connection area of the substrate in step S2 to form a first bonding layer. A copper, magnesium, tin, and lead metal multi-layer nano-gradient coating can be sequentially prepared on the surface of the second connection area of the sensor chip in step S3 to form a second bonding layer.

[0060] In step S5, heating can be performed according to the temperature curve T3, a pressure of 4 Mpa is applied, and ultrasonic treatment is performed at 20 kHz. As Figure 7 shown, before reaching the final reaction temperature of 90 °C, the temperature curve T1 includes four heating stages and three holding stages. After the reaction starts, the temperature is raised to 30 °C through the first heating stage and held at 30 °C in the first holding stage. Then, the temperature is raised to 40 °C through the second heating stage and held at 40 °C in the second holding stage. Then, the temperature is raised to 80 °C through the third heating stage and held at 80 °C in the third holding stage. Then, the temperature is raised to the final reaction temperature of 90 °C through the fourth heating stage. As described above, this process feature of stepwise increasing the reaction temperature and experiencing multiple holding stages can obtain high-quality eutectics and improve the reliability of the semiconductor package.

[0061] After step S5 ends, the final reaction temperature of 90 °C, the applied pressure, and the ultrasonic treatment can be maintained for a period of time and then cooled, which corresponds to Figure 7 the fourth holding stage and the subsequent cooling stage shown in

[0062] Next, subsequent processes such as gluing and curing are performed to complete the encapsulation. Figures 8 to 11 Hereinafter, a semiconductor package obtained by using a method for manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept and an imaging device including the semiconductor package will be described in detail with reference to

[0063] Figure 8 FIG. shows a schematic structural diagram of a semiconductor package according to a first embodiment of the inventive concept. As Figure 8 shown, the semiconductor package 100 according to the first embodiment of the inventive concept includes: a substrate 110 including a first connection region 111; a sensor chip 120 including a second connection region 121; a first bonding layer 130 on the first connection region 111; and a second bonding layer 140 on the second connection region 121. The substrate 110 and the sensor chip 120 are bonded to each other by forming a eutectic with the first bonding layer 130 and the second bonding layer 140. Both the first bonding layer 130 and the second bonding layer 140 include a multi-layer nano low-melting-point metal material having different melting point gradients.

[0064] Figure 8The semiconductor package 100 of the first embodiment in can be a package with a COB package structure. In the embodiment, the substrate 110 can be a substrate of any type and material commonly used in the art for semiconductor packages. The first connection region 111 can be directly provided or buried on the substrate 110. For example, the first connection region 111 can be provided on the upper surface of the substrate 110. However, the inventive concept is not limited thereto, and the first connection region can also be provided on the lower surface of the substrate.

[0065] In the embodiment, the first connection region 111 can be a conductive pad or a conductive bonding pad, or a region capable of being electrically connected to a conductive pad or a conductive bonding pad. The first connection region 111 can be provided at an edge portion of the substrate 110. However, the inventive concept is not limited thereto, and the first connection region can also be provided at the center of the substrate.

[0066] In the embodiment, the sensor chip 120 can be any type of image sensor chip commonly used in imaging devices of electronic products in the art. The second connection region 121 can be provided on the sensor chip 120. For example, the second connection region 121 can be directly provided or buried on the lower surface of the sensor chip 120. However, the inventive concept is not limited thereto, and the second connection region can also be provided on the upper surface of the sensor chip.

[0067] In the embodiment, the second connection region 121 can be a conductive pad or a conductive bonding pad, or a region capable of being electrically connected to a conductive pad or a conductive bonding pad. The second connection region 121 can be provided at an edge portion of the sensor chip 120. However, the inventive concept is not limited thereto, and the second connection region can also be provided at the center of the sensor chip.

[0068] In the embodiment, the positions of the first connection region 111 and the second connection region 121 can correspond to each other such that when the substrate 110 and the sensor chip 120 are stacked on each other, the first bonding layer 130 and the second bonding layer 140 can be aligned, thereby avoiding poor connection caused by misalignment of the bonding layers and resulting in electrical performance defects of the package.

[0069] In the embodiment, the first bonding layer 130 and the second bonding layer 140 can be respectively provided on the first connection region 111 and the second connection region 121 via a coating process. Here, the coating process can be a nano-coating preparation process commonly used in the prior art. The coating process can also be a physical or chemical film-forming process commonly used in the prior art such as chemical vapor deposition or physical sputtering. In the embodiment, the first bonding layer 130 and the second bonding layer 140 can be formed of a low-temperature eutectic material with a thickness in the nanometer range. For example, the substrate 110 and the sensor chip 120 can be bonded to each other by forming a eutectic fusion at a lower temperature by the first bonding layer 130 and the second bonding layer 140 to form a eutectic.

[0070] In an embodiment, the multi-layer nano low-melting-point metal material forming the first bonding layer 130 and the second bonding layer 140 may include at least two layers, for example, three layers, four layers or more metal layers. The melting point of each layer may decrease as it is farther away from the first connection region 111 or the second connection region 121 to form a melting point gradient.

[0071] In an embodiment, each layer of the multi-layer nano low-melting-point metal material forming the first bonding layer 130 and the second bonding layer 140 may include one of gold, silver, aluminum, copper, zinc, tin, lead, antimony, bismuth, lithium, indium, magnesium, gallium, cadmium and their alloys. In an embodiment, the thickness of each layer of the multi-layer nano low-melting-point metal material may be about 10 - 800 nanometers. In an embodiment, the first bonding layer 130 and the second bonding layer 140 may be composed of the same or different materials selected from the above nano low-melting-point metals or alloys.

[0072] Figure 9 A schematic structural diagram of a semiconductor package according to a second embodiment of the inventive concept is shown. Except that the shape and structure of the substrate are different, Figure 9 the shown semiconductor package and Figure 8 the shown semiconductor package have a similar structure. Therefore, the differences between the two will be mainly described below.

[0073] As Figure 9 shown, the semiconductor package 200 according to the second embodiment of the inventive concept includes: a substrate 210 including a first connection region 211 provided on the substrate 210; a sensor chip 220 including a second connection region 221 provided on the sensor chip 220; a first bonding layer 230 provided on the first connection region 211; and a second bonding layer 240 provided on the second connection region 221. The substrate 210 and the sensor chip 220 are bonded to each other by forming a eutectic crystal with the first bonding layer 230 and the second bonding layer 240. Both the first bonding layer 230 and the second bonding layer 240 include a multi-layer nano low-melting-point metal material having different melting point gradients.

[0074] Figure 9 The semiconductor package 200 in the second embodiment in [[ ]] may be a package with a Flip chip flip-chip package structure. In an embodiment, the substrate 210 may include a first part 210A and a second part 210B both in an inverted L shape. The first part 210A and the second part 210B may be disposed opposite to each other to form an opening window 210C. The sensor chip 220 may be built in the opening window 210C.

[0075] In an embodiment, the first connection region 211 may be located on the inner surfaces of the first portion 210A and the second portion 210B of the substrate 210. For example, each of the first portion 210A and the second portion 210B may include a horizontal portion HP (horizontal portion) extending in the horizontal direction and a vertical portion VP (vertical portion) extending in the vertical direction. The horizontal portion HP may have an inner surface S1 facing the sensor chip 220 and an outer surface S2 facing the outside. The first connection regions 211 of the first portion 210A and the second portion 210B of the substrate 210 may be respectively disposed on the inner surface S1 of the horizontal portion HP of the first portion 210A and the second portion 210B.

[0076] Continuing to refer to Figure 9 , in an embodiment, the second connection region 221 may be located on the upper surface of the sensor chip 220. The first bonding layer 230 and the second bonding layer 240 may be aligned and bonded to each other in the vertical direction. For example, the second connection region 221 may be located at the edge portion of the upper surface of the sensor chip 220. When the sensor chip 220 is built into the opening 210C, the first connection region 211 and the second connection region 221 may face each other and be aligned with each other in the vertical direction, so that the first bonding layer 230 and the second bonding layer 230 do not misalign during the fitting and pressing process, thereby avoiding deterioration of the electrical performance of the package.

[0077] After the substrate 210 and the sensor chip 220 are bonded to each other, when viewed from a plan view, the first bonding layer 230 and the second bonding layer 240 are blocked by the horizontal portion HP of the substrate 210, thereby protecting the connection portion from damage by external factors and improving the reliability of the package.

[0078] Figure 10 Schematic diagram showing the structure of an imaging device according to a first embodiment of the inventive concept. Figure 11 Schematic diagram showing the structure of an imaging device according to a second embodiment of the inventive concept. The imaging device includes a camera module. Figure 10 The camera module includes the semiconductor package 100 according to the first embodiment of the inventive concept. Figure 11 The camera module includes the semiconductor package 200 according to the second embodiment of the inventive concept. In addition, the camera module may further include a lens 300, a filter 400, a circuit board 500, etc. For example, the circuit board 500 may be a rigid PCB circuit board, or a rigid-flexible circuit board or a flexible printed circuit board.

[0079] A semiconductor package according to an exemplary embodiment of the inventive concept can be applied to a camera module of an imaging device. Compared with the conventional camera chip packaging process, the camera chip packaging process provided by the inventive concept does not require wire bonding or ball bonding, which is beneficial to the thinning of the camera packaging to solve the problem of ultra-thin packaging of the camera module.

[0080] By summarizing and reviewing, the exemplary embodiments of the inventive concept adopt the technology of low-temperature eutectic alloy and the technology of gradient nano-coating to prepare corresponding nano low-temperature eutectic alloy on the connection area of the sensor chip and the corresponding connection area of the substrate respectively. And by using the low-temperature eutectic technology, metal eutectic fusion can be achieved at a relatively low temperature. At the same time, by utilizing the high activity of the nano material, the reaction temperature can be further reduced. Finally, the bonding of the chip and the substrate is carried out at a temperature of 30 - 180 °C, a pressure of 1 - 8 Mpa and an ultrasonic vibration of 10 - 30 kHz, so that the chip and the substrate are directly connected. The packaging process of the exemplary embodiments of the inventive concept neither requires wire bonding nor ball bonding of the conventional packaging process, and at the same time does not require complex processes such as high temperature and high pressure. It only needs to achieve the packaging of the chip and the substrate at a relatively low temperature, even at room temperature, which can significantly reduce the packaging height of the camera, is beneficial to the thinning of the camera packaging, and has beneficial effects such as small investment in production equipment, low production energy consumption and low cost.

[0081] Although embodiments of the inventive concept have been shown and described herein, it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the inventive concept as defined by the claims.

Claims

1. A method for manufacturing a semiconductor package, comprising: Preparing a substrate having a first connection area and a sensor chip having a second connection area; Providing a first bonding layer including a multi-layer nano low-melting-point metal material having different melting point gradients on the first connection area of the substrate; Providing a second bonding layer including a multi-layer nano low-melting-point metal material having different melting point gradients on the second connection area of the sensor chip; Stacking the substrate and the sensor chip on top of each other so that the first bonding layer and the second bonding layer are aligned and pressed against each other to obtain a composite structure; and Processing the composite structure at a temperature of 30 - 180 °C, a pressure of 1 - 8 Mpa, and ultrasonic waves of 10 - 30 kHz for a period of time so that the first bonding layer and the second bonding layer form a eutectic.

2. The method according to claim 1, wherein, The melting point of each layer of the multi-layer nano low-melting-point metal material decreases as it is farther away from the first connection area or the second connection area.

3. The method according to claim 2, wherein Each layer of the multi-layer nano low-melting-point metal material includes one of gold, silver, aluminum, copper, zinc, tin, lead, antimony, bismuth, lithium, indium, magnesium, gallium, cadmium, and their alloys.

4. The method according to claim 1, wherein, The first bonding layer and the second bonding layer are composed of different nano low-melting-point metal materials.

5. The method according to claim 1, wherein The thickness of each layer of the multi-layer nano low-melting-point metal material is 10 - 800 nanometers.

6. The method according to claim 1, wherein The step of processing the composite structure includes increasing the processing temperature stepwise to reach the final reaction temperature, and including at least one heat preservation stage before reaching the final reaction temperature.

7. A semiconductor package, comprising: A substrate including a first connection area; A sensor chip including a second connection area; A first bonding layer on the first connection area; And A second bonding layer on the second connection area, wherein the substrate and the sensor chip are bonded to each other by forming a eutectic through processing the first bonding layer and the second bonding layer at a temperature of 30 - 180 °C, a pressure of 1 - 8 Mpa, and ultrasonic waves of 10 - 30 kHz for a period of time, and wherein both the first bonding layer and the second bonding layer include a multi-layer nano low-melting-point metal material having different melting point gradients.

8. The semiconductor package according to claim 7, wherein, The melting point of each layer of the multi-layer nano low-melting-point metal material decreases as it is farther away from the first connection area or the second connection area.

9. The semiconductor package according to claim 8, wherein, Each layer of the multi-layer nano low-melting-point metal material includes one of gold, silver, aluminum, copper, zinc, tin, lead, antimony, bismuth, lithium, indium, magnesium, gallium, cadmium, and their alloys.

10. The semiconductor package according to claim 7, wherein, The substrate includes a first part and a second part both in an inverted L shape, the first part and the second part are arranged opposite to each other to form a window, and the sensor chip is built in the window.

11. An imaging device, comprising: A camera module including a lens, a filter, and a semiconductor package, the semiconductor package including: A substrate including a first connection area; A sensor chip including a second connection area; A first bonding layer on the first connection area; and A second bonding layer on the second connection area, Wherein, the substrate and the sensor chip are bonded to each other by forming a eutectic crystal through treatment of the first bonding layer and the second bonding layer at a temperature of 30-180 °C, a pressure of 1-8 Mpa, and ultrasonic waves of 10-30 kHz for a period of time, and wherein, both the first bonding layer and the second bonding layer include multi-layered nano low-melting-point metal materials having different melting point gradients.

12. The imaging device according to claim 11, Among them, the melting point of each layer of the multi-layered nano low-melting-point metal material decreases as it is farther away from the first connection region or the second connection region.

13. The imaging device according to claim 12, Among them, each layer of the multi-layered nano low-melting-point metal material includes one of gold, silver, aluminum, copper, zinc, tin, lead, antimony, bismuth, lithium, indium, magnesium, gallium, cadmium, and their alloys.

14. The imaging device according to claim 11, Among them, the substrate includes a first part and a second part both in an inverted L shape, the first part and the second part are arranged opposite to each other to form a window opening, and the sensor chip is built in the window opening.

15. The imaging device according to claim 11, Among them, the substrate is a circuit board.

16. The imaging device according to claim 14, Among them, the substrate is mounted on a circuit board.

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