Semiconductor structures and their fabrication methods, memories and memory systems

Abstract

This invention provides a semiconductor structure and its fabrication method, a memory, and a memory system. The semiconductor structure includes a substrate, a stacked structure, and a gate gap structure. The stacked structure is disposed on the substrate and includes multiple gate structures and an insulating layer electrically isolating the multiple gate structures. The multiple gate structures extend along a first direction parallel to the substrate, and the material of the gate structures includes metal silicide. The gate gap structure extends through the stacked structure into the substrate along a longitudinal direction perpendicular to the substrate, and extends along a second direction parallel to the substrate and perpendicular to the first direction. The insulating layer is also located between the gate gap structure and the multiple gate structures. The semiconductor structure provided by this invention uses metal silicide as the material of the gate structure, replacing the gate structure prepared by the replacement process, thereby effectively avoiding damage to the semiconductor structure caused by fluorine generated in the replacement process in subsequent processes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method, a memory, and a storage system. Background Technology

[0002] As the number of stacked layers in 3D NAND flash memory continues to increase, the thickness of the stacked structure is usually reduced to decrease the difficulty of etching to form channel holes and gate openings during the fabrication of channel and gate gap structures.

[0003] However, how to ensure the reliability of 3D NAND flash memory while reducing the thickness of the stacked structure is a problem that needs to be solved. Summary of the Invention

[0004] To address the above-mentioned or other problems, the present invention provides the following technical solutions.

[0005] A semiconductor structure, the semiconductor structure comprising:

[0006] Base;

[0007] A stacked structure disposed on the substrate includes a plurality of gate structures and an insulating layer electrically isolating the plurality of gate structures, wherein the plurality of gate structures extend along a first direction parallel to the substrate, and the material of the gate structures includes metal silicide; and,

[0008] The gate slot structure extends through the stacked structure into the substrate in a longitudinal direction perpendicular to the substrate, and extends in a second direction parallel to the substrate and perpendicular to the first direction;

[0009] The insulating layer is also located between the gate gap structure and the plurality of gate structures.

[0010] According to a semiconductor structure of an embodiment of the present invention, the substrate includes a common source layer and a stop layer, the stop layer being located between the common source layer and the stacked structure, the gate gap structure extending along the longitudinal direction into the stop layer, wherein the material of the stop layer includes a nitride.

[0011] According to an embodiment of the present invention, the semiconductor structure further includes a channel structure and a protective layer, wherein the channel layer of the channel structure extends longitudinally through the stacked structure into the common source layer, and the protective layer is disposed on the stacked structure, covers the channel structure, and is penetrated by the gate gap structure.

[0012] According to an embodiment of the semiconductor structure of the present invention, the material of the gate gap structure includes at least one of polycrystalline silicon and tungsten.

[0013] A memory, comprising:

[0014] The semiconductor structure described in any of the preceding claims; and,

[0015] The peripheral circuit is electrically connected to the semiconductor structure.

[0016] A storage system, comprising:

[0017] The aforementioned memory; and,

[0018] A controller, electrically connected to the memory, is used to control the memory.

[0019] A method for fabricating a semiconductor structure, the method comprising:

[0020] A stacked structure and a gate slot opening through the stacked structure along a longitudinal direction perpendicular to the substrate are formed on the substrate, wherein the stacked structure consists of a plurality of dielectric layers and a plurality of polysilicon layers;

[0021] Multiple dielectric layers are removed to obtain multiple cavities communicating with the gate slot openings;

[0022] Metal layers are formed on the surfaces of the multiple polycrystalline silicon layers through the multiple cavities;

[0023] Multiple gate structures are formed by chemically reacting the multiple polysilicon layers with the metal layer;

[0024] An insulating layer is formed in the plurality of cavities to electrically isolate the plurality of gate structures.

[0025] According to a method for fabricating a stacked structure according to an embodiment of the present invention, the steps of forming a stacked structure on a substrate and opening a gate slot through the stacked structure along a longitudinal direction perpendicular to the substrate specifically include:

[0026] A stop layer, a stacked structure, and a channel structure extending through the stacked structure and into the substrate in a longitudinal direction perpendicular to the substrate are formed on the substrate.

[0027] A protective layer is formed on the stacked structure, the protective layer covering the channel structure;

[0028] A gate slot opening is formed along the longitudinal direction, passing through the protective layer and the stacked structure, and extending into the stop layer.

[0029] According to a method for fabricating a product according to an embodiment of the present invention, wherein the metal layer is further formed on the surface of the stop layer and the surface of the protective layer, and prior to the step of forming an insulating layer in the plurality of cavities to electrically isolate the plurality of gate structures, the method further includes:

[0030] An acidic liquid is introduced into the gate slot opening to remove the metal layer located on the surface of the stop layer and the surface of the protective layer.

[0031] According to a preparation method of an embodiment of the present invention, the metal layer is formed using atomic layer deposition.

[0032] According to a preparation method of an embodiment of the present invention, the material of the metal layer includes at least one of nickel and cobalt.

[0033] According to a preparation method of an embodiment of the present invention, a plurality of gate structures are formed by chemically reacting a plurality of polysilicon layers with a metal layer through an annealing process.

[0034] According to a method for fabricating a product according to an embodiment of the present invention, wherein the insulating layer is further located between the gate gap opening and the plurality of gate structures, and after the step of forming an insulating layer in the plurality of cavities to electrically isolate the plurality of gate structures, the method further includes:

[0035] At least one of polycrystalline silicon and tungsten is deposited in the gate slot opening to form a gate slot structure.

[0036] According to a method for fabricating a gate slot structure according to an embodiment of the present invention, after the step of depositing at least one of polycrystalline silicon and tungsten in the gate slot opening to form a gate slot structure, the method further includes:

[0037] Remove the protective layer.

[0038] According to a method for fabricating a gate slot structure according to an embodiment of the present invention, after the step of depositing at least one of polycrystalline silicon and tungsten in the gate slot opening to form a gate slot structure, the method further includes:

[0039] Remove the substrate and the functional layer of the channel structure;

[0040] A common source electrode layer is formed that is connected to the channel layer of the channel structure.

[0041] The beneficial effects of this invention are as follows: This invention provides a semiconductor structure and its fabrication method, a memory, and a memory system. The semiconductor structure includes a substrate, a stacked structure, and a gate gap structure. The stacked structure is disposed on the substrate and includes multiple gate structures and an insulating layer electrically isolating the multiple gate structures. The multiple gate structures extend along a first direction parallel to the substrate, and the material of the gate structures includes metal silicide. The gate gap structure extends through the stacked structure into the substrate along a longitudinal direction perpendicular to the substrate, and extends along a second direction parallel to the substrate and perpendicular to the first direction. The insulating layer is also located between the gate gap structure and the multiple gate structures. The semiconductor structure provided by this invention, by using metal silicide as the material of the gate structure instead of the gate structure prepared by the replacement process, effectively avoids the damage to the semiconductor structure caused by fluorine generated in the replacement process in subsequent processes. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the various embodiments made according to the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0043] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present invention.

[0044] Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0045] Figure 3 This is a further schematic flowchart of the method for fabricating a semiconductor structure provided by an embodiment of the present invention.

[0046] Figures 4a to 4i This is a schematic diagram of the process flow for fabricating a semiconductor structure according to an embodiment of the present invention.

[0047] Figure 5 This is a schematic diagram of the structure of a memory provided according to an embodiment of the present invention.

[0048] Figure 6 This is a schematic diagram of the structure of a storage system provided according to an embodiment of the present invention. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0050] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0051] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0052] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0053] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0054] The embodiments of the present invention can solve the reliability problems arising from reducing the thickness of the stacked structure in the semiconductor structure in some embodiments. Specifically, it can solve the problems that arise when replacing the sacrificial layer in the stacked structure of the semiconductor structure. For example, because the thickness of the stacked structure is too small, the replacement of the sacrificial layer in the stacked structure becomes increasingly difficult. At the same time, the residual fluorine during the replacement process can damage the semiconductor structure in subsequent processes.

[0055] Please see Figure 1 , Figure 1 A cross-sectional schematic diagram of a semiconductor structure 100 provided according to an embodiment of the present invention is shown.

[0056] like Figure 1 As shown, the semiconductor structure 100 includes: a substrate 110, a stacked structure 120, and a gate gap structure 130. Next, combined with... Figure 1 The above components will be described in detail.

[0057] A stacked structure 120 is disposed on a substrate 110. The stacked structure 120 includes a plurality of gate structures 121 and an insulating layer 122 electrically isolating the plurality of gate structures 121. The plurality of gate structures 121 extend along a first direction X1 parallel to the substrate 110, and the material of the gate structure 121 includes metal silicide. Specifically, exemplary materials of metal silicide include, but are not limited to, nickel silicide (chemical formula: NiSix) and cobalt silicide (chemical formula: CoSix).

[0058] It should be noted that, in the embodiments of the present invention, the plurality of gate structures 121 made of metal silicide can replace the gate structures prepared by the substitution process in some embodiments. Therefore, since the substitution process is not required, the fluorine element (F) in the tungsten hexafluoride (WF6) gas, which serves as the carrier of tungsten (W), can be avoided from being introduced into the semiconductor structure 100 in the above-mentioned substitution process, thereby avoiding damage to the semiconductor structure 100 by the fluorine element in subsequent processes.

[0059] The gate gap structure 130 extends through the stacked structure 120 into the substrate 110 along a longitudinal direction Y perpendicular to the substrate 110, and extends along a second direction parallel to the substrate 110 and perpendicular to the first direction X1, wherein the insulating layer 122 is also located between the gate gap structure 130 and the plurality of gate structures 121.

[0060] For details, please continue reading. Figure 1 The aforementioned substrate 110 may specifically include a common source layer 111 and a stop layer 112, wherein the stop layer 112 is located between the common source layer 111 and the stacked structure 120, and the gate gap structure 130 extends along the longitudinal direction Y into the stop layer 112.

[0061] It should be noted that the stop layer 112 is used as an etching stop layer for the gate slot structure 130 during the formation of the gate slot structure 130. The material of the stop layer 112 can be nitride or other suitable materials. In the embodiments of the present invention, the material of the stop layer 112 is not limited.

[0062] For details, please continue reading. Figure 1 The semiconductor structure 100 also includes a channel structure 140 and a protective layer 150. The channel layer 141 of the channel structure 140 extends through the stacked structure 120 along the longitudinal direction Y to the common source layer 111, and the common source layer 111 is used as the source lead-out structure of the channel structure 140. The protective layer 150 is disposed on the stacked structure 120 and covers the channel structure 140, and the protective layer 150 is penetrated by the gate gap structure 130.

[0063] It should be noted that the aforementioned protective layer 150 is used as a protective structure to prevent the channel structure 140 from being affected by etching and deposition processes during the formation of the gate slot structure 130. Furthermore, in other embodiments according to the present invention, the protective layer 150 may be removed after the gate slot structure 130 is fabricated.

[0064] Furthermore, since the channel structure 140 has a channel layer 141, in order to balance the stress generated by the channel layer 141 in the channel structure 140, the material of the gate gap structure 130 may include at least one of polysilicon (Poly) and tungsten (W).

[0065] For further information, please refer to [link / reference]. Figure 1 The semiconductor structure 100 also includes a lead-out structure 160, which is electrically connected to the channel layer 141 of the channel structure 140 and serves as the drain lead-out structure of the channel structure 140.

[0066] According to the foregoing embodiments, the present invention provides a semiconductor structure 100, including a substrate 110, a stacked structure 120, and a gate gap structure 130. The stacked structure 120 is disposed on the substrate 110 and includes a plurality of gate structures 121 and an insulating layer 122 electrically isolating the plurality of gate structures 121. The plurality of gate structures 121 extend along a first direction X1 parallel to the substrate 110, and the material of the gate structures 121 includes metal silicide. The gate gap structure 130 extends through the stacked structure 120 into the substrate 110 along a longitudinal direction Y perpendicular to the substrate 110, and extends along a second direction parallel to the substrate 110 and perpendicular to the first direction X1. The insulating layer 122 is also located between the gate gap structure 130 and the plurality of gate structures 121. The semiconductor structure 100 provided by the present invention uses metal silicide as the material of the gate structure 121, replacing the gate structure prepared by the replacement process, thereby effectively avoiding damage to the semiconductor structure 100 caused by fluorine generated in the replacement process in subsequent processes.

[0067] Please see Figure 2 as well as Figures 4a to 4i , Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor structure 100 according to an embodiment of the present invention is shown. Figures 4a to 4i A schematic diagram of the process flow for fabricating a semiconductor structure 100 provided in an embodiment according to the present invention is shown.

[0068] like Figure 2 , Figures 4b to 4e as well as Figure 4g As shown, the fabrication method of the semiconductor structure 100 specifically includes the following steps:

[0069] Step S101 is provided: a stacked structure 120 and a gate slot opening 130' passing through the stacked structure 120 along a longitudinal direction Y perpendicular to the substrate 111' are formed on the substrate 111', wherein the stacked structure 120 is composed of a plurality of dielectric layers 122' and a plurality of polysilicon layers 121';

[0070] Cavity forming step S102: Remove multiple dielectric layers 122' to obtain multiple cavities communicating with gate slot openings 130';

[0071] Metal layer formation step S103: Metal layer 123 is formed on the surface of multiple polysilicon layers 121' through multiple cavities;

[0072] Gate structure formation step S104: Multiple polysilicon layers 121' are chemically reacted with metal layer 123 to form multiple gate structures 121;

[0073] Gate structure electrical isolation step S105: An insulating layer 122 is formed in multiple cavities to electrically isolate multiple gate structures 121.

[0074] It should be noted that, in the embodiments of the present invention, a metal silicide that can serve as a gate structure 121 is formed by chemically reacting the polysilicon layer 121' in the stacked structure 120 with the metal layer 123 deposited in the cavity. That is, in the preparation method provided by the present invention, the above-mentioned gate structure formation step S104 can replace the replacement process required in some embodiments for preparing the gate structure. On the one hand, this avoids the introduction of fluorine (F) from the tungsten hexafluoride (WF6) gas, which serves as a tungsten (W) carrier, into the semiconductor structure 100 during the replacement process, thus preventing damage to the semiconductor structure 100. On the other hand, since the process window for tungsten deposition in the replacement process does not need to be considered, the thickness of the polysilicon layer 121' and the dielectric layer 122' in the stacked structure can be further reduced in the embodiments of the present invention, thereby increasing the capacity of the formed semiconductor structure 100 per unit volume.

[0075] Further, please refer to Figure 3 , Figure 4a as well as Figure 4b ,in, Figure 3 A further schematic flowchart of a method for fabricating a semiconductor structure 100 provided according to an embodiment of the present invention is shown.

[0076] like Figure 3 , Figure 4a as well as Figure 4b As shown, in this embodiment, the above-mentioned step S101 may specifically include the following steps:

[0077] Channel structure formation sub-step S1011: A stop layer 112, a stacked structure 120, and a channel structure 140 extending through the stacked structure 120 and into the substrate 111' are formed on the substrate 111'.

[0078] Protective layer formation sub-step S1012: A protective layer 150 is formed on the stacked structure 120, and the protective layer 150 covers the channel structure 140;

[0079] Gate slot opening formation sub-step S1013: Forming a gate slot opening 130' that runs longitudinally Y through the protective layer 150 and the stacked structure 120 and extends into the stop layer 112.

[0080] It should be noted that in the above-mentioned channel structure formation sub-step S1011, a stop layer 112 is formed above the substrate 111'. The stop layer 112 can serve as an etching stop layer when etching to form the gate slot opening 130', so as to prevent the gate slot opening 130' from extending into the substrate 111'. Therefore, the metal layer 123 is prevented from being formed on the surface of the substrate 111' in the metal layer formation step S103, thereby preventing the substrate 111' from reacting chemically with the metal layer 123 to generate metal silicide.

[0081] Specifically, the material of the stop layer 112 can be a nitride or other suitable material. In the embodiments made according to the present invention, the material of the stop layer 112 is not limited.

[0082] It should be noted that in the metal layer formation step S103 described above, the metal layer 123 can be formed using, for example, atomic layer deposition (ALD) to make the formed metal layer 123 have better step coverage and better film quality. Thus, in the subsequent gate structure formation step S104, the multiple polysilicon layers 121' can fully react with the metal layer 123 to form a gate structure 121 with good electrical properties.

[0083] Furthermore, the material of the aforementioned metal layer 123 may include at least one of nickel (Ni) and cobalt (Co).

[0084] It should be noted that in the gate structure formation step S104 described above, multiple gate structures 121 are formed by chemically reacting multiple polysilicon layers 121' with the metal layer 123 through an annealing process. Specifically, this gate structure formation step S104 can be performed using two annealing processes, wherein the temperature of the second annealing process is higher than the temperature of the first annealing process.

[0085] Furthermore, such as Figure 4eAs shown, in the metal layer formation step S103 described above, metal layer 123 is also formed on the surface of stop layer 112 and the surface of protective layer 150. Since the metal layer 123 formed on the surface of stop layer 112 and protective layer 150 in gate structure formation step S104 does not chemically react with stop layer 112 or protective layer 150, in order to prevent these non-chemically reacted metal layers 123 from affecting the electrical properties of semiconductor structure 100, these non-chemically reacted metal layers 123 need to be removed.

[0086] Therefore, please refer to Figure 3 as well as Figure 4f ,in, Figure 3 A further schematic flowchart of a method for fabricating a semiconductor structure 100 provided according to an embodiment of the present invention is shown.

[0087] like Figure 3 as well as Figure 4f As shown, prior to the above-described gate structure electrical isolation step S105, the procedure further includes:

[0088] Cleaning step S106: Acidic liquid is introduced into the gate gap opening 130' to remove the metal layer 123 on the surface of the stop layer 112 and the surface of the protective layer 150.

[0089] For further information, please refer to [link / reference]. Figure 3 as well as Figure 4h After the above-described gate structure electrical isolation step S105, the method further includes:

[0090] Gate gap structure formation step S107: Deposit at least one of polycrystalline silicon and tungsten in the gate gap opening 130' to form the gate gap structure 130.

[0091] It should be noted that, as Figure 4a As shown, the semiconductor structure 100 also includes a channel structure 140, which extends longitudinally Y through the stacked structure 120 into the substrate 111'. Specifically, the channel structure 140 has a channel layer ( Figure 4a (Not shown in the text) The polysilicon and tungsten deposited into the gate slot opening 130' in the gate slot structure formation step S107 are to balance the stress generated by the channel layer in the channel structure 140.

[0092] For details, please continue reading. Figure 4h The insulating layer 122 formed in the gate structure electrical isolation step S105 is also located between the gate gap structure 130 and the plurality of gate structures 121.

[0093] Further, please refer to Figure 4bThe protective layer 150 formed in step S101 described above will cover the channel structure 140. The protective layer 150 is used as a protective structure to prevent the channel structure 140 from being affected by processes such as etching and deposition during the formation of the gate gap structure 130.

[0094] It should be noted that, in some embodiments of the present invention, after the gate slot structure 130 is prepared, the protective layer 150 may be removed.

[0095] Further, please refer to Figure 3 as well as Figure 4i ,like Figure 3 as well as Figure 4i As shown, in this embodiment, after the above-described gate gap structure forming step S107, the method further includes:

[0096] Substrate removal step S108: Remove substrate 111' and functional layer 142 of channel structure 140;

[0097] Common source electrode layer formation step S109: Form a common source electrode layer 111 connected to the channel layer 141 of the channel structure 140.

[0098] It should be noted that the common source layer 111 formed in the common source layer formation step S109 is used as the source lead-out structure of the channel structure 140.

[0099] Furthermore, such as Figure 4i As shown, in this embodiment, after the above-mentioned gate gap structure forming step S107, the method further includes:

[0100] An outgoing structure 160 is formed that is electrically connected to the channel layer 141 of the channel structure 140.

[0101] It should be noted that the lead-out structure 160 is used as the drain lead-out structure of the channel structure 140.

[0102] According to the foregoing embodiments, the present invention provides a method for fabricating a semiconductor structure 100, comprising: forming a stacked structure 120 and a gate slot opening 130' passing through the stacked structure 120 along a longitudinal direction Y perpendicular to the substrate 111' on a substrate 111', wherein the stacked structure 120 is composed of a plurality of dielectric layers 122' and a plurality of polysilicon layers 121', removing the plurality of dielectric layers 122' to obtain a plurality of cavities communicating with the gate slot opening 130', forming a metal layer 123 on the surface of the plurality of polysilicon layers 121' through the plurality of cavities, and causing the plurality of polysilicon layers 121' and the metal layer 123 to undergo a chemical reaction to form a plurality of Gate structure 121, and then, insulating layer 122 is formed in multiple cavities to electrically isolate the multiple gate structures 121. The method for preparing semiconductor structure 100 provided by the present invention forms a metal silicide that can serve as gate structure 121 by chemically reacting the polysilicon layer 121' in the stacked structure 120 with the metal layer 123 deposited in the cavity. This replaces the replacement process required in some embodiments for preparing the gate structure. It not only effectively avoids the fluorine generated in the replacement process from damaging the semiconductor structure 100 in subsequent processes, but also improves the capacity of semiconductor structure 100 per unit volume.

[0103] Please see Figure 5 , Figure 5 A schematic diagram of the structure of a memory 500 provided according to an embodiment of the present invention is shown. The memory 500 may be a three-dimensional memory, such as a 3D NAND or 3D NOR memory.

[0104] Specifically, the memory 500 includes a semiconductor structure 501 and peripheral circuitry 502. The semiconductor structure 501 can be the semiconductor structure 100 described in the above embodiments, and the peripheral circuitry 502 can be a complementary metal-oxide-semiconductor (CMOS) circuit. The peripheral circuitry 502 is electrically connected to the semiconductor structure 501 for signal transmission. The peripheral circuitry 502 can be used for logic operations and for controlling and detecting the switching states of each memory cell in the semiconductor structure 501 via metal interconnects, thereby enabling data storage and retrieval operations.

[0105] Please see Figure 6 , Figure 6A schematic diagram of a storage system 600 provided according to an embodiment of the present invention is shown. The storage system 600 includes a memory 601 and a controller 602. The memory 601 can be the memory in any of the above embodiments, and the memory 601 may include the aforementioned semiconductor structure. The controller 602 is electrically connected to the memory 601 and is used to control the memory 601 to perform data operations, etc. The memory 601 can perform data storage operations based on the control of the controller 602.

[0106] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0107] In addition to the embodiments described above, the present invention may have other implementations. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by the present invention.

[0108] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: Base; A stacked structure disposed on the substrate includes a plurality of gate structures and an insulating layer electrically isolating the plurality of gate structures, wherein the plurality of gate structures extend along a first direction parallel to the substrate, and the material of the gate structures includes metal silicide; and, The gate slot structure extends through the stacked structure into the substrate in a longitudinal direction perpendicular to the substrate, and extends in a second direction parallel to the substrate and perpendicular to the first direction; The insulating layer is also located between the gate gap structure and the plurality of gate structures; The material of the gate slot structure includes at least one of polycrystalline silicon and tungsten.

2. The semiconductor structure according to claim 1, characterized in that, The substrate includes a common source layer and a stop layer, the stop layer being located between the common source layer and the stacked structure, the gate gap structure extending longitudinally into the stop layer, wherein the material of the stop layer includes a nitride.

3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes a channel structure and a protective layer, wherein the channel layer of the channel structure extends longitudinally through the stacked structure into the common source layer, and the protective layer is disposed on the stacked structure, covers the channel structure, and is penetrated by the gate gap structure.

4. A memory, characterized in that, include: The semiconductor structure as described in any one of claims 1-3; as well as, The peripheral circuit is electrically connected to the semiconductor structure.

5. A storage system, characterized in that, include: The memory as described in claim 4; as well as, A controller, electrically connected to the memory, is used to control the memory.

6. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A stacked structure and a gate slot opening through the stacked structure along a longitudinal direction perpendicular to the substrate are formed on the substrate, wherein the stacked structure consists of a plurality of dielectric layers and a plurality of polysilicon layers; Multiple dielectric layers are removed to obtain multiple cavities communicating with the gate slot openings; Metal layers are formed on the surfaces of the multiple polycrystalline silicon layers through the multiple cavities; Multiple gate structures are formed by chemically reacting the multiple polysilicon layers with the metal layer; An insulating layer is formed in the plurality of cavities to electrically isolate the plurality of gate structures.

7. The preparation method according to claim 6, characterized in that, The steps of forming a stacked structure on the substrate and opening a gate slot through the stacked structure along a longitudinal direction perpendicular to the substrate specifically include: A stop layer, a stacked structure, and a channel structure extending through the stacked structure and into the substrate in a longitudinal direction perpendicular to the substrate are formed on the substrate. A protective layer is formed on the stacked structure, the protective layer covering the channel structure; A gate slot opening is formed along the longitudinal direction, passing through the protective layer and the stacked structure, and extending into the stop layer.

8. The preparation method according to claim 7, characterized in that, The metal layer is also formed on the surface of the stop layer and the surface of the protective layer, and prior to the step of forming an insulating layer in the plurality of cavities to electrically isolate the plurality of gate structures, the method further includes: An acidic liquid is introduced into the gate slot opening to remove the metal layer located on the surface of the stop layer and the surface of the protective layer.

9. The preparation method according to claim 6, characterized in that, The metal layer is formed using atomic layer deposition.

10. The preparation method according to claim 6, characterized in that, The material of the metal layer includes at least one of nickel and cobalt.

11. The preparation method according to claim 6, characterized in that, Multiple gate structures are formed by chemically reacting multiple polysilicon layers with the metal layer through an annealing process.

12. The preparation method according to claim 7, characterized in that, The insulating layer is also located between the gate gap opening and the plurality of gate structures, and after the step of forming an insulating layer in the plurality of cavities to electrically isolate the plurality of gate structures, the method further includes: At least one of polycrystalline silicon and tungsten is deposited in the gate slot opening to form a gate slot structure.

13. The preparation method according to claim 12, characterized in that, Following the step of depositing at least one of polysilicon and tungsten in the gate slot opening to form the gate slot structure, the method further includes: Remove the protective layer.

14. The preparation method according to claim 12, characterized in that, Following the step of depositing at least one of polysilicon and tungsten in the gate slot opening to form the gate slot structure, the method further includes: Remove the substrate and the functional layer of the channel structure; A common source electrode layer is formed that is connected to the channel layer of the channel structure.

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