Lateral bipolar junction transistor device and method of manufacturing such a device

Abstract

The present disclosure relates to a lateral bipolar junction transistor device and a method of manufacturing such a device. A non-uniform base width bipolar junction transistor (BJT) device includes a semiconductor substrate having an upper surface, and a BJT device including a collector region, a base region, and an emitter region located in the semiconductor substrate, the base region located between the collector region and the emitter region; the base region including a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to various novel embodiments of lateral bipolar junction transistor (BJT) devices, and various novel methods of fabricating such lateral BJT devices. BACKGROUND

[0002] Bipolar junction transistor (BJT) devices are widely used in many integrated circuit products. Generally, a BJT device includes a collector region, a base region, and an emitter region. A BJT device can be a PNP device or an NPN device. In a PNP BJT device, current flows from the emitter to the base, and out of the BJT device via the collector. In an NPN BJT device, current flows from the collector to the base, and out of the BJT device via the emitter. Device designers are under constant pressure to improve the operating speed and electrical performance of BJT devices and integrated circuit products that employ such BJT devices.

[0003] A system on chip (SoC) is an integrated circuit product that includes all of the components desired for a system, such as a computer. Such a SOC chip can include one or more central processors and co-processors, graphics drivers, memory, power management circuitry, wireless communication interfaces, and other components of a fully functional system. Moreover, since the signals between the various components on the SoC remain on-die, the power requirements of the system on the SoC can be reduced. SoC devices can be formed using BiCMOS technology, which involves forming BJT devices and CMOS field effect transistors (N-type and P-type) on a single chip. In BiCMOS technology applications, techniques are needed to effectively and efficiently form BJT devices and CMOS transistors. SUMMARY

[0004] The following presents a simplified summary of at least one disclosed embodiment in order to provide a basic understanding of some aspects of the subject matter described herein. This summary is not an extensive overview of all contemplated aspects of the subject matter described herein. It is not intended to identify key or critical elements of the subject matter described herein. Its sole purpose is to present some concepts of the subject matter in a simplified form as a prelude to the more detailed description that is presented later in the application.

[0005] The present disclosure relates generally to various novel embodiments of lateral bipolar junction transistor (BJT) devices, and various novel methods of fabricating such lateral BJT devices.

[0006] An exemplary device disclosed herein according to embodiments includes a semiconductor substrate having an upper surface, and a bipolar junction transistor (BJT) device including a collector region, a base region, and an emitter region located in the semiconductor substrate, the base region located between the collector region and the emitter region; the base region including a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

[0007] A lateral bipolar junction transistor (BJT) device according to embodiments includes a collector region, a base region, and an emitter region located in a semiconductor substrate, the base region located between the collector region and the emitter region; the base region including a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the lateral BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the lateral BJT device, wherein a portion of the collector region and a portion of the emitter region extend below a portion of the base region and are separated by a distance equal to the second width.

[0008] A method according to embodiments includes providing a semiconductor substrate having an upper surface, and forming a bipolar junction transistor (BJT) device in the semiconductor substrate, the BJT device including a collector region, a base region, and an emitter region located in the semiconductor substrate, the base region located between the collector region and the emitter region and including a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device. BRIEF DESCRIPTION OF DRAWINGS

[0009] The present disclosure can be understood with reference to the following description in conjunction with the drawings, in which like reference characters designate the same elements, and in which:

[0010] Fig. 1-27 Various novel embodiments of lateral bipolar junction transistor (BJT) devices, and various novel methods of fabricating such lateral BJT devices, are shown. The drawings are not drawn to scale.

[0011] While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein is not intended to limit the application to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the application as defined by the appended claims. DETAILED DESCRIPTION

[0012] Various illustrative embodiments of the present application are described below. In order to clarify the structure of the various illustrative embodiments of the present application, all of the features of an actual implementation are not described in the present specification. It is understood that, in the development of any such actual implementation, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0013] The subject inventive matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and are not limitation of the present disclosure. Included in the drawings are flow diagrams illustrating example operations, methods, and processes. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations. The present disclosure is directed to all novel and nonobvious combinations and subcombinations of the various elements, features, and / or functions described herein. No structure, act or other implementation is impliedly or explicitly essential to the practice of the application, unless expressly indicated as such. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims and their equivalents. The word and phrase "example" in reference to an implementation of the present application means that a feature, structure, act, or element is included in at least one implementation of the present application, and can be included in more than one implementation. Thus, use of the word example does not mean that the feature, structure, act or element is essential, required, or critical to the application or any particular implementation of the application. In addition, it is important to note that the word "comprising" does not specify an exhaustive or exhaustive list of elements or components. Rather, it states that the composition or method includes the recited elements, but not excluding others. The word "comprising" is used to specify or delineate the presence of the indicated features, elements, components or steps, but does not exclude the presence of one or more additional features, elements, components or steps. No language is intended to mean that the claimed application will necessarily include all of the recited features, elements, components or steps.

[0014] Fig. 1-27An integrated circuit (IC) product 100 is shown that includes one or more lateral BJT devices 104 located on a semiconductor substrate 101. In one exemplary example, the IC product 100 can also include a CMOS-based integrated circuit that includes NFET and PFET transistors (not shown) formed on the semiconductor substrate 101. The NFET and PFET transistors can have any configuration, such as FinFET devices, planar devices, etc. Those skilled in the art will understand, upon complete review of this application, that the various process flows disclosed herein are compatible with the various process flows performed in order to form such a CMOS-based integrated circuit. Moreover, the lateral BJT devices 104 disclosed herein can be either NPN devices or PNP devices. In the examples described herein, the BJT devices 104 will be PNP devices. Moreover, in the examples described herein, the lateral BJT devices 104 will be formed in a fin structure 103. However, the presently disclosed subject matter should not be considered limited to such fin-based structures.

[0015] Fig. 1 is a simplified plan view of one exemplary embodiment of the IC product 100 disclosed herein. The lateral BJT devices 104 will be formed in the exemplary fin structure 103. The lateral BJT devices 104 include an emitter region (E), a base region (B), and a collector region (C). The base width (BW) direction of the lateral BJT devices 104, as well as the locations at which the various cross-sectional views presented in the figures are taken, are also shown in Fig. 1 More specifically, the cross-sectional view“X-X” is taken along the fin structure 103 in a direction corresponding to the base width direction (i.e., along the long axis of the fin structure 103). The view“Y-Y” is taken in a direction transverse to the base width direction (i.e., transverse to the long axis of the fin structure 103). While the lateral BJT devices 104 are shown as being formed over a single fin 103, the lateral BJT devices 104 can include any desired number of fins.

[0016] In the example shown, and with reference to Fig. 2The lateral BJT device 104 of the IC product 100 will be formed over a semiconductor substrate 101. The substrate 101 can have a variety of configurations, such as a bulk semiconductor substrate as described herein, or it can take the form of a semiconductor-on-insulator (SOI) substrate. Such an SOI substrate includes a base semiconductor layer, a buried insulating layer located on the base semiconductor layer, and an active semiconductor layer located over the buried insulating layer. In some applications, the substrate 101 can be made of silicon, or it can be made of a semiconductor material other than silicon. Thus, the term "substrate" or "semiconductor substrate" should be understood to encompass all semiconductor materials, as well as all forms of such materials. Moreover, in some cases, the substrate 101 can include an N-type or P-type dopant material. In the examples described herein, it will be assumed that the substrate 101 is doped with a P-type dopant.

[0017] Fig. 2 (see Fig. X-X ) and 3 (view Y-Y) illustrate the IC product 100 after a number of process operations have been performed. First, the fin 103 is formed by performing known manufacturing process operations. In practice, many other fins (not shown) will be formed in the substrate 101 at the same time as the depicted fin 103. However, for purposes of explanation, the formation of only the depicted single fin 103 will be discussed. For example, the fin 103 can be formed by performing one or more etching processes, such as anisotropic etching processes, with the aid of a patterned fin-formation etching mask (not shown) to form a plurality of fin-formation trenches 102 (see Fig. 3 ) in the substrate 101, thereby defining the fin 103. The width and height of the fin 103 can vary depending on the particular application. Moreover, the overall size, shape, and configuration of the fin-formation trenches 102 and the fin 103 can vary depending on the particular application. In the example shown herein, the fin 103 will be simply depicted as having a rectangular cross-sectional configuration with a substantially uniform thickness throughout the height of the fin 103. In actual devices, the fin 103 can have a tapered cross-sectional configuration, where the width of the fin 103 decreases as the height of the fin 103 increases. In other words, the width of the fin 103 at the top surface 103S is less than the width of the base of the fin 103. Fig. 3 The width of the top surface 103S of the fin 103 shown (i.e., the top critical dimension) is less than the width of the base of the fin 103. Moreover, the axial length of the fin 103 can also vary depending on the particular application. Of course, the physical dimensions of the fin 103 can vary depending on the particular application and technological advances.

[0018] Next, by performing conventional fabrication techniques, a recessed layer of insulating material 105 (e.g., silicon dioxide) is formed adjacent to the fin 103, which has a recessed upper surface 105R. The insulating material layer 105 is initially deposited, and then the upper surface of the insulating material layer 105 is planarized. At this point, a recess etch process is performed to remove a portion of the vertical thickness of the layer on the insulating material 105 until the final desired thickness is reached. This is sometimes referred to as a "fin exposure" process because it exposes the desired vertical height 103H of the fin 103 above the recessed upper surface 105R of the insulating material layer 105. Thereafter, by performing known fabrication techniques, an isolation structure 107 is formed in the fin 103. The isolation structure 107 can be composed of any insulating material (e.g., silicon dioxide).

[0019] Fig. 4 and 5 The IC product 100 is shown after several process operations are performed. First, an ion implantation process is performed to form an N-well region 109 in the semiconductor substrate 101. The dopant concentration of the N-type dopant material in the N-well region 109 can vary according to particular applications, such as 1e 14 -1e 16 atoms / cm 3 . In one particular embodiment, the dopant concentration of the N-type dopant material in the N-well region 109 can be approximately 1e 15 atoms / cm 3 . The N-well region 109 can be doped with any kind of N-type dopant material. Next, another ion implantation process is performed to form an N - implant region 111 within the N-well region 109. Those skilled in the art, after a complete reading of this application, will understand that the N - implant region 111 will be the base region of the lateral BJT device 104. The N - implant region 111 can vary according to particular applications, such as 1e 16 -1e 18 atoms / cm 3 . In one particular embodiment, the dopant concentration of the N-type dopant material in the N - implant region 111 can be approximately 1e 17 atoms / cm 3 . The N - implant region 111 can be doped with any kind of N-type dopant material. The N - implant region 111 and the N-well region 109 need not be doped with the same kind of N-type dopant material, although this can be the case in some applications.

[0020] Fig. 6An IC product 100 is shown after several process operations have been performed. In one exemplary process flow, a portion of the base region of a lateral BJT device 104 can be formed by utilizing N-type... - The sacrificial gate structure 113 above the injection region 111 is part of a process operation performed to fabricate the final gate structure (not shown) of various transistor devices (not shown) using known alternative gate fabrication techniques. Fig. 6 The diagram also shows a gate cap 115 and sidewall spacers 117. Various process flows can be performed to form these structures. In one exemplary process flow, the materials of the sacrificial gate structure 113 and the gate cap 115 can be blanket-deposited over the substrate 101. Subsequently, one or more masking and etching processes can be performed on these deposited materials to form the sacrificial gate structure 113 with the gate cap 115. Next, the simply depicted sidewall spacers 117 can be formed adjacent to the generally vertically oriented sidewalls of the sacrificial gate structure 113. Although only a single sidewall spacer 117 is shown in the diagram, multiple sidewall spacers can be formed adjacent to the sacrificial gate structure 113 as processing progresses. In one example, the sidewall spacers 117 can be formed by performing a conformal deposition process to form a conformal layer of sidewall spacer material on the sacrificial gate structure 113. At this point, an anisotropic etching process can be performed to remove the horizontally oriented portion of the spacer material layer, thereby forming sidewall spacers 117 located on or adjacent to the substantially vertically oriented sidewalls of the sacrificial gate structure 113. In terms of materials, the sacrificial gate structure 113 typically includes a sacrificial gate insulating layer (not shown separately), such as silicon dioxide, formed on the fin 103, and a sacrificial gate electrode (not shown separately), formed on the sacrificial gate insulating layer, which is made, for example, of polycrystalline or amorphous silicon. The gate cap 115 may be made of a material such as silicon nitride, and the sidewall spacers 117 may be made of a low-k insulating material (k value less than about 3.4).

[0021] Still referencing Fig. 6 After forming the sidewall spacers 117, a lightly doped drain (LDD) ion implantation process is performed to implant N-type ions. - Within the injection region 111, that is, within the base region of the lateral BJT device 104, a P-type electrode is formed. + LDD injection region 121. P + The dopant concentration of the P-type dopant material in the LDD injection region 121 can be varied depending on the specific application, for example, 1e 17 -1e 20 atoms / cm 3 In one particular embodiment, P + The dopant concentration of the P-type doped material in the LDD injection region 121 can be approximately 1 e.19 atoms / cm 3 P + LDD injection region 121 can be doped with any kind of P-type dopant material.

[0022] As will be described more fully below, various process operations will be performed to form an overall epitaxial cavity 122 in the semiconductor substrate 101 on opposite sides of the gate structure 113 that will form the emitter and collector regions of the lateral BJT device 104. Each of the overall epitaxial cavities 122 has the same basic configuration. Therefore, Fig. 7 An IC product 100 is shown after performing a first etching process (e.g., an anisotropic etching process) to form a plurality of upper epitaxial cavities 123 in fin 103. The upper epitaxial cavities 123 have N... - The bottom surface 123X stops within the injection region 111, i.e., within the base region of the lateral BJT device 104, but this is not the case in all applications. The depth of the upper epitaxial cavity 123 can vary depending on the specific application. In one exemplary embodiment, based on current technology, the depth of the upper epitaxial cavity 123 below the upper surface 103S of the fin 103 can be approximately 40-60 nm. In the currently disclosed example, the upper epitaxial cavity 123 is substantially vertically oriented and substantially self-aligned relative to the adjacent sidewall spacers 117 and the isolation structure 107.

[0023] Fig. 8 The diagram illustrates an IC product 100 after a conformal deposition process is performed to form an insulating material conformal layer 125 on the product 100 and within the upper epitaxial cavity 123. The insulating material conformal layer 125 can be made of various different materials, such as silicon dioxide and silicon nitride, and can be formed to any desired thickness, such as 4-5 nm, based on current technology.

[0024] Fig. 9An IC product 100 after several process operations are shown. First, an anisotropic etching process is performed on an insulating conformal layer 125 to remove a substantially horizontally oriented portion of the insulating conformal layer 125. This operation results in the formation of sacrificial inner sidewall spacers 125S within each upper epitaxial cavity 123. Note that after the formation of the inner sidewall spacers 125S, the bottom surface 123X of each upper epitaxial cavity 123 is exposed. Subsequently, another anisotropic etching process is performed to form another epitaxial cavity 127 below each upper epitaxial cavity 123. As shown, in an exemplary embodiment, the epitaxial cavity 127 is substantially self-aligned relative to the inner sidewall spacers 125S within each upper epitaxial cavity 123, and the epitaxial cavity 127 effectively extends the depth of the upper epitaxial cavity 123. The epitaxial cavity 127 has a bottom surface 127X located at a layer level within the substrate 101 below the bottom surface 123X of the upper epitaxial cavity 123. In one exemplary instance, based on current technology, the difference 129 between the vertical positions of the bottom surface 123X of the upper epitaxial cavity 123 and the bottom surface 127X of the epitaxial cavity 127 can be approximately 10-20 nm. In the example shown, the bottom surface 127X of the epitaxial cavity 127 stops within the N-well region 109, but this is not the case in all applications.

[0025] Fig. 10 An IC product 100 is shown after a crystallization wet etching process. This etching process can be performed using etchants such as TMAH (tetramethylammonium hydroxide), KOH, etc. This process operation results in the formation of a lower epitaxial cavity 131 at the bottom of each upper epitaxial cavity 123. In an exemplary embodiment, the lower epitaxial cavity 131 may have a sigma-shaped (or rhomboid) cross-sectional configuration in a cross-section taken along a direction corresponding to the substrate width direction of the lateral BJT device 104. The silicon substrate 101 has a crystalline structure in which… <100> The crystal orientation is indicated by double arrow 140, and the substrate 101 is... <110> The crystal orientation is indicated by double arrows 142. The lower epitaxial cavity 131 is partially defined by the bottom surface 127X of the basic plane, the lower faceted surface 131B, and the upper faceted surface 131C. The substrate 101 <111> The fundamental crystal orientation is normal to the lower facet surface 131B and is indicated by arrow 133. Those skilled in the art will understand that this wet etching process based on TMAH or KOH... <100> The etching rate of the crystal orientation is significantly greater than that of the crystal orientation. <111> Etching rate of crystal orientation. As shown in the figure, facet surfaces 131B and 131C intersect at vertex 131A. Of course, those skilled in the art will understand after fully reading this application that the overall size and configuration of the lower epitaxial cavity 131 may vary depending on the specific application and are not limited to it. Fig. 10 The exemplary sigma-shaped (or rhomboid) cross-sectional configuration shown is possible because the lower epitaxial cavity 131 can have a variety of different configurations.

[0026] In the illustrated example, the upper epitaxial cavity 123 extends from the surface 130S of the fin 103 to the lower epitaxial cavity 131. Each integral epitaxial cavity 122 includes the upper epitaxial cavity 123 and the lower epitaxial cavity 131. The physical dimensions of the example sigma-shaped lower epitaxial cavity 131 and the final positioning relative to other structures or features on the IC product 100 can vary depending on the particular application. Thus, the following example dimensions are provided merely as examples based on current technology, and such dimension examples should not be considered limiting of the various applications disclosed herein. The lower epitaxial cavity 131 has a total width 131W (in the base width direction) and a total height or vertical thickness 131G. In one example instance, the total width 131W can be approximately 30-60 nm and the total height or vertical thickness 131G can be approximately 10-20 nm. The bottom surface 127X of the lower epitaxial cavity 131 can be located at a distance 131D of approximately 50-80 nm below the upper surface 103S of the fin 103. The apex 131A of the lower epitaxial cavity 131 can be located at a distance 131E of approximately 45 nm-70 nm below the upper surface 103S of the fin 103. In one particularly example instance, the apex 131A of each lower epitaxial cavity 131 can extend a distance 131F below and from the sidewall 113X of the gate structure 113. In one example instance, the dimension 131F can be approximately 1-10 nm. In other applications, the apex 131A of each lower epitaxial cavity 131 can not extend below the sidewall 113X of the gate structure 112 at all. It should be noted that the lateral width of the lower epitaxial cavity 131 in the base width direction of the lateral BJT device 104 is greater than the lateral width of the substantially vertically oriented upper epitaxial cavity 123 in the base width direction of the lateral BJT device 104. In one example instance, the vertical distance 131J between the upper surface 103S of the fin 103 and the uppermost surface of the lower epitaxial cavity 131 (e.g., at the bottom of the inner spacer 125S) can be approximately 30-60 nm. Further, in one example instance, the vertical distance between the bottom surface 107A of the isolation structure 107 and the apex 131A of the lower epitaxial cavity 131 can be approximately 0-40 nm. In some applications, the bottom surface 107A of the isolation structure 107 can be positioned at approximately level with the midpoint of the vertical thickness 131G of the lower epitaxial cavity 131.

[0027] With continued reference to Fig. 10 Upon a complete reading of this application, those skilled in the art will understand that the base region (N - the injection region 111) of the novel BJT device 104 disclosed herein has a very novel configuration when viewed in cross-section taken through the base region 111 along a direction corresponding to the base width direction of the lateral BJT device 104. More particularly, the base region 111 has a very novel configuration in that the base region 111 is formed in a substantially vertically oriented upper epitaxial cavity 123 that is located above and spaced apart from a laterally oriented lower epitaxial cavity 131.+ The upper lateral width 111X at the location of the LDD implant region 121 (if present) below) is greater than the lower lateral width 111Y of the base region 111 at the bottom 111B of the base region 111 where the base region 111 intersects the N-well 109. According to an embodiment, the lower lateral width 111Y can be approximately 50% to 95% of the upper lateral width 111X in terms of percentage. However, in general, the magnitude of the difference between the dimensions 111X and 111Y can vary depending on the particular application. The apex 131A of the lower epitaxial cavity 131 can be at a level above or below the level of the bottom surface 111B of the base region 111. In one particular example, the apex 131A of the lower epitaxial cavity 131 can be at a level approximately flush with the bottom surface 111B of the base region 111. It is also noted that in one embodiment (see Fig. 12 ), the apex 131A of the emitter region 135E and the collector region 135C can extend below the portion of the base region 111.

[0028] Those skilled in the art, upon reading the present application in its entirety, will appreciate that the novel configuration of the base region 111 of the novel lateral BJT device 104 disclosed herein provides significant benefits compared to prior art lateral BJT devices whose base region has a substantially uniform width (along the base width direction) over the entire vertical height of the base region. In general, for lateral BJT devices, there are two competing operational frequency parameters, namely the cutoff frequency (f T ) and the maximum oscillation frequency (f max ). For example, f T may be improved (i.e., increased) by providing a base region with a smaller width, thereby reducing the base transit time. However, since f max is proportional to the square root of f T / R B , where R B is the resistance of the base region, a higher f T results in a lower f max , and vice versa. However, the novel configuration of the base region 111 of the novel lateral BJT device 104 disclosed herein addresses this situation by providing a smaller base width 111Y at the bottom of the base region 111 and a larger base width 111X at the upper portion of the base region 111, which results in an increase in f t and f max and an increase in the DC current gain (β).

[0029] Fig. 11 An IC product 100 after performing an etching process to remove the inner sidewall spacers 125S from the product 100 and in particular from the overall epitaxial cavity 122 is shown.

[0030] Fig. 12 An IC product is shown after performing an epitaxial growth process to form P+ doped epitaxial semiconductor material regions 135E (for the emitter regions of the devices) and 135C (for the collector regions of the devices) in the bulk epitaxial cavity 122. The P+ doped epitaxial semiconductor material regions 135E and 135C will be referred to collectively using the reference 135. In one exemplary process flow, the P+ doped epitaxial semiconductor material regions 135 can be doped in situ, i.e., dopant material can be added during the epitaxial growth process. In other applications, the epitaxial semiconductor material 135 can be initially formed as a substantially undoped epitaxial semiconductor material, and then an ion implantation process can be performed to introduce dopant material into the previously undoped epitaxial semiconductor material 135. In the latter case, the dopant concentration of the P+ doped epitaxial semiconductor material 135E and 135C can be different from one another. Regardless of how the P-type dopant material is introduced into the epitaxial semiconductor material 135, the dopant concentration of the P-type dopant material in the P+ doped epitaxial semiconductor material 135 can vary depending on the particular application, e.g., 1e 17 -1e 21 atoms / cm 3 In one particular embodiment, the dopant concentration of the P-type dopant material in the P+ doped epitaxial semiconductor material 135 can be approximately 1e 20 atoms / cm 3 The P+ doped epitaxial semiconductor material 135 can be doped with any kind of P-type dopant material. The epitaxial semiconductor material regions 135 can be made of any desired semiconductor material, e.g., P-doped silicon germanium for PNP devices, N-doped silicon carbon for NPN devices, etc. In the illustrated example, the epitaxial growth process is controlled so that the upper surface 135ES of the P+ doped epitaxial semiconductor material 135 is approximately flush with the upper surface 103S of the fins 103. In other cases, the P+ doped epitaxial semiconductor material 135 can be grown so that its upper surface 137 (depicted in dashed lines) is located above the upper surface 103S of the fins 103, i.e., a raised source / drain region.

[0031] Fig. 13 An IC product 100 is shown after performing several process operations. First, an insulating material layer 139, e.g., silicon dioxide, low-k material, etc., is formed adjacent to the sacrificial sidewall spacers 117. Prior to forming the insulating material layer 139, a conformal etch stop layer (not shown) can be formed. The insulating material layer 139 can be initially formed to cover the gate cap 115. Then, one or more processing steps (e.g., planarization, etching) are performed to remove the sacrificial gate structures 113, thereby forming base region cavities 141 that expose the base regions 111.

[0032] Fig. 14An exemplary sidewall spacer 117X (shown in dashed lines) is shown positioned adjacent to a sacrificial gate structure (not shown, one to the left of the emitter region 135E and one to the right of the collector region 135C). Fig. 14 The IC product 100 is shown after a number of process operations have been performed. First, another layer of insulating material 143, such as silicon dioxide, low-k material, etc., is formed in the base region cavities 141, and then a CMP operation is performed to planarize the upper surface of the insulating material layer 143. As previously mentioned, a conformal etch stop layer (not shown) can be formed in the base region cavities 141 prior to the formation of the insulating material layer 143.

[0033] In one exemplary process flow, the conductive contact structures for the emitter region 135E, the base region 111, and the collector region 135C of the lateral BJT device 104 can be formed concurrently with other conductive structures (not shown) formed on the IC product 100 for various transistor devices (not shown). For example, the conductive contact structures for the lateral BJT device 104 can be formed concurrently with conductive source / drain metallization structures (not shown) for contacting source / drain regions of transistor devices (not shown) on the IC product 100, and they can be made of the same material as the conductive source / drain metallization structures, such as a trench silicide material. Thus, Fig. 15 The IC product 100 is shown after an etch process has been performed to form contact openings 144A, 144B, and 144C (collectively referred to using the reference number 144) that respectively expose the emitter region 135E, the base region 111, and the collector region 135C of the lateral BJT device 104.

[0034] Fig. 16 The IC product 100 is shown after exemplary conductive contact structures 145A, 145B, and 145C (collectively referred to using the reference number 145) have been formed that respectively electrically contact the emitter region 135E, the base region 111, and the collector region 135C of the lateral BJT device 104. As mentioned above, the conductive contact structures 145 can be composed of the same material as, and formed concurrently with, conductive source / drain metallization structures (e.g., trench silicide material) formed at other locations on the IC product 100. All of the conductive contact structures 145 need not have the same physical dimensions, although this can be the case in some applications. Note that in this exemplary process flow, the conductive contact structures 145 are formed in a self-aligned manner between the spacer structures 117.

[0035] It should also be noted that the conductive contact structure 145 can also be formed by performing a conventional fabrication process, such as etching a contact opening in the insulating material 139, 141 that exposes at least a portion of the emitter region 135E, the base region 111, and the collector region 135C, depositing a liner layer and a conductive material in the contact opening, and performing a CMP operation to remove the conductive material that is outside the contact opening and that is above the upper surface of the insulating material 139, 141.

[0036] Fig. 17 (see Fig. X-X ) and Fig. 18 (see view Y-Y) illustrates an alternative embodiment of the novel lateral BJT device 104 disclosed herein. Starting from the point of fabrication shown, i.e., after the base region cavity 141 is formed, Fig. 13 Fig. 17 and 18 illustrates the IC product 100 after performing an epitaxial growth process to form an N+ doped epitaxial semiconductor material region 147 in the base region cavity 141 between the sidewall spacers 117 and on the base region 111. This additional epitaxial semiconductor material 147 is part of the entire base region of the lateral BJT device 104, and the epitaxial semiconductor material 147 can be referred to as an extrinsic (or additional) base region because it adds to the physical volume of the base region 111 formed in the fin 103 via ion implantation (this base region is referred to as the intrinsic (or initial) base region). In one exemplary process flow, the epitaxial semiconductor material 147 can be doped in situ, i.e., dopant material can be added during the epitaxial growth process. In other applications, the epitaxial semiconductor material 147 can initially be formed as a substantially undoped epitaxial semiconductor material, and then an implantation process can be performed to introduce dopant material to the previously undoped epitaxial semiconductor material 147. Regardless of how the N-type dopant material is introduced into the epitaxial semiconductor material 147, the dopant concentration of the N-type dopant material in the N+ doped epitaxial semiconductor material 147 can vary depending on the particular application, such as 1e 19 -1e 21 atoms / cm 3 In one particular embodiment, the dopant concentration of the N-type dopant material in the N+ doped epitaxial semiconductor material 147 can be approximately 1e 20 atoms / cm 3 ​The N+ doped epitaxial semiconductor material 147 can be doped with any kind of N-type dopant material. The epitaxial semiconductor material region 147 can be made of any desired semiconductor material, e.g., N-doped silicon carbon for PNP devices, P-doped silicon germanium for NPN devices, etc. The volume of the epitaxial semiconductor material 147 formed can also vary depending on the particular application. In one exemplary embodiment, the epitaxial semiconductor material 147 formed on the exposed upper and side surfaces of the fin 103 can have a substantially uniform thickness.

[0037] Fig. 19 An IC product 100 is shown after the formation of the above-described conductive contact structure 145 on the lateral BJT device 104.

[0038] As noted above, the overall epitaxial cavity 122 (e.g., the combination of the lower epitaxial cavity 131 and the upper epitaxial cavity 123) can have a variety of different configurations. Fig. 20-21 Another exemplary embodiment of the lateral BJT device 104 is shown in which the lower epitaxial cavity 131 of the overall epitaxial cavity 122 has a generally circular or elliptical configuration. In one particular example, the elliptical or circular lower epitaxial cavity 131 has dimensions substantially similar to those described above for the sigma-shaped (or diamond-shaped) lower epitaxial cavity 131. In some applications, the bottom surface 107A of the isolation structure 107 can be positioned at a level substantially flush with the midpoint of the vertical thickness 129 of the elliptical or circular lower epitaxial cavity 131. Fig. 20 The midpoint of the vertical thickness 129 of the elliptical or circular lower epitaxial cavity 131 is shown at a level substantially flush with the bottom surface 107A of the isolation structure 107.

[0039] Reference is made to Fig. 20 After the formation of the inner sidewall spacer 125S (see Fig. 9 ) in the upper epitaxial cavity 123, one or more etching processes are performed to form the elliptical or circular lower epitaxial cavity 131. The etching processes used to form the lower epitaxial cavity 131 can have isotropic and anisotropic characteristics. The overall dimensions of the circular lower epitaxial cavity 131 can vary depending on the particular application.

[0040] Fig. 21 An IC product 100 is shown after the formation of the above-described emitter region 135, collector region 135C, epitaxial semiconductor material 147, and conductive contact structure 145 on the lateral BJT device 104. As with the previous embodiments, the epitaxial semiconductor material 147 can be omitted if desired.

[0041] The above-described figures show the formation of a single lateral BJT device 104 surrounded by the isolation structure 107. In practice, several such lateral BJT devices 104 can be formed laterally adjacent to one another and the isolation structure 107 can be positioned around the entire set of lateral BJT devices 104. Fig. 22This is a simplified planar view showing three lateral BJT devices 104A, 104B, and 104C (partial), all referred to by the designation 104. Lateral BJT device 104A includes emitter region 1 (E1), base region 1 (B1), and collector region 1 (C1). Lateral BJT device 104B includes emitter region 2 (E2), base region 2 (B2), and collector region 2 (C2). Only emitter region 3 (E3) and base region (B3) of lateral BJT device 104C are shown.

[0042] Fig. 23 yes Fig. 22 The exemplary lateral BJT device 104 shown is a cross-sectional view, wherein the lower epitaxial cavity 131 of the integral epitaxial cavity 122 has a sigma-shaped (or rhomboid) lower epitaxial cavity 131. Fig. 24 yes Fig. 22 The exemplary lateral BJT device 104 shown is a cross-sectional view, wherein the lower epitaxial cavity 131 of the integral epitaxial cavity 122 has a generally circular or elliptical configuration. Fig. 23 and 24 It does not include all the details shown in the previous cross-sectional view; for example, P is omitted. + LDD injection area 121, etc., to prevent... Fig. 23 and 24 Too complicated.

[0043] The simulations already performed demonstrate that, compared to a corresponding lateral BJT device (hereinafter referred to as a uniform substrate width BJT device (UBW BJT device)) with a base region having a substantially uniform lateral width (along the substrate width direction) over substantially the entire vertical height of the uniform-width base region, the BJT device with corresponding doped intrinsically doped base epitaxial semiconductor material has a base region with a substantially uniform lateral width (along the substrate width direction). Fig. 19 The novel non-uniform base-lateral BJT device 104 (hereinafter referred to as NUBW BJT 104), featuring a doped extrinsic base epitaxial semiconductor material 147 and a base region 111 (with different upper and lower lateral widths 111X and 111Y, respectively), exhibits significant performance capabilities. For simulation purposes, both the NUBW BJT 104 and the UBW BJT device are modeled as PNP devices. Furthermore, the upper lateral width 111X and lower lateral width 111Y of the base region 111 of the NUBW BJT 104 are 20 nm and 10 nm, respectively, while the UBW BJT device has a uniform substrate width of approximately 20 nm (along the substrate width direction). Moreover, the doping levels in all different regions (e.g., well region, collector region, and emitter region) are substantially the same.

[0044] Fig. 25-27 It is shown Fig. 19NUBW BJT 104 in comparison to various performance parameters of UBW BJT devices.

[0045] Fig. 25 is a plot of the relationship between the current gain (β) and the voltage across the base-emitter (Vbe) for the NUBW BJT 104 and UBW BJT devices according to embodiments. As can be seen from this plot, the current gain (β) of the NUBW BJT 104 is significantly increased relative to the UBW BJT devices. For example, at the point where Vbe = approximately 0.7 V, Fig. 19 the β of the NUBW BJT 104 is approximately one hundred times the β of the UBW BJT devices.

[0046] Fig. 26 is a plot of the relationship between the cutoff frequency (f T ) and the voltage across the base-emitter (Vbe) for the NUBW BJT 104 and UBW BJT devices according to embodiments. As can be seen from this plot, the f T of the NUBW BJT 104 is significantly increased relative to the f T of the UBW BJT devices. For example, at the point where Vbe = approximately 0.7 V, Fig. 19 the f T of the NUBW BJT 104 is approximately one hundred percent greater than the f T of the UBW BJT devices.

[0047] Fig. 27 is a plot of the relationship between the maximum oscillation frequency (f max ) and the collector current for the NUBW BJT 104 and UBW BJT devices according to embodiments. As can be seen from this plot, the f max of the NUBW BJT 104 is significantly increased relative to the f max of the UBW BJT devices. For example, Fig. 19 the f max of the NUBW BJT 104 is approximately 15% greater than the f max of the UBW BJT devices. Generally, the f max is improved over a typical range of collector currents.

[0048] The particular embodiments disclosed above are considered illustrative only of the presently preferred embodiment of the application and are not intended to limit the scope of the application. For example, the process steps described above can be performed in a different order than that described. Furthermore, to the extent that the configuration or design of the present application can be changed or modified without departing from the scope and spirit of the application, it is desired that such changes be considered as equivalents of the original features. Accordingly, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement or design which is different but which would serve the same purpose can be substituted for the specific embodiments shown and described without departing from the spirit and scope of the application. It should be noted that the use of terms such as "first", "second", "third" or "fourth" to describe various processes or structures in the specification and claims are used only as shorthand for these steps / structures and do not necessarily imply an order of execution / forming of such steps / structures. Of course, depending on the exact claim language, ordered sequences of these processes can or can not be required. Accordingly, the protection sought is set forth in the following claims.

Claims

1. A semiconductor device, comprising: a semiconductor substrate having an upper surface; and a bipolar junction transistor (BJT) device including a collector region, a base region, and an emitter region located in the semiconductor substrate, the base region being located between the collector region and the emitter region; the base region including a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device, wherein the collector region includes epitaxial semiconductor material formed within a first cavity, the emitter region includes epitaxial semiconductor material formed within a second cavity, and wherein a portion of the first cavity and a portion of the second cavity extend below a portion of the base region. the top surface of the base region is located at the upper surface of the semiconductor substrate.

2. The semiconductor device of claim 1, wherein, the BJT device is one of an NPN BJT device or a PNP BJT device.

3. The semiconductor device of claim 1, wherein, the semiconductor substrate includes a fin structure, wherein at least a portion of the collector region, the base region, and the emitter region are located in the fin structure, and wherein the upper surface of the semiconductor substrate is an upper surface of the fin structure.

4. The semiconductor device of claim 1, wherein, the portion of the first cavity and the portion of the second cavity are separated by a distance equal to the second width of the bottom surface of the base region in the base width direction of the BJT device.

5. The semiconductor device of claim 1, wherein, the second width is 50-95% of the first width.

6. The semiconductor device of claim 1, wherein, 7. A lateral bipolar junction transistor (BJT) device, comprising: a collector region, a base region, and an emitter region located in a semiconductor substrate, the base region being located between the collector region and the emitter region; the base region including a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the lateral BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the lateral BJT device, wherein a portion of the collector region and a portion of the emitter region extend below a portion of the base region and are separated by a distance equal to the second width, wherein the collector region includes epitaxial semiconductor material formed within a first cavity, the emitter region includes epitaxial semiconductor material formed within a second cavity, and wherein a portion of the first cavity and a portion of the second cavity extend below the portion of the base region. the top surface of the base region is located at an upper surface of the semiconductor substrate.

8. The lateral BJT device of claim 7, wherein, the BJT device is one of an NPN BJT device or a PNP BJT device.

9. The lateral BJT device of claim 7, wherein, the semiconductor substrate includes a fin structure, wherein at least a portion of the collector region, the base region, and the emitter region are located in the fin structure, and wherein an upper surface of the semiconductor substrate is an upper surface of the fin structure.

10. The lateral BJT device of claim 7, wherein, the second width is 50-95% of the first width.

11. The lateral BJT device of claim 7, wherein, 12. A method for a semiconductor device, comprising: providing a semiconductor substrate having an upper surface; and ​ and forming a bipolar junction transistor (BJT) device in the semiconductor substrate, the BJT device including a collector region, a base region, and an emitter region in the semiconductor substrate, the base region being between the collector region and the emitter region and including a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device, forming the collector region in a first cavity in the semiconductor substrate; and forming the emitter region in a second cavity in the semiconductor substrate, wherein a portion of the first cavity and a portion of the second cavity extend below a portion of the base region.

13. The method of claim 12, wherein, the semiconductor substrate includes a fin structure, the method further including positioning at least a portion of the collector region, the base region, and the emitter region in the fin structure, and wherein the upper surface of the semiconductor substrate is an upper surface of the fin structure.

14. The method of claim 12, further comprising forming epitaxial semiconductor material within the first cavity and the second cavity.

15. The method of claim 12, wherein, the portion of the first cavity and the portion of the second cavity are separated by a distance, the distance being equal to the second width of the bottom surface of the base region in the base width direction of the BJT device.

16. The method of claim 12, wherein, the second width is 50-95% of the first width.

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