Semiconductor Structure and Method for Forming the Same

Abstract

The present application provides a semiconductor structure and a method for forming the same. The method includes: providing a semiconductor substrate, the semiconductor substrate including a first region and a second region and an isolation structure isolating the first region and the second region, a first well region and a second well region being respectively formed in the semiconductor substrates of the first region and the second region; forming a pre-doped first gate layer and a second gate layer on the semiconductor substrates of the first region and the second region respectively. In the method for forming the semiconductor structure according to the present application, an in-situ doping process is used to form the pre-doped gate layer, which can avoid the polycrystalline penetration effect caused by a large amount of particle injection into the gate layer, and impurity particles entering the channel to affect the device performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] TFET (Tunneling Field Effect Transistor) devices with excellent subthreshold characteristics can be hybrid integrated with traditional CMOS devices to reduce the overall power consumption of the circuit. The high-frequency part of the circuit is completed by conventional CMOS devices, and the low-frequency part is completed by TFET devices. On the premise of being compatible with the existing CMOS process, the structure and performance of TFET devices are still unstable and there is a large room for improvement.

[0003] Therefore, it is necessary to provide a more reliable and effective technical solution. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same, which can avoid the polycrystalline penetration effect caused by a large number of particle injections into the gate layer, and impurity particles entering the channel and affecting the device performance.

[0005] One aspect of this application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, the semiconductor substrate including a first region and a second region and an isolation structure isolating the first region and the second region, a first well region and a second well region being respectively formed in the semiconductor substrates of the first region and the second region; respectively forming a pre-doped first gate layer and a second gate layer on the semiconductor substrates of the first region and the second region; respectively forming lightly doped source and lightly doped drain in the semiconductor substrates on both sides of the first gate layer and the second gate layer; respectively forming sidewalls on both sides of the first gate layer and the second gate layer; respectively forming heavily doped source and heavily doped drain in the semiconductor substrates on both sides of the first gate layer and the second gate layer; forming an interlayer dielectric layer covering the semiconductor substrate and the first gate layer and the second gate layer on the semiconductor substrate; forming a contact structure penetrating the interlayer dielectric layer and electrically connecting the first gate layer and the second gate layer in the interlayer dielectric layer.

[0006] In some embodiments of the present application, the method for forming a pre-doped first gate layer and a second gate layer on the semiconductor substrate in the first region and the second region respectively includes: sequentially forming a first gate oxide layer and a pre-doped first gate layer on the semiconductor substrate; removing the first gate oxide layer and the pre-doped first gate layer located in the second region; sequentially forming a second gate oxide layer and a pre-doped second gate layer on the second region and the pre-doped first gate layer; removing the second gate oxide layer and the pre-doped second gate layer that are higher than the pre-doped first gate layer; removing the first gate oxide layer and the pre-doped first gate layer, and the second gate oxide layer and the pre-doped second gate layer that are not above the channel.

[0007] In some embodiments of the present application, the method for removing the first gate oxide layer and the pre-doped first gate layer located in the second region includes: forming a photoresist layer on the surface of the first gate layer in the first region; etching and removing the first gate oxide layer and the first gate layer located in the second region; removing the photoresist layer.

[0008] In some embodiments of the present application, the method for forming the first gate oxide layer includes a thermal oxidation process, and the method for forming the pre-doped first gate layer includes an in-situ doping process.

[0009] In some embodiments of the present application, the method for forming the second gate oxide layer includes a thermal oxidation process, and the method for forming the pre-doped second gate layer includes an in-situ doping process.

[0010] In some embodiments of the present application, the doping types of the first gate layer and the first well region are opposite, and the doping types of the second gate layer and the second well region are opposite.

[0011] In some embodiments of the present application, the doping concentration of the first gate layer is 1×10 19 -1×10 21 atom / cm 3 , and the concentration of the second gate layer is 1×10 19 -1×10 21 atom / cm 3 .

[0012] In some embodiments of the present application, the doping particles of the first gate layer include phosphorus, boron, arsenic, indium, and antimony, and the doping particles of the second gate layer include phosphorus, boron, arsenic, indium, and antimony.

[0013] In some embodiments of the present application, the doping types of the lightly doped source and the lightly doped drain are opposite, and the doping types of the heavily doped source and the heavily doped drain are opposite.

[0014] Another aspect of the present application provides a semiconductor structure, comprising: a semiconductor substrate including a first region and a second region, and an isolation structure isolating the first region and the second region, wherein a first well region and a second well region are respectively formed in the semiconductor substrates of the first region and the second region; a pre-doped first gate layer and a second gate layer respectively located on the semiconductor substrates of the first region and the second region; lightly doped source and lightly doped drain respectively located in the semiconductor substrates on both sides of the first gate layer and the second gate layer; sidewalls located on both sides of the first gate layer and the second gate layer; heavily doped source and heavily doped drain respectively located in the semiconductor substrates on both sides of the first gate layer and the second gate layer; an interlayer dielectric layer located on the semiconductor substrate to cover the semiconductor substrate, the first gate layer and the second gate layer; and a contact structure penetrating the interlayer dielectric layer and electrically connecting the first gate layer and the second gate layer.

[0015] In some embodiments of the present application, the doping types of the first gate layer and the first well region are opposite, and the doping types of the second gate layer and the second well region are opposite.

[0016] In some embodiments of the present application, the doping concentration of the first gate layer is 1×10 19 -1×10 21 atom / cm 3 and the doping concentration of the second gate layer is 1×10 19 -1×10 21 atom / cm 3 .

[0017] In some embodiments of the present application, the doping particles of the first gate layer include phosphorus, boron, arsenic, indium, and antimony, and the doping particles of the second gate layer include phosphorus, boron, arsenic, indium, and antimony.

[0018] In some embodiments of the present application, the doping types of the lightly doped source and the lightly doped drain are opposite, and the doping types of the heavily doped source and the heavily doped drain are opposite.

[0019] For the semiconductor structure and its forming method described in the present application, an in-situ doping process is used to form the pre-doped gate layer, which can avoid the polycrystalline penetration effect caused by a large number of particle injections into the gate layer, and prevent impurity particles from entering the channel and affecting the device performance. Description of the Drawings

[0020] The following drawings detail the exemplary embodiments disclosed in the present application. Wherein the same reference numerals denote similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0021] Figures 1 to 12 It is a schematic structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. Detailed implementation manners

[0022] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content in the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the disclosed embodiments, but to the broadest scope consistent with the claims.

[0023] The technical solution of the present invention will be described in detail below in conjunction with the embodiments and the drawings.

[0024] In the formation process of TFET, since the doping types of the source and drain are opposite, the source and drain of TFET will inject impurity ions of opposite types, which will cause different types of impurity ions to be injected into the polysilicon gate, forming a PN junction in the polysilicon gate, seriously affecting the function of the polysilicon gate.

[0025] To ensure correct doping of the polysilicon gate, pre-doping is usually achieved by pre-injection (pre-doing) to prevent the doping type from reversing due to impurity compensation. That is, a large dose of impurity ions (usually 2-3 times the doping concentration of the source and drain) is injected into the polysilicon gate in advance. In this way, even if different types of impurity ions are injected into the polysilicon gate when the source and drain are formed subsequently, since the inverted impurity ions are neutralized by the high-concentration impurity ions in the polysilicon gate, a PN junction will no longer be formed.

[0026] However, due to the large impurity compensation ratio of TFET, the injection dose required for the corresponding pre-doping is also relatively high. A typical dose is, for example, 5E15atom / cm 3 , and the large-dose injection is likely to damage the polysilicon, resulting in the polycrystalline penetration effect, and the impurity ions enter the channel, affecting the transistor performance.

[0027] In view of the above problems, the present application provides a method for forming a semiconductor structure. By using an in-situ doping process to form a pre-doped gate layer, the polycrystalline penetration effect caused by a large number of particle injections into the gate layer can be avoided, and impurity particles entering the channel can be prevented from affecting device performance.

[0028] Figures 1 to 12 FIGS. are schematic structural diagrams of the steps in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0029] An embodiment of the present application provides a method for forming a semiconductor structure, including: referring to Figure 1 , providing a semiconductor substrate 100, the semiconductor substrate 100 including a first region 101 and a second region 102 and an isolation structure 103 isolating the first region 101 and the second region 102, and a first well region 111 and a second well region 112 are respectively formed in the semiconductor substrates of the first region 101 and the second region 102; referring to Figures 2 to 8 , respectively forming a pre-doped first gate layer 121 and a second gate layer 122 on the semiconductor substrates of the first region 101 and the second region 102.

[0030] Referring to Figure 1 as shown, providing a semiconductor substrate 100, the semiconductor substrate 100 including a first region 101 and a second region 102 and an isolation structure 103 isolating the first region 101 and the second region 102, and a first well region 111 and a second well region 112 are respectively formed in the semiconductor substrates of the first region 101 and the second region 102.

[0031] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide or gallium indium phosphide; or (iv) a combination of the above.

[0032] In some embodiments of the present application, the material of the isolation structure 103 includes silicon oxide, silicon nitride or silicon oxynitride, etc. The isolation structure 103 is used to isolate active devices in the semiconductor substrates of the first region 101 and the second region 102.

[0033] In some embodiments of the present application, the first well region 111 and the second well region 112 are formed by doping the semiconductor substrates in the first region 101 and the second region 102.

[0034] In some embodiments of the present application, the first well region 111 may be a P-type well region doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium), or an N-type well region doped with an N-type dopant (e.g., phosphorus or arsenic); the second well region 112 may be a P-type well region doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium), or an N-type well region doped with an N-type dopant (e.g., phosphorus or arsenic). In some embodiments of the present application, the doping types of the first well region 111 and the second well region 112 are different.

[0035] Reference Figures 2 to 8 , a pre-doped first gate layer 121 and a second gate layer 122 are formed on the semiconductor substrate 100 of the first region 101 and the second region 102, respectively.

[0036] Reference Figure 2 As shown, a first gate oxide layer 131 and a pre-doped first gate layer 121 are sequentially formed on the semiconductor substrate 100.

[0037] In some embodiments of the present application, the method of forming the first gate oxide layer 131 includes a chemical vapor deposition process, a physical vapor deposition process, or a thermal oxidation process.

[0038] In some embodiments of the present application, in order to obtain an oxide layer with better mass purity, the method of forming the first gate oxide layer 131 is a thermal oxidation process. Reference Figure 2 , in the thermal oxidation process, only the surface of the semiconductor substrate 100 can be oxidized to form the first gate oxide layer 131, while the surface of the isolation structure 103 will not form the first gate oxide layer 131.

[0039] In some embodiments of the present application, the material of the first gate oxide layer 131 includes silicon oxide.

[0040] In some embodiments of the present application, the method of forming the pre-doped first gate layer 121 includes an in-situ doping process. The first gate layer 121 covers the top surface of the isolation structure 103 and the surface of the first gate oxide layer 131. The in-situ doping process is to dope impurity particles into the gate material while depositing the gate material, so as to directly form a gate layer doped with impurity particles.

[0041] In some embodiments of the present application, the material of the first gate layer 121 includes polysilicon.

[0042] In some embodiments of the present application, the doping types of the first gate layer 121 and the first well region 111 are opposite. When the first well region 111 is a P-type well region, the first gate layer 121 is N-type doped; when the first well region 111 is an N-type well region, the first gate layer 121 is P-type doped.

[0043] In some embodiments of the present application, the doping concentration of the first gate layer 121 is 1×10 19 -1×10 21 atom / cm 3 , in order to ensure that a PN junction is not formed in the first gate layer 121 when the source and drain are formed subsequently, the doping concentration of the first gate layer 121 should be greater than that of the source and drain (usually 2-3 times).

[0044] In some embodiments of the present application, the doping particles of the first gate layer 121 include phosphorus, boron, arsenic, indium, antimony, etc. Specifically, it can be selected according to the required particle type (P-type or N-type).

[0045] Referring to Figures 3 to 5 as shown, the first gate oxide layer 131 and the pre-doped first gate layer 121 located on the second region 102 are removed.

[0046] Referring to Figure 3 as shown, a photoresist layer 140 is formed on the surface of the first gate layer 121 on the first region 101; referring to Figure 4 as shown, the first gate oxide layer 131 and the first gate layer 121 located on the second region 102 are etched and removed; referring to Figure 5 as shown, the photoresist layer 140 is removed.

[0047] Referring to Figure 6 as shown, a second gate oxide layer 132 and a pre-doped second gate layer 122 are sequentially formed on the second region 102 and the pre-doped first gate layer 121.

[0048] In some embodiments of the present application, the method for forming the second gate oxide layer 132 includes chemical vapor deposition process, physical vapor deposition process or thermal oxidation process.

[0049] In some embodiments of the present application, in order to obtain an oxide layer with better mass purity, the method for forming the second gate oxide layer 132 is a thermal oxidation process. Referring to Figure 6 , in the thermal oxidation process, only the surfaces of the semiconductor substrate 100 and the first gate layer 121 can be oxidized to form the second gate oxide layer 132, and the surface of the isolation structure 103 will not form the second gate oxide layer 132.

[0050] In some embodiments of the present application, the material of the second gate oxide layer 132 includes silicon oxide.

[0051] In some embodiments of the present application, the method of forming the pre-doped second gate layer 122 includes an in-situ doping process. The second gate layer 122 covers the top surface of the isolation structure 103 and the surface of the second gate oxide layer 132. The in-situ doping process is to dope impurity particles into the gate material while depositing the gate material, so as to directly form a gate layer doped with impurity particles.

[0052] In some embodiments of the present application, the material of the second gate layer 122 includes polysilicon.

[0053] In some embodiments of the present application, the doping types of the second gate layer 122 and the second well region 112 are opposite. When the second well region 112 is a P-type well region, the second gate layer 122 is N-type doped; when the second well region 112 is an N-type well region, the second gate layer 122 is P-type doped.

[0054] In some embodiments of the present application, the doping concentration of the second gate layer 122 is 1×10 19 -1×10 21 atom / cm 3 , in order to ensure that a PN junction will not be formed in the second gate layer 122 when forming the source and drain subsequently, so the doping concentration of the second gate layer 122 should be greater than the doping concentrations of the source and drain (usually 2-3 times).

[0055] In some embodiments of the present application, the doping particles of the second gate layer 122 include phosphorus, boron, arsenic, indium, antimony, etc. Specifically, it can be selected according to the required particle type (P-type or N-type).

[0056] Refer to Figure 7 as shown, remove the second gate oxide layer 132 and the pre-doped second gate layer 122 that are higher than the pre-doped first gate layer 121. The method of removing the second gate oxide layer 132 and the second gate layer 122 is, for example, a chemical mechanical polishing process.

[0057] Refer to Figure 8 as shown, remove the first gate oxide layer 131 and the pre-doped first gate layer 121, the second gate oxide layer 132 and the pre-doped second gate layer 122 that are not above the channel. The method of removing the first gate oxide layer 131 and the pre-doped first gate layer 121, the second gate oxide layer 132 and the pre-doped second gate layer 122 that are not above the channel is, for example, wet etching or dry etching, etc.

[0058] In a conventional process, the method of forming a polysilicon gate layer doped with impurity particles is usually as follows: First, a polysilicon gate layer is deposited using a chemical vapor deposition process or a physical vapor deposition process; then, impurity particles are implanted into the polysilicon gate layer using an ion implantation process. However, since the impurity particle concentration requirement for the polysilicon gate layer is relatively high, the corresponding implantation dose required for doping is also high, and high-dose implantation easily damages the polysilicon, resulting in a polycrystalline penetration effect, where impurity ions enter the channel and affect device performance. To solve the above problems, in the method for forming the semiconductor structure described in the present application, the first gate layer 121 and the second gate layer 122 are formed by an in-situ doping process, avoiding high-dose ion implantation, so that the polysilicon material is not damaged and device performance is not affected. In addition, in the method for forming the semiconductor structure described in the present application, no unconventional additional process steps are introduced, so it can be compatible with a conventional CMOS process.

[0059] In some embodiments of the present application, the method for forming the semiconductor structure further includes: Referring to Figure 9 and Figure 10 , lightly doped source and lightly doped drain are formed in the semiconductor substrate on both sides of the first gate layer and the second gate layer respectively; referring to Figure 11 , sidewalls are formed on both sides of the first gate layer and the second gate layer respectively; referring to Figure 12 , heavily doped source and heavily doped drain are formed in the semiconductor substrate on both sides of the first gate layer and the second gate layer respectively.

[0060] Referring to Figure 9 , a first mask layer 141 is formed on the semiconductor substrate 100, and the first mask layer 141 covers the semiconductor substrate near the isolation structure 103 and part of the first gate layer 121 and the second gate layer 122; a first ion implantation process is used to form a lightly doped source 151 in the exposed semiconductor substrate of the first region 101 and a lightly doped drain 152 in the exposed semiconductor substrate of the second region 102.

[0061] In some embodiments of the present application, the doping type of the lightly doped source 151 in the first region 101 is the same as the doping type of the first well region 111.

[0062] In some embodiments of the present application, the doping type of the lightly doped drain 152 in the second region 102 is opposite to the doping type of the second well region 112.

[0063] Referring to Figure 10, remove the first mask layer 141, and form a second mask layer 142 on the semiconductor substrate 100. The second mask layer 142 covers the edge portion of the semiconductor substrate and a portion of the first gate layer 121 and the second gate layer 122 near the edge; use a first ion implantation process to form a lightly doped drain 161 in the semiconductor substrate of the exposed first region 101, and form a lightly doped source 162 in the semiconductor substrate of the exposed second region 102.

[0064] In some embodiments of the present application, the doping type of the lightly doped drain 161 in the first region 101 is opposite to the doping type of the first well region 111.

[0065] In some embodiments of the present application, the doping type of the lightly doped source 162 in the second region 102 is the same as the doping type of the second well region 112.

[0066] Reference Figure 11 , remove the second mask layer 142, and form sidewalls 170 on both sides of the first gate oxide layer 131 and the first gate layer 121, and the second gate oxide layer 132 and the second gate layer 122 respectively.

[0067] In some embodiments of the present application, the material of the sidewall 170 includes silicon nitride or silicon oxynitride, etc. The method of forming the sidewall 170 includes chemical vapor deposition process and etching process.

[0068] Reference Figure 12 As shown, form a heavily doped source 181 and a heavily doped drain 191 in the semiconductor substrate 100 on both sides of the first gate layer 121 respectively; form a heavily doped source 182 and a heavily doped drain 192 in the semiconductor substrate 100 on both sides of the second gate layer 122 respectively. The method of forming the heavily doped source 181 and the heavily doped drain 191, and the heavily doped source 182 and the heavily doped drain 192 is the same as the method of forming the lightly doped source and the lightly doped drain shown in Figure 9 and Figure 10 , and will not be described herein again.

[0069] In some embodiments of the present application, the doping types of the lightly doped source and the lightly doped drain in the same region are opposite, and the doping types of the heavily doped source and the heavily doped drain in the same region are opposite.

[0070] In some embodiments of the present application, the doping depth and doping concentration of the heavily doped source in the same region are both higher than the doping depth and doping concentration of the lightly doped source; the doping depth and doping concentration of the heavily doped drain in the same region are also both higher than the doping depth and doping concentration of the lightly doped drain.

[0071] The method for forming the semiconductor structure according to the embodiment of the present application further includes: forming an interlayer dielectric layer on the semiconductor substrate to cover the semiconductor substrate, the first gate layer, and the second gate layer; forming a contact structure in the interlayer dielectric layer that penetrates the interlayer dielectric layer and electrically connects the first gate layer and the second gate layer. The methods for forming the interlayer dielectric layer and the contact structure are similar to conventional processes and will not be elaborated here.

[0072] The method for forming the semiconductor structure according to the present application uses an in-situ doping process to form a pre-doped gate layer, which can avoid the polycrystalline penetration effect caused by a large number of particle injections into the gate layer and prevent impurity particles from entering the channel and affecting device performance.

[0073] An embodiment of the present application further provides a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate including a first region and a second region and an isolation structure isolating the first region and the second region, a first well region and a second well region are respectively formed in the semiconductor substrates of the first region and the second region; a pre-doped first gate layer and a second gate layer, respectively located on the semiconductor substrates of the first region and the second region; lightly doped source and lightly doped drain, respectively located in the semiconductor substrates on both sides of the first gate layer and the second gate layer; sidewalls, located on both sides of the first gate layer and the second gate layer; heavily doped source and heavily doped drain, respectively located in the semiconductor substrates on both sides of the first gate layer and the second gate layer; an interlayer dielectric layer, located on the semiconductor substrate to cover the semiconductor substrate, the first gate layer, and the second gate layer; a contact structure, penetrating the interlayer dielectric layer and electrically connecting the first gate layer and the second gate layer.

[0074] Reference Figure 12 As shown, the semiconductor substrate 100 includes a first region 101 and a second region 102 and an isolation structure 103 isolating the first region 101 and the second region 102, and a first well region 111 and a second well region 112 are respectively formed in the semiconductor substrates of the first region 101 and the second region 102.

[0075] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide, etc.; or (iv) a combination of the above.

[0076] In some embodiments of the present application, the material of the isolation structure 103 includes silicon oxide, silicon nitride, or silicon oxynitride, etc. The isolation structure 103 is used to isolate active devices in the semiconductor substrates of the first region 101 and the second region 102.

[0077] In some embodiments of the present application, the first well region 111 and the second well region 112 are formed by doping the semiconductor substrate in the first region 101 and the second region 102.

[0078] In some embodiments of the present application, the first well region 111 may be a P-type well region doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium), or an N-type well region doped with an N-type dopant (e.g., phosphorus or arsenic); the second well region 112 may be a P-type well region doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium), or an N-type well region doped with an N-type dopant (e.g., phosphorus or arsenic). In some embodiments of the present application, the doping types of the first well region 111 and the second well region 112 are different.

[0079] Continuing to refer to Figure 12 As shown, a first gate oxide layer 131 and a pre-doped first gate layer 121, as well as a second gate oxide layer 132 and a pre-doped second gate layer 122, are respectively formed on the semiconductor substrates of the first region and the second region.

[0080] In some embodiments of the present application, the material of the first gate oxide layer 131 includes silicon oxide.

[0081] In some embodiments of the present application, the material of the first gate layer 121 includes polysilicon.

[0082] In some embodiments of the present application, the doping type of the first gate layer 121 is opposite to that of the first well region 111. When the first well region 111 is a P-type well region, the first gate layer 121 is N-type doped; when the first well region 111 is an N-type well region, the first gate layer 121 is P-type doped.

[0083] In some embodiments of the present application, the doping concentration of the first gate layer 121 is 1×10 19 -1×10 21 atom / cm 3 , in order to ensure that a PN junction is not formed in the first gate layer 121 when forming the source and drain subsequently, the doping concentration of the first gate layer 121 should be greater than the doping concentrations of the source and drain (usually 2 - 3 times).

[0084] In some embodiments of the present application, the doping particles of the first gate layer 121 include phosphorus, boron, arsenic, indium, antimony, etc. Specifically, it can be selected according to the required particle type (P-type or N-type).

[0085] In some embodiments of the present application, the material of the second gate oxide layer 132 includes silicon oxide.

[0086] In some embodiments of the present application, the material of the second gate layer 122 includes polysilicon.

[0087] In some embodiments of the present application, the doping types of the second gate layer 122 and the second well region 112 are opposite. When the second well region 112 is a P-type well region, the second gate layer 122 is N-type doped; when the second well region 112 is an N-type well region, the second gate layer 122 is P-type doped.

[0088] In some embodiments of the present application, the doping concentration of the second gate layer 122 is 1×10 19 -1×10 21 atom / cm 3 . In order to ensure that a PN junction is not formed in the second gate layer 122 when forming the source and drain subsequently, the doping concentration of the second gate layer 122 should be greater than the doping concentrations of the source and drain (usually 2-3 times).

[0089] In some embodiments of the present application, the doping particles of the second gate layer 122 include phosphorus, boron, arsenic, indium, antimony, etc. Specifically, it can be selected according to the required particle type (P-type or N-type).

[0090] In the semiconductor structure described in the present application, the first gate layer 121 and the second gate layer 122 are pre-doped, avoiding high-dose ion implantation. Therefore, the polysilicon material is not damaged and the device performance is not affected.

[0091] Continuing to refer to Figure 12 as shown, lightly doped source 151 and lightly doped drain 161 are formed in the semiconductor substrate 100 on both sides of the first gate layer 121; lightly doped source 152 and lightly doped drain 162 are formed in the semiconductor substrate 100 on both sides of the second gate layer 122.

[0092] In some embodiments of the present application, the doping type of the lightly doped source 151 in the first region 101 is the same as the doping type of the first well region 111.

[0093] In some embodiments of the present application, the doping type of the lightly doped drain 152 in the second region 102 is opposite to the doping type of the second well region 112.

[0094] In some embodiments of the present application, the doping type of the lightly doped drain 161 in the first region 101 is opposite to the doping type of the first well region 111.

[0095] In some embodiments of the present application, the doping type of the lightly doped source 162 in the second region 102 is the same as the doping type of the second well region 112.

[0096] Continue to refer to Figure 12 On both sides of the first gate layer 121 and the second gate layer 122, sidewalls 170 are formed.

[0097] In some embodiments of the present application, the material of the sidewall 170 includes silicon nitride, silicon oxynitride, etc.

[0098] Continue to refer to Figure 12 As shown, heavily doped source electrodes 181 and heavily doped drain electrodes 191 are further formed in the semiconductor substrate 100 on both sides of the first gate layer 121; heavily doped source electrodes 182 and heavily doped drain electrodes 192 are further formed in the semiconductor substrate 100 on both sides of the second gate layer 122.

[0099] In some embodiments of the present application, the doping types of the lightly doped source electrode and the lightly doped drain electrode in the same region are opposite, and the doping types of the heavily doped source electrode and the heavily doped drain electrode in the same region are opposite.

[0100] In some embodiments of the present application, the doping depth and doping concentration of the heavily doped source electrode in the same region are both higher than those of the lightly doped source electrode; the doping depth and doping concentration of the heavily doped drain electrode in the same region are also both higher than those of the lightly doped drain electrode.

[0101] The semiconductor structure described in the embodiments of the present application further includes: an interlayer dielectric layer (not shown in the figure) located on the semiconductor substrate and covering the semiconductor substrate, the first gate layer, and the second gate layer; a contact structure (not shown in the figure) penetrating the interlayer dielectric layer and electrically connecting the first gate layer and the second gate layer.

[0102] For the semiconductor structure described in the present application, an in-situ doping process is used to form a pre-doped gate layer, which can avoid the polycrystalline penetration effect caused by a large number of particle injections into the gate layer, and impurity particles entering the channel and affecting the device performance.

[0103] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of the present application.

[0104] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be intermediate elements.

[0105] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be intermediate elements. In contrast, the term "directly" means without intermediate elements. It should also be understood that the terms "comprise", "comprising", "include" or "including", when used in this application document, specify the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0106] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.

[0107] In addition, the present application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or three-dimensional views. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Thus, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but should include deviations in the shapes caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a semiconductor substrate, the semiconductor substrate including a first region and a second region and an isolation structure isolating the first region and the second region, a first well region and a second well region being respectively formed in the semiconductor substrate of the first region and the second region; Respectively forming a pre-doped first gate layer and a second gate layer on the semiconductor substrate of the first region and the second region; Respectively forming lightly doped source and lightly doped drain in the semiconductor substrate on both sides of the first gate layer and the second gate layer; Respectively forming sidewalls on both sides of the first gate layer and the second gate layer; Respectively forming heavily doped source and heavily doped drain in the semiconductor substrate on both sides of the first gate layer and the second gate layer; Forming an interlayer dielectric layer on the semiconductor substrate to cover the semiconductor substrate, the first gate layer and the second gate layer; Forming a contact structure in the interlayer dielectric layer that penetrates the interlayer dielectric layer and electrically connects the first gate layer and the second gate layer.

2. The method for forming a semiconductor structure as described in claim 1, wherein, The method of respectively forming a pre-doped first gate layer and a second gate layer on the semiconductor substrate of the first region and the second region includes: Sequentially forming a first gate oxide layer and a pre-doped first gate layer on the semiconductor substrate; Removing the first gate oxide layer and the pre-doped first gate layer located on the second region; Sequentially forming a second gate oxide layer and a pre-doped second gate layer on the second region and on the pre-doped first gate layer; Removing the second gate oxide layer and the pre-doped second gate layer higher than the pre-doped first gate layer; Removing the first gate oxide layer and the pre-doped first gate layer and the second gate oxide layer and the pre-doped second gate layer that are not above the channel.

3. The method for forming the semiconductor structure as described in claim 2, wherein The method of removing the first gate oxide layer and the pre-doped first gate layer located on the second region includes: Forming a photoresist layer on the surface of the first gate layer on the first region; Etching to remove the first gate oxide layer and the first gate layer located on the second region; Removing the photoresist layer.

4. The method for forming a semiconductor structure according to claim 2, wherein, The method of forming the first gate oxide layer includes a thermal oxidation process, and the method of forming the pre-doped first gate layer includes an in-situ doping process.

5. The method for forming a semiconductor structure according to claim 2, wherein The method of forming the second gate oxide layer includes a thermal oxidation process, and the method of forming the pre-doped second gate layer includes an in-situ doping process.

6. The method for forming a semiconductor structure as claimed in claim 1, wherein, The doping types of the first gate layer and the first well region are opposite, and the doping types of the second gate layer and the second well region are opposite.

7. The method for forming a semiconductor structure as claimed in claim 1, wherein The doping concentration of the first gate layer is 1×10 19 -1×10 21 atom / cm 3 , and the doping concentration of the second gate layer is 1×10 19 -1×10 21 atom / cm 3 .

8. The method for forming a semiconductor structure as described in claim 1, wherein, The doping particles of the first gate layer include phosphorus, boron, arsenic, indium, antimony, and the doping particles of the second gate layer include phosphorus, boron, arsenic, indium, antimony.

9. The method for forming a semiconductor structure as claimed in claim 1, wherein The doping types of the lightly doped source and the lightly doped drain are opposite, and the doping types of the heavily doped source and the heavily doped drain are opposite.

10. A semiconductor structure, characterized in that, Formed by using any one of claims 1 to 9, including: A semiconductor substrate, the semiconductor substrate including a first region and a second region and an isolation structure isolating the first region and the second region, a first well region and a second well region being respectively formed in the semiconductor substrate of the first region and the second region; A pre-doped first gate layer and a second gate layer, respectively located on a semiconductor substrate in the first region and the second region; Lightly doped source and lightly doped drain, respectively located in the semiconductor substrate on both sides of the first gate layer and the second gate layer; Sidewalls, located on both sides of the first gate layer and the second gate layer; Heavily doped source and heavily doped drain, respectively located in the semiconductor substrate on both sides of the first gate layer and the second gate layer; An interlayer dielectric layer, located on the semiconductor substrate to cover the semiconductor substrate, the first gate layer and the second gate layer; A contact structure, penetrating through the interlayer dielectric layer and electrically connecting the first gate layer and the second gate layer.

11. The semiconductor structure according to claim 10, wherein, The doping types of the first gate layer and the first well region are opposite, and the doping types of the second gate layer and the second well region are opposite.

12. The semiconductor structure according to claim 10, wherein, The doping concentration of the first gate layer is 1×10 19 -1×10 21 atom / cm 3 , and the doping concentration of the second gate layer is 1×10 19 -1×10 21 atom / cm 3 .

13. The semiconductor structure according to claim 10, wherein The doping particles of the first gate layer include phosphorus, boron, arsenic, indium, antimony, and the doping particles of the second gate layer include phosphorus, boron, arsenic, indium, antimony.

14. The semiconductor structure according to claim 10, wherein The doping types of the lightly doped source and the lightly doped drain are opposite, and the doping types of the heavily doped source and the heavily doped drain are opposite.

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