Three-dimensional memory device including horizontal and vertical wordline interconnects and method of forming the same

Abstract

The present invention discloses a method for forming a three-dimensional memory device, the method comprising forming a vertically alternating sequence of insulating layers and spacer material layers above a substrate, such that the spacer material layer is formed as a conductive layer or is subsequently replaced with a conductive layer; iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first portion of a mesa region including a set of stepped surfaces extending in a first horizontal direction; and performing a second set of offset layer patterning processing steps to form a second portion of the mesa region and form a stepped vertical cross-sectional profile of the patterned surfaces of the vertically alternating sequence along a second horizontal direction perpendicular to the first horizontal direction.

Description

[0001] Related applications

[0002] This patent application claims the benefit of priority to U.S. non-provisional patent application serial number 16 / 782,307, filed on February 5, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular, to a three-dimensional memory device having horizontal wordline interconnects and vertical wordline interconnects and a method of forming the same. Background Art

[0004] A three-dimensional semiconductor device including three-dimensional vertical NAND strings with one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell," IEDM Proc. (2001) 33-36. Summary of the Invention

[0005] According to an embodiment of the present disclosure, a method for forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers above a substrate, such that the spacer material layers are formed as conductive layers or are subsequently replaced with conductive layers; iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first portion of a mesa region including a set of stepped surfaces extending in a first horizontal direction; and performing a second set of offset layer patterning processing steps to form a second portion of the mesa region and form a stepped vertical cross-sectional profile of the patterned surfaces of the vertically alternating sequence along a second horizontal direction perpendicular to the first horizontal direction.

[0006] According to another aspect of the present disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulating layers and conductive layers, the alternating stack positioned above a substrate; and memory stack structures extending through a memory array region of the alternating stack, wherein all layers of the alternating stack are present, wherein the alternating stack comprises: a first memory array region comprising a first subset of the memory stack structures; a second memory array region comprising a second subset of the memory stack structures and being laterally spaced apart from the first memory array region along a first horizontal direction; and a mesa region, The mesa region includes a set of stepped surfaces positioned between the first memory array region and the second memory array region, and wherein: the alternatingly stacked sidewalls have a stepped vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction; and the stepped vertical cross-sectional profile includes: upper tapered sidewall surfaces of an upper subset of the alternatingly stacked layers; lower tapered sidewall surfaces of a lower subset of the layers in the vertically alternating sequence, the lower tapered sidewall surfaces being below the upper subset of the layers in the vertically alternating sequence; and a horizontal top surface of one of the layers in the vertically alternating sequence, the horizontal top surface being adjacent to a bottom edge of the upper tapered sidewall surface and a top edge of the lower tapered sidewall surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a plan view of a semiconductor die including multiple three-dimensional memory array regions according to embodiments of the present disclosure.

[0008] Figure 1B yes Figure 1A Magnified view of area M1.

[0009] Figure 1C yes Figure 1B Magnified view of region M2.

[0010] Figure 1D It is along Figure 1C A schematic vertical cross-sectional view of an exemplary structure of a portion of region M2 taken along a vertical plane DD'.

[0011] Figure 1E It is along Figure 1C A schematic vertical cross-sectional view of an exemplary structure of region M2 taken along a vertical plane EE'.

[0012] Figure 1F is included Figure 1A A perspective view of a portion of an exemplary structure of two adjacent pairs of mesa regions in a semiconductor die.

[0013] Figure 1G It is along Figure 1C A schematic vertical sectional view of a first alternative configuration of the exemplary structure taken along a vertical plane DD'.

[0014] Figure 1H It is along Figure 1C A schematic vertical sectional view of a first alternative configuration of the exemplary structure taken along a vertical plane EE'.

[0015] Figure 1I It is along Figure 1C A schematic vertical sectional view of a second alternative configuration of the exemplary structure taken along a vertical plane DD'.

[0016] Figure 1J It is along Figure 1C A schematic vertical sectional view of a second alternative configuration of the exemplary structure taken along a vertical plane EE'.

[0017] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a first vertical alternating sequence of semiconductor devices, lower level dielectric layers, lower metal interconnect structures, semiconductor material layers, and first insulating layers and first spacer material layers according to an embodiment of the present disclosure.

[0018] Figure 3 is a vertical cross-sectional view of a first configuration of an exemplary structure after forming a stepped surface in the mesa region according to an embodiment of the present disclosure.

[0019] Figures 4A to 4E is a top view of patterned photoresist material layers that can be used to form Figure 2 The positions of the line trenches to be formed subsequently are juxtaposed on a top view of the patterned photoresist material layer.

[0020] Figures 5A to 5E is a vertical cross-sectional view along a first horizontal direction of a second configuration of an exemplary structure during formation of a stepped surface in a mesa region according to an embodiment of the present disclosure. A patterned photoresist material layer is schematically shown.

[0021] Figures 6A to 6E is along the line corresponding to Figure 1C The vertical plane of the plane D-D' is Figures 5A to 5E A vertical cross-sectional view along a second horizontal direction of a second configuration of the exemplary structure during a processing step of .

[0022] Figure 7A is a vertical cross-sectional view of a mesa region of a second configuration of the exemplary structure after forming a stepped surface and a portion of a first dielectric material overlying the stepped surface.

[0023] Figure 7BAfter forming the stepped surface and the first dielectric material portion covering the stepped surface Figure 7A A vertical cross-sectional view of the array interconnect region of the second configuration of the exemplary structure.

[0024] Figure 7C It will Figure 7A and Figure 7B A vertical partial perspective view of a second configuration of the exemplary structure of the combined view.

[0025] Figure 7D yes 7A to 7C A top view of a second configuration of an exemplary structure of FIG. The vertical plane AA' corresponds to Figure 7A The vertical plane BB' corresponds to Figure 7B The view in .

[0026] Figure 8A is a plan view of a pattern of a first trimmable masking material layer used to form a first subset of stepped surfaces for a second configuration of exemplary structures according to an embodiment of the present disclosure.

[0027] Figure 8B is a plan view of a pattern of a second trimmable masking material layer used to form a second subset of stepped surfaces for a second configuration of exemplary structures according to an embodiment of the present disclosure.

[0028] Figure 9 is a vertical cross-sectional view of an exemplary structure after forming a first level opening-filling structure according to an embodiment of the present disclosure.

[0029] Figure 10 is a vertical cross-sectional view of the exemplary structure after forming a second vertical alternating sequence of second insulating layers and second spacer material layers according to an embodiment of the present disclosure.

[0030] Figure 11A is a vertical cross-sectional view of a first configuration of an exemplary structure along a vertical plane including mesa regions after forming an additional stepped surface on the second vertical alternating sequence and the second dielectric material portion according to an embodiment of the present disclosure.

[0031] Figure 11B is Figure 11A A vertical cross-sectional view of a first configuration of an exemplary structure along a vertical plane including the array connection area at a processing step of .

[0032] Figure 12A is a vertical cross-sectional view of a second configuration of the exemplary structure along a vertical plane including mesa regions after forming additional stepped surfaces on the second vertical alternating sequence and second dielectric material portions according to an embodiment of the present disclosure.

[0033] Figure 12Bis Figure 12A A vertical cross-sectional view of a second configuration of the exemplary structure along a vertical plane including the array connection area at a processing step of .

[0034] Figure 13 is a vertical cross-sectional view of an exemplary structure after forming a second layer of openings through a second vertical alternating sequence according to an embodiment of the present disclosure.

[0035] 14A to 14D Sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure according to an embodiment of the present disclosure are shown.

[0036] Figure 15 is a vertical cross-sectional view of an exemplary structure after forming a memory opening filling structure and a support pillar structure according to an embodiment of the present disclosure.

[0037] Figure 16 is a vertical cross-sectional view of an exemplary structure after forming a contact-level dielectric layer according to an embodiment of the present disclosure.

[0038] Figure 17 is a vertical cross-sectional view of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0039] Figure 18 is a vertical cross-sectional view of an exemplary structure after forming various contact via structures according to an embodiment of the present disclosure.

[0040] Figure 19 is a vertical cross-sectional view of a second configuration of the exemplary structure after forming contact via structures and metal interconnect structures providing interconnection between the first memory array region and the second memory array region according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] As discussed above, embodiments of the present disclosure relate to a three-dimensional memory device including both horizontal word line interconnects and vertical word line interconnects and a method of forming the same without requiring a hard mask.

[0042] The drawings are not drawn to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that there is no repetition of the element. Sequence numbers such as "first," "second," and "third" are used only to identify similar elements, and different sequence numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0043] The same reference numerals represent the same or similar elements. Unless otherwise indicated, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise indicated, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, a first element is "directly" positioned on a second element if there is physical contact between the surface of the first element and the surface of the second element.

[0044] As used herein, a first element is "electrically connected to" a second element if an electrically conductive path comprised of at least one electrically conductive material exists between the first element and the second element. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure that is subsequently modified in shape or composition of at least one component thereof.

[0045] As used herein, a "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. Additionally, a layer may be an area of ​​a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of a first continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0046] As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from vertical by an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or the substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0047] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the memory element array and a second horizontal plane including the bottommost surface of the memory element array. As used herein, a "through-stack" element refers to an element that extends vertically through a memory level.

[0048] As used herein, "semiconductor material" refers to a material having a -5 S / m to 1.0×10 5 As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, a "heavily doped semiconductor material" refers to a material that is doped with electrical dopants at a sufficiently high atomic concentration to become conductive (i.e., provide a conductivity greater than 1.0×10 5 S / m) of semiconductor material. "Doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0 to 10 -5 S / m to 1.0×10 7 S / m) in the range of 100 Å / s. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. Doped semiconductor materials can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0049] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate can be thinned or removed from the memory levels before bonding, but because the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. The substrate may include integrated circuits manufactured thereon, such as driver circuits for the memory device.

[0050] Various three-dimensional memory devices disclosed herein include single-unit three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein. A single-unit three-dimensional NAND string is positioned in a single-unit three-dimensional NAND string array located above a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

[0051] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded through, for example, by flip-chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes.

[0052] The same concurrent operations can be performed in each plane within the same die, but some limitations may apply. In the case where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0053] See also Figures 1A to 1J, a semiconductor die 1000 including multiple three-dimensional memory array regions and mesa regions is shown in various views. The semiconductor die 1000 may include multiple planes, each plane including two memory array regions 100 separated by corresponding inter-array regions 200, such as a first memory array region and a second memory array region (100A, 100B). Generally speaking, the semiconductor die 1000 may include a single plane or multiple planes. The total number of planes in the semiconductor die 1000 may be selected based on the performance requirements of the semiconductor die 1000. A pair of memory array regions 100 within a plane may be laterally spaced apart along a first horizontal direction (e.g., a word line direction) hd1. The second horizontal direction (e.g., a bit line direction) hd2 may be perpendicular to the first horizontal direction hd1.

[0054] Each memory array region 100 includes at least one vertical alternating sequence of insulating layers and conductive layers (e.g., word lines). Each vertical alternating sequence of insulating layers and conductive layers is referred to herein as an alternating stack. When multiple alternating stacks are stacked vertically, the bottommost alternating stack is referred to herein as a first alternating stack, the alternating stack directly overlying the first alternating stack is referred to herein as a second vertical alternating sequence, and so on. The first alternating stack may include a first insulating layer 132 and a first conductive layer 146, the second vertical alternating sequence may include a second insulating layer 232 and a second conductive layer 246, and so on. When multiple alternating stacks are stacked vertically, memory openings extending through the respective alternating stacks may be vertically stacked with overlapping regions to form inter-layer memory openings. Each inter-layer memory opening may extend vertically through the multiple alternating stacks. A memory opening filling structure may be formed in each inter-layer memory opening. Each memory opening filling structure includes a vertical semiconductor channel and a memory film. The memory film may include a layer stack comprising a tunneling dielectric layer, a charge storage layer (such as a silicon nitride layer), and an optional blocking dielectric layer. Each contiguous combination of a vertical semiconductor channel and a memory film constitutes a memory stack structure.

[0055] The alternating stacks of insulating layers (132, 232) and conductive layers (146, 246) can be formed by providing an in-process alternating stack of a continuous insulating layer and a continuous sacrificial material layer (which may include silicon nitride or a semiconductor material that is selectively removable with respect to the material of the continuous insulating layer) extending over all areas of the memory array region 100 and the inter-array region 200; dividing the in-process alternating stack into a plurality of alternating stacks of insulating layers (132, 232) and sacrificial material layers that are laterally separated by linear grooves extending laterally along a first horizontal direction hd1 and laterally separated from each other along a second horizontal direction hd2; and replacing the remaining portion of the sacrificial material layer with a conductive layer (146, 246) through the linear grooves.

[0056] like Figures 1D to 1F As shown, the line trenches may be filled with a dielectric material such as silicon oxide to form dielectric wall structures 76. Each dielectric wall structure 76 may be positioned between corresponding laterally adjacent groups of alternating stacks of insulating layers (132, 232) and conductive layers (146, 246). Each dielectric wall structure 76 may extend vertically from a semiconductor material layer 110 overlying an underlying material layer (such as a lower level dielectric material layer 760) to the topmost surface of the alternating stacks (132, 146, 232, 246). Each dielectric wall structure 76 may extend laterally through the entire length of the inter-array region 200 and through the entire length of each of the two memory array regions 100 adjacent to the inter-array region 200. Each dielectric wall structure 76 may have a corresponding uniform width along the second horizontal direction hd2. In one embodiment, an optional source local interconnect (e.g., a source electrode) may extend through the corresponding dielectric wall structure 76 to a source region positioned in the semiconductor material layer 110. For clarity, the dielectric wall structures 76 are not shown in FIG. Figure 1F All dielectric wall structures 76 are shown in FIG.

[0057] like Figure 1B 、 Figure 1C and Figure 1F As shown, each portion of the inter-array region 200 positioned between adjacent pairs of dielectric wall structures 76 may include a mesa region 210 and an array interconnect region (e.g., a "bridge" region) 220 or a vertical interconnect via region 240 when viewed in the second horizontal direction hd2. When viewed in the first horizontal direction hd1, the ends of the vertical interconnect via region 240 may be adjacent to corresponding ends of a pair of mesa regions 210 and array interconnect regions 220, as shown in FIG. Figure 1C Each mesa region 210 includes a stepped surface including vertical steps S that are laterally spaced apart from each other along a first horizontal direction hd1. The stepped surface may have different configurations depending on various embodiments of the present disclosure as will be described in further detail below.

[0058] The alternatingly stacked conductive layers (146, 246) are disconnected along a first horizontal direction hd1 in the mesa regions 210 in the inter-array region 200 positioned between adjacent pairs of memory array regions 100 to provide a stepped surface (i.e., a step "S") within each mesa region 210. However, a lower subset of the alternatingly stacked lower conductive layers (146, 246) continuously extends along the first horizontal direction hd1 between adjacent pairs of memory array regions 100 in the inter-array region 200 through each array interconnect region 220 between the mesa regions 210 and the dielectric wall structures 76. The first portion of the lower conductive layer within each array interconnect region 220 provides electrical connection between second portions of the lower conductive layer, which are positioned in two memory array regions 100 laterally separated by the inter-array region 200 and between corresponding adjacent pairs of dielectric wall structures 76. Thus, the alternating stack of lower conductive layers (146, 246) is electrically connected along the first horizontal direction hd1 between adjacent pairs of memory array regions 100 across the array interconnect region (e.g., the "bridge" region) 220. In contrast, the upper subset comprising the alternating stack of one or more upper conductive layers (146, 246) is not electrically connected along the first horizontal direction hd1 between adjacent pairs of memory array regions 100 in the array interconnect region (e.g., the "bridge" region) 220, as will be described in more detail below.

[0059] like Figure 1D As shown, at least one dielectric material portion (such as the first backward stepped dielectric material portion 165 and / or the second backward stepped dielectric material portion 265) may be formed in each mesa region 210. As used herein, a "backward stepped" element refers to an element having a stepped surface at its bottom portion. A layer contact via structure (e.g., a word line contact via structure) 86 may be formed through the dielectric material portion (such as the first backward stepped dielectric material portion 165 and / or the second backward stepped dielectric material portion 265) to provide electrical contact to a corresponding conductive layer (e.g., a word line) (146, 246). Each layer contact via structure 86 contacts a set of stepped surfaces of the alternating stacks (132, 146, 232, 246) disposed in the mesa region 210. Figure 1C 、 Figure 1D and Figure 1F The horizontal surface shown (ie, step "S").

[0060] like Figure 1D As shown, due to the inherent taper of the etching process, the inner surfaces 247 of the alternating stacks (132, 146, 232, 246) in the array interconnect region 220 can be tapered. Each inner surface 247 can contact a corresponding dielectric material portion (165, 265). The inner surfaces 247 can have an average taper angle (as measured from the vertical) of less than 45 degrees. The taper angle can be in the range of 10 degrees to 40 degrees (such as 15 degrees to 30 degrees).

[0061] The vertical interconnect via region 240 may include all layers within the alternating stacks positioned between corresponding adjacent pairs of dielectric wall structures 76 and may extend laterally between adjacent pairs of dielectric wall structures 76 along a second horizontal direction hd2. Laterally isolated vertical interconnect structures (484, 486) may be formed through the alternating stacks (132, 146, 232, 246) in the vertical interconnect via region 240. Each laterally isolated vertical interconnect structure (484, 486) may include a through-memory level conductive via structure 486 and a tubular insulating spacer 484 that laterally surrounds the conductive via structure 486. Each through-memory level conductive via structure 486 may contact a lower level metal interconnect structure 780 positioned in the lower level dielectric material layer 760, as shown. Figure 1E shown.

[0062] like Figure 1B and Figure 1C As shown, a pair of mesa regions 210 may abut dielectric wall structures 76 and may have the same lateral extent along a first horizontal direction hd1. Multiple pairs of mesa regions 210 may be arranged along a second horizontal direction hd2. Each alternating stack positioned between adjacent pairs of dielectric wall structures 76 includes a corresponding mesa region 210. Pairs of mesa regions 210 may be laterally staggered along the first horizontal direction hd1 at a different offset than each other pair of mesa regions 210 arranged along the second horizontal direction 210. For example, each odd-numbered pair of mesa regions 210 may be closer to the first memory array region 100 adjacent to the first end (e.g., the left end) of the inter-array region 200, and each even-numbered pair of mesa regions 210 may be closer to the second memory array region 100 adjacent to the second end (e.g., the right end) of the inter-array region 200. The lateral offset of the mesa region 210 along the first horizontal direction hd1 can be selected so that the central portion 200C of the inter-array region 200 includes an area that includes only the vertical interconnect via regions 240 between each adjacent pair of dielectric wall structures 76, as shown in FIG. Figure 1C The central portion 200C of the inter-array region 200 may be equidistant from each of the memory array regions in the memory array region 100 .

[0063] See also Figure 1C 、 Figure 1G and Figure 1H, showing a first alternative configuration of an exemplary structure. The first alternative configuration of the exemplary structure includes a patterned edge of a first alternating stack (132, 146) of a first insulating layer 132 and a first conductive layer 146 extending laterally along a first horizontal direction hd1. The first alternating stack (132, 146) can be formed by: alternating the stack during a first patterning process of forming the first insulating layer 132 and the first sacrificial material layer over the semiconductor material layer 110; forming a first backward stepped dielectric material portion 165 over a patterned surface of the alternating stack during the first patterning process of the first insulating layer 132 and the first sacrificial material layer; forming a backside trench; forming a backside recess by selectively removing the first sacrificial material layer with respect to the first insulating layer 132; and forming the first conductive layer 146 in the volume of the backside recess. The dielectric wall structure 76 can then be formed in the backside trench. Layer contact via structures 86 may then be formed through the first backward stepped dielectric material portion 165 , and laterally isolated vertical interconnect structures ( 484 , 486 ) may then be formed through the alternating stack of first insulating layers 132 and first conductive layers 146 .

[0064] According to one aspect of the present disclosure, the sidewalls of the alternating stack of the first insulating layer 132 and the first sacrificial material layer during the first patterning process, which extend laterally along the first horizontal direction hd1, can be patterned to reduce the total area occupied by the sidewalls. This can reduce the total device area and the spacing between adjacent dielectric wall structures 76 along the second horizontal direction hd2. The lower portion of the alternating stack (132, 146) during the first patterning process includes sidewalls positioned within corresponding tapered planes, and these sidewalls have variable taper angles that gradually increase with vertical distance from the semiconductor material layer 110. The upper portion of the alternating stack during the first patterning process includes sidewalls that are laterally offset from the sidewalls of the lower portion of the alternating stack during the same first patterning process. After replacing the first sacrificial material layer with the first conductive layer, the first alternating stack of the first insulating layer 132 and the first conductive layer 146 is formed. The lower portion of each first alternating stack (132, 146) includes sidewalls positioned within respective tapered planes, the sidewalls having variable tapered angles that gradually increase with vertical distance from the semiconductor material layer 110, and the upper portion of each first alternating stack (132, 146) includes sidewalls that are laterally offset from the sidewalls of the underlying lower portion of the same first alternating stack (132, 146), as Figure 1G shown.

[0065] In an illustrative example, a first contiguous subset S1 of layers, including the bottommost layer of the first alternating stack (132, 146), may include sidewalls having a first average taper angle α1 that extend laterally along a first horizontal direction hd1 and contact the first backward stepped dielectric material portion 165. A second contiguous subset S2 of layers, including the layer in the first alternating stack (132, 146) that contacts the topmost layer of the first contiguous subset S1, may include sidewalls having a second average taper angle α2 that extend laterally along the first horizontal direction hd1 and contact the first backward stepped dielectric material portion 165. The second average taper angle α2 may be greater than the first average taper angle α1. A third contiguous subset S3 of layers, including the layer in the first alternating stack (132, 146) that contacts the topmost layer of the second contiguous subset S2, may include sidewalls having a third average taper angle α3 that extend laterally along the first horizontal direction hd1 and contact the first backward stepped dielectric material portion 165. The third average taper angle α3 may be greater than the second average taper angle α2. A fourth contiguous subset S4 of layers, including a layer in the first alternating stack (132, 146) that contacts the topmost layer of the third contiguous subset S3 and including the topmost layer of the first alternating stack (132, 146), may include sidewalls having a fourth average taper angle α4 that extend laterally along the first horizontal direction hd1 and contact the first rear stepped dielectric material portion 165. The fourth average taper angle α4 may be greater than the second average taper angle α2. The fourth average taper angle α4 may be the same as, greater than, or less than the third average taper angle α3. In one embodiment, the first average taper angle α1 may be in the range of 3 degrees to 10 degrees, the second average taper angle α2 may be in the range of 6 degrees to 15 degrees, and the third average taper angle α3 and the fourth average taper angle α4 may be in the range of 10 degrees to 30 degrees, such as 12 degrees to 20 degrees.

[0066] The bottom edge of the fourth adjacent subset S4 of the layers of the first alternating stack (132, 146) extending laterally along the first horizontal direction hd1 may be laterally offset from the top edge of the third adjacent subset S3 of the layers of the first alternating stack (132, 146) along the second horizontal direction hd2 by a lateral offset distance lod. The total number of layers within the second subset S2 of the layers of the first alternating stack (132, 146) may be greater than the total number of layers within the first subset S1 of the layers of the first alternating stack (132, 146). In one embodiment, the total number of layers within the second subset S2 of the layers of the first alternating stack (132, 146) may be approximately twice the total number of layers within the first subset S1 of the layers of the first alternating stack (132, 146). In an illustrative example, if the total number of layers within the first subset S1 of the layers of the first alternating stack (132, 146) is 2 N , where N is an integer greater than 1 (such as 2 2=4), the total number of layers in the second subset S2 of the first alternating stack (132, 146) may be 2 N+1 (such as 2 2+1 =8). The total number of layers within the third subset S3 of the layers of the first alternating stack (132, 146) may be greater than the total number of layers within the second subset S2 of the layers of the first alternating stack (132, 146). In one embodiment, the total number of layers within the third subset S3 of the layers of the first alternating stack (132, 146) may be approximately twice the total number of layers within the second subset S2 of the layers of the first alternating stack (132, 146). In an illustrative example, if the total number of layers within the second subset S2 of the layers of the first alternating stack (132, 146) is 2 N+1 (such as 2 2+1 =8), the total number of layers in the third subset S3 of the first alternating stack (132, 146) can be 2 N+2 (such as 2 2+2 =16). In one embodiment, the total number of layers in the fourth subset S4 of the layers of the first alternating stack (132, 146) may be approximately the same as the total number of layers in the third subset S3 of the layers of the first alternating stack (132, 146). In the illustrative example, if the total number of layers in the third subset S3 of the layers of the first alternating stack (132, 146) is 2 N+2 (such as 2 2+2 =16), the total number of layers in the fourth subset S4 of the first alternating stack (132, 146) may be 2 N+2 (such as 2 2+2 =16).

[0067] See also Figure 1C11 and 1J illustrate a second alternative configuration of the exemplary structure. The second alternative configuration of the exemplary structure includes patterned edges of a first alternating stack (132, 146) of first insulating layer 132 and first conductive layer 146 extending laterally along a first horizontal direction hd1, and patterned edges of a second alternating stack (232, 246) of second insulating layer 232 and second conductive layer 246 extending laterally along the first horizontal direction hd1. The alternating stack of first insulating layer 132 and first sacrificial material layer can be formed over semiconductor material layer 110 during a first patterning process, and a first rear stepped dielectric material portion 165 can be formed over a patterned surface of the alternating stack of first insulating layer 132 and first sacrificial material layer during the first patterning process. The second insulating layer 232 and the second sacrificial material layer alternately stacked during the second patterning process may be formed over the second insulating layer 132 and the second sacrificial material layer alternately stacked during the first patterning process, and the second backward stepped dielectric material portion 265 may be formed over the patterned surface of the second insulating layer 232 and the second sacrificial material layer alternately stacked during the second patterning process. A backside trench may be formed through the second insulating layer 232 and the second sacrificial material layer alternately stacked during the second patterning process and through the first insulating layer 232 and the first sacrificial material layer alternately stacked during the first patterning process.

[0068] A backside recess can be formed by selectively removing the first sacrificial material layer and the second sacrificial material layer from the first insulating layer 132 and the second insulating layer 232. A first conductive layer 146 is formed within the volume of the backside recess formed by removing the first sacrificial material layer, and a second conductive layer 246 is formed within the volume of the backside recess formed by removing the second sacrificial material layer. A dielectric wall structure 76 can then be formed in the backside trench. A layer contact via structure 86 can then be formed through the second rear stepped dielectric material portion 265 and optionally through the first rear stepped dielectric material portion 165. Laterally isolated vertical interconnect structures (484, 486) can then be formed through the alternating stacks of the second insulating layer 232 and the second conductive layer 246 and through the alternating stacks of the first insulating layer 132 and the first conductive layer 146.

[0069] According to one aspect of the present disclosure, the sidewalls of the alternating stack of the first insulating layer 132 and the first sacrificial material layer, extending laterally along the first horizontal direction hd1, during a first patterning process can be patterned to reduce the total area occupied by the alternating stack of sidewalls during the first patterning process. The lower portion of the alternating stack during the first patterning process includes sidewalls positioned within respective tapered planes, with these sidewalls having a variable taper angle that increases with vertical distance from the semiconductor material layer 110. As in the first alternative embodiment of the exemplary structure, the upper portion of the alternating stack during the first patterning process includes sidewalls that are laterally offset from the sidewalls of the lower portion of the alternating stack during the same first patterning process. Additionally, the sidewalls of the alternating stack of the second insulating layer 232 and the second sacrificial material layer, extending laterally along the first horizontal direction hd1, during a second patterning process can be patterned to reduce the total area occupied by the alternating stack of sidewalls during the first patterning process. The lower portion of the alternating stack during the second patterning process includes sidewalls positioned within respective tapered planes, with these sidewalls having a variable taper angle that increases with vertical distance from the semiconductor material layer 110. The upper portion of the alternating stack of the second patterning process includes sidewalls that are laterally offset from the sidewalls of the underlying lower portion of the alternating stack of the same second patterning process, such as Figure 1G and Figure 1I As shown. The first insulating layer 132 and the first conductive layer 146 are alternately stacked in Figure 1I There are Figure 1G The same configuration as in FIG, as well as the same cone angle and lateral offset distance (lod), are described herein and will not be further described for the sake of brevity.

[0070] After replacing the second sacrificial material layer with the second conductive layer, a second alternating stack of second insulating layers 232 and second conductive layers 246 is formed. The lower portion of each second alternating stack (232, 246) includes sidewalls positioned within a respective tapered plane, the sidewalls having a variable tapered angle that gradually increases with vertical distance from the semiconductor material layer 110. The upper portion of each second alternating stack (232, 246) includes sidewalls that are laterally offset from the sidewalls of the underlying lower portion of the same second alternating stack (232, 246), as shown. Figure 1I shown.

[0071] In an illustrative example, a first contiguous subset T1 of layers, including the bottommost layer of the second alternating stack (232, 246), may include sidewalls having a first average taper angle β1 that extend laterally along a first horizontal direction hd1 and contact the second backward stepped dielectric material portion 265. A second contiguous subset T2 of layers, including the layer in the second alternating stack (232, 246) that contacts the topmost layer of the first contiguous subset T1, may include sidewalls having a second average taper angle β2 that extend laterally along the first horizontal direction hd1 and contact the second backward stepped dielectric material portion 265. The second average taper angle β2 may be greater than the first average taper angle β1. A third contiguous subset T3 of layers, including the layer in the second alternating stack (232, 246) that contacts the topmost layer of the second contiguous subset T2, may include sidewalls having a third average taper angle β3 that extend laterally along the first horizontal direction hd1 and contact the second backward stepped dielectric material portion 265. The third average taper angle b3 may be greater than the second average taper angle β2. A fourth contiguous subset T4 of layers, including a layer in the second alternating stack (232, 246) that contacts the topmost layer of the third contiguous subset T3 and including the topmost layer of the second alternating stack (232, 246), may include sidewalls having a fourth average taper angle β4 that extend laterally along the first horizontal direction hd1 and contact the second rear stepped dielectric material portion 265. The fourth average taper angle β4 may be greater than the second average taper angle β2. The fourth average taper angle β4 may be the same as, greater than, or less than the third average taper angle β3. In one embodiment, the first average taper angle β1 may be in the range of 3 degrees to 10 degrees, the second average taper angle β2 may be in the range of 6 degrees to 15 degrees, and the third average taper angle β3 and the fourth average taper angle β4 may be in the range of 10 degrees to 30 degrees, such as 12 degrees to 20 degrees.

[0072] The bottom edge of the fourth adjacent subset T4 of the layers of the second alternating stack (232, 246) extending laterally along the first horizontal direction hd1 may be laterally offset from the top edge of the third adjacent subset T3 of the layers of the second alternating stack (232, 246) along the second horizontal direction hd2 by a lateral offset distance lod', which may be the same as or different from the lateral offset distance lod of the first alternating stack (132, 146). The total number of layers within the second subset T2 of the layers of the second alternating stack (232, 246) may be greater than the total number of layers within the first subset T1 of the layers of the second alternating stack (232, 246). In one embodiment, the total number of layers within the second subset T2 of the layers of the second alternating stack (232, 246) may be approximately twice the total number of layers within the first subset T1 of the layers of the second alternating stack (232, 246). In an illustrative example, if the total number of layers within the first subset T1 of the layers of the second alternating stack (232, 246) is 2 N, where N is an integer greater than 1 (such as 2 2 =4), the total number of layers in the second subset T2 of the second alternating stack (232, 246) may be 2 N+1 (such as 2 2+1 =8). The total number of layers within the third subset T3 of the layers of the second alternating stack (232, 246) may be greater than the total number of layers within the second subset T2 of the layers of the second alternating stack (232, 246). In one embodiment, the total number of layers within the third subset T3 of the layers of the second alternating stack (232, 246) may be approximately twice the total number of layers within the second subset T2 of the layers of the second alternating stack (232, 246). In an illustrative example, if the total number of layers within the second subset T2 of the layers of the second alternating stack (232, 246) is 2 N+1 (such as 2 2+1 =8), the total number of layers in the third subset T3 of the second alternating stack (232, 246) can be 2 N+2 (such as 2 2+2 =16). In one embodiment, the total number of layers within the fourth subset T4 of the second alternating stack (232, 246) of layers may be approximately the same as the total number of layers within the third subset T3 of the second alternating stack (232, 246). In the illustrative example, if the total number of layers within the third subset T3 of the second alternating stack (232, 246) of layers is 2 N+2 (such as 2 2+2 =16), the total number of layers in the fourth subset T4 of the second alternating stack (232, 246) may be 2 N+2 (such as 2 2+2 =16).

[0073] Can be manufactured using a sequence of processing steps Figures 1A to 1J See the example structure of Figure 2 , used to form Figures 1A to 1J An exemplary structure of a structure of is shown as a vertical cross-sectional view taken along a first horizontal direction (e.g., a wordline direction) hd1. After forming a first vertical alternating sequence of semiconductor devices 720 disposed on a substrate semiconductor layer 9 at least within an upper portion of a substrate 8, a lower-level dielectric layer 760, a lower-level metal interconnect structure 780 embedded in the lower-level dielectric layer 760 (schematically represented by a dashed area including a physical implementation of the lower-level metal interconnect structure), a semiconductor material layer 110, and a first insulating layer 132 and a first spacer material layer (which may include a first sacrificial material layer 142), a first vertical alternating sequence of semiconductor devices 720 disposed on a substrate semiconductor layer 9 within an upper portion of a substrate 8 is provided. Figure 2The structure shown. The substrate semiconductor layer 9 may include a top portion (e.g., a doped well) of a semiconductor substrate 8 (such as a silicon wafer) or a semiconductor layer positioned above a substrate (such as a silicon-on-insulator substrate or a semiconductor substrate). The semiconductor device 720 may include a field effect transistor formed above the top surface of the substrate 8. The lower level dielectric layer 760 may be an interconnect-level dielectric material layer embedded in the lower level metal interconnect structure 780.

[0074] A first vertical alternating sequence of first insulating layers 132 and first spacer layers can be formed. Generally, the spacer material layer within each alternating stack is formed as a conductive layer or subsequently replaced with a conductive layer. Thus, the first spacer material layer can be formed as the first conductive layer 146 or can subsequently be replaced with such first conductive layers.

[0075] The first insulating layer 132 may be composed of a first material, and the first sacrificial material layer 142 may be composed of a second material different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that can be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0076] The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selectively with respect to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0077] The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may be subsequently replaced with a conductive electrode, which may be used, for example, as a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride.

[0078] See also Figure 3, shows a first configuration of an exemplary structure according to the first embodiment after forming a set of stepped surfaces in each mesa region 210. Multiple sets of stepped surfaces can be formed in multiple mesa regions 210 at the same time. Multiple sets of stepped surfaces can be formed in the mesa regions 210 of the first vertical alternating sequence (132, 142) by iteratively performing a set of layer patterning processing steps at least twice. The set of layer patterning processing steps includes a patterned photoresist material layer forming step and a pattern transfer step, in which a corresponding patterned photoresist material layer having a corresponding array of openings is formed above the first vertical alternating sequence (132, 142) and in which a pattern in the corresponding patterned photoresist material layer is transferred through a corresponding number of layers within the first vertical alternating sequence (132, 142). Each patterned photoresist material layer can be removed after the pattern transfer step, for example, by ashing.

[0079] In one embodiment, each of the plurality of stepped surfaces may include a stair region surface 23S formed in the stair region 21S and a cliff region surface 23C formed in the cliff region 21C. As used herein, a cliff region 21C is a region having an average cone angle (as determined by measuring the total lateral extent of the tapered and / or stepped surfaces and the total vertical extent of the tapered and / or stepped surfaces) of less than 45 degrees. The cliff region 21C may be contiguous with the perimeter of the stair region 21S.

[0080] In one embodiment, the average lateral spacing between adjacent pairs of vertical steps in cliff region 21C can be less than the sum of the average thickness of first insulating layer 132 and the average thickness of first spacer material layer (such as first sacrificial material layer 142). Conversely, in one embodiment, the average lateral spacing between adjacent pairs of vertical steps in stair region 21S can be greater than the sum of the average thickness of first insulating layer 132 and the average thickness of first spacer material layer (such as first sacrificial material layer 142). In one embodiment, the lateral extent of stair region 21S along the first horizontal direction hd1 can be at least five times the lateral extent of cliff region 21C along the first horizontal direction hd1, and can be at least ten times, such as 10 to 50 times, the lateral extent of cliff region 21C along the first horizontal direction hd1.

[0081] In the first configuration of the first embodiment, the height of the horizontal surface of the stepped surface along the first horizontal direction hd1 may monotonically or strictly increase with the lateral distance along the first horizontal direction hd1 from one of the memory array areas 100 to another of the memory array areas 100. In other words, the stepped surface in the staircase region 21S may monotonically increase or monotonically decrease for each staircase region 21S.

[0082] Figures 4A to 4Eis a top view of patterned photoresist material layers (410, 420, 430, 440, 450) having corresponding openings (310, 320, 330, 340, 350) that can be used sequentially to form a stepped surface in the mesa region 210 according to the second configuration of the exemplary structure of the second embodiment of the present disclosure. The positions of the dielectric wall structures 76 formed in the corresponding linear trenches are then juxtaposed with the top view of the patterned photoresist material layers (410, 420, 430, 440, 450). In the example shown, Figure 4A A first patterned photoresist layer 410 is shown in FIG. Figure 4B The second patterned photoresist layer 420 is shown in FIG. Figure 4C The third patterned photoresist layer 430 is shown in FIG. Figure 4D A fourth patterned photoresist layer 440 is shown in FIG. Figure 4E A fifth patterned photoresist layer 450 is shown in FIG.

[0083] Figures 5A to 5E and Figures 6A to 6E According to the embodiments of the present disclosure, Figures 4A to 4E A vertical cross-sectional view of an exemplary structure during formation of a stepped surface in the mesa region 200 by corresponding patterned photoresist material layers ( 410 , 420 , 430 , 440 , 450 ). Figures 5A to 5E is a view along a first horizontal direction (eg, word line direction) hd1, and Figures 6A to 6E is a corresponding view along the second horizontal direction (eg, bit line direction) hd2. Figures 5A to 5E The corresponding one of Figures 6A to 6E The corresponding one of Figures 4A to 4E A patterned photoresist material layer (410, 420, 430, 440, 450).

[0084] Figure 5A and Figure 6A The mesa region 210 is shown after a first pattern transfer step in which a pattern in a first patterned photoresist material layer 410 is transferred from a first set of first insulating layers 132 and first sacrificial material layers 142 (e.g., such as five layers) through a first vertical alternating sequence (132, 142). Figure 5B and Figure 6B The mesa region 210 is shown after a second pattern transfer step in which a pattern in a second patterned photoresist material layer 420 is transferred from a second set of first insulating layers 132 and first sacrificial material layers 142 (e.g., seven layers) through a first vertical alternating sequence (132, 142). Figure 5C and Figure 6CThe mesa region 210 is shown after a third pattern transfer step in which a pattern in a third patterned photoresist material layer 430 is transferred from a third set of first insulating layers 132 and first sacrificial material layers 142 (e.g., 14 layers) through a first vertical alternating sequence (132, 142). Figure 5D and Figure 6D The mesa region 210 is shown after a fourth pattern transfer step in which a pattern in a fourth patterned photoresist material layer 440 is transferred from a fourth set of first insulating layers 132 and first sacrificial material layers 142 (e.g., 28 layers) through the first vertical alternating sequence (132, 142). Figure 5E and Figure 6E The mesa region 210 is shown after a fifth pattern transfer step in which a pattern in a fifth patterned photoresist material layer 450 is transferred from a fifth set of first insulating layers 132 and first sacrificial material layers 142 (e.g., 37 layers) through the first vertical alternating sequence (132, 142). This patterning can be performed without using a hard mask layer (e.g., an insulating mask) overlying the alternating sequence (142, 242), thereby simplifying the process.

[0085] Generally speaking, N patterned photoresist layers (410, 420, 430, 440, 450) may be employed, where N is an integer greater than 1. Each of the N patterned photoresist layers (410, 420, 430, 440, 450) may be used as a corresponding patterned photoresist layer in a corresponding one of the layer patterning processing steps. Each of the N patterned photoresist layers (410, 420, 430, 440, 450) may provide a different opening pattern therein, so that at most two N There are two types of regions, depending on whether each of the N patterned photoresist layers (410, 420, 430, 440, 450) covers the corresponding region. N The staircase region 21S may be patterned with all or only some of the types of regions and a corresponding number of steps may be provided.

[0086] In a second configuration of the second embodiment, edges of the openings within the N patterned photoresist layers (410, 420, 430, 440, 450) may be positioned such that at least one vertical step S has a height greater than the sum of the thickness of the first insulating layer 132 and the thickness of the first sacrificial material layer 142. In this case, sidewalls of the plurality of first insulating layers 132 and the plurality of first sacrificial material layers 142 may be physically exposed at a subset of the vertical steps S within the staircase region 21S positioned within the mesa region 210.

[0087] Generally, a three-dimensional memory device can be provided by forming a vertically alternating sequence of insulating layers (such as first insulating layer 132 or second insulating layer 232) and spacer material layers (such as first sacrificial material layer or first conductive layer 146 and / or second sacrificial material layer or second conductive layer 246) over a substrate (which may include, for example, semiconductor material layer 110). The spacer material layer is formed as a conductive layer (such as first conductive layer 146 and / or second conductive layer 246) or is subsequently replaced with a conductive layer. The method further includes iteratively performing the first set of non-offset layer patterning process steps at least twice, such as 5A to 5D and 6A to 6D As shown, to form a first portion of the mesa region 210 including a set of stepped surfaces extending in a first horizontal direction hd1; and performing a second set of offset layer patterning process steps, such as Figure 5E and Figure 6E As shown, a second portion of the mesa region 210 is formed and a stepped vertical cross-sectional profile of the patterned surface is formed in a vertical alternating sequence along a second horizontal direction perpendicular to the first horizontal direction, as shown in FIG. Figure 6E shown.

[0088] The first set of layer patterning processing steps may be performed at least twice using non-offset lithography. The first set of layer patterning processing steps corresponds to Figure 5A and Figure 6A 、 Figure 5B and Figure 6B 、 Figure 5C and Figure 6C as well as Figure 5D and Figure 6D Each of the first set of layer patterning processing steps includes a first patterned photoresist material layer forming step in which a corresponding first patterned photoresist material layer (410, 420, 430, and / or 440) having a corresponding first array of openings (310, 320, 330, and / or 340) therein is formed over a vertical alternating sequence. The first array of openings (310, 320, 330, and / or 340) may have different lengths and / or different positions (e.g., along a first horizontal direction (e.g., wordline direction) hd1) along a first horizontal direction (e.g., wordline direction) hd1. 5A to 5D ), but may have substantially the same width (eg, bit line direction hd2) along the second horizontal direction (eg, bit line direction hd2). 6A to 6D shown).

[0089] The vertical alternating sequence may include alternating stacking of the first insulating layer 132 and the first sacrificial material layer 142 during the first patterning process, or alternating stacking of the second insulating layer 232 and the second sacrificial material layer 242 during the first patterning process. Each of the first set of layer patterning processing steps includes a first anisotropic etching step in which the pattern in the corresponding first patterned photoresist material layer (410, 420, 430 and / or 440) is transferred through the corresponding number of layers within the vertical alternating sequence by anisotropically etching the unmasked portion of the vertical alternating sequence.

[0090] The longitudinal edges of the openings along the first horizontal direction hd1 may overlap within the overlay tolerance of the photolithography exposure process across different first patterned photoresist material layers (410, 420, 430, and / or 440) in different iterations of the first patterned photoresist material layer formation step. In other words, the longitudinal edges of the openings (310, 320, 330, and / or 340) may overlap along the first horizontal direction hd1 in different photolithography exposure processes, and the widths of the openings (310, 320, 330, and / or 340) in the second horizontal direction hd2 may be the same. Such overlap of the longitudinal edges of the openings (310, 320, 330 and / or 340) of the first patterned photoresist material layer (410, 420, 430 and / or 440) may occur at positions corresponding to longitudinal edges of the first rear-facing stepped dielectric material portion 165 along the first horizontal direction hd1, and / or at positions corresponding to longitudinal edges of the second rear-facing stepped dielectric material portion 265 along the second horizontal direction hd2.

[0091] A second set of layer patterning processing steps may be performed. The second set of layer processing steps corresponds to Figure 5E and Figure 6E The second set of layer patterning processing steps includes a second patterned photoresist material layer forming step in which a second patterned photoresist material layer 450 having a second array of openings 350 therein is formed over the vertical alternating sequence, and a second anisotropic etching step in which the pattern in the second patterned photoresist material layer 450 is transferred through the layers within the vertical alternating sequence (e.g., 132, 142) by anisotropically etching unmasked portions of the vertical alternating sequence.

[0092] The width of the opening 350 in the second patterned photoresist material layer 450 in the second horizontal direction hd2 may be greater than the width of the opening (310, 320, 330, and / or 340) in the first patterned photoresist material layer (410, 420, 430, and / or 440) in the second horizontal direction hd2. In other words, the opening 350 through the second patterned photoresist material layer 450 is wider in the second horizontal direction hd2 than the opening (310, 320, 330, and / or 340) through the corresponding first patterned photoresist material layer (410, 420, 430, and / or 440).

[0093] The longitudinal edges of the openings 350 through the second patterned photoresist material layer 450 along the first horizontal direction hd1 may be laterally offset from the longitudinal sidewalls of the underlying patterned portion of the vertical alternating sequence by a lateral offset distance (lod or lod′) along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 to provide a stepped vertical cross-sectional profile of the patterned surface of the vertical alternating sequence along the second horizontal direction, e.g. Figure 6E The lateral offset distance (lod or lod') may be greater than an overlay tolerance of a photolithography exposure process of the first set of layer patterning process steps, and may be greater than twice the overlay tolerance of the photolithography exposure process of the first set of layer patterning process steps.

[0094] exist Figure 6E In one embodiment shown, longitudinal edges of openings 350 through the second patterned photoresist material layer 450 along a first horizontal direction hd1 can be laterally offset from longitudinal sidewalls of underlying patterned portions of the vertical alternating sequence (e.g., 132, 142) such that a lateral dimension of openings 350 along a second horizontal direction hd2 is greater than a lateral spacing LS between underlying pairs of longitudinal sidewalls of the vertical alternating sequence (132, 142) along the second horizontal direction hd2. In one embodiment, the lateral spacing of longitudinal edges of openings 350 through the second patterned photoresist material layer 450 along the first horizontal direction hd1 can be greater than the lateral spacing between underlying pairs of longitudinal sidewalls of the vertical alternating sequence along the second horizontal direction hd2 by at least two times the overlay tolerance of the photolithographic exposure process for the first set of layer patterning process steps and / or at least four times the overlay tolerance of the photolithographic exposure process for the first set of layer patterning process steps.

[0095] In one embodiment, the lateral offset distance (lod or lod') is at least twice the overlay tolerance of the photolithographic exposure process of the first set of layer patterning processing steps. In one embodiment, the respective number of layers within the vertical alternating sequence (132, 142) through which the pattern in the respective first patterned photoresist material layer (410, 420, 430 and / or 440) is transferred is different in different first anisotropic etching steps.

[0096] For example, the corresponding number of layers for one of the first anisotropic etching steps (such as Figure 5A and Figure 6A Anisotropic etching steps and Figure 5B and Figure 6B anisotropic etching step) is 4, and for the other one of the first anisotropic etching steps (such as Figure 5C and Figure 6C anisotropic etching step) is 8, and for another of the first anisotropic etching steps (such as Figure 5D and Figure 6D anisotropic etching step) is 16.

[0097] In one embodiment, the total number of layers within the vertical alternating sequence (132, 142) through which the pattern in the second patterned photoresist material layer 450 is transferred during the second anisotropic etching step is the same as or greater than the maximum number of layers within the vertical alternating sequence (132, 142) through which the pattern in the corresponding first patterned photoresist material layer (410, 420, 430 and / or 440) is transferred during each of the first anisotropic etching steps. Figure 5D and Figure 6D The process steps of the invention are to pattern 16 or more layers of a vertical alternating sequence (132, 142) and can be Figure 5E and Figure 6E At least the same number of layers or a greater number of layers of the vertical alternating sequence (132, 142) are patterned at the processing step.

[0098] In one embodiment, all sidewalls of the vertical alternating sequence (132, 142) are formed with respective taper angles with respect to the vertical that are less than 15 degrees during the first anisotropic etching step, these first anisotropic etching steps being Figure 5A and Figure 6A 、 Figure 5B and Figure 6B 、 Figure 5C and Figure 6C as well as Figure 5D and Figure 6D In one embodiment, a subset of the sidewalls of the vertically alternating sequence are formed with respective taper angles relative to the vertical in the range of 15 degrees to 30 degrees during the second anisotropic etching step, the second anisotropic etching step being Figure 5E and Figure 6E A subset of the processing steps.

[0099] In one embodiment, at least one layer within the vertical alternating sequence (132, 142) is formed with backward tapered sidewalls during the last of the first anisotropic etching steps such that the lateral extent of the at least one layer increases with vertical distance from the substrate, as Figure 6D The backward stepped sidewalls can be the result of the direct vertical overlap of the sidewalls patterned by the first photolithographic patterning process and the tendency of the first anisotropic etch step to undercut the previously formed sidewalls, as shown in FIG. Figure 6C shown.

[0100] exist Figure 6C In the illustrated example, a set of layers within the vertically alternating sequence of first insulating layers 132 and first sacrificial material layers 142 are formed with a backward stepped sidewall having a backward taper angle y. The backward taper angle is the angle that causes each overlying portion of the sidewall to protrude further outward than any underlying portion of the sidewall. The magnitude of the backward taper angle y can be in the range of 0.1 degrees to 10 degrees, such as 0.5 degrees to 5 degrees.

[0101] Therefore, the subsequent first anisotropic etching step may exacerbate undercutting within a subset of layers in the vertical alternating sequence (132, 142), e.g. Figure 6D shown. Figure 6D The backward stepped sidewall can be the result of direct vertical overlap of the sidewall patterned by the first photolithographic patterning process and the tendency of the first anisotropic etch step to undercut the previously formed sidewall. The backward stepped sidewall can have a variable backward taper angle that decreases with increasing vertical distance from the semiconductor material layer 110.

[0102] For example, Figure 6D The lower portion of each backward stepped sidewall of the vertical alternating sequence of the first insulating layer 132 and the first sacrificial material layer 142 may have a first average backward taper angle δ1, and Figure 6D The upper portion of each rear stepped sidewall of the vertical alternating sequence of the first insulating layer 132 and the first sacrificial material layer 142 may have a second average rear taper angle δ2 that is less than the first average rear taper angle δ1. For example, the first rear taper angle δ1 may be in a range of 1 to 15 degrees (such as 3 to 10 degrees), and the second rear taper angle δ2 may be in a range of 0.1 to 10 degrees (such as 0.5 to 5 degrees).

[0103] Subsequently, the backward tapered sidewalls may be converted to tapered sidewalls during a second anisotropic etching step such that the lateral extent of the at least one layer decreases with vertical distance from the substrate, e.g. Figure 6EFor example, each layer in the first subset S1, second subset S2, and third subset S3 of layers within the first alternating stack of first insulating layers 132 and first sacrificial material layers 142 may have a respective segment of a continuously tapered sidewall extending from the top surface of the semiconductor material layer 110 to the topmost layer of the third subset S3 of layers within the first alternating stack (132, 142).

[0104] In one embodiment, after each of the first anisotropic etching steps, the angles (α1, α2, α3) between the vertical direction and a two-dimensional plane including the topmost portions of the sidewalls of the vertical alternating sequence below the longitudinal edges of the respective first patterned photoresist material layers (410, 420, 430 and / or 440) are in the range of 0 degrees to 15 degrees, as Figure 6A 、 Figure 6B 、 Figure 6C and Figure 6D After the second anisotropic etching step, the angle α4 between the vertical direction and the two-dimensional plane including the topmost portion of the sidewalls of the vertical alternating sequence below the longitudinal edge of the second patterned photoresist material layer 450 is in the range of 15 degrees to 30 degrees, as shown in FIG. Figure 6E shown.

[0105] exist Figure 6E In one embodiment shown, the stepped vertical cross-sectional profile includes: an upper tapered sidewall surface of an upper subset of layers in the vertical alternating sequence (such as the sidewalls of the fourth subset S4 or the sidewalls of the fourth subset T4); a lower tapered sidewall surface of a lower subset of layers in the vertical alternating sequence below the upper subset of layers in the vertical alternating sequence (such as the union of the first subset S1, the second subset S2 and the third subset S3, or the union of the first subset T1, the second subset T2 and the third subset T3); and a horizontal top surface (HTS) of one of the layers in the vertical alternating sequence (132, 142), which is adjacent to the bottom edge of the upper tapered sidewall surface and the top edge of the lower tapered sidewall surface.

[0106] In one embodiment, the lower tapered sidewall surface has a variable taper angle (α1, α2, α3) relative to the vertical direction, such that the variable taper angle increases with the vertical distance from the substrate 8.

[0107] In one embodiment, multiple sets of stepped surfaces are formed in an area of ​​a vertical alternating sequence (132, 142) patterned by a first set of layer patterning processing steps and a second set of layer patterning processing steps; and a dielectric material portion (such as a first backward stepped dielectric material portion 165 or a second backward stepped dielectric material portion 265) is formed on each of the multiple sets of stepped surfaces.

[0108] Figure 7A1 is a general illustration of the alternating stacking (132, 142) of the lower portion of the insulating layer 132 and the sacrificial material layer 142 in the staircase region 21S prepared according to the second embodiment. The staircase region 21S may include at least one positive staircase area FSA and at least one reverse staircase area RSA. As used herein, a positive staircase refers to a height of a horizontal surface along a horizontal direction (such as a first horizontal direction hd1, for example). Figure 7A A contiguous subset of stepped surfaces that increases consistently with each vertical step (from left to right in the figure), the contiguous subset of stepped surfaces extending laterally from the bottom-most horizontal surface of all contiguous stepped surfaces toward the top-most horizontal surface of all contiguous stepped surfaces. The area in which positive stairs are located is referred to herein as a positive stair area FSA. As used herein, negative stairs refers to a horizontal surface whose height increases along a horizontal direction (such as a first horizontal direction hd1, e.g., Figure 7A 220 ).

[0109] In one embodiment, the pair of memory array regions 100 adjacent to each inter-array region 200 may include a first memory array region 100A and a second memory array region 100B. The bottommost horizontal surface of the staircase region 21S may be disposed on a side of the second memory array region 100B, and the topmost horizontal surface of the staircase region 21S may be disposed on a side of the first memory array region 100A. For vertically adjacent pairs of spacer material layers within each forward staircase, the vertical steps of the overlying spacer material layer (such as the overlying first sacrificial material layer 142) are closer to the first memory array region 100A than the vertical steps of the underlying spacer material layer are closer to the first memory array region 100A. For vertically adjacent pairs of spacer material layers within each reverse staircase, the vertical steps of the overlying spacer material layer (such as the overlying first sacrificial material layer 142) are less close to the first memory array region 100A than the vertical steps of the underlying spacer material layer are closer to the first memory array region 100A.

[0110] Each vertical interconnect via region 240 can be non-patterned and, therefore, can include all layers within the first vertical alternating sequence for both the first configuration and the second configuration. A first layer structure is formed that includes the first vertical alternating sequence (132, 142) and the first backward stepped dielectric material portion 165. The stepped surface in the first layer structure is referred to herein as a first stepped surface.

[0111] See also Figure 7A and Figure 7B , showing a second configuration of the exemplary structure after forming the stepped surface and the first dielectric material portion (referred to herein as the first backward stepped dielectric material portion 165) overlying the stepped surface of the first vertical alternating stack (132, 142). Figure 7C It will Figure 7A and Figure 7B A vertical partial perspective view of a second configuration of the exemplary structure of the combined view of FIG, with the first rearward stepped dielectric material portion 165 removed for clarity. Figure 7D yes 7A to 7C A top view of a second configuration of an exemplary structure of FIG. The vertical plane AA' corresponds to Figure 7A The vertical plane BB' corresponds to Figure 7B The view in .

[0112] like Figure 7B and Figure 7C As shown, since no hard mask is used during the patterning step, Figures 5A to 5E and Figures 6A to 6E During the illustrated steps, an upper subset of layers within the first vertical alternating sequence (132, 142) is trimmed (i.e., patterned) within the array interconnect region 220. Consequently, an upper subset of upper conductive layers (e.g., 146) to be formed in the structure will not be electrically connected through the array interconnect region 220. Consequently, the tapered portion of the mesa region 210 positioned between the cliff region 21C and the vertical interconnect via region 240 can have a stepped surface for subsequently forming contact via structures thereon and is referred to herein as a via contact region VCR. The via contact region VCR can extend laterally into adjacent portions of the array interconnect region 220 and can subsequently be used to form via contact structures therein that interconnect the upper subset of the upper conductive layer 146 extending between the memory array regions 100A and 100B. Generally speaking, a via contact region VCR may be formed in each region where the physical continuity of the first sacrificial material layer 142 is interrupted along the first horizontal direction hd1 (i.e., the upper sacrificial material layer 142 does not extend through the array interconnection region 220). The stepped surface 23V of the via contact region VCR has a greater taper (i.e., slope) than the cliff region surface 23C, as shown in FIG. Figure 7AA dielectric material portion (such as the first backward stepped dielectric material portion 165 ) may be formed on each of the plurality of stepped surfaces in the vertically alternating sequence ( 132 , 242 ) in each mesa region 210 .

[0113] In a certain embodiment, at least one layer of trimmable mask material may be employed to form the stepped surfaces (eg, surface 23V) within via contact region VCR and optionally an upper subset of the surfaces within the stepped surfaces of staircase region 21S. Figure 8A and Figure 8B Shown are patterns of trimmable mask material layers (eg, photoresist layers) that may be used to form the stepped surface within the via contact region VCR and optionally an upper subset of the surface within the stepped surface of the staircase region 21S.

[0114] Figure 8A FIG2 is a plan view of a pattern of a first trimmable mask material layer for forming a first subset of stepped surfaces for a second configuration of an exemplary structure. The location of a subsequently formed dielectric wall structure 76 is shown in dashed lines. Additionally, the location of a subsequently formed layer contact via structure 86 is shown in dashed lines. The first trimmable mask material layer can be formed as an unpatterned photoresist material layer and photolithographically patterned to form a first rectangular opening S1 having edges parallel to a second horizontal direction hd2. A first anisotropic etching process can be performed to etch at least the topmost first insulating layer 132 and the topmost first sacrificial material layer 142 within the region of the first rectangular opening S1. Vertical steps are formed along the perimeter of the first rectangular opening S1. Subsequently, an isotropic photoresist trimming process can be performed to isotropically etch the first trimmable mask material layer. The first rectangular opening S1 is laterally expanded to provide a second rectangular opening S2 having a pair of edges parallel to the second horizontal direction hd2. A second anisotropic etching process may be performed to etch at least one pair of the first insulating layer 132 and the first sacrificial material layer 142 within the region of the second rectangular opening S2. Additional vertical steps may be formed along the periphery of the second rectangular opening S2. Another isotropic trimming process may be performed to isotropically etch the first trimmable mask material layer. The second rectangular opening S2 is laterally expanded to provide a third rectangular opening S3 having a pair of edges parallel to the second horizontal direction hd2. A third anisotropic etching process may be performed to etch at least one pair of the first insulating layer 132 and the first sacrificial material layer 142 within the region of the third rectangular opening S3. Additional vertical steps may be formed along the periphery of the third rectangular opening S3. Subsequently, the first trimmable mask material layer may be removed, for example, by ashing.

[0115] Figure 8Bis a plan view of a pattern of a second trimmable mask material layer for forming a second subset of stepped surfaces for a second configuration of the exemplary structure. The second trimmable mask material layer can be formed as a non-patterned photoresist material layer and can be photolithographically patterned to form a fourth rectangular opening S4 including edges parallel to the second horizontal direction hd2. The edges of the fourth rectangular opening S4 extending along the second horizontal direction hd2 can be aligned with the edges extending along the second horizontal direction hd2 and aligned with the edges of the fourth rectangular opening S4 extending along the second horizontal direction hd2. Figure 8A The vertical steps formed at the processing step are laterally offset. A fourth anisotropic etching process may be performed to etch at least one pair of the first insulating layer 132 and the first sacrificial material layer 142 within the region of the fourth rectangular opening S4. Vertical steps are formed along the periphery of the fourth rectangular opening S4. Subsequently, an isotropic trimming process may be performed to isotropically etch the second trimmable mask material layer. The fourth rectangular opening S4 is laterally expanded to provide a fifth rectangular opening S5 having a pair of edges parallel to the second horizontal direction hd2. A fifth anisotropic etching process may be performed to etch at least one pair of the first insulating layer 132 and the first sacrificial material layer 142 within the region of the fifth rectangular opening S5. Additional vertical steps may be formed along the periphery of the fifth rectangular opening S5. Another isotropic trimming process may be performed to isotropically etch the second trimmable mask material layer. The fifth rectangular opening S5 is laterally expanded to provide a sixth rectangular opening S6 having a pair of edges parallel to the second horizontal direction hd2. A sixth anisotropic etching process may be performed to etch at least one pair of the first insulating layer 132 and the first sacrificial material layer 142 within the region of the sixth rectangular opening S6. Additional vertical steps may be formed along the periphery of the sixth rectangular opening S6. Subsequently, the second trimmable mask material layer may be removed, for example, by ashing.

[0116] While the present disclosure has been described using an embodiment in which six vertical steps are formed using two trimmable mask material layers, the number of trimmable mask material layers and the number of trimming steps used to expand the openings in the respective trimmable mask material layers can be modified as desired. Generally speaking, at least two vertical steps can be formed using at least one trimmable mask material layer. Additional vertical steps can be formed in the via contact region VCR and, optionally, within the stepped surface of the staircase region 21S.

[0117] like Figure 8BAs shown, openings S1 to S6 may cut all the way through the upper component layers in the array interconnect region 220 in some memory blocks (e.g., blocks B2 and B3) positioned between adjacent dielectric wall structures 76. Therefore, the upper conductive layers 146 in these memory blocks (B2, B3) will be individually connected by connecting their corresponding via contact regions VCR, as will be described in more detail below. However, openings S1 to S6 may not cut through the upper component layers in the array interconnect region 220 in some other memory blocks (e.g., blocks B1 and B4) positioned between other adjacent dielectric wall structures 76. Therefore, in these memory blocks (B1, B4), the upper conductive layers 146 are connected through the array interconnect region (e.g., the "bridge" region) 220. Therefore, stepped via contact regions VCR are not formed in these memory blocks (B1, B4).

[0118] Generally speaking, as the corresponding Figures 4A to 4E 、 Figures 5A to 5E and Figures 6A to 6E Before, after, or between the instances of performing the set of layer patterning process steps employed at the processing steps of the embodiment of the present invention, a layer of trimmable mask material having a first pattern may be applied above the first vertical alternating sequence (132, 142). A first etching process may be employed to transfer the first pattern in the trimmable mask material layer to a layer below the first vertical alternating sequence (132, 142). The trimmable mask material layer may be isotropically trimmed after the first etching process to provide a second pattern in the trimmable mask material layer. A second etching process may be employed to transfer the second pattern in the trimmable mask material layer to the first vertical alternating sequence (132, 142). The trimming step and the pattern transfer step may be repeated as many times as desired. Additionally, additional layers of trimmable mask material may optionally be employed to pattern additional vertical steps.

[0119] See also Figure 9 Various first layer openings may be formed through the first vertical alternating sequence (132, 142) into the semiconductor material layer 110. A photoresist layer (not shown) may be applied over the first vertical alternating sequence (132, 142) and may be photolithographically patterned to form the various openings therethrough.

[0120] The pattern of openings in the photoresist layer can be transferred through a first vertical alternating sequence (132, 142) into the semiconductor material layer 110 by a first anisotropic etching process to form various first layer openings simultaneously (i.e., during the first isotropic etching process). The various first layer openings may include first layer memory openings formed in the memory array region 100 and first layer support openings formed in the inter-array region 200. Each cluster of first layer memory openings may be formed as a two-dimensional array of first layer memory openings. The first layer support openings are openings formed in the inter-array region 200 and are subsequently used to form support post structures. A subset of the first layer support openings may be formed through corresponding horizontal surfaces of the stepped surface. It should be noted that although Figure 9 , a first configuration of the first embodiment including only a forward staircase area (FSA) is shown for simplicity, but a second configuration of the second embodiment including a reverse staircase area (RSA) in addition to the FSA may alternatively be formed.

[0121] A sacrificial first layer opening fill portion (148, 128) may be formed in the various first layer openings. For example, a sacrificial first layer fill material may be deposited simultaneously in each of the first layer openings. The sacrificial first layer fill material may include a material that may be selectively removed from the first insulating layer 132 and the first sacrificial material layer 142.

[0122] In one embodiment, the sacrificial first layer fill material may include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by non-conformal deposition or conformal deposition methods.

[0123] In another embodiment, the sacrificial first layer fill material may include a silicon oxide material having a higher etch rate than the material of the first insulating layer 132. For example, the sacrificial first layer fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than the etch rate of dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densifying in an annealing process) in 100:1 diluted hydrofluoric acid. In this case, a thin etch stop liner (such as a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by non-conformal deposition or conformal deposition methods.

[0124] In yet another embodiment, the sacrificial first layer filler material may include a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently removed selectively to the material of the first alternating stack (132, 142).

[0125] Portions of the deposited sacrificial material may be removed from above the topmost layer of the first vertical alternating sequence (132, 142), such as from above the topmost first insulating layer 132. For example, the sacrificial first layer fill material may be recessed to the top surface of the topmost first insulating layer 132 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the topmost first insulating layer 132 may serve as an etch stop or a planarization stop.

[0126] The remaining portions of the sacrificial first layer fill material comprise sacrificial first layer opening fill portions (148, 128). Specifically, each remaining portion of the sacrificial material in the first layer memory openings constitutes a sacrificial first layer memory opening fill portion 148. Each remaining portion of the sacrificial material in the first layer support openings constitutes a sacrificial first layer support opening fill portion 128. The various sacrificial first layer opening fill portions (148, 128) are formed simultaneously, i.e., during the same set of processes, including a deposition process that deposits the sacrificial first layer fill material and a planarization process that removes the first layer deposition process from above the first alternating stack (132, 142), such as from above the top surface of the topmost first insulating layer 132. The top surface of the sacrificial first layer opening fill portions (148, 128) may be coplanar with the top surface of the topmost first insulating layer 132. Each of the sacrificial first layer opening fill portions (148, 128) may or may not include a cavity therein.

[0127] See also Figure 10 , a second vertical alternating sequence of second insulating layers 232 and second spacer material layers may be formed. The second spacer material layer may be a second sacrificial material layer 242 that is subsequently replaced with a second conductive layer. The second insulating layer 232 may have the same material composition and the same thickness as the first insulating layer 132. The second spacer material layer may have the same material composition and the same thickness as the second spacer material layer.

[0128] In general, at least one additional vertical alternating sequence of additional insulating layers and additional spacer material layers may optionally be formed over the first vertical alternating sequence (132, 142) and the first backward stepped dielectric material portion 165. The additional spacer material layers may be formed as additional conductive layers or subsequently replaced with additional conductive layers.

[0129] See also Figure 11A and Figure 11B, showing a first configuration of the exemplary structure after patterning the second vertical alternating sequence (232, 242). Figure 3 The processing steps are performed to pattern the second vertical alternating sequence (232, 242) and provide an additional stepped surface in each mesa region 210. A second backward stepped dielectric material portion 265 may be formed on the additional stepped surface in the mesa region 210.

[0130] See also Figure 12A and Figure 12B , shows a second configuration of the exemplary structure after patterning the second vertical alternating sequence (232, 242). Thus, in the case where the second configuration is adopted instead of the first configuration, it is possible to perform Figures 5A to 5E 、 Figures 6A to 6E 、 7A to 7D and Figure 8A and Figure 8B The processing steps are performed to pattern the second vertical alternating sequence (232, 242) and provide an additional stepped surface in each mesa region 210. A second layer structure is formed including the second vertical alternating sequence (232, 242) and the second backward stepped dielectric material portion 265. The stepped surface in the second layer structure is referred to herein as a second stepped surface.

[0131] Generally speaking, when at least one additional vertical alternating sequence of additional insulating layers and additional spacer material layers is employed, additional multiple sets of stepped surfaces may be formed on each additional vertical alternating sequence. The additional set of layer patterning processing step may be performed iteratively at least twice. The additional set of layer patterning processing step may include an additional patterned photoresist material layer forming step, in which a corresponding additional patterned photoresist material layer having a corresponding array of openings is formed above the additional vertical alternating sequence, and an additional pattern transfer step, in which a pattern in the corresponding additional patterned photoresist material layer is transferred across a corresponding number of layers within the additional vertical alternating sequence. An additional dielectric material portion may be formed on each set of stepped surfaces in the additional multiple sets of stepped surfaces in the additional vertical alternating sequence.

[0132] Although the present disclosure is described using embodiments utilizing two vertical alternating sequences of insulating and spacer material layers, embodiments utilizing a single vertical alternating sequence or three or more vertical alternating sequences are expressly contemplated herein.

[0133] See also Figure 13, various second layer openings can be formed through the second layer structure (232, 242, 265). A photoresist layer (not shown) can be applied over the second layer structure, and the photoresist layer can be photolithographically patterned to form various openings therethrough. The pattern of the openings can be the same as the pattern of the various first layer openings (149, 129), which are the same as the sacrificial first layer opening filling portions (148, 128). Therefore, the photoresist layer can be patterned using the photolithographic mask used to pattern the first layer openings (149, 129).

[0134] The pattern of openings in the photoresist layer can be transferred through the second layer structure (232, 242, 265) by a second anisotropic etching process to simultaneously (i.e., during the second anisotropic etching process) form various second layer openings. The various second layer openings can include second layer memory openings 249 and second layer support openings 229. The second layer memory openings 249 are formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening filling portions 148. The second layer support openings 229 are formed directly on the top surface of a corresponding one of the sacrificial first layer support opening filling portions 128. In addition, a subset of the second layer support openings 229 can be formed through horizontal surfaces within the second stepped surface, including the interfacial surfaces between the second vertical alternating sequence (232, 242) and the second backward stepped dielectric material portion 265.

[0135] See also Figure 14A The sacrificial first layer filling material of the sacrificial first layer opening filling portion (148, 128) can be removed using an etching process that etches the sacrificial first layer filling material selectively to the materials of the first and second insulating layers (132, 232) and the first and second sacrificial material layers (142, 242). A memory opening (also referred to as an interlayer memory opening 49) is formed in each combination of the second layer memory opening and the volume from which the sacrificial first layer memory opening filling portion 148 is removed, and a support opening (also referred to as an interlayer support opening) is formed in each combination of the second layer support opening and the volume from which the sacrificial first layer support opening filling portion 128 is removed. The interlayer memory opening 49 extends through the first and second layer structures.

[0136] See also Figure 14B, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the interlayer memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer that consists essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metal element and oxygen, or may consist essentially of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1 nm to 20 nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may serve as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0137] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may comprise a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 comprises a silicon nitride layer.

[0138] In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coinciding sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layer (142, 242) may be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and anisotropic etching process may be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 may be in the range of 2 nm to 20 nm, although smaller and larger thicknesses may also be used.

[0139] The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2 nm to 20 nm, but smaller and larger thicknesses may also be used. The stack of the blocking dielectric layer 52 , the charge storage layer 54 , and the tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits.

[0140] The semiconductor channel material layer 60L includes a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may have a uniform doping. In one embodiment, the semiconductor channel material layer 60L has a p-type doping, wherein the p-type dopant (such as boron atoms) is present at a concentration of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 Such as 1.0×10 14 / cm 3 to 1.0×10 17 cm 3 In one embodiment, the semiconductor channel material layer 60L includes boron-doped amorphous silicon or boron-doped polysilicon and / or consists essentially of boron-doped amorphous silicon or boron-doped polysilicon. In another embodiment, the semiconductor channel material layer 60L has n-type doping, wherein the n-type dopant (such as phosphorus atoms or arsenic atoms) is present at an atomic concentration of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 Such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3The semiconductor channel material layer 60L exists at an atomic concentration within a range of 100 nm to 100 nm. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2 nm to 10 nm, although smaller and larger thicknesses may also be used. A cavity 49 ′ is formed in the volume of each interlayer memory opening 49 that is not filled with the deposited material layer ( 52 , 54 , 56 , 60L).

[0141] See also Figure 14C , in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)) or by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the top second insulating layer 232 can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface and the bottom surface of the top second insulating cap layer 232. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0142] See also Figure 14D and Figure 15 , a doped semiconductor material having a second conductivity type can be deposited in a cavity overlying the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and portions of blocking dielectric layer 52 overlying the horizontal plane (which includes the top surface of the top second insulating layer 232) can be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0143] Each remaining portion of the second conductivity type doped semiconductor material constitutes a drain region 63. The dopant concentration in the drain region 63 may be between 5.0×10 19 / cm 3 to 2.0×10 21 cm 3 The doped semiconductor material may be, for example, doped polysilicon.

[0144] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60 through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each adjacent group of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 together constitutes a memory film 50 that can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after forming the backside recess. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of the memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0145] Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the interlayer memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunneling dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. The memory stack structure 55 can be formed across the memory array area 100 of the first vertical alternating sequence and the second vertical alternating sequence, wherein all layers of the first vertical alternating sequence and the second vertical alternating sequence are present. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the interlayer memory opening 49 constitutes a memory opening filling structure 58.

[0146] Each interlayer support opening may be filled with a corresponding set of material portions having the same material composition as the corresponding components in the memory opening filling structure 58. Each set of material portions filling the interlayer support opening is referred to herein as a support post structure 20. It should be noted that Figure 1B The memory opening filling structure 58 positioned in the memory array region 100 is shown in FIG. 1 and is not shown in FIG. 1 for clarity. Figures 1A to 1J The support pillar structure 20 is shown in FIG. The semiconductor material layer 110 , the first layer structure ( 132 , 142 , 165 ), the second layer structure ( 232 , 242 , 265 ), the memory opening filling structure 58 and the support pillar structure 20 together constitute a memory level assembly.

[0147] See also Figure 16 A contact-level dielectric layer 280 may be formed over the second layer structure (232, 242, 265). The contact-level dielectric layer 280 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the contact-level dielectric layer 280 may include undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be used.

[0148] A photoresist layer (not shown) may be applied over the contact level dielectric layer 280 and may be photolithographically patterned to form linear openings extending laterally along a first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2. The pattern of the linear openings in the photoresist layer may be similar to Figures 1B to 1J The pattern of dielectric wall structures 76 is shown to be the same.Linear openings in the photoresist layer may be formed in areas where memory opening fill structures 58 or support post structures 20 are not present.

[0149] Line trenches (not explicitly shown) may be formed by transferring a pattern in a photoresist layer (not shown) through the contact level dielectric layer 280, the second layer structure (232, 242, 265) and the first layer structure (132, 142, 165) into the semiconductor material layer 110. The pattern of the line trenches may be similar to that of the first layer structure (132, 142, 165). Figures 1B to 1J The pattern of dielectric wall structures 76 shown is the same. Portions of contact-level dielectric layer 280, second layer structures (232, 242, 265), first layer structures (132, 142, 165), and semiconductor material layer 110 below the linear opening in the photoresist layer can be removed by an anisotropic etching process to form linear trenches. In one embodiment, linear trenches can be formed between clusters of memory stack structures 55. Clusters of memory stack structures 55 can be laterally separated by linear trenches along a second horizontal direction hd2.

[0150] Each vertical alternating sequence {(132, 142), (232, 242)} is divided by line trenches into a plurality of alternating stacks of insulating layers (132 or 232) and spacer material layers (such as sacrificial material layers (142, 242)) (e.g., memory blocks). Each line trench may extend laterally along a first horizontal direction hd1 through the inter-array region 200 and a pair of memory array regions 100 adjacent to the inter-array region 200. In addition, each line trench may extend vertically through the entire thickness of the vertical alternating sequence {(132, 142), (232, 242)}. Each patterned portion of the first vertical alternating sequence positioned between adjacent pairs of line trenches constitutes a first alternating stack of a first insulating layer 132 and a first spacer material layer (such as a first sacrificial material layer 142). Each patterned portion of the second vertical alternating sequence positioned between adjacent pairs of line trenches constitutes a second alternating stack of a second insulating layer 232 and a second spacer material layer (such as a second sacrificial material layer 242). A plurality of alternating stacks of insulating layers (132 or 232) and spacer material layers (which may be the first sacrificial material layer 142 or the second sacrificial material layer 242) may be formed. In one embodiment, each of the plurality of alternating stacks includes a corresponding one of the staircase regions 21S and a corresponding one of the cliff regions 21C.

[0151] See also Figure 17 If the spacer material layer includes a sacrificial material layer (142, 242), the sacrificial material layer (142, 242) is removed selectively relative to the insulating layer (132, 232), the contact-level dielectric layer 280, and the semiconductor material layer 110. For example, an etchant that selectively etches the material of the sacrificial material layer (142, 242) relative to the material of the insulating layer (132, 232), the material of the backward stepped dielectric material portion (165, 265), and the material of the outermost layer of the memory film 50 can be introduced into the line trench, for example, using an isotropic etching process. For example, the sacrificial material layer (142, 242) can include silicon nitride, and the material of the insulating layer (132, 232), the backward stepped dielectric material portion (165, 265), and the outermost layer of the memory film 50 can include silicon oxide.

[0152] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced into the line trench in a vapor phase. For example, if the sacrificial material layer (142, 242) comprises silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0153] A backside recess is formed in the volume from which the sacrificial material layer (142, 242) is removed. The backside recess includes a first backside recess formed in the volume from which the first sacrificial material layer 142 is removed and a second backside recess formed in the volume from which the second sacrificial material layer 242 is removed. Each of the backside recesses can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses can be greater than the height of the corresponding backside recess. Multiple backside recesses can be formed in the volume from which the material of the sacrificial material layer (142, 242) is removed.

[0154] Each of the backside recesses may extend substantially parallel to the top surface of the substrate semiconductor layer 9. The backside recess may be vertically bounded by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses may have a uniform height throughout.

[0155] An optional backside blocking dielectric layer (not shown) can optionally be deposited in the backside recesses and line trenches and over the contact-level dielectric layer 280. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide (eg, aluminum oxide), silicon oxide, or combinations thereof.

[0156] At least one conductive material may be deposited in the plurality of backside recesses, on the sidewalls of the line trenches, and above the contact-level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

[0157] In one embodiment, the at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive filler material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, the at least one conductive material used to fill the backside recess may be a combination of a titanium nitride layer and a tungsten filler material.

[0158] A conductive layer (146, 246) can be formed in the backside recess by depositing the at least one conductive material. A plurality of first conductive layers 146 can be formed in the plurality of first backside recesses, a plurality of second conductive layers 246 can be formed in the plurality of second backside recesses, and a continuous metal material layer (not shown) can be formed on the sidewalls of each linear trench and above the contact-level dielectric layer 280. Each of the first conductive layer 146 and the second conductive layer 246 can include a corresponding conductive metal nitride liner and a corresponding conductive filler material. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) can be replaced with the first conductive layer and the second conductive layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 can be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each linear trench that is not filled with the continuous metal material layer.

[0159] Residual conductive material can be removed from the interior of the linear trenches. Specifically, the deposited metal material of the continuous metal material layer can be etched back from the sidewalls of each linear trench and from above the contact-level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes a second conductive layer 246. The sidewalls of the first conductive material layer 146 and the second conductive layer can be physically exposed to the corresponding linear trenches. The linear trenches can have a pair of curved sidewalls with a non-periodic width variation along the first horizontal direction hd1 and a nonlinear width variation along the vertical direction.

[0160] Each conductive layer (146, 246) may be a conductive sheet including openings therein. A first subset of the openings through each conductive layer (146, 246) may be filled with a memory opening filling structure 58. A second subset of the openings through each conductive layer (146, 246) may be filled with a support pillar structure 20.

[0161] A subset of the conductive layers (146, 246) may include word lines for memory elements. The semiconductor devices in the semiconductor device 720 below may include word line switch devices (which are configured to control the bias voltage to the corresponding word lines) and / or bit line driver devices, such as sense amplifiers. The memory level assembly is positioned above the substrate semiconductor layer 9. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 vertically extending through the at least one alternating stack (132, 146, 232, 246). Each of the memory stack structures 55 includes a vertical stack of memory elements positioned at each level of the conductive layers (146, 246).

[0162] A dielectric material such as silicon oxide may be conformally deposited in the line trenches by a conformal deposition process. Each portion of the deposited dielectric material that fills the line trenches constitutes a dielectric wall structure 76. The dielectric wall structure 76 may be formed as follows: Figures 1B to 1J The configuration shown is arranged.

[0163] See also Figure 18Various contact via structures (88, 86, 486) may be formed through the contact-level dielectric layer 280 and, optionally, through the underlying material portion on the corresponding underlying conductive structure. The various contact via structures (88, 86, 486) may include drain contact via structures (e.g., drain electrodes) 88 formed through the contact-level dielectric layer 280 on the top surface of the corresponding drain region 63 in the memory array region 100. The various contact via structures (88, 86, 486) may include word line contact via structures 86 formed through the contact-level dielectric layer 280 and at least one backward stepped dielectric material portion (165, 265) on a corresponding one of the conductive layers (146, 246) in the mesa region 210. In addition, laterally isolated vertical interconnect structures (484, 486) may be formed through the alternating stacks (132, 146, 232, 246) in the vertical interconnect via region 240. Each laterally isolated vertical interconnect structure (484, 486) may include a through-memory level conductive via structure 486 and a tubular insulating spacer 484 that laterally surrounds the conductive via structure 486. Each through-memory level conductive via structure 486 may contact a corresponding one of the lower level metal interconnect structures 780 embedded within the lower level dielectric material layer 760. A bit line 98 is then formed that is in electrical contact with the drain contact via structure 88. A source region or source line may be formed in or above the semiconductor material layer 110 and electrically connected to the semiconductor device 700 in the peripheral region (not shown).

[0164] See also Figure 19 , shows a vertical cross-sectional view of a second configuration of the exemplary structure after forming metal interconnect structures 96 that extend vertically and horizontally over the mesa region 210 adjacent to the array interconnect region 220. The metal interconnect structures 96 are connected to each conductive layer (e.g., word lines (146, 246)) in a corresponding through-hole contact region (VCR). Thus, the metal interconnect structures 96 electrically connect the upper conductive layers (e.g., word lines) of the upper group that do not extend through the array interconnect region 220 (i.e., in the Figure 8A and Figure 8B into the array interconnect region 220 during the patterning step). Thus, Figure 19 The metal interconnect structure 96 in provides interconnection between corresponding upper word lines in the first memory array region 100A and the second memory array region 100B in the same vertical level.

[0165] At least one conductive layer (146 or 246) including the topmost conductive layer of each alternating stack {(132,146), (232,246)} is broken into discrete portions positioned in the first memory array region 100A and the second memory array region 100B, and since it is possible to employ, for example, Figure 8A and Figure 7B The stepped surface formed by the processing steps does not extend along the first horizontal direction hd1 across the array interconnect region 220. A portion of each such disconnected conductive layer (146 or 246) (including the topmost conductive layer) in the first memory array region 100A and a portion of each such disconnected conductive layer (146 or 246) (including the topmost conductive layer) in the second memory array region 100B can be electrically connected using a metal interconnect structure 96 that extends at least partially in a vertical direction perpendicular to the top surface of the substrate.

[0166] exist Figure 19 In one embodiment shown, the method of the embodiments of the present disclosure includes forming a metal interconnect structure 96 that electrically connects a portion of the topmost conductive layer 246T in the first memory array area 100A and a portion of the topmost conductive layer 246T in the second memory array area 100B and extends above a horizontal plane of the topmost conductive layer 246 in the first memory array area 100A and a portion of the topmost conductive layer 246T in the second memory array area 100B.

[0167] Therefore, the memory block (e.g. Figure 8B The upper conductive layers (146, 246) (including the topmost conductive layer 246T) ​​in each alternating stack in at least one of (B2 and B3 in each memory block) are connected between the first and second memory array regions (100A, 100B) by a corresponding metal interconnect structure 96. Each corresponding metal interconnect structure 96 extends above a mesa region 210 positioned above the horizontal plane of the corresponding conductive layers (146, 246) in the first and second memory array regions (100A, 100B), the corresponding metal interconnect structure 96 electrically connecting these corresponding conductive layers to each other. The lower conductive layers (146, 246) in each alternating stack in each memory block extend continuously through an array interconnect region (e.g., a "bridge" region) 220 in the same horizontal plane between the first and second memory array regions (100A, 100B). Furthermore, in one embodiment, the upper conductive layer (146, 246) in each alternating stack of some other memory blocks (e.g., B1, B4) extends continuously across the array interconnect region (e.g., a "bridge" region) 220 in the same horizontal plane between the first and second memory array regions (100A, 100B).

[0168] exist 7A to 7D In one embodiment shown, a portion of each respective lower conductive layer (146, 246) in the first memory array region 100A and a portion of each respective lower conductive layer (146, 246) in the second memory array region 100B are electrically connected by a respective conductive region (146, 246) that extends in an array interconnect region 220 in a horizontal plane of each respective lower conductive layer (146, 246) in the first memory array region 100A and each respective lower conductive layer (146, 246) in the second memory array region 100B. The array interconnect region 220 is adjacent to a respective one of the staircase regions 21S and a respective one of the cliff regions 23C and is laterally offset from the respective one of the staircase regions 21S and the respective one of the cliff regions 23C along a second horizontal direction hd2. The conductive regions (146, 246) extending in the array interconnect region 220 include portions of the lower conductive layer positioned in the array interconnect region 220 that provide a conductive path between the first memory array region 110A and the second memory array region 100B.

[0169] On the contrary, Figure 19 As shown, the topmost conductive layer 246T is broken into discrete portions positioned in the first memory array region 100A and the second memory array region 100B and does not extend through the array interconnect region 220. The stepped surface 23V of the via contact region VCR has a greater taper than the cliff region surface 23C, and the metal interconnect structure 96 contacts the topmost conductive layer 246T in the via contact region VCR.

[0170] Preferably, but not necessarily, a hard mask (eg, a dielectric mask other than photoresist) is not used during the step of forming the plurality of stepped surfaces in the mesa region 210 .

[0171] See also 7A to 7D 、 FIG. 12A to FIG. 12B and Figure 19According to a second embodiment of the present disclosure, a three-dimensional memory device is provided. The three-dimensional memory device may include alternating stacks {(132, 146) and / or (232, 246)} of insulating layers (132 and / or 232) and conductive layers (146 and / or 246) positioned above a substrate 8, wherein the alternating stacks {(132, 146) and / or (232, 246)} are laterally spaced apart from each other by linear trenches extending laterally along a first horizontal direction hd1; and a memory stack structure 55 extending through a memory array region 100 of the alternating stacks {(132, 146) and / or (232, 246)}, wherein there are alternating stacks {(132, 146) and / or (232, 246)}. , 246)}, wherein each alternating stack {(132, 146) and / or (232, 246)} includes: a first memory array area 100A, which includes a corresponding first subset of the memory stacking structure 55; a second memory array area 100B, which includes a corresponding second subset of the memory stacking structure 55 and is laterally spaced from the first memory array area 100A along a first horizontal direction hd1; and a mesa area 210, which includes a set of stepped surfaces and is positioned between the first memory array area 100A and the second memory array area 100B. The set of stepped surfaces includes at least one positive staircase area FSA, wherein, for vertically adjacent pairs of conductive layers (146 or 246), a vertical step of the overlying conductive layer (146 or 246) is closer to the first memory array region 100A than a vertical step of the underlying conductive layer (146 or 246) is closer to the first memory array region 100A. The set of stepped surfaces includes at least one reverse staircase area RSA, wherein, for vertically adjacent pairs of conductive layers (146 or 246), a vertical step of the overlying conductive layer (146 or 246) is less close to the first memory array region 100A than a vertical step of the underlying conductive layer (146 or 246) is closer to the first memory array region 100A.

[0172] Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. Each mesa region 210 may include a corresponding staircase region 21S and a corresponding cliff region 21C. The corresponding cliff region 21C and the corresponding staircase region 21S may be laterally spaced apart along a first horizontal direction hd1. In one embodiment, the first memory array region 100A may be closer to a corresponding one of the staircase regions 21S than to a corresponding one of the cliff regions 21C. The second memory array region 100B may be closer to a corresponding one of the cliff regions 21C than to a corresponding one of the staircase regions 21S. The array interconnect region 220 may be adjacent to a corresponding one of the staircase regions 21S and a corresponding one of the cliff regions 21C and may be laterally offset from the corresponding one of the staircase regions 21S and a corresponding one of the cliff regions 21C along a second horizontal direction hd2. The portion of the conductive layer (146 and / or 246) in the array interconnect region 220 provides a conductive path between the first memory array region 100A and the second memory array region 100B.

[0173] exist Figure 19 In one embodiment shown, the first and second portions of each lower conductive layer (146 and / or 246) positioned in the respective first and second memory array regions (100A, 100B) are electrically connected by a third portion of each respective lower conductive layer (146 and / or 246) in the array interconnect region 220 positioned in the horizontal plane of the first and second portions of each lower conductive layer (146 and / or 246). In contrast, the first and second portions of the topmost conductive layer 246T positioned in the respective first and second memory array regions (100A, 100B) are electrically connected by a metal interconnect structure 96 that extends above the mesa region 210 above the horizontal plane of the first and second portions of the topmost conductive layer 246T.

[0174] In one embodiment, the array interconnect region 220 may contact the corresponding dielectric material portion (such as the first backward stepped dielectric material portion 165 and / or the second backward stepped dielectric material portion 265) at the additional cliff region, as shown in FIG. Figure 1D The average lateral spacing between adjacent pairs of vertical steps along the second horizontal direction hd2 is less than the sum of the average thickness of the insulating layer (132 and / or 232) and the average thickness of the conductive layer (146 and / or 246).

[0175] In one embodiment, each set of stepped surfaces in a corresponding mesa region 200 includes: a stair region surface positioned in a corresponding stair region 21S, wherein the average lateral spacing between adjacent pairs of vertical steps is greater than the sum of the average thickness of the insulating layer (132 and / or 232) and the average thickness of the conductive layer (146 and / or 246); and a cliff region surface 23C positioned in a corresponding cliff region 21C adjacent to the periphery of the corresponding stair region 21S, wherein the vertical steps of the cliff region surface 23C have an average lateral spacing between adjacent pairs of vertical steps, which is less than the sum of the average thickness of the insulating layer (132 and / or 232) and the average thickness of the conductive layer (146 and / or 246).

[0176] In one embodiment, the respective cliff region 21C and the respective stair region 21S are laterally spaced apart along the first horizontal direction hd1 ; and the lateral extent of the respective stair region 21S along the first horizontal direction hd1 is at least five times the lateral extent of the respective cliff region 21C.

[0177] In one embodiment, each set of stepped surfaces in a respective mesa region 210 is contacted by a respective dielectric material portion (such as first backward stepped dielectric material portion 165 or second backward stepped dielectric material portion 265); and the respective dielectric material portions contact sidewalls of portions of the conductive layer (146 or 246) in the array interconnect region 220 that extend laterally along a first horizontal direction hd1.

[0178] See also Figure 19And according to various embodiments of the present disclosure, there is provided a three-dimensional memory device, comprising: alternating stacks of insulating layers (132 and / or 232) and conductive layers (146 and / or 246) positioned above a substrate 8, wherein the alternating stacks {(132, 146) and / or (232, 246)} are laterally spaced apart from each other by line trenches that extend laterally along a first horizontal direction hd1; and a memory stack structure 55 extending through a memory array region 100 of the alternating stacks {(132, 146) and / or (232, 246)}, wherein all layers of a corresponding one of the alternating stacks {(132, 146) and / or (232, 246)} are present. Each alternating stack {(132, 146) and / or (232, 246)} includes: a first memory array region 100A, which includes a corresponding first subset of the memory stacking structures 55; a second memory array region 100B, which includes a corresponding second subset of the memory stacking structures 55 and is laterally spaced from the first memory array region 100A along a first horizontal direction hd1; a mesa region 210, which includes a set of stepped surfaces and is positioned between the first memory array region 100A and the second memory array region 100B; and an array interconnect region 220, which is adjacent to the mesa region 210 and is laterally offset from the mesa region along a second horizontal direction hd2.

[0179] The first and second portions of each lower conductive layer (146, 246) positioned in the respective first and second memory array regions (100A, 100B) are electrically connected by a third portion of each respective lower conductive layer (146, 246) in the array interconnect region 220 positioned in the horizontal plane of the first and second portions of each lower conductive layer (146, 246). Conversely, the first and second portions of the topmost conductive layer 246T positioned in the respective first and second memory array regions (100A, 100B) are electrically connected by a metal interconnect structure 96 that extends above the mesa region 210 above the horizontal plane of the first and second portions of the topmost conductive layer 246T.

[0180] The second alternating stack 100B includes a via contact region VCR positioned above a surface 23C of a cliff region 21C, with a stepped surface 23V of the via contact region VCR having a greater taper than the cliff region surface 23C. A metal interconnect structure 96 contacts the topmost conductive layer 246T in the via contact region VCR.

[0181] In one embodiment, the group of stepped surfaces includes: a stair area surface positioned in a corresponding stair area 21S, wherein the average lateral spacing between adjacent pairs of vertical steps is greater than the sum of the average thickness of the insulating layer (132 and / or 232) and the average thickness of the conductive layer (146 and / or 246); and a cliff area surface 23C positioned in a corresponding cliff area 21C, which is adjacent to the periphery of the corresponding stair area 21S, wherein the vertical steps of the cliff area surface have an average lateral spacing between adjacent pairs of vertical steps, which is less than the sum of the average thickness of the insulating layer (132 and / or 232) and the average thickness of the conductive layer (146 and / or 246).

[0182] In one embodiment, the set of stepped surfaces includes: at least one forward staircase area FSA, wherein, for vertically adjacent pairs of conductive layers (146 or 246), the vertical steps of the overlying conductive layer (146 or 246) are closer to the first memory array region 100A than the vertical steps of the underlying conductive layer (146 or 246) are closer to the first memory array region 100A; and at least one reverse staircase area RSA, wherein, for vertically adjacent pairs of conductive layers (146 or 246), the vertical steps of the overlying conductive layer (146 or 246) are less close to the first memory array region 100A than the vertical steps of the underlying conductive layer (146 or 246) are closer to the first memory array region 100A.

[0183] Various embodiments of the present disclosure can be used to form a stepped surface using a set of patterned photoresist material layers. Thus, a hard mask need not be used to pattern the stepped surface. Cliff region 21C can be provided by overlapping edges of adjacent patterned photoresist material layers. The use of patterned photoresist material layers and the elimination of hard mask layers can reduce the processing cost of forming the stepped surface and enhance the pattern fidelity of the stepped surface by using patterned photoresist material layers in place of one or more hard mask layers.

[0184] Generally, a memory stack structure 55 can be formed across a vertically alternating sequence of memory array regions 100, wherein all layers of the vertically alternating sequence are present. The vertically alternating sequence can be divided into a plurality of alternating stacks by forming line trenches, such as backside trenches 79, that extend through the entire thickness of the vertically alternating sequence along a first horizontal direction hd1.

[0185] Optionally, at least one metal interconnect structure 98 may be formed that electrically connects a portion of the topmost conductive layer (146 or 246) in the first memory array region 100A and a portion of the topmost conductive layer (146 or 246) in the second memory array region 100B and extends above a horizontal plane of the topmost conductive layer (146 or 246) in the first memory array region 100A and a portion of the topmost conductive layer (146 or 246) in the second memory array region 100B.

[0186] According to one aspect of the present disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulating layers (132 or 232) and conductive layers (146 or 246) positioned above a substrate 8; and a memory stack structure 55 extending through a memory array region 100 of the alternating stack, wherein all layers of the alternating stack are present. The alternating stack comprises: a first memory array region 100A comprising a first subset of the memory stack structures 55; a second memory array region 100B comprising a second subset of the memory stack structures 55 and laterally spaced apart from the first memory array region 100A along a first horizontal direction hd1; and a mesa region comprising a set of stepped surfaces positioned between the first memory array region 100A and the second memory array region 100B. The alternatingly stacked sidewalls have a stepped vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1 (e.g., a plane extending in the second horizontal direction hd2); and the stepped vertical cross-sectional profile includes: an upper conical sidewall surface of an upper subset of the alternatingly stacked layers; a lower conical sidewall surface of a lower subset of the layers in the vertical alternating sequence, the lower conical sidewall surface being below the upper subset of the layers in the vertical alternating sequence; and a horizontal top surface of one of the layers in the vertical alternating sequence, the horizontal top surface being adjacent to a bottom edge of the upper conical sidewall surface and a top edge of the lower conical sidewall surface.

[0187] In one embodiment, the lower tapered sidewall surface has a variable taper angle relative to a vertical direction, such that the variable taper angle increases with vertical distance from the substrate.

[0188] In one embodiment, the backward stepped dielectric material portion (165 or 265) can contact the stepped surface in the mesa region and can contact the upper tapered sidewall surface, the lower tapered sidewall surface, and the horizontal top surface of the stepped vertical cross-sectional profile.

[0189] In one embodiment, contact via structure 86 may extend vertically through the rear stepped dielectric material portion (165 or 265) and may contact a corresponding horizontal surface of the conductive layer (146 or 246) within the stepped surface. Memory stack structure 55 may include vertical semiconductor channel 60 and memory film 50.

[0190] Various embodiments of the present disclosure can be used to reduce the lateral extent of the sidewalls of the alternating stacks of insulating layers and conductive layers extending laterally along the word line direction hd1 in the bit line direction hd2. The electrical conductivity of the portion of the conductive layer connecting the first memory array region 100A and the second memory array region 100B can be enhanced by reducing the area occupied by the alternating stacks of tapered sidewalls and by increasing the width of the connecting portion of the conductive layer in the interconnect region 220.

[0191] Although specific embodiments have been mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those skilled in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or the words "consisting of" replace the words "comprising" or "including." Where embodiments using specific structures and / or configurations are shown in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitution is not expressly prohibited or otherwise deemed impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A method for forming a three-dimensional memory device, the method comprising: forming a vertically alternating sequence of insulating layers and layers of spacer material over the substrate, wherein the layers of spacer material are formed as conductive layers or are subsequently replaced with conductive layers; iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first portion of the mesa region including a set of stepped surfaces extending in a first horizontal direction and forming the vertical alternating sequence of longitudinal sidewalls along a second horizontal direction perpendicular to the first horizontal direction; as well as A second set of offset layer patterning steps is performed to form a second portion of the mesa region and a stepped vertical cross-sectional profile of the vertically alternating sequence of patterned surfaces along a second horizontal direction perpendicular to the first horizontal direction.

2. The method according to claim 1, wherein: each first set of non-offset layer patterning processing steps comprises a first patterned photoresist material layer forming step and a first anisotropic etching step, wherein in the first patterned photoresist material layer forming step, a respective first patterned photoresist material layer having a respective first array of openings therein is formed over the vertical alternating sequence, and in the first anisotropic etching step, a pattern in the respective first patterned photoresist material layer is transferred through a respective number of layers within the vertical alternating sequence by anisotropically etching unmasked portions of the vertical alternating sequence, wherein longitudinal edges of the openings along a first horizontal direction overlap within an overlay tolerance of a photolithographic exposure process across different first patterned photoresist material layers in different iterations of the first patterned photoresist material layer forming step; as well as Performing the second set of offset layer patterning processing steps includes a second patterned photoresist material layer forming step and a second anisotropic etching step, in which the second patterned photoresist material layer having a second array of openings therein is formed above the vertical alternating sequence, and in the second anisotropic etching step, the pattern in the second patterned photoresist material layer is transferred through the layer within the vertical alternating sequence by anisotropically etching an unmasked portion of the vertical alternating sequence, wherein longitudinal edges of the openings passing through the second patterned photoresist material layer along the first horizontal direction are laterally offset from longitudinal sidewalls of the underlying patterned portion of the vertical alternating sequence along a second horizontal direction perpendicular to the first horizontal direction by a lateral offset distance to provide the stepped vertical cross-sectional profile of the patterned surface of the vertical alternating sequence. 3 . The method of claim 2 , wherein the opening through the second patterned layer of photoresist material is wider in the second horizontal direction than the opening through the corresponding first patterned layer of photoresist material.

4. The method of claim 2 , wherein the longitudinal edges of the openings through the second patterned photoresist material layer along the first horizontal direction are laterally offset from the longitudinal sidewalls of the underlying patterned portions of the vertical alternating sequence such that the lateral dimensions of the openings through the second patterned photoresist material layer along the second horizontal direction are greater than the lateral spacing between the underlying pairs of longitudinal sidewalls of the vertical alternating sequence along the second horizontal direction. The method of claim 2 , wherein the lateral offset distance is at least twice the overlay tolerance of the photolithography exposure process.

6. The method of claim 2, wherein the respective number of layers within the vertical alternating sequence through which the pattern in the respective first patterned photoresist material layer is transferred is different in different first anisotropic etching steps.

7. The method of claim 6, wherein the corresponding number of layers is 4 for one of the first anisotropic etching steps, 8 for another of the first anisotropic etching steps, and 16 for yet another of the first anisotropic etching steps.

8. The method according to claim 2, wherein: All sidewalls of the vertical alternating sequence are formed with respective taper angles with respect to vertical that are less than 15 degrees during the first anisotropic etching step; and A subset of the sidewalls of the vertical alternating sequence are formed during the second anisotropic etching step with respective taper angles relative to the vertical direction in the range of 15 degrees to 30 degrees.

9. The method according to claim 8, wherein: forming at least one layer within the vertical alternating sequence with backward-tapered sidewalls during a last first anisotropic etching step in the first anisotropic etching steps such that a lateral extent of the at least one layer increases with vertical distance from the substrate; and The backward tapered sidewalls are converted into tapered sidewalls during the second anisotropic etching step such that the lateral extent of the at least one layer decreases with the vertical distance from the substrate.

10. The method according to claim 8, wherein: an angle between a vertical direction and a two-dimensional plane comprising topmost portions of sidewalls of the vertical alternating sequence underlying a longitudinal edge of the respective first patterned photoresist material layer after each of the first anisotropic etching steps is in a range of 0 degrees to 15 degrees; and An angle between the vertical direction and a two-dimensional plane comprising topmost portions of the vertical alternating sequence of sidewalls beneath longitudinal edges of the second patterned photoresist material layer after the second anisotropic etching step is in the range of 15 to 30 degrees.

11. The method of claim 1 , wherein the stepped vertical cross-sectional profile comprises: upper tapered sidewall surfaces of an upper subset of said vertically alternating sequence of layers; lower tapered sidewall surfaces of a lower subset of said layers of said vertically alternating sequence, said lower tapered sidewall surfaces underlying said upper subset of said layers of said vertically alternating sequence; and A horizontal top surface of one of the layers of the vertical alternating sequence, the horizontal top surface abutting a bottom edge of the upper tapered sidewall surface and a top edge of the lower tapered sidewall surface. 12 . The method of claim 11 , wherein the lower tapered sidewall surface has a variable taper angle relative to a vertical direction such that the variable taper angle increases with a vertical distance from the substrate.

13. The method of claim 1, wherein: forming a plurality of sets of stepped surfaces in the areas of the vertically alternating sequence patterned by the first set of non-offset layer patterning process steps and the second set of offset layer patterning process steps; and The method also includes forming a dielectric material portion on each set of stepped surfaces in the plurality of sets of stepped surfaces.

14. The method of claim 1, further comprising forming a memory stack structure including vertical semiconductor channels and memory films across a memory array region of the vertical alternating sequence, wherein all layers of the vertical alternating sequence are present.

15. The method of claim 14 , further comprising forming a metal interconnect structure electrically connecting a portion of the topmost conductive layer in the first memory array region and a portion of the topmost conductive layer in the second memory array region and extending above a horizontal plane of the topmost conductive layer in the first memory array region and a portion of the topmost conductive layer in the second memory array region. 16 . The method of claim 1 , further comprising dividing the vertical alternating sequence into a plurality of alternating stacks by forming linear grooves extending through an entire thickness of the vertical alternating sequence along the first horizontal direction.

17. A three-dimensional memory device, comprising: an alternating stack of insulating layers and conductive layers, the alternating stack positioned above the substrate; and a memory stack structure extending through a memory array region of said alternating stack, wherein all layers of said alternating stack are present; The alternating stacking includes: a first memory array region including a first subset of the memory stack structure; a second memory array region comprising a second subset of the memory stack structures and laterally spaced apart from the first memory array region along a first horizontal direction; and a mesa region comprising a set of stepped surfaces positioned between the first memory array region and the second memory array region; wherein the alternately stacked side walls have a stepped vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction; and The stepped vertical cross-sectional profile comprises: upper tapered sidewall surfaces of an upper subset of said alternatingly stacked layers; lower tapered sidewall surfaces of a lower subset of said alternatingly stacked layers, said lower tapered sidewall surfaces underlying said upper subset of said alternatingly stacked layers; and A horizontal top surface of one of the alternatingly stacked layers, the horizontal top surface adjoining a bottom edge of the upper tapered sidewall surface and a top edge of the lower tapered sidewall surface.

18. The three-dimensional memory device according to claim 17, wherein: The lower tapered sidewall surface has a variable taper angle relative to a vertical direction, such that the variable taper angle increases with vertical distance from the substrate; and Each memory stack structure includes a vertical semiconductor channel and a memory film.

19. The three-dimensional memory device of claim 17 , further comprising a backward stepped dielectric material portion contacting the stepped surface in the mesa region and contacting the upper tapered sidewall surface, the lower tapered sidewall surface, and the horizontal top surface of the stepped vertical cross-sectional profile.

20. The three-dimensional memory device of claim 19, further comprising a contact via structure extending vertically through the backward stepped dielectric material portion and contacting a corresponding horizontal surface of the conductive layer within the stepped surface.

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