Adaptive Dead-Time Control of a Synchronous Buck Converter

Abstract

A switched-mode power supply (SMPS) gradually increases the duty cycle during startup while reducing the initial dead time to a final optimal dead time for normal operation. A larger initial dead time improves reliability and reduces ringing of the switching transistor under low voltage conditions early in the startup process. As the voltage approaches the operating level, efficiency is improved by reducing the optimal dead time. The initial dead time is pre-calculated as a function of the input voltage and the initial duty cycle. The optimal dead time is pre-calculated as a function of the output voltage and the output current. The optimal dead time is adjusted during each iteration of a second loop that also increases the duty cycle until a target operating output voltage is reached. The pre-calculated dead time is based on the time required for the parasitic drain-to-source capacitance of the switching transistor in the SMPS circuit to fully charge and discharge.

Description

Technical Field

[0001] The present invention relates to a power converter, and more particularly to a startup process for preventing ringing in a switched - mode power supply (SMPS). Background Art

[0002] Power converters such as DC - DC converters are widely used. A switched - mode power supply (SMPS) rapidly turns transistors on and off to charge an output capacitor to a desired output voltage. Controlling such switches to efficiently obtain the desired output voltage, especially when charging the converter, can be very difficult.

[0003] Figure 1 Shows a switched - mode power supply (SMPS) of the prior art. The input power supply voltage VIN+ is to be converted to an output power supply voltage VOUT+. Both the input and output use a common ground GND, but some systems have separate grounds.

[0004] The input capacitor 320 between VIN+ and GND filters the input to the drains of the pull - up transistors 302, 306, while the ground is connected to the sources of the pull - down transistors 304, 308. The source of the pull - up transistor 302 and the drain of the pull - down transistor 304 are connected together to drive VOUT+ through an inductor 312 to charge the output capacitor 330.

[0005] The gate G1 of the pull - up transistor 302 is driven high to turn on the transistor 302 for a period of time to charge the output capacitor 330. Once G1 is driven low, the gate of the pull - down transistor 304 is driven high to discharge the output capacitor 330. The signals of G1, G2 are typically clock signals in the kHz frequency range, and the duty cycle is adjusted for a specific input voltage VIN+ to obtain the desired output voltage VOUT+. For example, a higher VOUT+ can be obtained by increasing the high - level time (duty cycle) of G1 relative to G2.

[0006] Similarly, the source of the pull - up transistor 306 and the drain of the pull - down transistor 308 are connected together to drive VOUT+ through an inductor 314 to charge the output capacitor 330. The switching signals applied to the gates of the transistors 306, 308 can be 180 degrees out of phase with the switching signals driving the gates of the transistors 302, 304 to reduce the output ripple.

[0007] Transistors 302, 304, 306, and 308 can be n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), but gallium nitride (GaN) transistors are recently being used because they can provide higher currents for a given physical transistor size. GaN transistors allow for higher-density power converter modules because, for a given size, using GaN devices can provide a higher power current. Compared to MOS transistors, GaN transistors have a smaller input capacitance, providing a faster switching response time and enabling higher-frequency applications. Lower switching losses result in better efficiency.

[0008] Figure 2 Show Figure 1 The operating waveform of the SMPS. The gate voltage G1 of transistor 302 pulses to a high level to charge the output capacitor 330, and then the gate voltage G2 of transistor 304 pulses to a high level to discharge the output capacitor 330. The waveforms of G3 and G4 have a 180-degree phase delay compared to the waveforms of G1 and G2.

[0009] To prevent the two transistors 302 and 304 from being turned on simultaneously, a dead time TDEAD is added before the rise of G2 and before the rise of G1. Although these dead times may vary, they are typically set to the same value. If the two transistors 302 and 304 are turned on simultaneously, this dead time can prevent the occurrence of a current path from the power supply to ground. If no dead time is added or the dead time is too short, high current spikes may occur, which may cause heating and damage to transistors 302 and 304. A too-long dead time is also not advisable because it reduces the available pulse high-level time at any given switching frequency; thus, the efficiency decreases as the dead time increases.

[0010] Figure 3 Is Figure 1 The waveform of the SMPS startup. The operation of starting the SMPS can be tricky. When the power supply is turned on at time T0, the voltage and current are initially zero. The input voltage VIN generated by the system power supply rises until it reaches a high enough value at time T1, for example, within 5% of the target steady-state input voltage. Then, a cool-down (CD) delay is provided before turning on the SMPS at time T2. G1 - G4 start to switch on and off, but the duty cycle is very low and gradually increases until time TN. As this duty cycle increases, both the output voltage VOUT and the output current IOUT increase. Finally, at time TN, the duty cycle remains basically constant, and VOUT has reached the target output voltage. Normal operation can now be carried out after time TN.

[0011] Figure 4Waveforms showing that ringing problems may occur during startup when using GaN transistors in a SMPS. Simply replacing MOS transistors with GaN transistors in a SMPS causes problems. The inventors noticed that when using GaN transistors, ringing problems occur during startup of the SMPS.

[0012] When G1 goes low and turns off transistor 302, due to inductor 312 resisting the sudden change in current, the current continues to flow during this first dead time. The energy stored in the magnetic field around inductor 312 is released back into the circuit. The voltage across inductor 312 is now of the opposite polarity to the voltage across inductor 312 during the "on" period, and the current is forced to flow through the body diode of transistor 304 for a short time. Then, transistor 304 will be turned on to continue providing current to the load.

[0013] When G1 is high, transistor 302 is turned on, and G2 is low, transistor 304 is turned off, the voltage VDS(Q1) across the pull-up transistor 302 is close to zero. When G1 goes low, VDS(Q1) starts to rise, turning off transistor 302. When G2 is low, the voltage VDS(Q2) across the pull-down transistor 304 is large, turning off transistor 304. G1 going high turns on transistor 304, but when G1 goes low, VDS(Q2) starts to fall, turning off transistor 302. The current is pulled out of the intermediate node VM between transistors 302 and 304 by inductor 312.

[0014] This current charges the parasitic drain-to-source capacitor in transistor 302 (VDS Q1) and discharges the parasitic drain-to-source capacitor in transistor 304 (VDS Q2) during the first dead time.

[0015] When G2 goes high and turns on the pull-down transistor 304, the first dead time ends, and VDS(Q2) rapidly drops to zero. The voltage of the intermediate node VM drops to zero, causing the parasitic capacitance of the pull-up transistor 302 to be charged, and VDS Q1 rises to a high value.

[0016] The actual waveforms of VDS Q1 and VDS Q2 are more complex. The inventors noticed that if the VDS of transistor 304 does not drop to zero, or the VDS of transistor 302 does not rise to Vin during the dead time, then ringing occurs in the simulation when G2 goes high and the pull-down transistor 304 is turned on. This ringing of the intermediate node VM and the drain-to-source voltages of transistors 302 and 304 is considered to be caused by the resonant circuit of inductor 312 and the parasitic capacitance and inductance of transistors 302 and 304.

[0017] This ringing is undesirable because the high ringing current can spike and potentially damage the GaN transistor and other components. High ringing can cause ringing on both sides of the gate-source voltage (VGS) and may erroneously trigger the turn-on of the other side GaN transistor. Due to this ringing, the reliability of the SMPS may be reduced. This ringing is notoriously difficult to detect and observe, making this reliability issue even more difficult to solve.

[0018] The inventors have noticed that this ringing occurs during shorter values of dead time. Longer values of dead time can reduce or eliminate the ringing. However, a longer dead time reduces the efficiency of the SMPS. Therefore, it is not advisable to choose a larger dead time to prevent ringing.

[0019] There is a need for a startup process for the SMPS. There is a need for a startup process that can dynamically adjust the dead time as the conditions during startup change. There is a need for a startup process that can reduce the ringing of the GaN transistor when the SMPS is powered up to a higher output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Showing a switching mode power supply (SMPS) of the prior art.

[0021] Figure 2 Showing Figure 1 the operating waveforms of the SMPS.

[0022] Figure 3 Showing Figure 1 the startup waveforms of the SMPS.

[0023] Figure 4 Showing waveforms where ringing problems may occur during startup when using a GaN transistor in the SMPS.

[0024] Figure 5 Showing Figures 7A - 7B the waveforms with reduced ringing when implementing the

[0025] Figure 6 Showing Figure 1 the waveforms when the SMPS starts up.

[0026] Figures 7A - 7B Showing a flowchart of the SMPS startup process that optimizes the dead time to reduce ringing when the duty cycle increases.

[0027] Figure 8 Showing a graph of a first function for obtaining an initial dead time.

[0028] Figure 9 Showing a graph of a second function for obtaining an optimal dead time.

[0029] Figure 10 Schematic diagram showing parasitic capacitance and parasitic inductance in a buck converter in a SMPS. Detailed implementation

[0030] The present invention relates to an improvement in the startup of a SMPS. The following description is to enable a person of ordinary skill in the art to make and use the present invention in the context of a particular application and its requirements. Various modifications to the preferred embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments. Therefore, the present invention is not intended to be limited to the specific embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0031] The inventors have noticed that ringing occurs in simulations when G2 goes high and the pull - down transistor 304 ( Figure 1 ) turns on. This ringing of the intermediate node VM and the drain - to - source voltages of transistors 302, 304 is thought to be caused by the resonant circuit of inductor 312 and the parasitic capacitance and inductance of transistors 302, 304.

[0032] The inventors further note that this ringing occurs at short values of dead time. In the case of a longer dead time, this ringing can be reduced or eliminated. Eliminating the ringing can improve long - term reliability. However, a longer dead time is not desirable because it reduces the efficiency of the SMPS.

[0033] The present inventors hypothesize that for short dead times, the parasitic drain - to - source capacitances of transistors 302, 304 are not fully charged or discharged during that dead time. The present inventors propose to adjust the dead time to be long enough to fully charge and discharge these parasitic drain - to - source capacitances.

[0034] However, the dead time required to fully charge and discharge these parasitic capacitances is a complex function of circuit conditions such as input voltage, output voltage, output current, and duty cycle. These circuit conditions vary during startup.

[0035] The inventors have developed a startup process ( Figures 7A - 7B ) that, when the SMPS is first activated during startup, selects an initial dead time ( Figure 8 ) based on the input voltage and an initial duty cycle. Then as the duty cycle increases, the output voltage rises to a first target, and as the duty cycle continues to increase, the dead time is adjusted as a function of the output voltage and output current.

[0036] These functions ( Figure 8 , 9) is pre-calculated based on the dead time required for the parasitic drain-to-source capacitance on the GaN transistor in the SMPS circuit to fully charge and discharge. Considering the dimensions of the GaN transistor and other circuit components, the estimated parasitic capacitance and inductance, the input voltage, the output voltage, and the output current, as well as application operating parameters such as the current duty cycle, calculations can be performed using circuit simulation software such as MATLAB.

[0037] Figure 5 Shown during the startup process of Figures 7A - 7B is a waveform that reduces ringing. The dead time TDEAD is initially selected as a relatively long value, which is effective for normal operation. However, this longer dead time provides sufficient charging and discharging time for the parasitic drain-to-source capacitance of the GaN transistor in the SMPS circuit. Compared with Figure 4 the shorter dead time, this longer dead time allows these parasitic capacitances to fully charge and discharge, thus reducing the ringing on the actual VDS(Q1) and VDS(Q2) waveforms.

[0038] Figure 6 is the waveform of starting up the Figures 7A - 7B SMPS using the process of Figure 1 When power is turned on at time T0, the voltage and current are initially zero. The input voltage VIN generated by the system power supply rises until it reaches a sufficiently high value at time T1, for example, within 5% of the target steady-state input voltage. Then a cooling (CD) delay is provided before turning on the SMPS at time T2. G1 - G4 start switching, but the duty cycle is very low and then gradually increases until time TN. As this duty cycle increases, both the output voltage VOUT and the output current IOUT increase.

[0039] At time T2 when the SMPS is first turned on and VOUT and IOUT are at low values, the dead time is initially set to a high value. Lower VOUT values tend to produce more ringing compared to higher VOUT and IOUT values. As the duty cycle gradually increases, using the initial dead time and keeping it constant, the first process of Figure 7A is executed and looped.

[0040] Once the output voltage VOUT reaches the first target, as the duty cycle continues to increase, the second loop of Figure 7B is executed. For each iteration of the second loop, the optimal dead time for the current conditions of VOUT and IOUT is determined by Figure 9Determined by functions or graphs. As the duty cycle increases, the output current and output voltage continue to increase, and this optimal dead time also decreases. Once the output voltage reaches the second target, at time TN, the startup ends and the SMPS starts normal operation. During normal operation, the duty cycle remains basically constant, but can be slightly adjusted to maintain the target VOUT as the temperature, power supply voltage, or other conditions fluctuate.

[0041] Figures 7A - 7B A flowchart showing the SMPS startup process, which optimizes the dead time as the duty cycle increases to reduce ringing. In Figure 7A When the system is powered on, the input voltage VIN rises from zero and may be unstable or too low to be used safely. After the input voltage VIN reaches the brown-in voltage V_BROWN (step 202), an additional cooling (CD) delay is allowed to ensure that VIN is stable (step 204), and then the input voltage VIN is measured (step 206) to obtain the initial duty cycle for the controller to generate G1 - G4, for example, obtained from firmware. The initial duty cycle can be selected according to the topology of the circuit application. For example, the initial duty cycle of an LLC resonant converter may be 50%, while that of a buck converter may be <1%.

[0042] Using the measured VIN and the initial duty cycle, the initial dead time to be used is obtained from the first function (step 208). This first function can be stored in a lookup table of function results. These first function results are Figure 8 shown graphically in and can be pre-calculated for a range of possible values of VIN and the initial duty cycle and stored in the firmware.

[0043] The controller generates the gate signals G1 - G4 at a predetermined frequency and the initial duty cycle (step 214). These gate signals G1 - G4 are applied to the GaN transistors 302 - 308 ( Figure 1 ). The controller or other logic inserts the initial dead time obtained in step 208 before and after each pulse of G1 - G4.

[0044] The controller continues to pulse G1 - G4 for a period of time, allowing the SMPS to increase the output voltage by increasing the duty cycle as the output capacitor 330 is charged by the output current. After a period of time, the output voltage is measured and compared with the first output voltage target VSET1. When the output voltage is still lower than VSET1 (step 216), the first cycle is repeated. The duty cycle is increased (step 212), and the controller adjusts the pulses of G1 - G4 according to the new duty cycle with the same frequency and the initial dead time (step 214).

[0045] Finally, as the duty cycle increases and the pull-up transistor 302 is pulsed on for a longer period of time, the output voltage VOUT rises above the first output voltage target VSET1. When the output voltage is higher than VSET1 (step 216), the first cycle ends. The process continues with Figure 7B the second cycle in

[0046] In Figure 7B , the output current IOUT and the output voltage VOUT are measured (step 226). Using the measured IOUT and VOUT, the optimal dead time to be used is obtained from a second function (step 228). This second function can be stored in a look-up table of function results that are graphically displayed in Figure 9 . Instead of calculating the function results at startup or runtime, the possible value ranges of IOUT and VOUT are pre-calculated and stored in the firmware.

[0047] The duty cycle is increased (step 232), and the controller adjusts the pulses of G1 - G4 at the same frequency according to the new optimal dead time and the newly increased duty cycle (step 234). These adjusted gate signals G1 - G4 are applied to the GaN transistors 302 - 308 ( Figure 1 ).

[0048] The controller continues to pulse G1 - G4 for a period of time, allowing the SMPS to increase the output voltage by increasing the duty cycle as the output capacitor 330 continues to be charged by the output current. After a period of time, the output voltage is measured and compared with the second output voltage target VSET2. When the output voltage is still lower than VSET2 (step 236), the second cycle is repeated. VOUT and IOUT are measured (step 226) and used to obtain the optimal dead time under the new conditions (step 228). The duty cycle is increased again (step 232), and the controller adjusts the generated pulses of G1 - G4 (step 234).

[0049] Finally, as the duty cycle increases and the pull-up transistor 302 is pulsed on for an even longer time, the output voltage VOUT rises above the second output voltage target VSET2. When the output voltage is higher than VSET2 (step 236), the second cycle ends. Normal operation 240 can begin. VOUT can be used by downstream devices.

[0050] Figure 8It is a diagram of the first function for obtaining the initial dead time. The initial dead time is calculated as a first function of the initial duty cycle and the input voltage VIN. The surface 902 of the result of the first function shows that for a smaller initial duty cycle, a higher initial dead time is required. Compared with a larger VIN value, a lower VIN value also requires a slightly higher initial duty cycle, but this is a weaker dependency compared to the initial duty cycle.

[0051] The result value of the first function is obtained through Figure 10 circuit simulation or by using Equation (4) shown later. The initial dead time is the time required for the parasitic drain-to-source capacitance of the GaN transistor in the SMPS circuit to be fully charged and discharged.

[0052] Figure 9 It is a diagram of the second function for obtaining the optimal dead time. The optimal dead time is calculated as a second function of the output current IOUT and the output voltage VOUT. The surface 904 of the result of the second function shows that for a lower output voltage VOUT and for a lower output current IOUT, a higher optimal dead time is required.

[0053] The result value of the second function is obtained through Figure 10 circuit simulation or by using Equations (1) and (4) shown later. The optimal dead time is the time required for the parasitic drain-to-source capacitance of the GaN transistor in the SMPS circuit to be fully charged and discharged. A higher output voltage VOUT greatly reduces the optimal dead time. Therefore, as VOUT rises, the dead time can be reduced when the SMPS starts up.

[0054] Figure 10 It is a schematic diagram of the parasitic capacitance and parasitic inductance of the buck converter in the SMPS. In Figure 1 the simplified diagram of the interleaved buck converter shown, only the GaN transistors 302 and 304 are shown. The GaN transistors 302 and 304 drive current to the intermediate node VM, and then charge the output capacitor 330 through the inductor 312 to generate the output voltage VOUT.

[0055] The GaN transistor 302 receives G1 from the controller at its gate and is in series with the parasitic drain-to-source inductor 376 on its channel current path. The parasitic capacitor 372 is charged when the transistor 302 is turned off and discharged when the transistor 302 is turned on. When VM is greater than the diode conduction voltage higher than VIN, the diode 371 allows reverse current to flow. There may be additional parasitic inductors (not shown) to the power supply on the drain of the transistor 302 and the source of the transistor 304.

[0056] The GaN transistor 304 receives G2 from the controller at its gate and is in series with the parasitic drain - source inductance 378 on its channel current path. The parasitic capacitor 374 is charged when the transistor 304 is off and discharged when the transistor 304 is on. The GaN transistor 304 has a diode - like behavior, which is simulated by the diode 373, allowing reverse current to flow when VM is greater than the diode conduction voltage below ground.

[0057] Circuit simulations can be performed Figure 10 to obtain the initial dead - time ( Figure 8 ) or the optimal dead - time ( Figure 9 ). These dead - times are the times required to fully charge and discharge the parasitic drain - to - source capacitance, the parasitic capacitor 372, and the parasitic capacitor 374.

[0058] During startup, the duty cycle is low. This means that the transistor 302 is off most of the time, and the transistor 304 is on most of the time. When the transistor 302 is on and the transistor 304 is off, the C2 capacitor 374 starts to charge. However, due to the short on - time of the transistor 302, the C2 capacitor 374 is charged to a low Vds, but the Coss is large (MOS characteristics at low Vds). During the dead - time period (both transistors 302 and 304 are off), the C1 capacitor 372 is charging while the C2 capacitor 374 is discharging. Due to the large Coss of the transistor 304, the transistor 304 requires a larger dead - time to discharge. If the dead - time is not large enough, the C2 capacitor 374 cannot be fully discharged or the C1 capacitor 372 cannot be fully charged. Then when the transistor 302 is off and the transistor 304 is on, ringing may occur at that time.

[0059] The equations here are for simulating the optimal dead - time for each stage of startup.

[0060] The dead - time can also be calculated using the following equation:

[0061]

[0062]

[0063] where I_L is the load current through the inductor 312, L0 is the inductance of the inductor 312, V0 is the output voltage, V in is the input voltage VIN, t is the dead - time (seconds), t on is the duty cycle, expressed as the high - pulse width of G1. C oss is the parasitic drain - to - source capacitance of the GaN transistor 302, and V C1 is the drain - to - source voltage of the transistor 302.

[0064] The first term in Equation (1) comes from the inductor equation V = Ldi / dt, while the second term in Equation (1) is the capacitor equation I = CdV / dt or V = 1 / C(int(V)dt.

[0065] By substituting Equation (1) into Equation (2) and solving the integral in Equation (2), we can obtain:

[0066]

[0067] In Figure 8 the curve of, with the initial dead time as a function of (Vin, initial duty cycle), we assume Vc1 = Vin as our target charging voltage Vc1 = Vin. During startup, Vo is a low voltage, so we set Vo to 0.1V. Then we have a second-order equation, and Lo and Coss are known from the circuit and MOS datasheets or specifications.

[0068]

[0069] Next, from Equation 4, we can plot the relationship between Vin, the initial duty cycle (ton), and the dead time t.

[0070] In Figure 9 the curve of, with the optimal dead time as a function of (Vout, Iout), we assume Vin is fixed and only the duty cycle (ton) and Vo are variable. Since the output current Iout is equal to IL, we can express Iout as a function of ton and Vo according to Equation (1).

[0071] By solving Equations (1) and (4), we can plot the relationship between Iout, Vout, and the dead time t, as shown in Figure 9 shown.

[0072] Alternative Embodiments

[0073] The inventors have also added several other embodiments. For example, with the emergence of new technologies for implementing switching transistors, GaN transistors can be replaced with other devices. Additional components can be added, such as to better filter the input or output. Different types of capacitors can be used. For inductors, different magnetic core materials and winding methods can be used.

[0074] Although n-channel transistors have been described, p-channel transistors can also be used to invert the gate signal. Complementary p and n channel devices can be used for the pull-up and pull-down transistors.

[0075] Although a synchronous buck converter has been shown, other types of power circuits can be used instead, such as LLC. A half-bridge or full-bridge converter and bridge switches (high-side and low-side switches) can be used. These circuits can use other values for the initial duty cycle, such as 50% for LLC instead of 1% for the buck converter.

[0076] Different values of VIN, VOUT, IOUT, duty cycle, and dead time can be substituted, and the targets can also have different values. For example, the fixed frequency can be 400 kHz, the initial duty cycle is 1%, the initial dead time is 200 ns, and the final optimal dead time is 40 ns, which is also for the normal operating mode. VIN can be 50 v, the final target Vout is 12 v, VSET1 is 3 v when the first cycle ends, and VSET2 is 12 v when the second cycle ends and the normal operating mode starts.

[0077] Other sensing and control components can be added. For example, as an example, for measuring the current or voltage of a power control system that can adjust the duty cycle of G1 - G4. Some power converters may only have transistors 302, 304 and not transistors 306, 308. Other variations of the power converter circuit are also possible.

[0078] The waveforms are ideal and simplified for easier understanding. The actual waveforms, whether measured or simulated, may be much more complex, with additional bends and wobbles.

[0079] The duty cycle can be increased by 1% in each iteration, or increased by some other amount, such as 0.1%, 0.5%, 2% or other values. The duty cycle can increase linearly over time rather than in discrete steps. For example, when the duty cycle increases from D1 to D2 at step 232 ( Figure 7B ), for each C clock cycle during the operation of step 234, the duty cycle can increase by (D2 - D1) / C. For each cycle, the increase in the duty cycle can be small, such as 1%, and many cycles can be used. The dead time can be reduced in a similar way over a period of time.

[0080] Although a linearly increasing duty cycle has been described, this increase can be a piece-wise-linear (PWL) increase with multiple linear segments. There may be flat times when the duty cycle does not increase between the increasing periods. The rate of increase can vary. Therefore, the curves of the duty cycle and dead time may be more complex than the curves shown in the simplified waveforms.

[0081] Full charge does not necessarily mean 100% charge. It can also be a smaller value, such as 90%. The RC time constant can be used to define capacitor charging. For 1xRC, the capacitor can be charged to 63%; for 4xRC, the capacitor can be charged to 98%. The value of 4xRC can be regarded as full charge. Full charge can refer to the time to reach the target voltage between the drain and the source. A guard band or buffer can be added to the calculated dead time to better prevent ringing under different conditions.

[0082] Although equations have been proposed, these equations can be solved to obtain Figure 8 、 9 the plotted results in, but these results can also be obtained through more careful circuit simulations, including the effects of various parasitic elements, such as Figure 10 the GaN transistor shown. Alternatively, these results can also be generated using a low-order model or a simplified model. Known values can be substituted into these models to further simplify the generation of the dead time results. For example, the initial dead time is a function of the initial duty cycle and the measured input voltage VIN. The initial duty cycle can be set in the firmware and is therefore known, simplifying the first function to a function with only one variable VIN. It can be assumed that VIN is stable after waiting for the CD delay, and the stable VIN value can be known. Then, for this VIN value, the initial dead time will be known. The first function can simply return the value of this pre-calculated initial dead time. The firmware can program using this initial dead time, or use a larger dead time value to allow for fluctuations in VIN. Therefore, the initial dead time can be determined in advance, so that there is no need to access Figure 8 the first graph during actual operation, nor is it necessary to execute the first function. An approximation of the initial dead time is sufficient. The first function can be approximated as independent of VIN and is only a function of the initial duty cycle. If the initial duty cycle is large enough, the influence of VIN is small. However, when the initial duty cycle is very low (<1%), VIN has a large influence and this approximation is useless.

[0083] The optimal dead time can be pre-calculated for several combinations of VOUT and IOUT, and the closest VOUT, IOUT combination can be selected according to the actually measured VOUT, IOUT combination, and the pre-calculated optimal dead time of this closest pre-calculated point can be used. The more pre-calculated points used, the higher the accuracy and efficiency of the SMPS. These pre-calculated points can store their optimal dead time results in a lookup table.

[0084] The optimal dead time can be recalculated or adjusted for each iteration of the second loop or at a lower rate (e.g., after every 5 iterations, etc.). The duty cycle can be adjusted at the same rate as the adjustment of the optimal duty cycle, or at a faster or slower rate. Various rearrangements can be made to the Figures 7A - 7B steps in, and other alternatives and modifications can be made to the process.

[0085] The background section of the present invention may contain background information on the problems or environment of the present invention, rather than describing the prior art of others. Therefore, the materials included in the background section are not an admission by the applicant of the prior art.

[0086] Any method or process described herein is machine-implemented or computer-implemented and is intended to be performed by a machine, computer, or other device, and is not intended to be performed solely by a human without machine assistance. The tangible results produced may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio generation devices, and associated media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result.

[0087] Any advantages and benefits described do not necessarily apply to all embodiments of the present invention. When the term "means" appears in a claim element, the applicant intends that the claim element falls within the provisions of 35 USC Section 112, Paragraph 6. Generally, there is a label of one or more words before the term "means". One or more words before the term "means" are a label for the purpose of facilitating reference to the claim element and not for expressing a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although nails and screws have different constructions, they are equivalent structures because they both perform the fastening function. Claims that do not use the term "means" do not fall within the provisions of 35 USC Section 112, Paragraph 6. A signal is generally an electrical signal, but can also be an optical signal, for example, which can be transmitted through an optical fiber line.

[0088] The above description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The intention is that the scope of the present invention not be limited by this detailed description, but rather by the limitations appended to the claims.

Claims

1. A method for starting a switched - mode power supply (SMPS), comprising: Waiting upon power - on until the input voltage reaches a first target voltage; Setting a duty cycle to an initial duty cycle; Generating an initial dead - time from the input voltage and the initial duty cycle; (a) Generating a first switching signal and a second switching signal having a fixed frequency, and generating the first switching signal having the duty cycle, generating the first switching signal and the second switching signal having the initial dead - time, the initial dead - time being between the turn - off edge of the first switching signal and the turn - on edge of the second switching signal, wherein the first switching signal and the second switching signal are complementary and non - overlapping due to the initial dead - time; Applying the first switching signal to the gate of an upper - pull transistor, the upper - pull transistor conducting current between the input voltage and an intermediate node, driving an output capacitor through an inductor to generate an output voltage; Applying the second switching signal to the gate of a lower - pull transistor, the lower - pull transistor conducting current between ground and the intermediate node, driving the output capacitor through the inductor to generate the output voltage; Comparing the output voltage with a first set value, increasing the duty cycle, and repeating from (a) when the output voltage is lower than the first set value; When the output voltage is no longer lower than the first set value: (b) Measuring the output voltage and the output current; Obtaining an optimal dead - time using the output voltage and the output current; Increasing the duty cycle; Generating the first switching signal and the second switching signal having the fixed frequency, generating the first switching signal having the duty cycle, generating the first switching signal and the second switching signal having the optimal dead - time, the optimal dead - time being between the turn - off edge of the first switching signal and the turn - on edge of the second switching signal, wherein the first switching signal and the second switching signal are complementary and non - overlapping due to the optimal dead - time; Applying the first switching signal to the gate of the upper - pull transistor; Applying the second switching signal to the gate of the lower - pull transistor; Comparing the output voltage with a second set value, and repeating from (b) when the output voltage is lower than the second set value; When the output voltage is no longer lower than the second set value, operating the SMPS in a normal operating mode using the duty cycle and the optimal dead - time to generate the first switching signal and the second switching signal.

2. The method according to claim 1, wherein the optimal dead - time is less than the initial dead - time.

3. The method according to claim 2, wherein the second set value is the target output voltage of the normal operating mode of the SMPS.

4. The method according to claim 2, wherein the initial dead - time is sufficient to discharge the parasitic drain - to - source capacitance in the lower - pull transistor.

5. The method according to claim 2, wherein the initial dead time is sufficient to eliminate ringing of the pull - down transistor; wherein the optimal dead time is shorter than the initial dead time, and the optimal dead time is short enough to cause ringing of the pull - down transistor under the initial conditions of the input voltage, duty cycle, and output voltage; thereby avoiding ringing under the initial conditions, while still using the optimal dead time to improve efficiency in the normal operating mode.

6. The method according to claim 5, wherein the duty cycle increases linearly over a period of time.

7. The method according to claim 5, wherein when the optimal dead time is reduced, the optimal dead time linearly decreases in successive iterations of the second cycle starting from (b); Among them, the optimal dead time is continuously and linearly reduced.

8. The method according to claim 2, wherein the optimal dead time during the normal operating mode is less than one - quarter of the initial dead time.

9. The method according to claim 2, further comprising: generating a third switching signal that is 180 degrees out of phase with the first switching signal; generating a fourth switching signal that is 180 degrees out of phase with the second switching signal; applying the third switching signal to the gate of a second pull - up transistor, the second pull - up transistor conducting current between the input voltage and a second intermediate node, driving the output capacitor through a second inductor to further generate the output voltage; applying the fourth switching signal to the gate of a second pull - down transistor, the second pull - down transistor conducting current between ground and the second intermediate node.

10. The method according to claim 2, further comprising: waiting for an additional delay after the input voltage reaches the first target voltage, and then (a) generating the first switching signal and the second switching signal.

11. The method according to claim 2, wherein obtaining the optimal dead time using the output voltage and the output current further comprises: reading a second look - up table indexed by the output voltage and the output current, the second look - up table returning the optimal dead time as a stored result.

12. The method according to claim 11, wherein the optimal dead time stored in the second look - up table is pre - calculated as the amount of time required to discharge the parasitic drain - to - source capacitance in the pull - down transistor.

13. The method according to claim 11, wherein generating the initial dead time from the input voltage and the initial duty cycle further comprises: reading a first look - up table indexed by the input voltage and the initial duty cycle, the first look - up table returning the initial dead time as a stored result.

14. The method according to claim 13, wherein the initial dead time stored in the first look - up table is pre - calculated as the amount of time required to discharge the parasitic drain - to - source capacitance in the pull - down transistor.

15. An adaptive dead - time controller for starting a switched - mode power supply (SMPS), comprising: An initializer that waits for an input voltage to reach a stable target over a period of time; A first dead-time generator for generating an initial dead time as a function of the input voltage and a duty cycle, the duty cycle being set to an initial duty cycle; A pulse generator that generates a first switching signal having a fixed frequency and the duty cycle, and generates a second switching signal having the fixed frequency, the second switching signal being the inverse of the first switching signal, the initial dead time being inserted as a dead time to prevent overlap with the first switching signal; The first switching signal is applied to the gate of a first switching transistor in the SMPS; The second switching signal is applied to the gate of a second switching transistor in the SMPS; wherein the first switching transistor and the second switching transistor are connected to generate an output voltage and an output current; A first output comparator that compares the output voltage with a first set voltage and issues a signal indicating the end of the first cycle when the output voltage reaches the first set voltage; A duty-cycle increaser for increasing the duty cycle applied to the pulse generator; A second dead-time generator that is activated after the signal indicating the end of the first cycle and is used for each iteration of a second cycle to generate an optimal dead time using the values of the output voltage and the output current, the second dead-time generator sending the optimal dead time to the pulse generator to override the dead time; A second output comparator that compares the output voltage with a second set voltage and issues a signal indicating the end of the second cycle when the output voltage reaches the second set voltage.

16. The adaptive dead-time controller according to claim 15, wherein the first dead-time generator includes a look-up table, the entries of which contain pre-computed dead-time values that are pre-computed as a function of the input voltage and the duty cycle.

17. The adaptive dead-time controller according to claim 15, wherein the second dead-time generator includes a look-up table, the entries of which contain pre-computed dead-time values that are pre-computed as a function of the output voltage and the output current.

18. The adaptive dead-time controller according to claim 17, wherein the dead time stored in the look-up table is pre-computed as the amount of time required to discharge the parasitic drain-to-source capacitance in the second switching transistor.

19. A switched-mode power supply (SMPS) for reducing ringing, comprising: A pull-up transistor connected between an input voltage and an intermediate node, the gate of which is driven by a first switching signal; A pull-down transistor connected between ground and the intermediate node, the gate of which is driven by a second switching signal; An inductor connected between the intermediate node and an output node having an output voltage, wherein an output current flows through the inductor; An initializer for waiting for an input voltage to reach a stable target; A first dead-time generator for generating an initial dead time as a function of the input voltage and a duty cycle set to an initial duty cycle; A pulse generator that generates the first switching signal having a fixed frequency and the duty cycle, and generates the second switching signal having the fixed frequency, the second switching signal being the inverse of the first switching signal, and the initial dead time is inserted therein to prevent overlap with the first switching signal; A first output comparator that compares the output voltage with a first set voltage and issues a signal indicating the end of the first cycle when the output voltage reaches the first set voltage; A duty cycle increaser for increasing the duty cycle applied to the pulse generator; A second dead-time generator that is activated after the signal indicating the end of the first cycle and is used for each iteration of the second cycle to generate an optimal dead time using the values of the output voltage and the output current, and the second dead-time generator sends the optimal dead time to the pulse generator to overwrite the dead time; A second output comparator that compares the output voltage with a second set voltage and issues a signal indicating the end of the second cycle when the output voltage reaches the second set voltage.

20. The SMPS for reducing ringing according to claim 19, wherein the pull-up transistor and the pull-down transistor comprise gallium nitride (GaN) transistors.

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