Imaging device and electronic device

Abstract

An imaging device can be reduced in size in an in-plane direction without degrading operational performance. The imaging device includes a first pixel and a second pixel. The first pixel has m (m represents an integer not less than 2) first wirings and m first gate electrodes connected to the m first wirings, respectively. The second pixel has n (n represents a natural number smaller than m) second wirings and n second gate electrodes connected to the n second wirings, respectively.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an imaging device that performs imaging by performing photoelectric conversion, and an electronic apparatus including the imaging device. BACKGROUND

[0002] The applicant of the present application has proposed an imaging device including a silicon substrate having a stacked structure in which a photodiode and a memory are stacked in a light incident direction (see, for example, PTL 1).

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] PTL 1: International Publication No. WO 2016 / 136486 SUMMARY

[0006] Incidentally, such an imaging device is required to have a small size in a direction orthogonal to the light incident direction.

[0007] Therefore, it is desirable to provide an imaging device that allows downsizing in the in-plane direction without impairing the operation performance, and an electronic apparatus including the imaging device.

[0008] An imaging device according to an embodiment of the present disclosure includes a first pixel and a second pixel. The first pixel includes m (m represents an integer greater than or equal to 2) first wirings and m first gate electrodes connected to the m first wirings, respectively. The second pixel includes n (n represents a natural number smaller than m) second wirings and n second gate electrodes connected to the n second wirings, respectively.

[0009] Further, an electronic apparatus according to an embodiment of the present disclosure includes the imaging device described above. BRIEF DESCRIPTION OF DRAWINGS

[0010] FIG. 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present disclosure.

[0011] FIG. 2 is a circuit diagram showing a circuit configuration of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1 is a circuit diagram showing a circuit configuration of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in

[0012] FIG. 3A is a first schematic sectional view of a section in a stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1 is a first schematic sectional view of a section in a stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in

[0013] FIG. 3B is a first schematic sectional view of a section in a stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1A second schematic cross-sectional view of a cross section orthogonal to the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1.

[0014] FIG. 4A is a first schematic cross-sectional view of a cross section orthogonal to the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1. FIG. 1

[0015] FIG. 4B is a second schematic cross-sectional view of a cross section orthogonal to the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1. FIG. 1

[0016] FIG. 4C is a third schematic cross-sectional view of a cross section orthogonal to the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1. FIG. 1

[0017] FIG. 4D is a fourth schematic cross-sectional view of a cross section orthogonal to the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1. FIG. 1

[0018] FIG. 4E is a fifth schematic cross-sectional view of a cross section orthogonal to the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1. FIG. 1

[0019] FIG. 4F is a sixth schematic cross-sectional view of a cross section orthogonal to the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1. FIG. 1

[0020] FIG. 4G is a seventh schematic cross-sectional view of a cross section orthogonal to the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1. FIG. 1

[0021] FIG. 4H is an eighth schematic cross-sectional view of a cross section orthogonal to the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 1. FIG. 1

[0022] FIG. 4I is a schematic view showing an example of a layout of sensor pixels in a pixel array unit.

[0023] FIG. 5 ​​​​​​​​is a circuit diagram showing a circuit configuration of one normal pixel and one phase difference detection pixel in a solid-state imaging device according to a first modification of the present disclosure.

[0024] FIG. 6A is a first schematic sectional view of a section along a stacking direction of one normal pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 5

[0025] FIG. 6B is a second schematic sectional view of a section along a stacking direction of one normal pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 5

[0026] FIG. 7 is a schematic sectional view of a section orthogonal to a stacking direction of one normal pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 5

[0027] FIG. 8 is a circuit diagram showing a circuit configuration of one normal pixel and one phase difference detection pixel in a solid-state imaging device according to a second modification of the present disclosure.

[0028] FIG. 9A is a first schematic sectional view of a section along a stacking direction of one normal pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 8

[0029] FIG. 9B is a second schematic sectional view of a section along a stacking direction of one normal pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 8

[0030] FIG. 10 is a schematic sectional view of a section orthogonal to a stacking direction of one normal pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 8

[0031] FIG. 11 is a circuit diagram showing a circuit configuration of one normal pixel and one phase difference detection pixel in a solid-state imaging device according to a third modification of the present disclosure.

[0032] FIG. 12A is a first schematic sectional view of a section along a stacking direction of one normal pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 11

[0033] FIG. 12B is a second schematic sectional view of a section along a stacking direction of one normal pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 11 ​​​​​​​The image shows a second schematic cross-sectional view of the stacking direction of a normal pixel and a phase difference detection pixel in a solid-state imaging device.

[0034] FIG. 13 Is with FIG. 11 The diagram shows a schematic cross-sectional view of a regular pixel and a phase difference detection pixel in a solid-state imaging device, with their stacking directions orthogonal.

[0035] FIG. 14 This is a circuit diagram showing the circuit configuration of a common pixel and a phase difference detection pixel in a solid-state imaging apparatus according to a fourth variation of the present disclosure.

[0036] FIG. 15A It is along FIG. 14 The image shows a first schematic cross-sectional view of the stacking direction of a normal pixel and a phase difference detection pixel in a solid-state imaging device.

[0037] FIG. 15B It is along FIG. 14 The image shows a second schematic cross-sectional view of the stacking direction of a normal pixel and a phase difference detection pixel in a solid-state imaging device.

[0038] FIG. 16 Is with FIG. 14 The diagram shows a schematic cross-sectional view of a regular pixel and a phase difference detection pixel in a solid-state imaging device, with their stacking directions orthogonal.

[0039] FIG. 17 This is a circuit diagram showing the circuit configuration of a common pixel and a phase difference detection pixel in a solid-state imaging apparatus according to a fifth variation of the present disclosure.

[0040] FIG. 18A It is along FIG. 17 The image shows a first schematic cross-sectional view of the stacking direction of a normal pixel and a phase difference detection pixel in a solid-state imaging device.

[0041] FIG. 18B It is along FIG. 17 The image shows a second schematic cross-sectional view of the stacking direction of a normal pixel and a phase difference detection pixel in a solid-state imaging device.

[0042] FIG. 19 Is with FIG. 17 The diagram shows a schematic cross-sectional view of a regular pixel and a phase difference detection pixel in a solid-state imaging device, with their stacking directions orthogonal.

[0043] FIG. 20This is a circuit diagram showing the circuit configuration of a common pixel and a phase difference detection pixel in a solid-state imaging apparatus according to a sixth variation of the present disclosure.

[0044] FIG. 21A It is along FIG. 20 The image shows a first schematic cross-sectional view of the stacking direction of a normal pixel and a phase difference detection pixel in a solid-state imaging device.

[0045] FIG. 21B It is along FIG. 20 The image shows a second schematic cross-sectional view of the stacking direction of a normal pixel and a phase difference detection pixel in a solid-state imaging device.

[0046] FIG. 22 Is with FIG. 20 The diagram shows a schematic cross-sectional view of a regular pixel and a phase difference detection pixel in a solid-state imaging device, with their stacking directions orthogonal.

[0047] FIG. 23 This is a circuit diagram illustrating the circuit configuration of a common pixel and a phase difference detection pixel in a solid-state imaging apparatus according to a second embodiment of the present disclosure.

[0048] FIG. 24 It is along FIG. 23 The diagram shows a schematic cross-sectional view of the stacking direction of a normal pixel and a phase difference detection pixel in a solid-state imaging device.

[0049] FIG. 25 yes FIG. 23 The diagram shows a schematic planar view of the planar configuration of the front surface of a semiconductor substrate in a solid-state imaging device.

[0050] FIG. 26 This is a circuit diagram showing the circuit configuration of a common pixel and a phase difference detection pixel in a solid-state imaging apparatus according to a seventh variation of the present disclosure.

[0051] FIG. 27 It is along FIG. 26 The diagram shows a schematic cross-sectional view of the stacking direction of a normal pixel and a phase difference detection pixel in a solid-state imaging device.

[0052] FIG. 28 yes FIG. 26 The diagram shows a schematic planar view of the planar configuration of the front surface of a semiconductor substrate in a solid-state imaging device.

[0053] FIG. 29 This is a circuit diagram of a circuit configuration of a common pixel and a phase difference detection pixel in a solid-state imaging apparatus according to the eighth modification of this disclosure.

[0054] FIG. 30 is a schematic cross-sectional view of a cross section along the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 29

[0055] FIG. 31 is a schematic plan view of a planar configuration of a front surface of a semiconductor substrate in the solid-state imaging device shown in FIG. 29

[0056] FIG. 32 is a circuit diagram showing a circuit configuration of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device according to the ninth modification example of the present disclosure.

[0057] FIG. 33 is a schematic cross-sectional view of a cross section along the stacking direction of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device shown in FIG. 32

[0058] FIG. 34 is a schematic plan view of a planar configuration of a front surface of a semiconductor substrate in the solid-state imaging device shown in FIG. 32

[0059] FIG. 35 is a schematic diagram showing an example of an overall configuration of an electronic device.

[0060] FIG. 36 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0061] FIG. 37 is a diagram that assists in explaining an example of a mounting position of an outside-vehicle information detection unit and an imaging section.

[0062] FIG. 38 is a circuit diagram showing a circuit configuration of one ordinary pixel and one phase difference detection pixel in the solid-state imaging device according to the tenth modification example of the present disclosure.

[0063] FIG. 39 is a schematic plan view of a planar configuration of a front surface of a semiconductor substrate in the solid-state imaging device shown in FIG. 38

[0064] is a block diagram showing an example of a configuration of a solid-state imaging device according to the eleventh modification example of the present disclosure. FIG. 40A

[0065] is a block diagram showing an example of a configuration of a solid-state imaging device according to the twelfth modification example of the present disclosure. FIG. 40B

[0066] FIG. 41 ​​​​​is a schematic diagram showing an example of a layout of a sensor pixel in a pixel array unit according to a thirteenth modification of the present disclosure.

[0067] FIG. 42 is a schematic diagram showing an example of a layout of a sensor pixel in a pixel array unit according to a fourteenth modification of the present disclosure.

[0068] FIG. 43 is a schematic sectional view of a section along a stacking direction of one ordinary pixel and one phase difference detection pixel in a solid-state imaging device according to a fifteenth modification of the present disclosure.

[0069] FIG. 44 is a schematic diagram describing an off angle on a front surface of a Si substrate according to the present disclosure. DETAILED DESCRIPTION

[0070] An imaging pixel of a global shutter method (hereinafter, simply referred to as a global shutter pixel) described in PTL 1 described above requires a transistor that transfers a charge. This requires more transistors than an imaging pixel of a method other than the global shutter method (hereinafter, simply referred to as a non-global shutter pixel). Therefore, more signal lines are required to independently drive each of a plurality of global shutter pixels than to independently drive each of a plurality of non-global shutter pixels. Therefore, a larger number of signal lines are required in a case where a certain number of global shutter pixels are arranged in a region having a certain size than in a case where the same number of non-global shutter pixels are arranged. There is no choice but to reduce the width of each signal line or the pitch between a plurality of signal lines. Therefore, in addition to increasing the number of manufacturing steps and increasing the manufacturing time, problems such as an influence on the design of a drive circuit including a reduction in productivity and an increase in a time constant, an increase in a stabilization time, and the like can occur.

[0071] In view of these problems, the present disclosure is designed, and an object of the present disclosure is to provide an imaging device that allows downsizing in an in-plane direction without impairing operational performance and an electronic apparatus including the imaging device.

[0072] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Note that the description is made in the following order.

[0073] 1. First Embodiment

[0074] An example of a solid-state imaging device including an ordinary pixel and an image plane phase difference pixel as a MEM holding type global shutter pixel and in which a photoelectric conversion unit and a MEM are stacked.

[0075] 2. Modification of the First Embodiment

[0076] 2-1. First modification of the solid-state imaging device, in which the image plane phase difference pixel includes one less wiring than that for the normal pixel.

[0077] 2-2. Second modification of the solid-state imaging device, in which the image plane phase difference pixel includes one less wiring than that for the normal pixel.

[0078] 2-3. Third modification of the solid-state imaging device, in which the image plane phase difference pixel includes one less wiring than that for the normal pixel.

[0079] 2-4. Fourth modification of the solid-state imaging device, in which the image plane phase difference pixel includes two less wirings than that for the normal pixel.

[0080] 2-5. Fifth modification of the solid-state imaging device, in which the image plane phase difference pixel includes three less wirings than that for the normal pixel.

[0081] 2-6. Sixth modification of the solid-state imaging device, in which the image plane phase difference pixel includes four less wirings than that for the normal pixel.

[0082] 3. Second embodiment

[0083] Examples of the solid-state imaging device including the normal pixel and the image plane phase difference pixel and having the photoelectric conversion unit and the memory arranged in the same layer.

[0084] 4. Modification of the second embodiment

[0085] 4-1. Seventh modification of the solid-state imaging device, in which the image plane phase difference pixel includes three less wirings than that for the normal pixel.

[0086] 4-2. Eighth modification of the solid-state imaging device, in which the image plane phase difference pixel includes two less wirings than that for the normal pixel.

[0087] 4-3. Ninth modification of the solid-state imaging device, in which the image plane phase difference pixel includes one less wiring than that for the normal pixel.

[0088] 5. Application example of the electronic device

[0089] 6. Application example of the moving body

[0090] 7. Other modifications

[0091] Examples of the solid-state imaging device including the normal pixel and the image plane phase difference pixel as the FD hold type global shutter pixel and the like.

[0092] <1. First embodiment>

[0093] [Configuration of the solid-state imaging device 101]

[0094] FIG. 1 is a block diagram illustrating a functional configuration example of the solid-state imaging device 101 according to the first embodiment of the present technology.

[0095] The solid-state imaging device 101 is, for example, a back-illuminated image sensor of a so-called global shutter method such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The solid-state imaging device 101 receives light from a subject and performs photoelectric conversion. The solid-state imaging device 101 generates an image signal to capture an image.

[0096] The global shutter method is a method for performing global exposure in which exposure is started at substantially the same time for all pixels and exposure is ended at the same time for all pixels. Here, all pixels refer to all pixels present in a portion in an image and do not include dummy pixels and the like. Furthermore, the global shutter method also includes a method in which the region of global exposure is changed at the same time for a plurality of rows (for example, several tens of rows) instead of all pixels at the same time, in a case where a time difference or image distortion is small enough not to cause a problem. Furthermore, the global shutter method also includes a method in which global exposure is performed for pixels in a predetermined region instead of all pixels present in a portion in an image.

[0097] The back-illuminated image sensor refers to an image sensor having a configuration in which a photoelectric conversion unit such as a photodiode is disposed between a light-receiving surface and a wiring layer. The photoelectric conversion unit receives light from a subject and converts light into an electric signal. Light from a subject enters the light-receiving surface. The wiring layer is provided with a wiring that drives a transistor and the like for each pixel.

[0098] The solid-state imaging device 101 includes, for example, a pixel array unit 111, a vertical drive unit 112, a column signal processing unit 113, a data storage unit 119, a horizontal drive unit 114, a system control unit 115, and a signal processing unit 118.

[0099] In the solid-state imaging device 101, the pixel array unit 111 is formed on a semiconductor substrate 11 (described below). Peripheral circuits such as the vertical drive unit 112, the column signal processing unit 113, the data storage unit 119, the horizontal drive unit 114, the system control unit 115, and the signal processing unit 118 are disposed on the semiconductor substrate 11 as with the pixel array unit 111.

[0100] The pixel array unit 111 includes a plurality of sensor pixels PX each of which includes a photoelectric conversion unit PD (described below) that generates electric charges corresponding to the amount of light from a subject and accumulates the electric charges. As FIG. 1 As illustrated in the middle, the sensor pixels PX are arranged in both a horizontal direction (row direction) and a vertical direction (column direction). In the pixel array unit 111, a pixel drive line 116 is provided in the row direction for each of the pixel rows and a vertical signal line VSL is provided in the column direction for each of the pixel columns. Each of the pixel rows includes the sensor pixels PX arranged in a row in the row direction. Each of the pixel columns includes the sensor pixels PX arranged in a row in the column direction.

[0101] The vertical drive unit 112 includes a shift register, an address decoder, and the like. The vertical drive unit 112 simultaneously drives all of the plurality of sensor pixels PX in the pixel array unit 111 or drives the plurality of sensor pixels PX for each of the pixel rows by supplying a signal or the like to the plurality of sensor pixels PX via the plurality of pixel drive lines 116.

[0102] The signal output from each unit pixel in the selected row by the vertical drive unit 112 is supplied to the column signal processing unit 113 through each vertical signal line VSL. The column signal processing unit 113 performs predetermined signal processing on the signal output from each unit pixel in the selected row through the vertical signal line VSL for each pixel column of the pixel array unit 111 and temporarily holds the pixel signal subjected to the signal processing.

[0103] Specifically, for example, the column signal processing unit 113 includes a shift register, an address decoder, and the like and performs a noise removal process, a correlated double sampling process, an A / D (analog / digital) conversion process on an analog pixel signal, or the like to generate a digital pixel signal. The column signal processing unit 113 supplies the generated pixel signal to the signal processing unit 118.

[0104] The horizontal drive unit 114 includes a shift register, an address decoder, and the like and sequentially selects unit circuits corresponding to the pixel columns of the column signal processing unit 113. The selective scanning by this horizontal drive unit 114 causes the pixel signal subjected to the signal processing for each unit circuit in the column signal processing unit 113 to be sequentially output to the signal processing unit 118.

[0105] The system control unit 115 includes a timing generator that generates various timing signals and the like. The system control unit 115 performs drive control on the vertical drive unit 112, the column signal processing unit 113, and the horizontal drive unit 114 based on the timing signals generated by the timing generator.

[0106] The signal processing unit 118 performs signal processing such as arithmetic processing on the pixel signals supplied from the column signal processing unit 113 while temporarily storing data in the data storage unit 119 as necessary, and outputs an image signal including each pixel signal.

[0107] The data storage unit 119 temporarily holds data necessary for the signal processing unit 118 to perform signal processing.

[0108] [Configuration of sensor pixels PX]

[0109] (Circuit configuration example)

[0110] Next, a circuit configuration example of a sensor pixel PX provided in the pixel array unit 111 in the image pickup device 100 will be described with reference to FIG. 2 FIG. 1 FIG. 2 A circuit configuration example of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX included in the pixel array unit 111 is shown.

[0111] In the example shown in FIG. 2 , the sensor pixels PX (PX1 and PX2) in the pixel array unit 111 implement a memory hold type global shutter.

[0112] The sensor pixel PX1 is a normal pixel for image detection of visible light information. The sensor pixel PX1 includes a photoelectric conversion unit PD1, first to third transfer transistors TG1A to TG1C, a charge holding unit MEM1, a discharge transistor OFG1, a discharge unit OFD1, and a buffer BUF1. The first transfer transistor TG1A includes a transfer gate TRZ1, the second transfer transistor TG1B includes a transfer gate TRY1 and a transfer gate TRX1, and the third transfer transistor TG1C includes a transfer gate TRG1. Here, the gate electrode of the discharge transistor OFG1 is connected to a signal line SL1. The transfer gate TRZ1 is connected to a signal line SL2. The transfer gate TRY1 is connected to a signal line SL3. The transfer gate TRX1 is connected to a signal line SL4. The transfer gate TRG1 is connected to a signal line SL5.

[0113] ​​The sensor pixel PX1 further includes a power supply VDD, a charge-voltage conversion unit FD1, a reset transistor RST1, an amplification transistor AMP1, a selection transistor SEL1, and the like. The gate electrode of the reset transistor RST1 is connected to a signal line SL6. The gate electrode of the selection transistor SEL1 is connected to a signal line SL7. Note that the sensor pixel PX1 can share the charge-voltage conversion unit FD1, the reset transistor RST1, the amplification transistor AMP1, the selection transistor SEL1, and the like with a sensor pixel PX4 (described below) adjacent to the sensor pixel PX1. Like the sensor pixel PX1, the sensor pixel PX4 is a normal pixel for image detection to acquire visible light information.

[0114] The sensor pixel PX2 is a pixel to acquire information other than visible light information. Specifically, for example, the sensor pixel PX2 is a phase difference detection pixel for acquiring a phase difference signal for autofocusing (hereinafter referred to as a ZAF pixel). The sensor pixel PX2 includes a photoelectric conversion unit PD2, first to third transfer transistors TG2A to TG2C, a charge holding unit MEM2, and a buffer BUF2. However, the sensor pixel PX2 according to the present embodiment does not include any discharge transistor and any discharge unit. The first transfer transistor TG2A includes a transfer gate TRZ2, the second transfer transistor TG2B includes a transfer gate TRY2 and a transfer gate TRX2, and the third transfer transistor TG2C includes a transfer gate TRG2. Here, the transfer gate TRZ2 is connected to a signal line SL9. The transfer gate TRY2 is connected to a signal line SL10. The transfer gate TRX2 is connected to a signal line SL11. The transfer gate TRG2 is connected to a signal line SL12.

[0115] The sensor pixel PX2 further includes a power supply VDD, a charge-voltage conversion unit FD2, a reset transistor RST2, an amplification transistor AMP2, a selection transistor SEL2, and the like. Like the gate electrode of the reset transistor RST1, the gate electrode of the reset transistor RST2 is connected to the signal line SL6. Like the gate electrode of the selection transistor SEL1, the gate electrode of the selection transistor SEL2 is connected to the signal line SL7. Note that the sensor pixel PX2 can share the charge-voltage conversion unit FD2, the reset transistor RST2, the amplification transistor AMP2, the selection transistor SEL2, and the like with a sensor pixel PX3 (described below) adjacent to the sensor pixel PX2. Like the sensor pixel PX1, the sensor pixel PX3 is a normal pixel for image detection to acquire visible light information.

[0116] In this example, the first to third transfer transistors TG1A to TG1C and TG2A to TG2C, the reset transistors RST1 and RST2, the amplification transistors AMP1 and AMP2, and the selection transistors SEL1 and SEL2 are all N-type MOS transistors. Drive control based on the system control unit 115 provides drive signals to respective gate electrodes of the first to third transfer transistors TG1A to TG1C and TG2A to TG2C, the reset transistors RST1 and RST2, the amplification transistors AMP1 and AMP2, and the selection transistors SEL1 and SEL2 from the vertical drive unit 112 and the horizontal drive unit 114 through signal lines SL1 to SL7 and SL9 to SL12. Each of those drive signals is a pulse signal, whose high level state corresponds to an active state (on state) and whose low level state corresponds to an inactive state (off state). Note that the following will also refer to bringing a drive signal into the active state as turning on the drive signal and bringing the drive signal into the inactive state as turning off the drive signal.

[0117] Each of the photoelectric conversion units PD1 and PD2 is, for example, a photoelectric conversion element including a PN junction photodiode. Each of the photoelectric conversion units PD1 and PD2 is configured to receive light from a subject, generate a charge corresponding to an amount of the received light through photoelectric conversion, and accumulate the charge.

[0118] The charge holding units MEM1 and MEM2 are provided between the photoelectric conversion units PD1 and PD2 and the charge voltage conversion units FD1 and FD2, respectively. The charge holding units MEM1 and MEM2 are areas that temporarily hold the charges generated and accumulated in the photoelectric conversion units PD1 and PD2 until the charges are transferred to the charge voltage conversion units FD1 and FD2, respectively, to realize a global shutter function.

[0119] In the sensor pixel PX1, the first transfer transistor TG1A and the second transfer transistor TG1B are provided in order between the photoelectric conversion unit PD1 and the charge holding unit MEM1. The third transfer transistor TG1C is provided between the charge holding unit MEM1 and the charge voltage conversion unit FD1. The first transfer transistor TG1A and the second transfer transistor TG1B are configured to transfer the charge accumulated in the photoelectric conversion unit PD1 to the charge holding unit MEM1 in accordance with drive signals applied to their transfer gates TRZ1 and transfer gate TRY1 and the transfer gate TRX1, respectively.

[0120] Similarly, in the sensor pixel PX2, the first transfer transistor TG2A and the second transfer transistor TG2B are disposed in order between the photoelectric conversion unit PD2 and the charge holding unit MEM2. The third transfer transistor TG2C is disposed between the charge holding unit MEM2 and the charge voltage conversion unit FD2. The first transfer transistor TG2A and the second transfer transistor TG2B are configured to transfer the charge accumulated in the photoelectric conversion unit PD2 to the charge holding unit MEM2 according to the drive signals applied to the transfer gate TRZ2 and the transfer gate TRY2 and the transfer gate TRX2, respectively.

[0121] The third transfer transistor TG1C and the third transfer transistor TG2C are configured to transfer the charge temporarily held in the charge holding unit MEM1 and the charge holding unit MEM2 to the charge voltage conversion units FD1 and FD2 according to the drive signals applied to the transfer gates TRG1 and TRG2, respectively.

[0122] For example, in the sensor pixels PX1 and PX2, in a case where the second transfer transistors TG1B and TG2B are turned off and the third transfer transistors TG1C and TG2C are turned on, the charges held in the charge holding units MEM1 and MEM2 are transferred to the charge voltage conversion units FD1 and FD2 through the third transfer transistors TG1C and TG2C, respectively.

[0123] The buffer BUF1 in the sensor pixel PX1 is a charge accumulation region formed between the first transfer transistor TG1A and the second transfer transistor TG1B. The buffer BUF2 in the sensor pixel PX2 is a charge accumulation region formed between the first transfer transistor TG2A and the second transfer transistor TG2B.

[0124] The reset transistor RST1 in the sensor pixel PX1 has a drain connected to the power supply VDD and a source connected to the charge voltage conversion unit FD1. The reset transistor RST1 initializes or resets the charge voltage conversion unit FD1 according to a drive signal applied to its gate electrode. For example, in a case where the reset transistor RST1 is turned on by the drive signal, the potential of the charge voltage conversion unit FD1 is reset to the voltage level of the power supply VDD. In other words, the charge voltage conversion unit FD1 is initialized. Similarly, the reset transistor RST2 in the sensor pixel PX2 has a drain connected to the power supply VDD and a source connected to the charge voltage conversion unit FD2. The reset transistor RST2 initializes or resets the charge voltage conversion unit FD2 according to a drive signal applied to its gate electrode. For example, in a case where the reset transistor RST2 is turned on by the drive signal, the potential of the charge voltage conversion unit FD2 is reset to the voltage level of the power supply VDD.

[0125] The charge-voltage conversion unit FD1 in the sensor pixel PX1 is a floating diffusion region that converts charges transferred from the photoelectric conversion unit PD1 through the first to third transfer transistors TG1A to TG1C and the charge holding unit MEM1 into an electric signal (e.g., a voltage signal) and outputs the converted electric signal. The reset transistor RST1 is connected to the charge-voltage conversion unit FD1 and is connected to the vertical signal line VSL through the amplification transistor AMP1 and the selection transistor SEL1.

[0126] The charge-voltage conversion unit FD2 in the sensor pixel PX2 is a floating diffusion region that converts charges transferred from the photoelectric conversion unit PD2 through the first to third transfer transistors TG2A to TG2C and the charge holding unit MEM2 into an electric signal (e.g., a voltage signal) and outputs the converted electric signal. The reset transistor RST2 is connected to the charge-voltage conversion unit FD2 and is connected to the vertical signal line VSL through the amplification transistor AMP2 and the selection transistor SEL2.

[0127] The amplification transistor AMP1 outputs an electric signal corresponding to the potential of the charge-voltage conversion unit FD1. Further, the amplification transistor AMP2 outputs an electric signal corresponding to the potential of the charge-voltage conversion unit FD2. For example, each of the amplification transistors AMP1 and AMP2 is included in a source follower circuit and a constant current source provided in the column signal processing unit 113.

[0128] The selection transistors SEL1 and SEL2 are turned on, respectively, in the case where the sensor pixels PX1 and PX2 are selected. The selection transistors SEL1 and SEL2 output electric signals provided from the charge-voltage conversion units FD1 and FD2 through the amplification transistors AMP1 and AMP2, respectively, to the column signal processing unit 113 through the vertical signal line VSL.

[0129] The sensor pixel PX1 further includes, in addition to the charge-voltage conversion unit FD1, a discharge unit OFD1 as a transfer destination of charges of the photoelectric conversion unit PD1. The discharge transistor OFG1 is provided between the buffer BUF1 and the discharge unit OFD1.

[0130] The discharge transistor OFG1 has a drain connected to the discharge unit OFD1 and a source connected to the buffer BUF1. The discharge transistor OFG1 initializes or resets the photoelectric conversion unit PD1 according to a drive signal applied to a gate electrode. The reset photoelectric conversion unit PD1 means to deplete the photoelectric conversion unit PD1.

[0131] Further, the overflow transistor OFG1 forms an overflow path. The overflow transistor OFG1 discharges the charge overflowing from the photoelectric conversion unit PD1 to the overflow unit OFD1. In this way, in the sensor pixel PX1 according to the present embodiment, the overflow transistor OFG1 can directly reset the photoelectric conversion unit PD1. However, in the case of resetting the photoelectric conversion unit PD1, it is necessary to turn on the overflow transistor OFG1 and turn on the transfer gate TRZ1.

[0132] (Cross-sectional configuration example and planar configuration example)

[0133] Next, with reference to FIGS. 3A-4I , a cross-sectional configuration example and a planar configuration example of a sensor pixel PX provided in the pixel array unit 111 of FIG. 1 will be described.

[0134] FIG. 3A and FIG. 3B respectively show a cross-sectional configuration example of four sensor pixels PX1 to PX4 included in a plurality of sensor pixels PX in the pixel array unit 111. FIG. 3A shows a cross section in an arrow direction taken along a IIIA-IIIA cut line that passes through the sensor pixel PX1 and the sensor pixel PX2 shown in each of FIGS. 4A-4H and extends in the X-axis direction. Further, FIG. 3B shows a cross section in an arrow direction taken along a IIIB-IIIB cut line that extends in the Y-axis direction.

[0135] FIGS. 4A-4H respectively show a planar configuration example of four sensor pixels PX1 to PX4 arranged in a grid shape of two rows and two columns. Specifically, FIGS. 4A-4H respectively show a planar configuration at the height positions Lv1 to Lv8 shown in each of FIG. 3A and FIG. 3B Further, FIG. 4I is a schematic view showing an example of a layout pattern of the sensor pixels PX1 to PX4 in the pixel array unit 111. In FIG. 4I , Lv9 refers to a height position Lv9 shown in each of FIG. 3A and FIG. 3B . Lv9 is a height position corresponding to a light-blocking film formation layer included in the ZAF light-blocking film 16 described below. In the pixel array unit 111 according to the present embodiment, as shown in FIG. 4I , the sensor pixels PX1 to PX4 shown in FIGS. 4A-4H are used as a minimum unit and are arranged repeatedly in the X-axis direction and the Y-axis direction. As shown in FIG. 4IAs shown, however, not all sensor pixels PX2 in pixel array unit 111 must be ZAF pixels. It is sufficient if some sensor pixels PX2 arbitrarily selected in pixel array unit 111 are ZAF pixels. FIG. 4I In the image, the sensor pixel PX2, which has a ZAF light-shielding film 16, is a ZAF pixel.

[0136] Sensor pixels PX3 and PX4 are ordinary pixels with configurations substantially identical to those of sensor pixel PX1. Therefore, sensor pixels PX3 and PX4 include photoelectric conversion units PD3 and PD4, first to third transmission transistors TG3A to TG3C and TG4A to TG4C, charge retention units MEM3 and MEM4, discharge transistors OFG3 and OFG4, discharge units OFD3 and OFD4, buffers BUF3 and BUF4, and a power supply VDD. Furthermore, sensor pixel PX3 shares the vertical signal line VSL2, charge-to-voltage conversion unit FD2, reset transistor RST2, amplification transistor AMP2, and selection transistor SEL2 with sensor pixel PX2. Sensor pixel PX4 shares the vertical signal line VSL1, charge-to-voltage conversion unit FD1, reset transistor RST1, amplification transistor AMP1, and selection transistor SEL1 with sensor pixel PX1.

[0137] like FIG. 3A and FIG. 3B As shown, the pixel array unit 111 has a structure in which a first substrate S1, including a first layer LY1 and a second layer LY2, and a second substrate S2, including a third layer LY3, are bonded together at a bonding interface K. Wiring layers are bonded to each other at the bonding interface K. A so-called Cu-Cu bonding is preferred to bond the wiring layers together. In Cu-Cu bonding, for example, the surfaces of metal layers such as Cu (copper) are activated by plasma irradiation and bonded to each other.

[0138] Photoelectric conversion units PD (PD1 to PD4) are formed in the first layer LY1 of the pixel array unit 111. Each of the sensor pixels PX1 to PX4 includes a semiconductor substrate 11 and a photoelectric conversion unit PD (PD1 to PD4) in the first layer LY1. The semiconductor substrate 11 is formed using a semiconductor material such as Si (silicon). The photoelectric conversion units PD (PD1 to PD4) are embedded in the semiconductor substrate 11. Furthermore, the semiconductor substrate 11 includes a front surface 11S1 and a rear surface 11S2 opposite to the front surface 11S1. The rear surface 11S2 is a surface that receives light from the outside. A color filter forming layer including color filters CF (CF1 to CF4) is provided on the rear surface 11S2 (see reference). FIG. 3A , FIG. 3B and FIG. 4B). The color filters CF (CF1 to CF4) are further provided with on-chip lenses LS (LS1 to LS4) on the opposite side with respect to the back surface 11S2 (refer to FIG. 3A , FIG. 3B and FIG. 4A ). Further, the front end portions of the two vertical trench gates 51 and 52 are in contact with the photoelectric conversion units PD (PD1 to PD4) (refer to FIG. 3A , 3B and 4E). The two vertical trench gates 51 and 52 extend in the depth direction (+Z direction) from the lower portions of the transfer gates TRZ (TRZ1 to TRZ4). The transfer gates TRZ (TRZ1 to TRZ4) are provided on the front surface 11S1. Further, the sensor pixel PX2 is a ZAF pixel and thus the sensor pixel PX2 further includes a light-shielding film formation layer between the back surface 11S2 and a color filter formation layer including the color filter CF2. The light-shielding film formation layer includes a ZAF light-shielding film 16.

[0139] The element separation unit 12 is further provided in the first layer LY1 of the semiconductor substrate 11 to surround each of the photoelectric conversion units PD (PD1 to PD4) (refer to FIG. 3A , FIG. 3B and FIG. 4C ). The element separation unit 12 is a wall-like member that extends in the Z-axis direction at a boundary position between the sensor pixels PX adjacent to each other to penetrate the semiconductor substrate 11 and surround each photoelectric conversion unit PD. The element separation unit 12 electrically separates the sensor pixels PX adjacent to each other. Further, the element separation unit 12 prevents generation of noise such as color mixing caused by light leaking from the adjacent sensor pixels PX entering each photoelectric conversion unit PD (PD1 to PD4). For example, the element separation unit 12 includes an insulating material such as silicon oxide.

[0140] For example, the first to third transfer transistors TG1A to TG1C, TG2A to TG2C, TG3A to TG3C, and TG4A to TG4C, the charge holding units MEM1 to MEM4, the discharge transistors OFG1, OFG3, and OFG4, the discharge units OFD1, OFD3, and OFD4, the buffers BUF1 to BUF4, the power supply VDD, the charge voltage conversion units FD1 to FD4, and the like are formed in the second layer LY2 of the sensor pixels PX1 to PX4 (refer to FIG. 3A , FIG. 3B and FIG. 4G ). Note that, for example, the charge holding units MEM1 to MEM4 are located below the transfer gates TRY1 to TRY4, TRX1 to TRX4, and TRG1 to TRG4.

[0141] The second layer LY2 of the sensor pixels PX1 to PX4 is provided with two vertical trench gates 51 and 52 (refer to FIG. 3A , FIG. 3B , FIG. 4E and FIG. 4F ). The vertical trench gates 51 and 52 include in a part of the charge transport unit. The vertical trench gates 51 and 52 are connected to the photoelectric conversion units PD1 to PD4 and the transfer gates TRZ1 to TRZ4, respectively. The vertical trench gates 51 and 52 function as a path for transferring the charge from the photoelectric conversion units PD1 to PD4 to the charge holding units MEM1 to MEM4 through the buffers BUF1 to BUF4. The charge holding units MEM1 to MEM4 are the transfer destinations. Note that only one vertical trench gate can be provided or three or more vertical trench gates can be provided.

[0142] Between the vertical trench gates 51 and 52 and the back surface 11S2, a horizontal light shielding film 13 (refer to FIG. 3A , FIG. 3B and FIG. 4D ) is provided. The horizontal light shielding film 13 extends along the XY plane to overlap the vertical trench gates 51 and 52 in the Z-axis direction. For example, the horizontal light shielding film 13 is connected to the end portion of the element separation unit 12 opposite to the back surface 11S2. As shown in FIG. 4D , in a part of the horizontal light shielding film 13, openings 13K1 to 13K4 are provided to partially separate the photoelectric conversion units PD1 to PD4 in the Z-axis direction. The charge generated in the photoelectric conversion units PD1 to PD4 moves to the vertical trench gates 51 and 52 through the openings 13K1 to 13K4, respectively. Note that the positions of the openings 13K1 to 13K4 in the XY plane are different from the positions of the openings 14K1 to 14K4 in the horizontal light shielding film 14 described below in the XY plane.

[0143] Further, between the photoelectric conversion units PD1 to PD4 and the charge holding units MEM1 to MEM4, a horizontal light shielding film 14 (refer to FIG. 3A , FIG. 3B and FIG. 4F). The horizontal light shielding film 14 extends along the XY plane. Like the horizontal light shielding film 13, the horizontal light shielding film 14 is a member that prevents light from entering the charge holding units MEM1 to MEM4. The horizontal light shielding film 14 suppresses the light that has passed through the photoelectric conversion units PD1 to PD4 from entering the charge holding units MEM1 to MEM4 and generation of noise. Note that the light from the rear surface 11B and that has passed through the photoelectric conversion units PD1 to PD4 without being absorbed by the photoelectric conversion units PD1 to PD4 is reflected on the horizontal light shielding film 14 and enters the photoelectric conversion units PD1 to PD4 again. In other words, the horizontal light shielding film 14 is also a reflector. The horizontal light shielding film 14 improves the photoelectric conversion efficiency by causing the light that has passed through the photoelectric conversion units PD1 to PD4 to enter the photoelectric conversion units PD1 to PD4 again. However, the horizontal light shielding film 14 is provided with openings 14K (14K1 to 14K4) that allow the charges generated by the photoelectric conversion units PD1 to PD4 to pass therethrough. The vertical trench gates 51 and 52 are provided so as to extend through the openings 14K1 to 14K4, respectively. The horizontal light shielding film 14 can be provided on the entire XY plane of the pixel array unit 111 except for the openings 14K1 to 14K4. For example, each of the horizontal light shielding films 13 and 14 has a double-layer structure including an inner layer portion and an outer layer portion that surrounds the outer periphery thereof. For example, the inner layer portion includes a material including at least one of a single-element metal, a metal alloy, a metal nitride, or a metal silicide having a light-shielding property. More specific examples of the material included in the inner layer portion include Al (aluminum), Cu (copper), Co (cobalt), W (tungsten), Ti (titanium), Ta (tantalum), Ni (nickel), Mo (molybdenum), Cr (chromium), Ir (iridium), platinum iridium, TiN (titanium nitride), a tungsten silicide compound, and the like. Among them, Al (aluminum) is the most optically preferable material. Note that the inner layer portion can include graphite, an organic material, or the like. For example, the outer layer portion includes an insulating material such as SiO x

[0144] ​Note that each of the horizontal light shielding films 13 and 14 extending on the XY plane, for example, can be formed by removing a portion of the semiconductor substrate 11 by a wet etching process to form a space inside the semiconductor substrate 11 and then filling the space with the material described above. In the wet etching process, for example, in the case where the semiconductor substrate 11 includes Si{111}, crystal anisotropic etching using a predetermined alkaline aqueous solution is performed by using a characteristic in which an etching rate differs depending on a plane orientation of Si{111}. More specifically, in the Si{111} substrate, a characteristic in which an etching rate in the <110> direction is sufficiently high relative to an etching rate in the <111> direction is used. Here, the <111> direction is a direction having three Si back bonds. Further, the <110> direction is a direction having one or two Si back bonds. In the present embodiment, the X-axis direction corresponds to the <110> direction. As the predetermined alkaline aqueous solution, an inorganic solution such as KOH, NaOH, or CsOH, or an organic solution such as EDP (ethylenediamine pyrocatechol aqueous solution), N2H4 (hydrazine), NH4OH (ammonium hydroxide), or TMAH (tetramethylammonium hydroxide) can be applied.

[0145] Further, in the present embodiment, for example, the semiconductor substrate 11 belongs to the P type (first conductive type) and the photoelectric conversion units PD and the charge holding units MEM1 to MEM4 belong to the N type (second conductive type).

[0146] The vertical signal lines VSL1 and VSL2, the charge voltage conversion units FD1 and FD2, the reset transistors RST1 and RST2, the amplification transistors AMP1 and AMP2, the selection transistors SEL1 and SEL2, and the like are formed in the third layer LY3 (refer to FIG. 3A , FIG. 3B and FIG. 4H ).

[0147] (Operation of sensor pixels PX)

[0148] Next, the operation of the sensor pixels PX is described with reference to FIGS. 2-4H and the like. In each of the sensor pixels PX as normal pixels except for the sensor pixel PX2 as the ZAF pixel, first, based on drive control of the system control unit 115, a high-level drive signal is supplied to each of the discharge transistor OFG and the transfer gate TRZ before exposure is performed. This turns on the discharge transistor OFG and the transfer gate TRZ. This causes the charge accumulated in the photoelectric conversion unit PD to be discharged to the discharge unit OFD and the photoelectric conversion unit PD to be reset.

[0149] After the photoelectric conversion units PD are reset, low-level drive signals are supplied to each of the discharge transistors OFG and the transfer gates TRZ based on drive control by the system control unit 115. This turns off the discharge transistors OFG and the transfer gates TRZ. This starts exposure of all the sensor pixels PX in the pixel array unit 111 and generates and accumulates charges in each photoelectric conversion unit PD that receives light from an object.

[0150] After a predetermined exposure time elapses, the drive signals of the transfer gates TRZ and the transfer gates TRY are turned on in all the sensor pixels PX in the pixel array unit 111 based on drive control by the system control unit 115. In each sensor pixel PX, this transfers the charges accumulated in the photoelectric conversion unit PD from the photoelectric conversion unit PD to the charge holding unit MEM through the transfer gates TRZ and the transfer gates TRY. The charges are temporarily held in the charge holding unit MEM.

[0151] Subsequently, the drive signals of the transfer gates TRZ and the transfer gates TRY are turned off based on drive control by the system control unit 115. Then, a readout operation is performed by sequentially reading out the charges held in the charge holding unit MEM of each sensor pixel PX. For example, the readout operation of the charges is performed for each row of the pixel array unit 111. Specifically, for each row to be read out, the transfer gate TRX and the transfer gate TRG are turned on by the drive signals. This transfers the charges held in the charge holding unit MEM of each sensor pixel PX to each charge voltage conversion unit FD row by row.

[0152] Then, in a case where the selection transistor SEL is turned on by the drive signal, an electric signal indicating a level corresponding to the charge held in the charge voltage conversion unit FD is sequentially passed through the amplification transistor AMP and the selection transistor SEL and output to the column signal processing unit 113 via the vertical signal line VSL.

[0153] [Effects of the solid-state imaging device 101]

[0154] Thus, the solid-state imaging device 101 according to the present embodiment includes the sensor pixel PX1 as the first pixel and the sensor pixel PX2 as the second pixel. The sensor pixel PX1 is a normal pixel. The sensor pixel PX2 is a ZAF pixel. The sensor pixel PX1 includes seven signal lines SL1 to SL7 and seven gate electrodes connected to the signal lines SL1 to SL7, respectively. In other words, the sensor pixel PX1 includes the gate electrode of the discharge transistor OFG1, the transfer gates TRZ1, TRY1, TRX1, and TRG1 of the first to third transfer transistors TG1A to TG1C, the gate electrode of the reset transistor RST1, the gate electrode of the amplification transistor AMP1, and the gate electrode of the selection transistor SEL1. As the second pixel, the sensor pixel PX2 as the ZAF pixel includes six signal lines SL6 to SL7 and SL9 to SL12 and six gate electrodes connected to the signal lines SL6 to SL7 and SL9 to SL12, respectively. In other words, the sensor pixel PX2 includes the transfer gates TRZ2, TRY2, TRX2, and TRG2 of the first to third transfer transistors TG2A to TG2C, the gate electrode of the reset transistor RST2, the gate electrode of the amplification transistor AMP2, and the gate electrode of the selection transistor SEL2. Thus, in the solid-state imaging device 101, the number of the signal lines SL connected to the sensor pixel PX2 is less than the number of the signal lines SL connected to the sensor pixel PX1. Thus, it is advantageous to miniaturize the overall configuration.

[0155] For example, in a case where a region having a predetermined area is provided with more signal lines SL in the same layer, since the adjacent signal lines SL have a shorter interval, there is a concern of short-circuit between the signal lines SL. Thus, in order to maintain the interval between the adjacent signal lines SL, it is necessary to further reduce the line width of each signal line SL. This case raises a problem of an increase in the resistance value of each signal line SL per unit length. Further, by providing a plurality of signal lines SL in different layers, it is possible to avoid the problems of short-circuit between the signal lines SL and the increase in the resistance value. However, this leads to an increase in the manufacturing process and an increase in the thickness of the solid-state imaging device.

[0156] Thus, the solid-state imaging device 101 according to the present embodiment has fewer signal lines SL connected to the sensor pixel PX2 to avoid the problems described above and to achieve miniaturization.

[0157] Note that in a case where the sensor pixel PX2 that is a ZAF pixel shares a charge-voltage conversion unit (FD) with another normal pixel, there is a concern that signal charges overflowing from the sensor pixel PX2 flow into the shared charge-voltage conversion unit and are superimposed on the signal of the normal pixel as noise when the normal pixel is read out. In order to avoid such a phenomenon, it is originally expected to provide the sensor pixel PX2 with a discharge transistor (OFG), turn on the discharge transistor, and prevent signal charges overflowing from the sensor pixel PX2 from flowing from the sensor pixel PX2 to the shared charge-voltage conversion unit. However, as with the sensor pixel PX2 in the solid-state imaging device 101 according to the present embodiment, although lacking a discharge transistor, in a case where the other normal pixel that shares the charge-voltage conversion unit is read out, it is also possible to prevent signal charges from flowing into the shared charge-voltage conversion unit by adjusting the design margin of the potential. Furthermore, the sensor pixel PX2 has the same configuration as that of the other normal pixel except that the sensor pixel PX2 does not include an arbitrary discharge transistor (OFG). In the sensor pixel PX2, this allows the charge holding unit MEM2 to have substantially the same characteristics (such as a saturation capacitance) as those of the other normal pixel.

[0158] <2. Modification of the first embodiment>

[0159] (2-1. First modification)

[0160] [Circuit configuration of sensor pixels PX in pixel array unit 111A]

[0161] FIG. 5 is a circuit diagram illustrating a circuit configuration of a sensor pixel PX in the pixel array unit 111A according to the first modification and corresponds to FIG. 2 in the first embodiment described above. Furthermore, FIG. 6A and FIG. 6B respectively illustrate cross-sectional configuration examples of four sensor pixels PX1 to PX4 among a plurality of sensor pixels PX included in the pixel array unit 111A. FIG. 6A and FIG. 6B respectively correspond to FIG. 3A and FIG. 3B in the first embodiment described above. Further, FIG. 7 illustrates FIG. 6A and FIG. 6B a planar configuration of the four sensor pixels PX1 to PX4 at the height position Lv7 illustrated in each of FIG. 7 corresponds to FIG. 4G in the first embodiment described above. Note that FIG. 6A illustrates a planar configuration of the four sensor pixels PX1 to PX4 alongFIG. 7 The cross section taken along the VIA-VIA cut line shown in FIG. 11A and extending in the arrow direction of the X-axis direction, and FIG. 6B The cross section taken along the VIB-VIB cut line shown in FIG. 11A and extending in the arrow direction of the Y-axis direction is shown. FIG. 7 The cross section taken along the VIB-VIB cut line shown in FIG. 11A and extending in the arrow direction of the Y-axis direction is shown.

[0162] In the pixel array unit 111A, as in the pixel array unit 111 according to the first embodiment described above, the ZAF pixel includes one less wiring than that for a normal pixel. In the pixel array unit 111 according to the first embodiment described above, the discharge transistor (OFG2) in the sensor pixel PX2 that is a ZAF pixel and the signal line (SL8) connected to the gate electrode of the discharge transistor (OFG2) are omitted. In contrast, in the pixel array unit 111A according to the first modified example, the sensor pixel PX2 that is a ZAF pixel includes the discharge transistor OFG2 and the signal line SL8 connected to the gate electrode of the discharge transistor OFG2. Meanwhile, the sensor pixel PX2 does not include the transfer gate TRX2 and the signal line SL11 connected to the transfer gate TRX2. Except for this, the pixel array unit 111A has substantially the same configuration as that of the pixel array unit 111 described above.

[0163] [Effects of the pixel array unit 111A]

[0164] As in the pixel array unit 111, in the pixel array unit 111A, the number of signal lines connected to the sensor pixel PX2 is smaller than the number of signal lines connected to the sensor pixel PX1. This is therefore advantageous in making the overall configuration compact.

[0165] Further, in the pixel array unit 111A, the sensor pixel PX2 that is a ZAF pixel includes the discharge transistor OFG2. This makes it possible to prevent signal charges overflowing from the sensor pixel PX2 from flowing into the shared charge-voltage conversion unit when a normal pixel is read out by turning on the discharge transistor OFG2 even in the case where the sensor pixel PX2 shares the charge-voltage conversion unit (FD) with another normal pixel. However, in the pixel array unit 111A, the sensor pixel PX2 does not include the transfer gate TRX2. Therefore, the upper limit of the saturation capacitance of the charge holding unit MEM2 is lower than that in the pixel array unit 111.

[0166] (2-2. Second Modified Example)

[0167] [Circuit configuration of the sensor pixel PX in the pixel array unit 111B]

[0168] FIG. 8 is a circuit diagram showing a circuit configuration of a sensor pixel PX in the pixel array unit 111B according to a second modification example and corresponds to FIG. 2 in the first embodiment described above. Further, FIG. 9A and FIG. 9B respectively show cross-sectional configuration examples of four sensor pixels PX1 to PX4 included in a plurality of sensor pixels PX in the pixel array unit 111B. FIG. 9A and FIG. 9B respectively correspond to FIG. 3A and FIG. 3B in the first embodiment described above. Further, FIG. 10 shows a planar configuration of the four sensor pixels PX1 to PX4 at the height position Lv7 shown in each of FIG. 9A and FIG. 9B The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 10 corresponds to FIG. 4G in the first embodiment described above. Note that, FIG. 9A shows a cross section in the arrow direction taken along the IXA-IXA cut line shown in FIG. 10 and FIG. 9B shows a cross section in the arrow direction taken along the IXB-IXB cut line shown in FIG. 10 .

[0169] As in the pixel array unit according to the first embodiment described above, in the pixel array unit 111B, the ZAF pixel includes one less wiring than that for a normal pixel. However, in the pixel array unit 111B according to the second modification example, the sensor pixel PX2 that is the ZAF pixel includes the discharge transistor OFG2 and the signal line SL8 connected to the gate electrode of the discharge transistor OFG2. Meanwhile, the sensor pixel PX2 does not include the second transfer transistor TG2B including the transfer gate TRY2 and the signal line SL10 connected to the transfer gate TRY2. Except for this, the pixel array unit 111B has substantially the same configuration as that of the pixel array unit 111 described above.

[0170] [Effects of the pixel array unit 111B]

[0171] As in the pixel array unit 111, in the pixel array unit 111B, the number of signal lines connected to the sensor pixel PX2 is smaller than the number of signal lines connected to the sensor pixel PX1. Therefore, this is advantageous in making the overall configuration compact.

[0172] Further, in the pixel array unit 111B, the sensor pixel PX2 as a ZAF pixel includes the discharge transistor OFG2. This makes it possible to prevent signal charges overflowing from the sensor pixel PX2 from flowing into the shared charge-voltage conversion unit when the normal pixel is read out by turning on the discharge transistor OFG2 even in the case where the sensor pixel PX2 shares the charge-voltage conversion unit (FD) with another normal pixel. However, in the pixel array unit 111B, the sensor pixel PX2 does not include the transfer gate TRY2. Therefore, the upper limit of the saturation capacitance of the charge holding unit MEM2 is lower than the upper limit of the saturation capacitance of the charge holding unit MEM2 of the sensor pixel PX2 in the pixel array unit 111. For a similar reason, the upper limit of the saturation capacitance of the photoelectric conversion unit PD2 in the pixel array unit 111B is lower than the upper limit of the saturation capacitance of the photoelectric conversion unit PD2 of the sensor pixel PX2 in the pixel array unit 111.

[0173] (2-3. Third Modified Example)

[0174] [Circuit configuration of sensor pixel PX in pixel array unit 111C]

[0175] FIG. 11 is a circuit diagram showing the circuit configuration of the sensor pixel PX in the pixel array unit 111C according to the third modified example and corresponds to FIG. 2 in the first embodiment described above. Further, FIG. 12A and FIG. 12B respectively show cross-sectional configuration examples of four sensor pixels PX1 to PX4 included in the plurality of sensor pixels PX in the pixel array unit 111C. FIG. 12A and FIG. 12B respectively correspond to FIG. 3A and FIG. 3B in the first embodiment described above. Further, FIG. 13 shows FIG. 12A and FIG. 12B the planar configuration of the four sensor pixels PX1 to PX4 at the height position Lv7 shown in each of FIG. 13 corresponds to FIG. 4G in the first embodiment described above. Note that, FIG. 12A shows a cross section in the arrow direction taken along the XIIA-XIIA cut line shown in FIG. 13 and FIG. 12B shows a cross section in the arrow direction taken along the XIIB-XIIB cut line shown in FIG. 13

[0176] ​As in the pixel array unit according to the first embodiment described above, in the pixel array unit 111C, the ZAF pixel includes one less wiring than that for the ordinary pixel. However, in the pixel array unit 111C according to the third modification example, the sensor pixel PX2 that is the ZAF pixel includes the discharge transistor OFG2 and the signal line SL8 connected to the gate electrode of the discharge transistor OFG2. Meanwhile, the sensor pixel PX2 does not include the first transfer transistor TG2A including the transfer gate TRZ2 and the signal line SL9 connected to the transfer gate TRZ2. Except for this, the pixel array unit 111C has substantially the same configuration as that of the pixel array unit 111 described above.

[0177] [Effects of the pixel array unit 111C]

[0178] As in the pixel array unit 111, in the pixel array unit 111C, the number of signal lines connected to the sensor pixel PX2 is smaller than the number of signal lines connected to the sensor pixel PX1. This is therefore advantageous in making the overall configuration compact.

[0179] Further, in the pixel array unit 111C, the sensor pixel PX2 that is the ZAF pixel includes the discharge transistor OFG2. This makes it possible to prevent signal charges overflowing from the sensor pixel PX2 from flowing into the shared charge-voltage conversion unit even when the sensor pixel PX2 shares the charge-voltage conversion unit (FD) with another ordinary pixel by turning on the discharge transistor OFG2 at the time of reading out the ordinary pixel. However, in the pixel array unit 111C, the sensor pixel PX2 does not include the transfer gate TRZ2. Therefore, the upper limit of the saturation capacitance of the charge holding unit MEM2 is lower than that of the sensor pixel PX2 in the pixel array unit 111. For a similar reason, the upper limit of the saturation capacitance of the photoelectric conversion unit PD2 is lower in the pixel array unit 111C than that of the sensor pixel PX2 in the pixel array unit 111.

[0180] (2-4. Fourth modification example)

[0181] [Circuit configuration of the sensor pixel PX in the pixel array unit 111D]

[0182] FIG. 14 is a circuit diagram showing the circuit configuration of the sensor pixel PX in the pixel array unit 111D according to the fourth modification example and corresponds to FIG. 2 in the first embodiment described above. Further, FIG. 15A and FIG. 15BCross-sectional configuration examples of four sensor pixels PX1 to PX4 included in the plurality of sensor pixels PX in the pixel array unit 111D are shown, respectively. FIG. 15A and FIG. 15B correspond to those in the first embodiment described above, respectively. Further, FIG. 3A and FIG. 3B correspond to those in the first embodiment described above, respectively. Further, FIG. 16 a planar configuration of the four sensor pixels PX1 to PX4 at the height position Lv7 shown in each of FIG. 15A and FIG. 15B is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 16 correspond to those in the first embodiment described above, respectively. Note that FIG. 4G correspond to those in the first embodiment described above, respectively. Note that FIG. 15A a cross section taken along the XVA-XVA cut line shown in FIG. 16 and FIG. 15B a cross section taken along the XVB-XVB cut line shown in FIG. 16 and extending in the arrow direction of the Y axis direction.

[0183] In the pixel array unit 111D, the ZAF pixel includes two fewer wirings than those for the ordinary pixel. In the pixel array unit 111D according to the fourth modification, the sensor pixel PX2 as the ZAF pixel includes the discharge transistor OFG2 and the signal line SL8 connected to the gate electrode of the discharge transistor OFG2. Meanwhile, the sensor pixel PX2 does not include the second transfer transistor TG2B including the transfer gate TRY2 and the transfer gate TRX2, the signal line SL10 connected to the transfer gate TRY2, and the signal line SL11 connected to the transfer gate TRX2. Except for these points, the pixel array unit 111D has substantially the same configuration as that of the pixel array unit 111 described above.

[0184] [Effects of the pixel array unit 111D]

[0185] In the pixel array unit 111D, two fewer signal lines are connected to the sensor pixel PX2 than those connected to the sensor pixel PX1. Therefore, this is more advantageous for making the overall configuration compact.

[0186] Further, in the pixel array unit 111D, the sensor pixel PX2 that is a ZAF pixel includes the discharge transistor OFG2. This makes it possible to prevent signal charge overflowing from the sensor pixel PX2 from flowing into the shared charge-voltage conversion unit when the normal pixel is read out by turning on the discharge transistor OFG2 even in the case where the sensor pixel PX2 shares the charge-voltage conversion unit (FD) with another normal pixel. However, in the pixel array unit 111D, the sensor pixel PX2 does not include the transfer gate TRY2 and the transfer gate TRX2. Therefore, the upper limit of the saturation capacitance of the charge holding unit MEM2 is lower than the upper limit of the saturation capacitance of the charge holding unit MEM2 of the sensor pixel PX2 in the pixel array unit 111. For a similar reason, the upper limit of the saturation capacitance of the photoelectric conversion unit PD2 in the pixel array unit 111D is lower than the upper limit of the saturation capacitance of the photoelectric conversion unit PD2 of the sensor pixel PX2 in the pixel array unit 111.

[0187] (2-5. Fifth Modified Example)

[0188] [Circuit configuration of sensor pixel PX of pixel array unit 111E]

[0189] FIG. 17 is a circuit diagram showing the circuit configuration of the sensor pixel PX in the pixel array unit 111E according to the fifth modified example and corresponds to FIG. 2 in the first embodiment described above. Further, FIG. 18A and FIG. 18B respectively show cross-sectional configuration examples of four sensor pixels PX1 to PX4 included in a plurality of sensor pixels PX in the pixel array unit 111E. FIG. 18A and FIG. 18B respectively correspond to FIG. 3A and FIG. 3B in the first embodiment described above. Further, FIG. 19 shows the planar configuration of the four sensor pixels PX1 to PX4 at the height position Lv7 shown in each of FIG. 18A and FIG. 18B The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 19 corresponds to FIG. 4G in the first embodiment described above. Note that, FIG. 18A shows a cross section in the arrow direction taken along the XVIIIA-XVIIIA cut line shown in FIG. 19 and FIG. 18B shows a cross section in the arrow direction taken along the XVIIIB-XVIIIB cut line shown in FIG. 19 ​

[0190] In the pixel array unit 111E, the ZAF pixel includes three fewer wirings than those for the ordinary pixel. In the pixel array unit 111E according to the fifth modification example, the sensor pixel PX2 as the ZAF pixel includes the discharge transistor OFG2 and the signal line SL8 connected to the gate electrode of the discharge transistor OFG2. Meanwhile, the sensor pixel PX2 does not include the first transfer transistor TG2A including the transfer gate TRZ2, the second transfer transistor TG2B including the transfer gate TRY2 and the transfer gate TRX2, the signal line SL9 connected to the transfer gate TRZ2, the signal line SL10 connected to the transfer gate TRY2, and the signal line SL11 connected to the transfer gate TRX2. Thus, the sensor pixel PX2 as the ZAF pixel functions as a non-global shutter pixel and does not include the MEM2. In the sensor pixel PX2, exposure and transfer of charges are performed by rolling. To achieve this, the pixel array unit 111E is designed to transfer the signal charges generated by photoelectric conversion in the photoelectric conversion unit PD2 to the front surface 11S1 of the semiconductor substrate 11 by diffusion. In other words, the photoelectric conversion unit PD2 extends to a region close to the transfer gate TRG2. Other than these points, the pixel array unit 111E has substantially the same configuration as that of the pixel array unit 111 described above.

[0191] [Effects of the pixel array unit 111E]

[0192] In the pixel array unit 111E, the signal lines SL connected to the sensor pixel PX2 are three fewer than those connected to the sensor pixel PX1. Thus, this is more advantageous in making the overall configuration compact.

[0193] Further, in the pixel array unit 111E, the sensor pixel PX2 as the ZAF pixel includes the discharge transistor OFG2. This makes it possible to prevent signal charges overflowing from the sensor pixel PX2 from flowing into the shared charge-voltage conversion unit even in the case where the sensor pixel PX2 shares the charge-voltage conversion unit (FD) with another ordinary pixel, by turning on the discharge transistor OFG2 at the time of reading out the ordinary pixel.

[0194] (2-6. Sixth Modification Example)

[0195] [Circuit configuration of sensor pixel PX in pixel array unit 111F]

[0196] FIG. 20 is a circuit diagram showing the circuit configuration of the sensor pixel PX in the pixel array unit 111F according to the sixth modification example and corresponds to FIG. 2 in the first embodiment described above. Further, FIG. 21A andFIG. 21B Examples of cross-sectional configurations of four sensor pixels PX1 to PX4, which are included in a plurality of sensor pixels PX in pixel array unit 111F, are shown respectively. FIG. 21A and FIG. 21B Compared with the first embodiment described above, respectively FIG. 3A and FIG. 3B Correspondingly. Furthermore, FIG. 22 It shows FIG. 21A and FIG. 21B The planar configuration of four sensor pixels PX1 to PX4 at height position Lv7 is shown in each of the diagrams. The four sensor pixels PX1 to PX4 are arranged in a grid of two rows and two columns. FIG. 22 Compared with the first embodiment described above FIG. 4G Correspondingly. It should be noted that, FIG. 21A It shows along FIG. 22 The cross-section shown is obtained from the XXIA-XXIA cutting line and extends in the direction of the arrow along the X-axis. FIG. 21B It shows along FIG. 22 The cross-section shown is obtained by the XXIB-XXIB cutting line and extends in the direction of the arrow along the Y-axis.

[0197] In pixel array unit 111F, the ZAF pixel includes four fewer wires than those used for ordinary pixels. In pixel array unit 111F according to the sixth variation, the sensor pixel PX2, which is a ZAF pixel, does not include discharge transistor OFG2, signal line SL8 connected to the gate electrode of discharge transistor OFG2, first transmission transistor TG2A containing transmission gate TRZ2, second transmission transistor TG2B containing transmission gate TRY2 and transmission gate TRX2, signal line SL9 connected to transmission gate TRZ2, signal line SL10 connected to transmission gate TRY2, and signal line SL11 connected to transmission gate TRX2. Therefore, the sensor pixel PX2, which is a ZAF pixel, acts as a non-global shutter pixel and does not include MEM2. In sensor pixel PX2, exposure and charge transfer are performed by rolling. To achieve this, pixel array unit 111F is designed to transfer the signal charge generated by photoelectric conversion in photoelectric conversion unit PD2 to the front surface 11S1 of semiconductor substrate 11 by diffusion. In other words, photoelectric conversion unit PD2 extends to the region close to transmission gate TRG2.

[0198] [Function and effect of pixel array unit 111F]

[0199] In pixel array unit 111F, there are four fewer signal lines SL connected to sensor pixel PX2 compared to those connected to sensor pixel PX1. Therefore, this is still more advantageous for miniaturizing the overall configuration.

[0200] <3. Second Implementation Plan>

[0201] [Configuration of Solid State Imaging Device 201]

[0202] FIG. 23 An example of the circuit configuration of two sensor pixels PX1 and PX2 among a plurality of sensor pixels in a pixel array unit of a solid-state imaging apparatus 201 according to a second embodiment of the present technology is shown, and is similar to that in the first embodiment described above. FIG. 2 Correspondingly.

[0203] In the first embodiment described above, a stacked solid-state imaging device 101 in which a photoelectric conversion unit and a memory are stacked is depicted. In contrast, in this embodiment, a planar solid-state imaging device 201 in which the photoelectric conversion unit and the memory are disposed in the same layer is described. From a circuit configuration perspective, the solid-state imaging device 201 differs significantly from the solid-state imaging device 101 in that the solid-state imaging device 201 does not include the transmission gate TRZ included in the stacked solid-state imaging device 101.

[0204] FIG. 24 An example of a cross-sectional configuration of two sensor pixels PX1 and PX2 among a plurality of sensor pixels PX in a pixel array unit included in a solid-state imaging device 201 is shown, and is consistent with the first embodiment described above. FIG. 3A Correspondingly. Furthermore, FIG. 25 The four sensor pixels PX1 to PX4 are shown in a planar configuration along the front surface 11S1. The four sensor pixels PX1 to PX4 are arranged in a grid of two rows and two columns. FIG. 25 Compared with the first embodiment described above FIG. 4G Correspondingly. It should be noted that, FIG. 24 It shows along FIG. 25 The cross-section shown is obtained by the XXIV-XXIV cutting line and extends in the direction of the arrow along the X-axis.

[0205] like FIG. 24 As shown, a light-shielding film 17 is arranged near the rear surface 11S2 and extends along the XY plane to block light entering the charge retention units MEM1 and MEM2. Component separation units 12 extending along the thickness direction (Z-axis direction) are disposed around the photoelectric conversion units PD1 and PD2. However, the component separation units 12 are partially removed in the charge transport path extending from the photoelectric conversion units PD1 and PD2 to the charge retention units MEM1 and MEM2.

[0206] As in the solid-state imaging device 101 according to the first embodiment described above, in the solid-state imaging device 201 according to the present embodiment, the sensor pixels PX2 are also ZAF pixels. Here, as shown in each of FIGS. 17A and 17B, the sensor pixels PX2 are not provided with the discharge transistor OFG2, the transfer gate TRY2, and the transfer gate TRX2, and the signal lines SL8 to SL10 connected thereto. FIGS. 23-25

[0207]

[0208] <4. Variations of the Second Embodiment>

[0209] (4-1. Seventh Variation)

[0210] [Solid-state Imaging Device 201A]

[0211] FIG. 26 is a circuit diagram showing a circuit configuration of a sensor pixel PX in a pixel array unit of a solid-state imaging device 201A according to the seventh variation and corresponds to FIG. 2 in the first embodiment described above. Further, FIG. 27 shows a cross-sectional configuration example of two sensor pixels PX1 and PX2 included in the pixel array unit of the solid-state imaging device 201A. Further, FIG. 28 shows a planar configuration of four sensor pixels PX1 to PX4 along the front surface 11S1. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 28 FIG. 4G corresponds to FIG. 27 FIG. 28 shows a cross section in an arrow direction taken along the XXVII-XXVII cut line shown in FIG. 17A and extending in the X-axis direction.

[0212] The solid-state imaging device 201A has a configuration similar to that of the solid-state imaging device 201 according to the second embodiment described above except that the solid-state imaging device 201A further includes the discharge transistor OFG2 and the signal line SL8 connected thereto.

[0213] (4-2. Eighth Variation)

[0214] [Solid-state Imaging Device 201B]

[0215] FIG. 29 ​​​​is a circuit diagram showing a circuit configuration of a sensor pixel PX in a pixel array unit of a solid-state imaging device 201B according to an eighth modification example and corresponds to that in the first embodiment described above. Further, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 2 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 30 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 31 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 31 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 4G Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 30 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 31 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns.

[0216] The solid-state imaging device 201B has a configuration similar to that of the solid-state imaging device 201 according to the second embodiment described above, except that the solid-state imaging device 201B further includes a discharge transistor OFG2, a signal line SL8 connected thereto, a transfer gate TRY2, and a signal line SL9 connected thereto.

[0217] (4-3. Ninth Modification Example)

[0218] [Solid-state Imaging Device 201C]

[0219] FIG. 32 is a circuit diagram showing a circuit configuration of a sensor pixel PX in a pixel array unit of a solid-state imaging device 201C according to a ninth modification example and corresponds to that in the first embodiment described above. Further, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201C is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 2 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 33 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 34 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 34 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 4G Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 33 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns. FIG. 34 Corresponding to the above, an example of a cross-sectional configuration of two sensor pixels PX1 and PX2 included in a plurality of sensor pixels PX in the pixel array unit of the solid-state imaging device 201B is shown. Further, a planar configuration of four sensor pixels PX1 to PX4 along a front surface 11S1 is shown. The four sensor pixels PX1 to PX4 are arranged in a grid form of two rows and two columns.

[0220] The solid-state imaging device 201C has a configuration similar to that of the solid-state imaging device 201 according to the above-described second embodiment, except that the solid-state imaging device 201C further includes a transfer transistor TRY2 and a signal line SL9 connected thereto.

[0221] <5. Application examples of electronic devices>

[0222] FIG. 35 is a block diagram showing a configuration example of a camera 2000 as an electronic device to which the present technology is applied.

[0223] The camera 2000 includes an optical unit 2001 including a lens group and the like, an imaging device (imaging device) 2002 that applies the above-described solid-state imaging device 101 and the like (hereinafter referred to as the solid-state imaging device 101 and the like), and a DSP (Digital Signal Processor) circuit 2003 as a camera signal processing circuit. Further, the camera 2000 also includes a frame memory 2004, a display unit 2005, a recording unit 2006, an operation unit 2007, and a power supply unit 2008. The DSP circuit 2003, the frame memory 2004, the display unit 2005, the recording unit 2006, the operation unit 2007, and the power supply unit 2008 are connected to each other through a bus 2009.

[0224] The optical unit 2001 absorbs incident light (image light) from a subject to form an image on an imaging surface of the imaging device 2002. The imaging device 2002 converts an amount of the incident light formed as an image on the imaging surface by the optical unit 2001 into an electric signal in units of pixels and outputs the converted electric signal as a pixel signal.

[0225] For example, the display unit 2005 includes a panel display such as a liquid crystal panel or an organic EL panel and displays a moving image or a still image captured by the imaging device 2002. The recording unit 2006 records a moving image or a still image captured by the imaging device 2002 in a recording medium such as a hard disk or a semiconductor memory.

[0226] The operation unit 2007 issues an operation instruction on various functions of the camera 2000 under the operation of a user. The power supply unit 2008 appropriately supplies various power supplies to the DSP circuit 2003, the frame memory 2004, the display unit 2005, the recording unit 2006, and the operation unit 2007 for the operation of these supply targets.

[0227] As described above, using the above-described solid-state imaging device 101 and the like as the imaging device 2002 makes it possible to expect to obtain a good image.

[0228] <6. Practical application examples of mobile bodies>

[0229] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device mounted on any type of moving body such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, or the like.

[0230] FIG. 36 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0231] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detecting unit 12030, an inside information detecting unit 12040, and a comprehensive control unit 12050. Further, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are shown as functional constitutions of the comprehensive control unit 12050. FIG. 36

[0232] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle in accordance with various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor, which generates the drive force of the vehicle, a drive force transmission mechanism that transmits the drive force to the wheels, a steering mechanism that adjusts the steering angle of the vehicle, a brake device that generates the braking force of the vehicle, and the like.

[0233] The body system control unit 12020 controls the operation of various devices provided to the body of the vehicle in accordance with various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as a headlamp, a tail lamp, a brake lamp, a turn signal lamp, a fog lamp, and the like. In this case, radio waves transmitted from a portable device that is a substitute for a key or signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lamps, and the like of the vehicle.

[0234] ​The vehicle exterior information detection unit 12030 detects information about the outside of the vehicle having the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected with an imaging section 12031. The vehicle exterior information detection unit 12030 causes the imaging section 12031 to image an image of the outside of the vehicle, and receives the captured image. On the basis of the received image, the vehicle exterior information detection unit 12030 can perform a detection process on an object such as a person, a vehicle, an obstacle, a sign or a symbol on a road surface, or a detection process on a distance to such an object.

[0235] The imaging section 12031 is an optical sensor for receiving light and outputting an electric signal corresponding to a light amount of the received light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information on a measured distance. Further, the light received by the imaging section 12031 can be visible light, or can be invisible light such as infrared rays.

[0236] The vehicle interior information detection unit 12040 detects information about the inside of the vehicle. For example, the vehicle interior information detection unit 12040 is connected with a driver state detection section 12041 that detects a state of a driver. The driver state detection section 12041 includes, for example, a camera that images the driver. On the basis of detection information input from the driver state detection section 12041, the vehicle interior information detection unit 12040 can calculate a degree of fatigue of the driver or a degree of concentration of the driver, or can determine whether the driver is dozing off.

[0237] The microcomputer 12051 can calculate a control target value of a driving force generation device, a steering mechanism, or a braking device on the basis of information about the inside or outside of the vehicle, which is obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing functions of an advanced driver assistance system (ADAS) including collision avoidance or impact mitigation of the vehicle, following travel based on an inter-vehicle distance, vehicle speed maintenance travel, vehicle collision warning, or vehicle lane departure warning, and the like.

[0238] Further, the microcomputer 12051 can perform cooperative control aimed at automatic driving, which autonomously causes the vehicle to travel by controlling the driving force generation device, the steering mechanism, the braking device, or the like, on the basis of information about the inside or outside of the vehicle, which is obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, without depending on an operation of the driver or the like.

[0239] Moreover, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of information about the outside of the vehicle that is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent glare by controlling the headlamp to change from a high beam to a low beam in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0240] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device that can visually or aurally notify a passenger of the vehicle or the outside of the vehicle of information. In FIG. 36 Examples of the output device include an audio speaker 12061, a display section 12062, and an instrument panel 12063. The display section 12062 can include at least one of a vehicle-mounted display and a head-up display.

[0241] FIG. 37 FIG. 13 is a diagram showing an example of a mounting position of the imaging section 12031.

[0242] In FIG. 37 The imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0243] The imaging sections 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions on the front nose, the side mirror, the rear bumper, and the rear door of the vehicle 12100 and at a position on the upper portion of the interior windshield. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the interior windshield mainly obtain images of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side mirror mainly obtain images of the side of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the rear door mainly obtains images of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the interior windshield is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, or a lane, and the like.

[0244] Incidentally, FIG. 37Examples of the imaging ranges of the imaging sections 12101 to 12104 are shown. The imaging range 12111 indicates the imaging range of the imaging section 12101 provided to the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging sections 12102 and 12103 provided to the side mirrors. The imaging range 12114 indicates the imaging range of the imaging section 12104 provided to the rear bumper or the rear door. For example, by superimposing the image data taken by the imaging sections 12101 to 12104, an overhead image of the vehicle 12100 viewed from above is obtained.

[0245] At least one of the imaging sections 12101 to 12104 can have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera constituted by a plurality of imaging elements, or can be an imaging element having pixels for phase difference detection.

[0246] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time variation of the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract the closest three-dimensional object as a preceding vehicle, in particular, the three-dimensional object that exists on the travel path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h). Further, the microcomputer 12051 can set in advance the inter-vehicle distance to be maintained in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, cooperative control aimed for automatic driving, which enables the vehicle to travel autonomously without relying on the operation of the driver or the like, can be performed.

[0247] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects on the basis of distance information obtained from the imaging sections 12101 to 12104 into three-dimensional object data on a two-wheeled vehicle, a standard-size vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by a driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a case where the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering by driving the system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collision.

[0248] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian is present in a captured image of the imaging section 12101 to 12104. Such identification of a pedestrian is performed, for example, by a program that extracts feature points in a captured image of the imaging section 12101 to 12104 as an infrared camera and by a program that determines whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian is present in a captured image of the imaging section 12101 to 12104 and thus identifies the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square outline for emphasis is displayed in a manner superimposed on the identified pedestrian. The sound / image output section 12052 can also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0249] An example of a vehicle control system to which the technology according to the present disclosure can be applied is described above. The technology according to the present disclosure can be applied to the imaging section 12031 in the components described above. Specifically, for example, FIG. 1 The solid-state imaging device 101 and the like illustrated in FIG. 7 are suitable for the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, an excellent operation of the vehicle control system can be expected.

[0250] <7. Other modifications>

[0251] Although the present disclosure is described above with reference to several embodiments and modifications, the present disclosure is not limited to the embodiments described above. Various modifications can be made. For example, the present disclosure is not limited to a back-illuminated image sensor, but is also applicable to a front-illuminated image sensor.

[0252] Further, the imaging device according to the present disclosure is not limited to one that detects a light amount distribution of visible light and acquires it as an image, but can be one that acquires an incident amount distribution of infrared rays, X-rays, microparticles, or the like as an image.

[0253] Further, the imaging device according to the present disclosure can also have the form of a module in which the imaging unit and the signal processing unit or the optical system are packaged together.

[0254] Further, in the embodiments described above, a back-illuminated image sensor of a memory holding type global shutter method is described, but the present disclosure is not limited thereto. For example, as shown in each of FIG. 38 and FIG. 39 , a back-illuminated image sensor of an FD holding type global shutter method can also be employed. In the solid-state imaging device 301, charges are held in a charge-voltage conversion unit FD instead of a charge holding unit MEM. The solid-state imaging device 301 further includes a sensor pixel PX1 that functions as a normal pixel and a sensor pixel PX2 that functions as a face phase difference pixel. Note that, FIG. 38 is a circuit diagram showing a circuit configuration of the solid-state imaging device 301 according to the tenth modification example of the present disclosure. FIG. 39 is a schematic plan view showing a planar configuration of a front surface of a semiconductor substrate in the solid-state imaging device 301. In the sensor pixel PX2, the solid-state imaging device 301 is not provided with a discharge transistor OFG2. This reduces the signal line SL connected thereto.

[0255] Further, for example, the solid-state imaging device according to the technology of the present disclosure can have the same configuration as those of the solid-state imaging device 101A shown in FIG. 40A and the solid-state imaging device 101B shown in FIG. 40B . FIG. 40A is a block diagram showing a configuration example of the solid-state imaging device 101A according to the eleventh modification example of the present disclosure. FIG. 40B is a block diagram showing a configuration example of the solid-state imaging device 101B according to the twelfth modification example of the present disclosure.

[0256] In FIG. 40AIn the solid-state imaging device 101A illustrated in FIG. 1, the data storage unit 119 is provided between the column signal processing unit 113 and the horizontal drive unit 114 and supplies the pixel signal output from the column signal processing unit 113 to the signal processing unit 118 through the data storage unit 119.

[0257] Further, FIG. 40B The solid-state imaging device 101B in FIG. 1B is provided with the data storage unit 119 and the signal processing unit 118 in parallel between the column signal processing unit 113 and the horizontal drive unit 114. In the solid-state imaging device 101B, the column signal processing unit 113 performs A / D conversion for each column of the pixel array unit 111 or for a plurality of columns of the pixel array unit 111. The A / D conversion converts an analog pixel signal into a digital pixel signal.

[0258] Further, in the above-described embodiments and the like, a case where an image surface phase difference detection pixel is used as the second pixel is shown, but the present disclosure is not limited to this. For example, the second pixel can be a polarizing pixel including an infrared light information acquisition pixel and a polarizer. FIG. 41 and FIG. 42 are schematic diagrams respectively illustrating a layout pattern of the sensor pixels PX1 to PX4 in the pixel array unit 111 according to the thirteenth and fourteenth modified examples of the present disclosure. In FIG. 41 In FIG. 1C, at the height position Lv2, an NIR pixel including a near-infrared color filter NIR instead of the color filter CF2 is arranged at the position of the sensor pixel PX2 that is the second pixel. The near-infrared color filter NIR selectively transmits near-infrared light. Further, in FIG. 42 In FIG. 1H, at the height position Lv9, a polarizing pixel in which a polarizer PL is arranged is arranged at the position of the sensor pixel PX2 that is the second pixel. However, all of the sensor pixels PX2 in the pixel array unit 111 are not necessarily NIR pixels or polarizing pixels. If some of the sensor pixels PX2 arbitrarily selected in the pixel array unit 111 are NIR pixels or polarizing pixels, this is sufficient.

[0259] Further, in the above-described embodiments and the like, a case where the second pixel does not include a part of the gate electrodes corresponding to the plurality of gate electrodes included in the first pixel is shown, but the present disclosure is not limited to this. For example, the gate electrodes corresponding to all of the gate electrodes in the sensor pixel PX1 that functions as the first pixel can all be included in the sensor pixel PX2 that functions as the second pixel. In this case, for example, as FIG. 43As in the pixel array unit 111G of the solid-state imaging device according to the fifteenth modification illustrated in FIG. 15, it is advantageous to avoid providing a signal line connected to a part of the plurality of gate electrodes in the second pixel. In the pixel array unit 111G, each of the transfer gates TRZ2, TRY2, and TRX2 is arranged and no (part of) wiring connected thereto is provided.

[0260] In the imaging device and the electronic apparatus according to the various embodiments of the present disclosure, the number of the second wirings in the second pixel is smaller than the number of the first wirings in the first pixel. This makes it possible to downsize the overall configuration while ensuring the operation performance required for the second pixel as much as possible.

[0261] Further, the Si{111} substrate according to the present disclosure refers to a substrate or wafer including a silicon single crystal and having a crystal plane represented by {111} in Miller index notation. The Si{111} substrate according to the present disclosure also includes a substrate or wafer whose crystal orientation is deviated by several degrees. For example, the crystal orientation is deviated from the {111} plane by several degrees in the nearest

[110] direction. Further, the Si{111} substrate also includes a silicon single crystal grown on a part or the entire surface of the substrate or the wafer by an epitaxial method or the like.

[0262] Further, in the notation of the present disclosure, the {111} plane is the total of the (111) plane, the (-111) plane, the (1-11) plane, the (11-1) plane, the (-1-11) plane, the (-11-1) plane, the (1-1-1) plane, and the (-1-1-1) plane, which are crystal planes equivalent to each other in terms of symmetry. Thus, for example, the description of the Si{111} substrate in the specification of the present disclosure or the like can also be read as a Si(1-11) substrate. Here, the bar symbol of the Miller index used to represent the index in the negative direction is replaced with a negative sign.

[0263] Further, the <110> direction in the description of the present disclosure is the total of the

[110] direction, the

[101] direction, the

[011] direction, the [-110] direction, the [1-10] direction, the [-101] direction, the [10-1] direction, the [0-11] direction, the [01-1] direction, the [-1-10] direction, the [-10-1] direction, and the [0-1-1] direction, which are crystal plane directions equivalent to each other in terms of symmetry. The <110> direction can also be read as any one of the above. However, in the present disclosure, etching is performed in a direction orthogonal to the element formation surface and further in a direction orthogonal to the direction orthogonal to the element formation surface (i.e., a direction parallel to the element formation surface).

[0264] Table 1 shows specific combinations of planes and orientations of etching in the <110> direction established in the {111} plane of the crystal face of the Si {111} substrate of the present application.

[0265] [Table 1]

[0266]

[0267] As shown in Table 1, there are 96 (= 8 x 12) combinations of {111} planes and <110> directions. However, the <110> direction according to the present disclosure is limited to a direction orthogonal to the {111} plane as an element formation surface and a direction parallel to the element formation surface. In other words, the combination of the element formation surface of the Si {111} substrate and the orientation in which etching is performed on the Si {111} substrate according to the present disclosure is selected from any one of the combinations indicated with a circle in Table 1.

[0268] Further, in the above-described first embodiment, a case where the Si {111} substrate is used to cause etching to be performed in the X-axis direction but not in the Y-axis direction or the Z-axis direction is shown. However, the present disclosure is not limited to this. It is enough if the etching orientation includes both the X-axis direction and the Y-axis direction or either one of the X-axis direction and the Y-axis direction. Further, for example, as shown in FIG. 44 The Si {111} substrate also includes a substrate whose front surface is processed to have an off-angle in the <112> direction, for example, as shown in Table 1. In a case where the off-angle is 19.47° or less, the substrate having the off-angle also maintains the relationship in which the etching rate in the <110> direction (or a direction having one Si back bond) is sufficiently higher than the etching rate in the <111> direction (or a direction having three Si back bonds). A larger off-angle causes the number of steps to increase. This increases the density of microsteps. Therefore, it is preferable that the off-angle be 5° or less. Note that a case where the substrate front surface has an off-angle in the <112> direction is described in the example of FIG. 44 A case where the substrate front surface has an off-angle in the <112> direction is described in the example of Table 1, but the substrate front surface can also have an off-angle in the <110> direction. It does not matter in which direction the off-angle is. Further, the Si plane orientation can be analyzed by using X-ray diffraction, electron beam diffraction, electron beam backscattering diffraction, or the like. The number of Si back bonds is determined by the Si crystal structure and thus the number of back bonds can also be analyzed by analyzing the Si plane orientation.

[0269] Note that the effects described in this specification are merely illustrative and not limited to the description. There can be other effects. Further, the present technology can have the following configurations.

[0270] (1) An imaging device including:

[0271] a first pixel including m (m represents an integer greater than or equal to 2) first wirings and m first gate electrodes connected to the m first wirings, respectively; and

[0272] a second pixel including n (n represents a natural number smaller than m) second wirings and n second gate electrodes connected to the n second wirings, respectively.

[0273] (2) The imaging device according to (1), wherein

[0274] the first pixel includes a first transistor including the first gate electrode, and

[0275] the second pixel includes a second transistor including the second gate electrode.

[0276] (3) The imaging device according to (1) or (2), wherein a first wiring corresponding to a part of the m first wirings and a second wiring corresponding to a part of the n second wirings are a common wiring shared.

[0277] (4) The imaging device according to (3), wherein

[0278] the common wiring includes a first common wiring and a second common wiring,

[0279] the first pixel includes a first reset transistor including the first gate electrode connected to the first common wiring and a first selection transistor including the first gate electrode connected to the second common wiring, and

[0280] the second pixel includes a second reset transistor including the second gate electrode connected to the first common wiring and a second selection transistor including the second gate electrode connected to the second common wiring.

[0281] (5) The imaging device according to any one of (1) to (4), wherein

[0282] the first pixel is an imaging pixel that acquires visible light information, and

[0283] the second pixel acquires information other than the visible light information.

[0284] (6) The imaging device according to (5), wherein the second pixel includes a phase difference detection pixel, an infrared light information acquisition pixel, or a polarizer.

[0285] (7) The imaging device according to any one of (1) to (6), wherein a shape of a formation region of the first pixel and a shape of a formation region of the second pixel are substantially the same.

[0286] (8) The imaging device according to any one of (1) to (7), wherein

[0287] the first pixel further includes a first photoelectric conversion unit configured to generate a first electric charge corresponding to an amount of received light by photoelectric conversion, and a first charge-voltage conversion unit that converts the first electric charge into a voltage signal,

[0288] the second pixel further includes a second photoelectric conversion unit configured to generate a second electric charge corresponding to an amount of received light by photoelectric conversion, and a second charge-voltage conversion unit that converts the second electric charge into a voltage signal,

[0289] the first pixel is provided with p (p represents a natural number smaller than m) first transistors between the first photoelectric conversion unit and the first charge-voltage conversion unit, and

[0290] the second pixel is provided with q (q represents an integer smaller than p and greater than or equal to 0) second transistors between the second photoelectric conversion unit and the second charge-voltage conversion unit.

[0291] (9) The imaging device according to (8), wherein the first pixel includes a global shutter pixel further including a charge holding unit configured to hold the first electric charge between the first photoelectric conversion unit and the first charge-voltage conversion unit.

[0292] (10) An electronic device including

[0293] an imaging device, wherein

[0294] the imaging device includes

[0295] a first pixel including m (m represents an integer greater than or equal to 2) first wirings and m first gate electrodes respectively connected to the m first wirings, and

[0296] a second pixel including n (n represents a natural number smaller than m) second wirings and n second gate electrodes respectively connected to the n second wirings.

[0297] This application claims priority to Japanese Patent Application No. 2019-222999 filed in the Japan Patent Office on December 10, 2019, the entire contents of which are incorporated herein by reference.

[0298] Those skilled in the art will appreciate that various modifications, combinations, subcombinations, and alterations can be made to the disclosed embodiments within the scope of the appended claims or their equivalents, such as, for example, by designing a system according to any equivalent theory.

Claims

1. An imaging device comprising: a first pixel including m first wirings and m first gate electrodes connected to the m first wirings, respectively, where m represents an integer greater than or equal to 2; and a second pixel including n second wirings and n second gate electrodes connected to the n second wirings, respectively, where n represents a natural number smaller than m, wherein the first pixel further includes a first photoelectric conversion unit configured to generate a first electric charge corresponding to an amount of received light by photoelectric conversion, and a first charge-voltage conversion unit that converts the first electric charge into a voltage signal, the second pixel further includes a second photoelectric conversion unit configured to generate a second electric charge corresponding to an amount of received light by photoelectric conversion, and a second charge-voltage conversion unit that converts the second electric charge into a voltage signal, the first pixel is provided with p first transistors between the first photoelectric conversion unit and the first charge-voltage conversion unit, where p represents a natural number smaller than m, and the second pixel is provided with q second transistors between the second photoelectric conversion unit and the second charge-voltage conversion unit, where q represents an integer smaller than p and greater than or equal to 0.

2. The imaging device according to claim 1, wherein the first pixel includes a first transistor including the first gate electrode, and the second pixel includes a second transistor including the second gate electrode.

3. The imaging device according to claim 1, wherein a first wiring corresponding to a part of the m first wirings and a second wiring corresponding to a part of the n second wirings are a shared common wiring.

4. The imaging device according to claim 3, wherein the common wiring includes a first common wiring and a second common wiring, the first pixel includes a first reset transistor including the first gate electrode connected to the first common wiring and a first selection transistor including the first gate electrode connected to the second common wiring, and the second pixel includes a second reset transistor including the second gate electrode connected to the first common wiring and a second selection transistor including the second gate electrode connected to the second common wiring.

5. The imaging device according to any one of claims 1 to 4, wherein the first pixel includes an imaging pixel that acquires visible light information, and the second pixel acquires information other than the visible light information.

6. The imaging device according to claim 5, wherein the second pixel includes an image plane phase difference detection pixel, an infrared light information acquisition pixel, or a polarizer.

7. The imaging device according to any one of claims 1 to 4, wherein a shape of a formation region of the first pixel and a shape of a formation region of the second pixel are substantially the same. ​ 8.The imaging device of claim 1, wherein the first pixel comprises a global shutter pixel further comprising a charge holding unit between the first photoelectric conversion unit and the first charge-voltage conversion unit, the charge holding unit configured to hold the first charge. 9.An electronic device comprising the imaging device of any one of claims 1-8.

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