Light receiving device

Abstract

In a light-receiving device (1), a light-receiving element (10) includes a first photoelectric conversion unit (PD) that converts light into electric charges, a first charge accumulation unit (MEM) that transfers the electric charges from the first photoelectric conversion unit, a first distribution gate (150) that distributes the electric charges from the first photoelectric conversion unit to the first charge accumulation unit, a second charge accumulation unit (MEM) that transfers the electric charges from the first photoelectric conversion unit, and a second distribution gate (150) that distributes the electric charges from the first photoelectric conversion unit to the second charge accumulation unit, wherein the first distribution gate and the second distribution gate are disposed at positions that are line-symmetrical to each other with respect to a first central axis that extends through the center of the first photoelectric conversion unit in a direction that intersects with the column direction at a predetermined angle when viewed from above the semiconductor substrate (200).

Description

Technical Field

[0001] This disclosure relates to a light-receiving device. Background Technology

[0002] As a method for measuring distance to an object, time-of-flight (TOF) sensors (light-receiving devices) are known. For example, in an indirect TOF sensor, an indirect TOF sensor is configured to emit illumination light having a predetermined period to the object and detect the phase difference between the illumination light and the reflected light, thereby measuring the distance to the object.

[0003] List of cited references

[0004] Patent documents

[0005] Patent Document 1: JP 2019-4149 A Summary of the Invention

[0006] Technical issues

[0007] For such TOF sensors (light receiving devices), high ranging accuracy must be ensured even when manufacturing deviations occur.

[0008] Therefore, in view of this situation, this disclosure proposes a light-receiving device configured to ensure high ranging accuracy by making the light-receiving device less susceptible to manufacturing deviations.

[0009] Solution to the problem

[0010] According to this disclosure, a light-receiving device is provided. The light-receiving device includes a light-receiving unit comprising a plurality of light-receiving elements arranged along row and column directions on a semiconductor substrate. In the light-receiving device, each light-receiving element includes: a first photoelectric conversion unit that converts light into electrical charge; a first charge accumulation unit that transfers charge from the first photoelectric conversion unit to the first charge accumulation unit; a first distribution gate that distributes charge from the first photoelectric conversion unit to the first charge accumulation unit; a second charge accumulation unit that transfers charge from the first photoelectric conversion unit to the second charge accumulation unit; and a second distribution gate that distributes charge from the first photoelectric conversion unit to the second charge accumulation unit. Furthermore, when viewed from above the semiconductor substrate, the first and second distribution gates are positioned linearly symmetrical to each other with respect to a first central axis that extends through the center of the first photoelectric conversion unit along a direction intersecting the column direction at a predetermined angle.

[0011] Furthermore, according to this disclosure, a light-receiving device is provided. The light-receiving device includes a light-receiving unit comprising a plurality of light-receiving elements arranged along a row and column direction on a semiconductor substrate. In the light-receiving device, each light-receiving element includes: a first photoelectric conversion unit that converts light into electrical charge; a first charge accumulation unit that transfers charge from the first photoelectric conversion unit to the first charge accumulation unit; a first distribution gate that distributes charge from the first photoelectric conversion unit to the first charge accumulation unit; a second charge accumulation unit that transfers charge from the first photoelectric conversion unit to the second charge accumulation unit; and a second distribution gate that distributes charge from the first photoelectric conversion unit to the second charge accumulation unit. Furthermore, when viewed from above the semiconductor substrate, the first distribution gate and the second distribution gate are positioned linearly symmetrical to each other with respect to a first central axis that extends along the column direction through the center of the first photoelectric conversion unit. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating an example configuration of the ranging module 1 according to an embodiment of the present disclosure.

[0013] Figure 2A This is an explanatory diagram (No. 1) showing a planar configuration example of the light-receiving unit 30 according to an embodiment of the present disclosure.

[0014] Figure 2B This is an explanatory diagram (No. 2) showing a planar configuration example of the light-receiving unit 30 according to an embodiment of the present disclosure.

[0015] Figure 2C This is an explanatory diagram (No. 3) showing a planar configuration example of the light-receiving unit 30 according to an embodiment of the present disclosure.

[0016] Figure 3 This is an equivalent circuit diagram of the light-receiving element 10 according to the embodiments of this disclosure.

[0017] Figure 4 This is an explanatory diagram illustrating the principle of the distance calculation method using the distance measuring module 1 according to the embodiment of this disclosure.

[0018] Figure 5 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the first embodiment of this disclosure.

[0019] Figure 6 It is along Figure 5 The cross-sectional view of the light-receiving element 10 taken by line A-A' in the figure.

[0020] Figure 7 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a first modification of the first embodiment of the present disclosure.

[0021] Figure 8 This is an equivalent circuit diagram of the light-receiving element 10 according to a second variation of the first embodiment of this disclosure.

[0022] Figure 9 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a second variation of the first embodiment of the present disclosure.

[0023] Figure 10 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a third variation of the first embodiment of the present disclosure.

[0024] Figure 11 It is along Figure 10 The cross-sectional view of the light-receiving element 10 taken by line A-A' in the figure.

[0025] Figure 12 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a fourth modification of the first embodiment of this disclosure.

[0026] Figure 13 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a fifth modification of the first embodiment of the present disclosure.

[0027] Figure 14 This is an equivalent circuit diagram of the light-receiving element 10 according to the sixth variation of the first embodiment of this disclosure.

[0028] Figure 15 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a sixth modification of the first embodiment of the present disclosure.

[0029] Figure 16 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a seventh modification of the first embodiment of the present disclosure.

[0030] Figure 17 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the eighth modification of the first embodiment of this disclosure.

[0031] Figure 18 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a ninth modification of the first embodiment of this disclosure.

[0032] Figure 19 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the tenth modification of the first embodiment of this disclosure.

[0033] Figure 20 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the eleventh modification of the first embodiment of this disclosure.

[0034] Figure 21This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the twelfth modification of the first embodiment of this disclosure.

[0035] Figure 22 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the thirteenth modification of the first embodiment of this disclosure.

[0036] Figure 23 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the fourteenth modification of the first embodiment of this disclosure.

[0037] Figure 24 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the fifteenth modification of the first embodiment of this disclosure.

[0038] Figure 25 This is an equivalent circuit diagram of the light-receiving element 10 according to the sixteenth variation of the first embodiment of this disclosure.

[0039] Figure 26 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the sixteenth variation of the first embodiment of this disclosure.

[0040] Figure 27 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the seventeenth modification of the first embodiment of this disclosure.

[0041] Figure 28 This is an equivalent circuit diagram of the light-receiving element 10 according to the eighteenth variation of the first embodiment of this disclosure.

[0042] Figure 29 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the eighteenth variation of the first embodiment of this disclosure.

[0043] Figure 30 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the nineteenth variation of the first embodiment of the present disclosure.

[0044] Figure 31 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twentieth variation of the first embodiment of the present disclosure.

[0045] Figure 32 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-first modification of the first embodiment of the present disclosure.

[0046] Figure 33 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-second variation of the first embodiment of the present disclosure.

[0047] Figure 34 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-third modification of the first embodiment of the present disclosure.

[0048] Figure 35 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-fourth variation of the first embodiment of the present disclosure.

[0049] Figure 36 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-fifth modification of the first embodiment of the present disclosure.

[0050] Figure 37 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-sixth variation of the first embodiment of the present disclosure.

[0051] Figure 38 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-seventh variation of the first embodiment of the present disclosure.

[0052] Figure 39 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-eighth variation of the first embodiment of the present disclosure.

[0053] Figure 40 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-ninth variation of the first embodiment of the present disclosure.

[0054] Figure 41 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirtieth variation of the first embodiment of the present disclosure.

[0055] Figure 42 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-first modification of the first embodiment of this disclosure.

[0056] Figure 43 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-second variation of the first embodiment of this disclosure.

[0057] Figure 44 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-third modification of the first embodiment of this disclosure.

[0058] Figure 45 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-fourth modification of the first embodiment of the present disclosure.

[0059] Figure 46This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-fifth modification of the first embodiment of the present disclosure.

[0060] Figure 47 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the thirty-sixth to fortieth modifications of the first embodiment of this disclosure.

[0061] Figure 48 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-sixth variation of the first embodiment of the present disclosure.

[0062] Figure 49 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-seventh modification of the first embodiment of the present disclosure.

[0063] Figure 50 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-eighth variation of the first embodiment of the present disclosure.

[0064] Figure 51 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-ninth variation of the first embodiment of the present disclosure.

[0065] Figure 52 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the fortieth variation of the first embodiment of the present disclosure.

[0066] Figure 53 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the forty-first modification of the first embodiment of this disclosure.

[0067] Figure 54 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the forty-first modification of the first embodiment of this disclosure.

[0068] Figure 55 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the second embodiment of this disclosure.

[0069] Figure 56A It is along Figure 55 The cross-sectional view of the light-receiving element 10 taken by line C-C' in the figure.

[0070] Figure 56B It is along Figure 55 The cross-sectional view of the light-receiving element 10 taken by line D-D' in the figure.

[0071] Figure 57 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the third embodiment of this disclosure.

[0072] Figure 58A It is along Figure 57 The cross-sectional view of the light-receiving element 10 taken by line E-E' in the figure.

[0073] Figure 58B It is along Figure 57 The cross-sectional view of the light-receiving element 10 taken by line F-F' in the figure.

[0074] Figure 59 This is a block diagram illustrating an example of the configuration of a smartphone 900, which is an electronic device to which the ranging module 1 is applicable according to an embodiment of the present disclosure.

[0075] Figure 60 This is a diagram illustrating an example of the schematic configuration of an endoscopic surgical system.

[0076] Figure 61 This is a diagram illustrating an example of the structure of an endoscope.

[0077] Figure 62 This is a block diagram illustrating an example of the functional configuration of a camera and a CCU.

[0078] Figure 63 This is a block diagram illustrating an example of the schematic configuration of a vehicle control system.

[0079] Figure 64 This is a diagram showing an example of the installation location of the vehicle exterior information detection unit and the imaging unit. Detailed Implementation

[0080] Preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. Note that in this specification and the drawings, constituent elements having substantially the same functional configuration are indicated by the same reference numerals, and redundant descriptions are omitted.

[0081] Furthermore, in this specification and accompanying drawings, in some cases, multiple constituent elements having substantially the same function are distinguished by adding different numbers after the same reference numeral. However, when it is not necessary to specifically distinguish multiple constituent elements having substantially the same or similar functions, each constituent element is simply labeled with the same reference numeral. Additionally, in some cases, similar constituent elements in different embodiments are distinguished by adding different letters after the same reference numeral. When it is not necessary to specifically distinguish multiple similar constituent elements, each constituent element is simply labeled with the same reference numeral.

[0082] Furthermore, the accompanying drawings referenced in the following description are for illustrative purposes and to facilitate understanding of embodiments of this disclosure. Therefore, for ease of understanding, the shapes, dimensions, proportions, etc., of the constituent elements shown in the drawings may differ from the actual constituent elements. Moreover, considering the following description and known technology, the constituent elements, etc., included in the components and devices shown in the drawings can be appropriately modified in the design.

[0083] Furthermore, the following description uses a back-illuminated type light-receiving device to which the embodiments of this disclosure are applicable as an example. Therefore, in this light-receiving device, light is incident on the back side of the substrate. Therefore, in the following description, when the side where light is incident is defined as the back side, the front side of the substrate refers to the surface facing the back side. Note that the embodiments of this disclosure are not limited to back-illuminated type light-receiving devices, but can also be applied to, for example, front-illuminated type light-receiving devices.

[0084] The specific shapes and positional relationships described below do not refer to geometrically defined shapes and positional relationships. Specifically, the descriptions of specific shapes, etc., in the following descriptions include permissible variations (errors / distortions) in the component, its manufacture, and its use and operation. For example, in the following descriptions, the expression "circular" or "approximately circular" means that the shape is not limited to a perfect circle, but includes shapes similar to a perfect circle, such as an ellipse.

[0085] Furthermore, in the following description of circuits (electrical connections), unless otherwise stated, the term "electrical connection" refers to the interconnection of multiple elements to enable electrical (signal) conduction. The term "electrical connection" in the following description includes not only direct electrical connections between multiple elements but also indirect electrical connections between multiple elements via other elements.

[0086] Furthermore, in the following description, unless otherwise stated, the term "shared" means that other elements are set to be shared by a plurality of one element; in other words, other elements are shared among a predetermined number of one elements.

[0087] Note that the explanations will be given in the following order.

[0088] 1. Configuration example of ranging module 1 according to the embodiment of this disclosure

[0089] 2. Configuration example of the light-receiving unit 30 according to the embodiment of this disclosure

[0090] 3. Equivalent circuit of the light-receiving element 10 according to the embodiment of this disclosure.

[0091] 4. The principle of the distance calculation method using the ranging module 1 according to the embodiment of this disclosure.

[0092] 5. Background of this implementation plan

[0093] 6. First Implementation Plan

[0094] 7. Second Implementation Plan

[0095] 8. Third Implementation Plan

[0096] 9. Summary

[0097] 10. Examples of the composition of electronic devices

[0098] 11. Examples of the application of endoscopic surgical systems

[0099] 12. Examples of applications of moving bodies

[0100] 13. Supplementary Explanation

[0101] <<1. Configuration Example of Distance Measuring Module 1 according to the Embodiment of this Disclosure>>

[0102] First, refer to Figure 1 This section describes the schematic configuration of the ranging module (light receiving device) 1 according to the embodiments of this disclosure. Figure 1 This is a block diagram illustrating an example configuration of the ranging module 1 according to an embodiment of the present disclosure. Specifically, as shown... Figure 1 As shown, the ranging module 1 mainly includes a light-emitting unit 20, a light-receiving unit 30, a control unit (light-emitting control unit) 40, and a processing unit 60. The functional blocks included in the ranging module 1 according to this embodiment will be described below.

[0103] (Light-emitting unit 20)

[0104] The light-emitting unit 20 includes a light-emitting diode (LED) light source (not shown) and optical elements (not shown). The wavelength of the emitted light can be changed by appropriately selecting the LED light source. Note that in this embodiment, for example, the light-emitting unit 20 emits infrared light in the wavelength range of 780 nm to 1000 nm, but not limited to that emitted in the range of 780 nm to 1000 nm. Furthermore, the light-emitting unit 20 is configured to emit light toward the object 800 having a brightness that changes periodically in sync with a periodic signal, such as a rectangular signal, supplied from the control unit 40 described later.

[0105] (Light-receiving unit 30)

[0106] The light-receiving unit 30 receives reflected light from the object 800. The light-receiving unit 30 includes a condenser lens (not shown) and a plurality of light-receiving elements 10 described later. The condenser lens has the function of converging the received light onto each of the light-receiving elements 10. Furthermore, the light-receiving elements 10 generate charges (e.g., electrons) based on the intensity of the received light, causing the generated charges to drive built-in transistors (distribution transistor VG; see below) synchronously with periodic signals such as rectangular signals supplied from the control unit 40 described later. Figure 3 ), and transfer the charge to the charge accumulation unit MEM (refer to Figure 3 Furthermore, the charge transferred to the charge accumulation unit MEM is converted into a signal and ultimately transmitted to the processing unit 60. Note that the light-receiving element 10 will be described in detail later.

[0107] (Control Unit 40)

[0108] The control unit 40 supplies periodic signals to the light-emitting unit 20 and the light-receiving unit 30 to control the emission timing of the illumination light and the driving timing of the transistors. The frequency of the signal can be, for example, 5–20 MHz, but is not limited to such a frequency in this embodiment. Furthermore, the control unit 40 differentially controls the transistors (e.g., the distribution transistor VG; see reference 1) Figure 3 It can be operated at different times.

[0109] (Processing Unit 60)

[0110] The processing unit 60 is configured to acquire the signal from the light-receiving unit 30 and, based on the acquired signal, obtain the distance to the object 800 via, for example, an indirect ToF (iToF) method. Note that the distance calculation method will be described later.

[0111] <<2. Configuration Example of Light Receiving Unit 30 according to the Embodiment of this Disclosure>>

[0112] Next, we will refer to Figures 2A to 2C This section describes an example of the planar configuration of the light-receiving unit 30 according to the embodiment of this disclosure. Figures 2A to 2C These are explanatory diagrams illustrating planar configuration examples of the light-receiving unit 30 according to embodiments of the present disclosure. Specifically, as shown... Figure 2A As shown, the light-receiving unit 30 according to this embodiment includes a pixel array unit 12, a vertical driving circuit unit 32, a column signal processing circuit unit 34, a horizontal driving circuit unit 36, an output circuit unit 38, a control circuit unit 44, etc., on a semiconductor substrate 200 made of, for example, silicon. The various blocks of the light-receiving unit 30 according to this embodiment will be described in detail below.

[0113] (Pixel array unit 12)

[0114] The pixel array unit 12 includes a plurality of light-receiving elements 10 arranged in a matrix (i.e., rows and columns in the row and column directions) on a semiconductor substrate 200. Each light-receiving element 10 includes a photoelectric conversion unit (photodiode PD) (not shown) that converts light into charge (e.g., electrons), a plurality of pixel transistors (e.g., metal-oxide-semiconductor (MOS) transistors (not shown), etc. In other words, the pixel array unit 12 includes a plurality of pixels that perform photoelectric conversion on incident light and output a signal according to the obtained charge. Thus, the pixel transistors may include, for example, transistors with various functions, such as transfer transistors, selection transistors, reset transistors, and amplification transistors. Note that the equivalent circuits of each light-receiving element 10 will be described in detail later.

[0115] Here, row direction refers to the horizontal arrangement of the light-receiving elements 10, and column direction refers to the vertical arrangement of the light-receiving elements 10. Row direction is... Figure 2A The left and right directions, and the column direction are... Figure 2A The vertical direction within the pixel array unit 12. For the matrix array of light-receiving elements 10, pixel drive lines 42 are routed along the row direction for each row, and vertical signal lines 48 are routed along the column direction for each column. For example, pixel drive lines 42 transmit drive signals for performing drive operations when reading signals from each light-receiving element 10.

[0116] (Vertical drive circuit unit 32)

[0117] The vertical drive circuit unit 32, for example, is composed of a shift register, an address decoder, etc., selects any pixel drive line 42, supplies pulses for driving the light-receiving element 10 to the selected pixel drive line 42, and drives all light-receiving elements 10 simultaneously or row by row. For example, the vertical drive circuit unit 32 sequentially drives the light-receiving elements 10 in the vertical direction row by row. Figure 2A The pixel array unit 12 selectively scans each light-receiving element 10 in the vertical direction and supplies pixel signals based on the charge generated according to the amount of light received by the photodiode PD of each light-receiving element 10 to each column signal processing circuit unit 34 described later via each vertical signal line 48.

[0118] (List signal processing circuit unit 34)

[0119] Column signal processing circuit units 34 are arranged in each column of the light-receiving element 10, and perform signal processing such as noise removal on the signals output from the light-receiving element 10 in each column. For example, column signal processing circuit units 34 perform signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion to remove the fixed-mode noise inherent in the light-receiving element 10.

[0120] (Horizontal drive circuit unit 36)

[0121] The horizontal drive circuit unit 36 ​​is composed of, for example, a shift register, an address decoder, etc., and is configured to output horizontal scanning pulses in sequence, sequentially select each of the above-mentioned column signal processing circuit units 34, and output signals from each of the column signal processing circuit units 34 to the horizontal signal line 46.

[0122] (Output circuit unit 38)

[0123] The output circuit unit 38 is configured to process the signals sequentially supplied from each column signal processing circuit unit 34 via the horizontal signal line 46 and output the processed signals. The output circuit unit 38 can function as, for example, a buffering unit, or perform processing such as column offset correction or various digital signal processing. Note that buffering refers to temporarily storing signals to compensate for differences in processing or transmission speeds during signal exchange.

[0124] (Control circuit unit 44)

[0125] The control circuit unit 44 receives an input clock and data for indicating the operating mode, and outputs data such as internal information about the light-receiving element 10. In other words, the control circuit unit 44 generates clock signals and control signals based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, which serve as operating references for the vertical drive circuit unit 32, the column signal processing circuit unit 34, the horizontal drive circuit unit 36, etc. Then, the control circuit unit 44 outputs the generated clock signals and control signals to the vertical drive circuit unit 32, the column signal processing circuit unit 34, the horizontal drive circuit unit 36, etc.

[0126] (Assigning transistor drive unit 50, signal processing unit 52, and data storage unit 54)

[0127] like Figure 2B and Figure 2C As shown, the light-receiving element 10 may be provided with a distribution transistor driving unit 50, a signal processing unit 52, and a data storage unit 54. In other words, the distribution transistor driving unit 50, the signal processing unit 52, and the data storage unit 54 may be disposed on the semiconductor substrate 200. However, this embodiment is not limited to this, and the distribution transistor driving unit 50, the signal processing unit 52, and the data storage unit 54 may be disposed on other semiconductor substrates (not shown). First, the distribution transistor driving unit 50 controls the distribution transistor VG (see below) described later. Figure 3 The operation of the transistor drive unit 50 is as follows. For example, the transistor drive unit 50 can be configured as follows: Figure 2B As shown, it is positioned adjacent to pixel array unit 12 in the column direction, or it can be as follows: Figure 2CThe diagram shows that the transistor driving unit 50 is positioned adjacent to the pixel array unit 12 in the row direction, and there are no particular limitations on the allocation of the transistor driving unit 50 in this embodiment. Furthermore, the signal processing unit 52 has at least computational processing capabilities and performs various signal processing operations, such as computational processing, based on the signal output from the output circuit unit 38. For the signal processing in the signal processing unit 52, the data storage unit 54 temporarily stores the data required for the signal processing.

[0128] Note that the planar configuration of the light-receiving unit 30 according to this embodiment is not limited to... Figures 2A to 2C The example shown may include, but is not specifically limited to, other circuits, etc.

[0129] <<3. Equivalent circuit of the light-receiving element 10 according to the embodiment of this disclosure>>

[0130] Next, refer to Figure 3 The equivalent circuit of the light-receiving element 10 according to the embodiment of this disclosure will be described. Figure 3 This is an equivalent circuit diagram of the light-receiving element 10 according to the embodiments of this disclosure.

[0131] Specifically, such as Figure 3 As shown, the light-receiving element 10 includes a photodiode PD as a photoelectric conversion element (photoelectric conversion unit) that converts light into charge, and an exhaust transistor OFG (although the exhaust transistor OFG is shown as a single transistor in an equivalent circuit, the exhaust transistor OFG may include multiple transistors electrically connected in parallel). Furthermore, the light-receiving element 10 includes two distribution transistors VG, two charge accumulation units (first and second charge accumulation units) MEM, two transfer transistors TG, two floating diffusion regions FD, two reset transistors RST, two amplification transistors AMP, and two selection transistors SEL.

[0132] like Figure 3 As shown, in the light-receiving element 10, one of the source / drain terminals of the discharge transistor OFG is electrically connected to the photodiode PD, which generates charge in response to light. Furthermore, the other of the source / drain terminals of the discharge transistor OFG is electrically connected to the power supply circuit (power supply potential VDD). The discharge transistor OFG is then configured to turn on according to the voltage applied to its own gate, and discharge the charge accumulated in the photodiode PD to the power supply circuit (power supply potential VDD).

[0133] In addition, such as Figure 3As shown, in the light-receiving element 10, one of the source / drain terminals of each of the distribution transistors VG1 and VG2 is electrically connected to the photodiode PD, and the other of the source / drain terminals of each of the distribution transistors VG1 and VG2 is electrically connected to charge accumulation units MEM1 and MEM2, respectively. The distribution transistors VG1 and VG2 are then configured to turn on according to the voltage applied to their own gates (first distribution gate and second distribution gate), and transfer the charge accumulated in the photodiode PD to the charge accumulation units MEM1 and MEM2. In other words, in this embodiment, the voltage applied to the gates of the distribution transistors VG1 and VG2 varies at different times, thus allowing the charge accumulated in the photodiode PD to be distributed to either of the two charge accumulation units MEM1 and MEM2. In other words, it can be said that the two charge accumulation units MEM1 and MEM2 share a single photodiode PD.

[0134] In addition, such as Figure 3 As shown, in the light-receiving element 10, one of the source / drain terminals of each of the transfer transistors TG1 and TG2 is electrically connected to the other of the source / drain terminals of each of the distribution transistors VG1 and VG2, as well as to each of the charge accumulation units MEM1 and MEM2. Furthermore, the other of the source / drain terminals of each of the transfer transistors TG1 and TG2 is electrically connected to each of the floating diffusion regions FD1 and FD2. The transfer transistors TG1 and TG2 are then configured to turn on according to a voltage applied to their own gates (transfer gates) and transfer the charge accumulated in the charge accumulation units MEM1 and MEM2 to the floating diffusion regions FD1 and FD2. Note that in embodiments of this disclosure, the two charge accumulation units MEM1 and MEM2 also allow the transfer transistors TG1 and TG2 to share a single floating diffusion region FD.

[0135] Furthermore, floating diffusion regions FD1 and FD2 are electrically connected to the gates of amplifying transistors AMP1 and AMP2. Each of amplifying transistors AMP1 and AMP2 converts (amplifies) charge into voltage and outputs the voltage as a signal (pixel signal). One of the source / drain terminals of each of amplifying transistors AMP1 and AMP2 is electrically connected to one of the source / drain terminals of each of select transistors SEL1 and SEL2. Select transistors SEL1 and SEL2 output the converted signal to signal lines VSL1 and VSL2 according to the selection signal. Additionally, the other of the source / drain terminals of each of amplifying transistors AMP1 and AMP2 is electrically connected to the power supply circuit (power supply potential VDD).

[0136] Furthermore, the other of the source / drain terminals of each of the selection transistors SEL1 and SEL2 is electrically connected to each of the signal lines VSL1 and VSL2, which transmit the voltage obtained through conversion as a signal, and is further electrically connected to the column signal processing circuit unit 34 described above. Additionally, the gates of the selection transistors SEL1 and SEL2 are electrically connected to the selection lines (not shown) for selecting rows to output signals, and are further electrically connected to the vertical drive circuit unit 32 described above. In other words, under the control of the selection transistors SEL1 and SEL2, the charge accumulated in the floating diffusion regions FD1 and FD2 is converted into voltage by the amplification transistors AMP1 and AMP2 and output to the signal lines VSL1 and VSL2.

[0137] In addition, such as Figure 3 As shown, each of the floating diffusion regions FD1 and FD2 is electrically connected to one of the drain / source terminals of each of the reset transistors RST1 and RST2, which are used to reset accumulated charge. The gate of each of the reset transistors RST1 and RST2 is electrically connected to a reset distribution transistor (not shown) and further electrically connected to the vertical drive circuit unit 32 described above. Additionally, the other of the drain / source terminals of each of the reset transistors RST1 and RST2 is electrically connected to a power supply circuit (power supply potential VDD). The reset transistors RST1 and RST2 are then configured to turn on according to the voltage applied to their own gates, and to reset the charge accumulated in the floating diffusion regions FD1 and FD2 (discharged to the power supply circuit (power supply potential VDD)).

[0138] Note that the equivalent circuit of the light-receiving element 10 according to this embodiment is not limited to... Figure 3 The example shown may include, but is not specifically limited to, other elements, etc.

[0139] Here, a brief example of the operation of the light-receiving element 10 will be described.

[0140] First, before light is received, a discharge operation is performed to remove the charge from the photodiode PD. In other words, discharge transistors OFG1 and OFG2 are turned on, and the charge in the photodiode PD is discharged to the power supply circuit (power supply potential VDD).

[0141] Next, when light is received, the distribution transistors VG1 and VG2 operate at different times (e.g., differentially). Specifically, during the first period, distribution transistor VG1 is turned on, thereby transferring the charge in the photodiode PD to the charge accumulation unit MEM1. On the other hand, during the second period, distribution transistor VG2 is turned on, thereby transferring the charge in the photodiode PD to the charge accumulation unit MEM2. In other words, the charge generated by the photodiode PD is distributed to the charge accumulation units MEM1 and MEM2 by distribution transistors VG1 and VG2.

[0142] Next, a charge removal operation is performed in the floating diffusion regions FD1 and FD2. In other words, reset transistors RST1 and RST2 are turned on, and the charge in the floating diffusion regions FD1 and FD2 is discharged to the power supply circuit (power supply potential VDD). Then, the charge (KTC noise) generated in the floating diffusion regions FD1 and FD2 is preferably removed by driving the CDS.

[0143] Then, transmission transistors TG1 and TG2 are turned on, and the charge accumulated in charge accumulation units MEM1 and MEM2 is transferred to floating diffusion regions FD1 and FD2. Then, when the light-receiving period ends, the light-receiving elements 10 in the pixel array unit 12 are selected sequentially. Among the selected light-receiving elements 10, selection transistors SEL1 and SEL2 are turned on. Therefore, the charge accumulated in floating diffusion regions FD1 and FD2 is output as a signal to signal lines VSL1 and VSL2.

[0144] Note that the operation of the light-receiving element 10 according to this embodiment is not limited to the example described above; for example, the order may be appropriately changed. In this embodiment, the distance to the object 800 is obtained from the distribution ratio of the charge accumulated in the two floating diffusion regions FD1 and FD2. The principle will be briefly explained below.

[0145] <<4. Principle of the distance calculation method using the ranging module 1 according to the embodiment of this disclosure>>

[0146] Next, we will refer to Figure 4 The principle of the distance calculation method (indirect) using the ranging module 1 according to the embodiment of this disclosure is explained. Figure 4 This is an explanatory diagram illustrating the principle of the distance calculation method using the ranging module 1 according to the embodiment of this disclosure. Specifically, Figure 4 The diagram schematically illustrates the change in the intensity of the illumination and reflected light in the ranging module 1 over time.

[0147] like Figure 4As shown, the ranging module 1 emits modulated light from the light-emitting unit 20 towards the object 800, causing the light intensity to change periodically. The emitted light is reflected by the object 800 and detected as reflected light by the light-receiving unit 30 of the ranging module 1. Figure 4 As shown, the detected reflected light ( Figure 4 The second one from the top) relative to the irradiated light ( Figure 4 The first one from the top has a phase difference φ, which increases as the distance from the ranging module 1 to the object 800 increases and decreases as the distance from the ranging module 1 to the object 800 decreases.

[0148] As described above, the light-receiving element 10 according to this embodiment includes, for example, differentially operating distribution transistors VG1 and VG2. Therefore, the distribution transistors VG1 and VG2 have operating periods that do not overlap with each other, and... Figure 4 During the periods of regions 802a and 802b, indicated in gray, the charge accumulated in the photodiode PD is distributed to charge accumulation units MEM1 and MEM2. Specifically, the charge distributed to charge accumulation units MEM1 and MEM2 is transferred to floating diffusion regions FD1 and FD2, ultimately converting into a signal corresponding to the area representing the integral value during the periods of regions 802a and 802b. Therefore, from Figure 4 It can be clearly seen that the difference between the integral value of region 802a and the integral value of region 802b varies according to the phase difference φ of the reflected light. Therefore, in this embodiment, the distance to object 800 can be calculated by calculating the phase difference φ based on the difference between the integral values ​​of region 802a and region 802b. Note that in this embodiment, the distance can also be calculated by using the ratio between integral values ​​instead of the difference between them.

[0149] <<5. Background of this Implementation Plan>>

[0150] The above describes the principles of the ranging module 1, the light-receiving unit 30, and the distance calculation method according to the embodiments of this disclosure. Before further explaining the details of this embodiment, the background of the inventor's creation of this embodiment will be briefly described.

[0151] As described above, in the indirect ranging module 1, the charge generated in the photodiode PD by the reflected light from the object 800 is distributed to charge accumulation units MEM1 and MEM2 via two distribution transistors VG1 and VG2. Furthermore, in the ranging module 1, the charge distributed to the charge accumulation units MEM1 and MEM2 is converted into a signal, and the phase difference φ is calculated based on the difference or ratio between the converted signals, thus obtaining the distance to the object 800.

[0152] However, for such a ranging module 1, in order to ensure high ranging accuracy, it is preferable that the distribution transistors VG1 and VG2 are formed in a more ideal state in all light-receiving elements 10. In other words, it is preferable that the charge distribution performance is equal among all light-receiving elements 10. Therefore, even in mass production, the distribution transistors VG1 and VG2 need to be uniformly formed in all light-receiving elements 10, even if manufacturing deviations (e.g., layout offsets, etc.) occur.

[0153] For example, although a planar configuration example of the light-receiving element 10 will be described in detail later, the gate electrodes of the distribution transistors VG1 and VG2 are arranged adjacent to the photodiode PD. When the gate electrodes are arranged at the same (approximately the same) distance from the photodiode PD, it can be said that the charge distribution performance is approximately equal between the distribution transistors VG1 and VG2. However, when the gate electrodes are not arranged at the same (approximately the same) distance from the photodiode PD due to manufacturing deviations, the charge distribution performance differs between the distribution transistors VG1 and VG2. Furthermore, when the performance difference between the distribution transistors VG1 and VG2 differs between the light-receiving elements 10 due to manufacturing deviations, the charge collected in the charge accumulation units MEM1 and MEM2 is non-uniform in the light-receiving element 10, thus there is a possibility of increased ranging error between the ranging modules 1.

[0154] Therefore, in view of the above, the inventors have created the present disclosure embodiment related to the planar configuration of the light-receiving element 10, which is less susceptible to manufacturing deviations and ensures high ranging accuracy. Specifically, in the embodiment of the present disclosure, the planar configuration of the light-receiving element 10 indicates that the gate electrodes of the distribution transistors VG1 and VG2 are disposed at positions that are linearly symmetrical to each other with respect to the center line extending through the center of the photodiode PD. In the embodiment of the present disclosure, with the above-described planar configuration, even if manufacturing deviations occur, the gate electrodes disposed at the same (approximately the same) distance from the photodiode PD ensure that the charge distribution performance is approximately equal between the distribution transistors VG1 and VG2. Therefore, even if manufacturing deviations occur, it is easy to uniformly form the distribution transistors VG1 and VG2 in all light-receiving elements 10, and the situation where there are differences in the performance of the distribution transistors VG1 and VG2 among the various light-receiving elements 10 can be avoided. Therefore, in the embodiment of the present disclosure, the charge collected in the charge accumulation units MEM1 and MEM2 becomes uniform in the light-receiving element 10. Therefore, the ranging module 1 can ensure high ranging accuracy. The details of the present invention's embodiments, created by the inventors, will be described below in sequence.

[0155] <<6. First Implementation Plan>>

[0156] <6.1 Plane Composition>

[0157] First, refer to Figure 5 This section describes a planar configuration example of each light-receiving element 10 according to the first embodiment of this disclosure. Figure 5 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to this embodiment, wherein the light-receiving element 10 is viewed from above the surface of the semiconductor substrate 200. Note that... Figure 5 The left and right directions in the middle correspond to Figure 2A The horizontal direction (left and right) in the middle. Figure 5 The up and down directions in the middle correspond to Figure 2A The column direction (vertical direction) in the text.

[0158] like Figure 5 As shown, an N-type semiconductor region 100 is formed within a P-type semiconductor substrate 200 at the center of the light-receiving element 10, and the N-type semiconductor region 100 partially constitutes a photodiode (first photoelectric conversion unit) PD. Furthermore, the gate electrodes (first distribution gate and second distribution gate) 150a and 150b of the distribution transistors VG1 and VG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to a center line (first central axis) 600 extending along the vertical direction (column direction) of the light-receiving element 10 through the center point (center) O of the photodiode PD. The distribution transistors VG1 and VG2 are configured to distribute the charge generated in the photodiode PD to the charge accumulation units MEM1 and MEM2, described later. The gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to overlap with at least a portion of the N-type semiconductor region 100.

[0159] Specifically, the distribution transistor VG1 includes a gate electrode 150a, a gate insulating film (not shown) located between the gate electrode 150a and the semiconductor substrate 200, an N-type semiconductor region 100 serving as the source region, and N-type semiconductor regions 102a and 102b serving as the drain regions. The N-type semiconductor region 100 serving as the source region is shared with the photodiode PD, and the N-type semiconductor region serving as the drain region is shared with the charge accumulation unit MEM1. Furthermore, the distribution transistor VG2 also has a similar configuration to the distribution transistor VG1.

[0160] Furthermore, charge accumulation units MEM1 and MEM2, which transfer the charge generated in the photodiode PD, are configured to be mirror-symmetrical with respect to the center line 600 and sandwich distribution transistors VG1 and VG2 from both sides. In other words, charge accumulation units MEM1 and MEM2 are positioned at a point-symmetrical (approximately point-symmetrical) location with respect to the center point (center) O of the photodiode PD. Specifically, charge accumulation unit MEM1 is constructed, for example, as a metal-oxide-semiconductor (MOS) type capacitor, which includes an electrode 154a, an insulating film (not shown) disposed below the electrode 154a, and an N-type semiconductor region (not shown) disposed below the insulating film. Furthermore, charge accumulation unit MEM2 also has a similar configuration to charge accumulation unit MEM1.

[0161] As described above, in this embodiment, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to be linearly symmetrical with respect to the center point O (specifically, center line 600) of the photodiode PD. Therefore, according to this embodiment, the charge distribution performance is substantially equivalent between the distribution transistors VG1 and VG2. Thus, in this embodiment, even if manufacturing deviations (e.g., layout offsets) occur, the situation where there are differences in performance between the distribution transistors VG1 and VG2 among all the light-receiving elements 10 can be avoided, and further, the ranging module 1 can ensure high ranging accuracy.

[0162] In addition, such as Figure 5 As shown, the gate electrodes 152a and 152b (first and second exit gates) of the discharge transistors OFG1 and OFG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center line (second central axis) 602 extending through the center point O of the photodiode PD and along the left-right direction (row direction) of the light-receiving element 10. Note that the center line 602 is perpendicular to the aforementioned center line 600. Furthermore, the gate electrodes 152a and 152b of the discharge transistors OFG1 and OFG2 are configured to overlap with at least a portion of the N-type semiconductor region 100.

[0163] Specifically, the discharge transistor OFG1 includes a gate electrode 152a, a gate insulating film (not shown) located between the gate electrode 152a and the semiconductor substrate 200, an N-type semiconductor region 100 serving as the source region, and an N-type semiconductor region (not shown) serving as the drain region. The N-type semiconductor region 100 serving as the source region is shared with the photodiode PD. Furthermore, the discharge transistor OFG2 also has a similar configuration to the discharge transistor OFG1.

[0164] Furthermore, the gate electrodes (first transmission gate and second transmission gate) 156a and 156b of the transmission transistors TG1 and TG2 are configured to be mirror-symmetrical with respect to the center line 600 and to clamp the distribution transistors VG1 and VG2 from both sides. In other words, the gate electrodes 156a and 156b of the transmission transistors TG1 and TG2 are located at positions that are point-symmetrical (approximately point-symmetrical) with respect to the center point (center) O of the photodiode PD. Specifically, the gate electrode 156a of the transmission transistor TG1 is positioned in a manner that is point-symmetrical (approximately point-symmetrical) with respect to the gate insulating film (not shown) located between the gate electrode 156a and the semiconductor substrate 200, and the electrode 154a of the charge accumulation unit MEM1. Figure 5 The electrodes are arranged adjacent to each other in the vertical (column) direction, with the gate electrode 156b of the transmission transistor TG2 and the electrode 154b of the charge accumulation unit MEM2 located at... Figure 5 The transistors are arranged adjacent to each other in the vertical (column) direction. Transfer transistors TG1 and TG2 are configured to transfer the charge accumulated in charge accumulation cells MEM1 and MEM2 to the floating diffusion regions FD1 and FD2, described later. Specifically, transfer transistor TG1 includes a gate electrode 156a, an N-type semiconductor region (not shown) serving as the source region, and an N-type semiconductor region (not shown) serving as the drain region. Furthermore, transfer transistor TG2 also has a similar configuration to transfer transistor TG1.

[0165] Furthermore, the reset transistors RST1 and RST2, the amplifying transistors AMP1 and AMP2, and the selecting transistors SEL1 and SEL2 are configured to be mirror-symmetrical with respect to the center line 602 and to clamp the discharge transistors OFG1 and OFG2 from both sides. In other words, the reset transistors RST1 and RST2, the amplifying transistors AMP1 and AMP2, and the selecting transistors SEL1 and SEL2 are positioned in a point-symmetrical (approximately point-symmetrical) manner with respect to the center point (center) O of the photodiode PD. Note that the reset transistor RST1, the amplifying transistor AMP1, and the selecting transistor SEL1 are located at... Figure 5 The transistors are arranged adjacent to each other in the left-right (row) direction, and the reset transistor RST2, amplifier transistor AMP2, and select transistor SEL2 are also located there. Figure 5 They are arranged adjacent to each other in the left and right (row) directions.

[0166] Specifically, reset transistor RST1 includes a gate electrode 158a, a gate insulating film (not shown) located between the gate electrode 158a and the semiconductor substrate 200, an N-type semiconductor region (not shown) serving as the source region, and an N-type semiconductor region serving as the source region. The N-type semiconductor region serving as the source region is shared with the floating diffusion region FD1, and the N-type semiconductor region serving as the drain region is shared with amplifying transistor AMP1. Furthermore, reset transistor RST2 also has a similar configuration to reset transistor RST1. Furthermore, amplifying transistor AMP1 includes a gate electrode 160a, a gate insulating film (not shown) located between the gate electrode 160a and the semiconductor substrate 200, an N-type semiconductor region (not shown) serving as the drain region, and an N-type semiconductor region (not shown) serving as the source region. The N-type semiconductor region serving as the drain region is shared with the drain region of reset transistor RST1. Furthermore, amplifying transistor AMP2 also has a similar configuration to amplifying transistor AMP1. Furthermore, the selection transistor SEL1 includes a gate electrode 162a, a gate insulating film (not shown) located between the gate electrode 162a and the semiconductor substrate 200, an N-type semiconductor region (not shown) serving as the drain region, and an N-type semiconductor region (not shown) serving as the source region. The N-type semiconductor region serving as the drain region is shared with the source region of the amplification transistor AMP1. Furthermore, the selection transistor SEL2 also has a similar configuration to the selection transistor SEL1.

[0167] Note that the planar configuration of the light-receiving element 10 according to this embodiment is not limited to... Figure 5 The example shown may include, but is not specifically limited to, other elements, etc.

[0168] <6.2 Cross-sectional Composition>

[0169] Next, we will refer to Figure 6 An example illustrating the cross-sectional configuration of the light-receiving element 10 according to the first embodiment of this disclosure. Figure 6 It is along Figure 5 The image shows a cross-sectional view of the light-receiving element 10 taken along line A-A'. Specifically, Figure 6 The upper side is the back side of the semiconductor substrate 200. Figure 6 The lower side is the surface side of the semiconductor substrate 200.

[0170] First, such as Figure 6 As shown, the light-receiving element 10 includes a P-type semiconductor substrate 200 made of, for example, a silicon substrate. Specifically, a photodiode PD is formed within the semiconductor substrate 200 by forming N-type semiconductor regions 100a and 100b within the P-type semiconductor substrate 200.

[0171] Next, from Figure 6The description will focus on the upper side (i.e., the back side of the semiconductor substrate 200). An on-chip lens 208 is disposed above the back side of the semiconductor substrate 200. This lens is made of styrene-based resin, acrylic resin, styrene-acrylic copolymer resin, siloxane resin, etc., and reflected light from the object 800 is incident upon it. A planarization film 204, made of, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), etc., is disposed below the on-chip lens 208. Furthermore, an anti-reflective film 202, made of an insulating film, is disposed below the planarization film 204. For example, the anti-reflective film 202 can be formed of hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), silicon oxide, etc., or a stack thereof.

[0172] A light-shielding film 206, used to prevent reflected light from object 800 from incident on adjacent light-receiving elements 10, is disposed above the anti-reflective film 202 and in the boundary region with the adjacent light-receiving element 10. The light-shielding film 206 is made of a light-shielding material, for example, it can be formed using a metal material such as tungsten (W), aluminum (Al), or copper (Cu).

[0173] Furthermore, a pixel isolation portion 210a (deep trench isolation (DTI)) extending from the back side of the semiconductor substrate 200 to the middle of the semiconductor substrate 200 in the thickness direction is provided below the light-shielding film 206. The pixel isolation portion 210a includes, for example, trenches provided in the semiconductor substrate 200 and an insulating film made of silicon oxide or a metal film made of aluminum buried in the trenches. The pixel isolation portion 210a is configured to prevent incident light from entering adjacent light-receiving elements 10. Therefore, charge crosstalk between adjacent light-receiving elements 10 can be prevented.

[0174] Next, for Figure 6 The description will focus on the lower side (i.e., the surface side of the semiconductor substrate 200). Two distribution transistors, VG1 and VG2, are formed to sandwich the N-type semiconductor region 100b. Specifically, distribution transistors VG1 and VG2 each include gate electrodes 150a and 150b, which are made of, for example, polysilicon films and disposed on the surface of the semiconductor substrate 200.

[0175] For example, charge accumulation units MEM1 and MEM2 are disposed within the semiconductor substrate 200 to clamp distribution transistors VG1 and VG2 from the left and right directions. For example, charge accumulation units MEM1 and MEM2 can be MOS capacitors, which include electrodes 154a and 154b made of metal film or polysilicon film, an insulating film (not shown) made of oxide film, and an N-type semiconductor region (in... Figure 6 (In the image, MEM1 and MEM2 are shown).

[0176] Then, the gate electrodes 156a and 156b of the transfer transistors TG1 and TG2 are disposed adjacent to the charge accumulation units MEM1 and MEM2 on the surface of the semiconductor substrate 200. Furthermore, the N-type semiconductor regions shown as floating diffusion regions FD1 and FD2 are formed within the semiconductor substrate 200 closer to the gate electrodes 156a and 156b of the transfer transistors TG1 and TG2.

[0177] Furthermore, a wiring layer 300 is provided on the surface of the semiconductor substrate 200. The wiring layer 300 includes an insulating film 302 and a metal film 304. In addition, an electrode 306 is provided on the surface of the wiring layer 300 opposite to the semiconductor substrate 200.

[0178] Furthermore, a substrate 400 is disposed on the surface of the wiring layer 300 opposite to the semiconductor substrate 200. The substrate 400 also includes an insulating film 402 and a metal film 404, and an electrode 406 is disposed on the surface closer to the wiring layer 300. In this embodiment, for example, the electrodes 306 of the wiring layer 300 and the electrode 406 of the substrate 400 are formed of copper (Cu) or the like, and the wiring layer 300 and the substrate 400 are bonded by contact with each other.

[0179] Note that the cross-sectional configuration of the light-receiving element 10 according to this embodiment is not limited to... Figure 6 The example shown may include, but is not specifically limited to, other elements, etc.

[0180] As described above, in this embodiment, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to be linearly symmetrical with respect to the center point O (specifically, center line 600) of the photodiode PD. Therefore, according to this embodiment, the charge distribution performance is substantially equivalent between the distribution transistors VG1 and VG2. Thus, even in the event of manufacturing deviations (e.g., layout misalignment), this embodiment avoids situations where there are differences in performance between the distribution transistors VG1 and VG2 among all the light-receiving elements 10, and further, the ranging module 1 can ensure high ranging accuracy.

[0181] <6.3 Variations>

[0182] Note that the light-receiving element 10 according to the first embodiment of this disclosure can be modified in various ways. Similarly, in these modifications, as in the embodiment described above, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center line passing through the center point O of the photodiode PD. Modifications of this embodiment will be described sequentially below.

[0183] (First variation)

[0184] First, refer to Figure 7 Explain the first variation. Figure 7 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a first modification of this embodiment. Also in the first modification, the gate electrodes 150a and 150b of the distributing transistors VG1 and VG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center line 600. Furthermore, in the first modification, as... Figure 7 As shown, a floating diffusion region FD is provided. In other words, a floating diffusion region FD is shared between the transmission transistors TG1 and TG2. According to a first variation with this configuration, a floating diffusion region FD can be shared between the two transmission transistors TG1 and TG2, thereby further miniaturizing the size of the light-receiving element 10.

[0185] (Second variation)

[0186] Next, refer to Figure 8 and Figure 9 Explain the second variation. Figure 8 This is an equivalent circuit diagram of the light-receiving element 10 according to the second modification of this embodiment. Figure 9 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a second modification of this embodiment. Similarly, in the second modification, as... Figure 9 As shown, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center line 600. Furthermore, in the second variation, as... Figure 8 As shown, charge accumulation units MEM1 and MEM2 and transfer transistors TG1 and TG2 are not provided. In other words, in the second variation, the charge generated in the photodiode PD is directly distributed to the floating diffusion regions FD1 and FD2 by the distribution transistors VG1 and VG2. Therefore, according to this variation, as described above, the charge accumulation units MEM1 and MEM2 and the transfer transistors TG1 and TG2 are not provided, and thus the size of the light-receiving element 10 can be made smaller.

[0187] (Third and fourth variations)

[0188] Next, refer to Figures 10-12 Explain the third and fourth variations. Figure 10 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the third modification of this embodiment. Figure 11 It is along Figure 10 The cross-sectional view of the light-receiving element 10 taken by line A-A' in the figure. Figure 12 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a fourth modification of this embodiment. Similarly, in the third and fourth modifications, as... Figure 10 and Figure 12As shown, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center line 600.

[0189] Furthermore, in the third variation, such as Figure 10 As shown by the dashed lines, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 have a pair of buried gate portions in the semiconductor substrate 200. Specifically, as... Figure 11 As shown, each of the gate electrodes 150a and 150b has two vertically embedded gate portions 170a and 170b in the semiconductor substrate 200. According to a third variation, this configuration allows the semiconductor region surrounding the pair of embedded gate portions 170a and 170b to be effectively modulated by applying a voltage to the pair of embedded gate portions 170a and 170b. Therefore, according to the third variation, this modulation allows the charge generated in the photodiode PD deep within the semiconductor substrate 200 to be transferred to the accumulation cells MEM1 and MEM2 at a higher speed.

[0190] Furthermore, in the fourth variation, such as Figure 12 As shown by the dashed lines, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 have a gate portion buried in one of the semiconductor substrates 200. Also in the fourth variation, by applying a voltage to the buried gate portions 170a and 170b, the semiconductor region surrounding the buried gate portions 170a and 170b can be effectively modulated, allowing the charge generated in the photodiode PD deep within the semiconductor substrate 200 to be transferred to the accumulation cells MEM1 and MEM2 at a higher speed. Furthermore, in the fourth variation, since a gate portion is included in one of the gate electrodes 150a and 150b, it is easier to miniaturize the gate electrodes 150a and 150b.

[0191] Furthermore, in the third and fourth variations, such as Figure 10 and Figure 12 As shown by the dashed lines, the gate electrodes 152a and 152b of the discharge transistors OFG1 and OFG2 can also have a pair or a single buried gate portion. According to the third and fourth modifications, this configuration allows for effective modulation of the semiconductor region surrounding the buried gate portion, enabling the charge generated in the photodiode PD deep within the semiconductor substrate 200 to be discharged at a higher speed.

[0192] (Fifth variation)

[0193] Next, refer to Figure 13 Explain the fifth variation. Figure 13This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to a fifth modification of this embodiment. Similarly, in the fifth modification, as... Figure 13 As shown, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center line 600. In other words, the center line 602 is formed by connecting a line (first line segment) that connects the center point (center) O1a of the gate electrode (first distribution gate) 150a of the distribution transistor VG1 to the center point (center) O of the photodiode (first photoelectric conversion unit) PD, and a line (second line segment) that connects the center point (center) O1b of the gate electrode (second distribution gate) 150b of the distribution transistor VG2 to the center point O of the photodiode PD, and the center line 602 is perpendicular to the center line (first central axis) 600.

[0194] Furthermore, in the fifth variation, such as Figure 13 As shown, a discharge transistor OFG is provided. Specifically, in the fifth variation, as... Figure 13 As shown, the light-receiving element 10 includes a gate electrode (third discharge gate) 152b of a discharge transistor OFG that discharges the charge generated in the photodiode PD. Furthermore, the center point O2 of the gate electrode 152b is located on the center line (first central axis) 600. According to a fifth variation having this configuration, the size of the light-receiving element 10 can be further miniaturized by using a single discharge transistor OFG.

[0195] (Sixth, seventh, and eighth variations)

[0196] Furthermore, the fifth variation described above can be further modified as follows. (Refer to...) Figures 14-17 Explain the sixth, seventh, and eighth variations. Figure 14 This is the equivalent circuit diagram of the light-receiving element 10 according to the sixth modification of this embodiment. Figure 15 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the sixth modification of this embodiment. Furthermore, Figure 16 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the seventh modification of this embodiment. Figure 17 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the eighth variation of this embodiment.

[0197] In the light-receiving element 10 of the sixth modification, such as Figure 14 As shown, a floating diffusion region FD, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL are provided. This configuration allows the light-receiving element 10 of the sixth modification example to, for example, employ... Figure 15 The planar structure shown.

[0198] Specifically, in the sixth variation, such as Figure 15 As shown, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center line 600. More specifically, in the sixth variation, the center line (first segment) 604a (extended in the illustration for clarity) connecting the center point (center) O1a of the gate electrode (first distribution gate) 150a of the distribution transistor VG1 and the center point (center) O of the photodiode (first photoelectric conversion unit) PD forms an acute angle with the center line (first central axis) 600. Furthermore, the center line (second segment) 604b (extended in the illustration for clarity) connecting the center point (center) O1b of the gate electrode (second distribution gate) 150b of the distribution transistor VG2 and the center point O of the photodiode PD forms an acute angle with the center line (first central axis) 600. Note that in the sixth variation, the size of the acute angle is not limited; for example, it can be 45 degrees.

[0199] Furthermore, in the sixth variation, such as Figure 15 As shown, charge accumulation units (first and second charge accumulation units) MEM1 and MEM2 and transmission transistors TG1 and TG2 are positioned at locations that are linearly symmetrical (approximately linearly symmetrical) to each other with respect to the center line (first central axis) 600.

[0200] According to the sixth modification, the closer arrangement of the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 enables high-speed distribution of charge to the charge accumulation cells MEM1 and MEM2, and the charge distribution performance becomes more uniform between the distribution transistors VG1 and VG2. As a result, according to the sixth modification, even if manufacturing deviations occur, the situation where there are differences in performance between the distribution transistors VG1 and VG2 among all the light-receiving elements 10 can be avoided, and further, the ranging module 1 can ensure high ranging accuracy.

[0201] Furthermore, in the seventh variation, such as Figure 16 As shown, the gate electrode 152 of the discharge transistor OFG is configured to be sandwiched between the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2. In the seventh variation, the closer arrangement of the distribution transistors VG1 and VG2 and the discharge transistor OFG improves the rate of transfer of unnecessary charge when switching from the charge accumulation cell MEM2 to the power supply potential VDD (discharge) when the destination of the charge generated in the photodiode PD switches from the charge accumulation cell MEM1 to the power supply potential VDD (discharge).

[0202] Specifically, in the eighth variation, such as Figure 17As shown, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center line 600. More specifically, in the eighth variation, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to be linearly symmetrical with respect to the center line (first central axis) 600 passing through the center point (center) O of the photodiode (first photoelectric conversion unit) PD. Furthermore, in the eighth variation, as... Figure 17 As shown, the charge accumulation units (first and second charge accumulation units) MEM1 and MEM2, as well as the transfer transistors TG1 and TG2, are also positioned at locations that are linearly symmetrical (approximately linearly symmetrical) to each other with respect to the center line (first central axis) 600.

[0203] According to the eighth modification, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are configured to be approximately linearly symmetrical, thus making the charge distribution performance more uniform between the distribution transistors VG1 and VG2. As a result, according to the eighth modification, even if manufacturing deviations occur, the situation where there are differences in performance between the distribution transistors VG1 and VG2 among all the light-receiving elements 10 can be avoided, and further, the ranging module 1 can ensure high ranging accuracy. Furthermore, in the eighth modification, as... Figure 17 As shown, the gate electrode 152 of the discharge transistor OFG is configured to be sandwiched between the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2. In the eighth variation, the closer arrangement of the distribution transistors VG1 and VG2 and the discharge transistor OFG improves the rate of transfer of unnecessary charge when switching from the charge accumulation cell MEM2 to the power supply potential VDD (discharge) when the destination of the charge generated in the photodiode PD switches from the charge accumulation cell MEM1 to the power supply potential VDD (discharge).

[0204] (Ninth and tenth variations)

[0205] Next, refer to Figure 18 and Figure 19 Explain the ninth and tenth variations. Figure 18 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the ninth modification of this embodiment. Figure 19This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the tenth variation of this embodiment. Also in this variation, the gate electrodes 150a and 150b of the distributing transistors VG1 and VG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center line passing through the center point O of the photodiode PD. However, in the ninth and tenth variations, this center line does not extend through the center line 600 of the light-receiving element 10 along the vertical direction (column direction) as described above, but rather extends through the center line (first central axis) 612 of the photodiode (first photoelectric conversion unit) PD at a predetermined angle to the column direction.

[0206] Specifically, in the ninth variation, such as Figure 18 As shown, the gate electrodes (first and second allocation gates) 150a and 150b of the allocation transistors VG1 and VG2 are located at positions that are linearly symmetrical (approximately linearly symmetrical) with respect to the center line (first central axis) 612. As described above, the center line 612 is along a line relative to... Figure 18 The vertical direction (column direction) of the light-receiving element 10 extends through the center point (center) O of the photodiode (first photoelectric conversion unit) PD at a predetermined angle. Note that in the ninth variation, the predetermined angle is not particularly limited, and can be, for example, 45 degrees.

[0207] Furthermore, in the seventh variation, such as Figure 18 As shown, the gate electrodes 152a and 152b of the discharge transistors OFG1 and OFG2 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center line 614 that passes through the center point O of the photodiode PD and is perpendicular to the center line 612.

[0208] Furthermore, in the ninth variation, such as Figure 18 As shown, the charge accumulation units MEM1 and MEM2, and the transfer transistors TG1 and TG2 are arranged to be mirror-symmetrical with respect to the center line 612 and to sandwich the distribution transistors VG1 and VG2 from both sides. In other words, the charge accumulation units MEM1 and MEM2, and the transfer transistors TG1 and TG2 are arranged at positions that are point-symmetrical (approximately point-symmetrical) with respect to the center point (center) O of the photodiode PD.

[0209] According to this modified example, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are arranged at an angle relative to the column direction or the row direction. Therefore, the layout freedom of the light-receiving element 10 on the semiconductor substrate 200 can be increased.

[0210] Furthermore, in the case where the floating diffusion region FD, reset transistor RST, amplification transistor AMP, and selection transistor SEL are shared, the following can be used: Figure 19 The tenth modified example shows a planar configuration of the light-receiving element. According to the tenth modified example, since the floating diffusion region FD, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are shared, it is easier to miniaturize the size of the light-receiving element 10.

[0211] (Examples 11 to 14)

[0212] In the above embodiments and their modifications, each component of the light-receiving element 10 is disposed on a semiconductor substrate 200. However, in this embodiment, the components are not limited to the configuration described above. Therefore, examples of the eleventh to fourteenth modifications in which each component of the light-receiving element 10 is disposed on two stacked substrates will be described. According to the eleventh to fourteenth modifications, due to the stacking of the two substrates, it is easier to miniaturize the size of the light-receiving element 10.

[0213] The following will refer to Figures 20-23 Explain the variations from eleventh to fourteenth. Figure 20 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the eleventh modification of this embodiment. Figure 21 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the twelfth modification of this embodiment. Furthermore, Figure 22 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the thirteenth modification of this embodiment. Figure 23 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the fourteenth variation of this embodiment.

[0214] First, in the eleventh variation, such as Figure 20 As shown, photodiodes PD, distribution transistors VG1 and VG2, discharge transistors OFG1 and OFG2, charge accumulation units MEM1 and MEM2, transfer transistors TG1 and TG2, and floating diffusion regions FD1 and FD2 are disposed on semiconductor substrate 200. Furthermore, amplification transistors AMP1 and AMP2, selection transistors SEL1 and SEL2, and reset transistors RST1 and RST2 are disposed on semiconductor substrate (other semiconductor substrate) 200b. Note that semiconductor substrate 200 and semiconductor substrate 200b are, for example, stacked on top of each other, and copper (Cu) electrodes disposed on semiconductor substrate 200 and semiconductor substrate 200b are bonded, and semiconductor substrate 200 and semiconductor substrate 200b are configured to be electrically connected to each other.

[0215] Next, in the twelfth variation, as... Figure 21As shown, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are in Figure 21 It is arranged in the vertical direction (column direction). According to the twelfth variation, when the pixel array unit 12 of the light receiving unit 30 of the ranging module 1 has a horizontal aspect ratio such as 4:3 or 16:9, the degradation of ranging accuracy caused by oblique light incident obliquely on the pixel array unit 12 can be mitigated.

[0216] Next, in the thirteenth variation, such as Figure 22 As shown, the floating diffusion region FD, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are shared. According to the thirteenth variation, due to the shared configuration of the floating diffusion region FD, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL, it is easier to miniaturize the size of the light-receiving element 10.

[0217] Next, in the fourteenth variation, as... Figure 23 As shown, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are in Figure 23 It is arranged in the vertical direction (column direction). According to the fourteenth variation, when the pixel array unit 12 of the light receiving unit 30 of the ranging module 1 has a horizontal aspect ratio such as 4:3 or 16:9, the degradation of ranging accuracy caused by oblique light incident obliquely on the pixel array unit 12 can be mitigated.

[0218] (Example 15)

[0219] Furthermore, in the twelfth to fourteenth modifications described above, the amplifying transistor AMP, the selecting transistor SEL, and the reset transistor RST are disposed on each semiconductor substrate 200b; however, this embodiment is not limited to this form. Therefore, as the fifteenth modification, an example in which the signal line (output wiring) VSL is disposed on the semiconductor substrate 200b is described. According to the fifteenth modification, the signal line VSL is disposed on the semiconductor substrate 200b instead of on the semiconductor substrate 200, thereby increasing the design freedom of the circuit for receiving the signal transmitted by the signal line VSL.

[0220] Below, refer to Figure 24 Explain the fifteenth variation. Figure 24 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the fifteenth modification of this embodiment. In the fifteenth modification, as... Figure 24As shown, photodiodes PD, distribution transistors VG1 and VG2, discharge transistors OFG1 and OFG2, charge accumulation units MEM1 and MEM2, transfer transistors TG1 and TG2, floating diffusion regions FD1 and FD2, amplification transistors AMP1 and AMP2, selection transistors SEL1 and SEL2, and reset transistors RST1 and RST2 are disposed on semiconductor substrate 200. Furthermore, signal lines VSL1 and VSL2 are disposed on semiconductor substrate 200b. According to a fifteenth variation having this configuration, signal lines VSL1 and VSL2 are disposed on semiconductor substrate 200b instead of semiconductor substrate 200, thus increasing the design freedom of the circuit for receiving signals transmitted by signal lines VSL1 and VSL2.

[0221] (Examples 16 and 17)

[0222] In the above embodiments and their variations, the light-receiving element 10 includes two allocation transistors VG1 and VG2, but this embodiment is not limited to two allocation transistors VG1 and VG2. For example, the light-receiving element 10 may include four allocation transistors VG1, VG2, VG3, and VG4. The following will refer to... Figures 25-27 Explain the sixteenth and seventeenth variations with this configuration. Figure 25 This is the equivalent circuit diagram of the light-receiving element 10 according to the sixteenth variation of this embodiment. Figure 26 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the sixteenth variation of this embodiment. Figure 27 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the seventeenth modification of this embodiment. Note that in Figure 26 and Figure 27 For ease of understanding, only the photodiode PD, distribution transistors VG1, VG2, VG3 and VG4, and discharge transistors OFG1 and OFG2 (or OFG) are shown.

[0223] like Figure 25 As shown, the light-receiving element 10 of the sixteenth modification includes four groups of combinations of distribution transistors VG, charge accumulation units MEM, transfer transistors TG, and floating diffusion regions FD. Furthermore, the light-receiving element 10 of the sixteenth modification also includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. According to the sixteenth modification, the arrangement of the four distribution transistors VG1, VG2, VG3, and VG4 can expand the ranging range.

[0224] The light-receiving element 10 of the sixteenth modified example having this configuration can be adopted as follows: Figure 26The planar configuration is shown. Similarly, in the sixteenth variation, the gate electrodes 150a, 150b, 150c, and 150d of the distribution transistors VG1, VG2, VG3, and VG4 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center point O of the photodiode PD and extending along the vertical direction (column direction) through the center line 600 of the light-receiving element 10. More specifically, in the sixteenth variation, as... Figure 26 As shown, the gate electrodes 150a and 150c of distribution transistors VG2 and VG4 face each other across the center point O of the photodiode PD, and the gate electrodes 150b and 150d of distribution transistors VG2 and VG4 face each other across the center point O of the photodiode PD. Similarly, in the sixteenth variation, since the gate electrodes 150a, 150b, 150c, and 150d of distribution transistors VG1, VG2, VG3, and VG4 are configured to be linearly symmetrical with respect to the center line 600, the charge distribution performance becomes approximately equal among the distribution transistors VG1, VG2, VG3, and VG4.

[0225] Furthermore, when using a single discharge transistor OFG, the following can be employed: Figure 27 The seventeenth modified example shows a planar configuration of the light-receiving element 10. According to the seventeenth modified example, the size of the light-receiving element 10 can be further miniaturized by using an exhaust transistor OFG.

[0226] (Example 18)

[0227] Furthermore, in this embodiment, the light-receiving element 10 may also include eight distribution transistors VG1 to VG8. Referring below... Figure 28 and Figure 29 This describes the eighteenth variation with this configuration. Figure 28 This is the equivalent circuit diagram of the light-receiving element 10 according to the eighteenth variation of this embodiment. Figure 29 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the eighteenth modification of this embodiment. According to this modification, providing eight distribution transistors VG1 to VG8 can expand the ranging range.

[0228] like Figure 28 As shown, the light-receiving element 10 of the eighteenth modification includes eight groups of combinations of a distribution transistor VG, a charge accumulation unit MEM, a transfer transistor TG, and a floating diffusion region FD. Furthermore, the light-receiving element 10 of the eighteenth modification also includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

[0229] The light-receiving element 10 of the eighteenth modified example with this configuration can be adopted as follows: Figure 29The planar configuration is shown. Similarly, in the eighteenth variation, the gate electrodes 150 of the distribution transistors VG1 to VG8 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center point O of the photodiode PD and extending along the vertical direction (column direction) through the center line 600 of the light-receiving element 10. Furthermore, the gate electrodes 150 of the distribution transistors VG1 to VG8 are configured to be linearly symmetrical (approximately linearly symmetrical) with respect to the center point O of the photodiode PD and extending along the horizontal direction (row direction) through the center line 602 of the light-receiving element 10.

[0230] According to the eighteenth modification, the light-receiving element 10 preferably operates as follows. Note that in the following description, the pixel array unit 12 of the light-receiving unit 30 of the ranging module 1 is divided into four regions, and each region is referred to as the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant according to its position.

[0231] Specifically, as described above, the pixel array unit 12 of the light-receiving unit 30 of the ranging module 1 includes a plurality of light-receiving elements 10 arranged in a matrix-like two-dimensional configuration in the row and column directions. When light enters the central region of the pixel array unit 12 with this configuration, the angle of incidence of the light is approximately 0 degrees, and the charge generated by the light in the photodiode PD can be easily distributed to the charge accumulation units MEM1 and MEM2 by the distribution transistors VG1 and VG2 in a substantially similar state. However, when light enters a region outside the central region of the pixel array unit 12 with this configuration, the light is incident at an angle. Therefore, it is difficult to distribute the charge generated by the light in the photodiode PD to the charge accumulation units MEM1 and MEM2 by the distribution transistors VG1 and VG2 in a substantially similar state. Therefore, it is difficult for the ranging module 1 to ensure high ranging accuracy.

[0232] Therefore, for example, in the eighteenth modification, distribution transistors VG1, VG8, and VG6 are used in the first quadrant of the pixel array unit 12. This allows the charge generated in the photodiode PD to be distributed in a substantially similar manner, thereby mitigating the degradation of ranging accuracy caused by the obliquely incident light described above. Furthermore, in the eighteenth modification, as described above, distribution transistors VG6, VG4, and VG2 are used in the second quadrant of the pixel array unit 12. This also allows the charge generated in the photodiode PD to be distributed in a substantially similar manner, thereby mitigating the degradation of ranging accuracy caused by the obliquely incident light described above.

[0233] Note that in the eighteenth modification, when the obliquely incident light has a slight effect, the distribution transistors VG1 and VG2 can be used to distribute the charge generated in the photodiode PD, and the distribution transistor VG5 can be used to discharge the charge. In the eighteenth modification, a large number of distribution transistors VG are used. Therefore, it is preferable to use distribution transistors VG located in appropriate positions for each region of the pixel array unit 12.

[0234] (Examples 19 to 22)

[0235] Furthermore, in this embodiment, the pixel array unit 12 of the light-receiving unit 30 of the ranging module 1 may include not only multiple light-receiving elements 10, but also multiple imaging elements. In this way, the ranging module 1 is configured not only to measure distance, but also to acquire an image (color information) of the object 800. The following will refer to... Figures 30-33 Explain the nineteenth to twenty-second variations that have this configuration. Figure 30 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the nineteenth variation of this embodiment. Figure 31 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twentieth variation of this embodiment. Furthermore, Figure 32 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-first modification of this embodiment. Figure 33 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-second variation of this embodiment.

[0236] First, in the pixel array unit 12 of the nineteenth variation, as Figure 30 As shown, not only are multiple light-receiving elements 10 disposed on the semiconductor substrate 200, but also multiple imaging elements 500 are disposed thereon. The imaging element 500 mainly includes a photodiode (second photoelectric conversion unit) (not shown) that converts light into charge, a floating diffusion region (second floating diffusion region) (not shown) that transfers charge from the photodiode to it, and a gate (third transfer gate) (not shown) of a transfer transistor that transfers charge from the photodiode to the floating diffusion region. Furthermore, as... Figure 30 As shown, the plurality of imaging elements 500 includes an imaging element (second imaging element) 500b for detecting blue light, an imaging element (third imaging element) 500g for detecting green light, and an imaging element (first imaging element) 500r for detecting red light, and these imaging elements 500b, 500g, and 500r are configured, for example, in a Bayer array. Figure 30In this embodiment, the light-receiving element 10a, which operates with a phase delay of 0° and 180° relative to the illumination light, is denoted as I(0° / 180°), and the light-receiving element 10b, which operates with a phase delay of 90° and 270° relative to the illumination light, is denoted as Q(90° / 270°). According to the nineteenth modification, the imaging element 500 that acquires RGB signals for color information and the light-receiving element 10 that performs ranging are arranged adjacent to each other on the same plane, so that imaging can be performed in addition to ranging.

[0237] Furthermore, in the twentieth variation, such as Figure 31 As shown, for the imaging elements 500b, 500g, and 500r configured in a 2×2 configuration, four light-receiving elements 10a (I(0° / 180°)) are arranged in a 2×2 configuration, and four light-receiving elements 10b (Q(90° / 270°)) are arranged in a 2×2 configuration. According to the twentieth variation, this configuration simplifies the layout and allows for easy fabrication of the pixel array unit 12.

[0238] Furthermore, in the twenty-first variation, such as Figure 32 As shown, the plurality of imaging elements 500 also includes an imaging element (fourth imaging element) 500i for detecting near-infrared light (IR). Note that in this variation, imaging elements 500b, 500g, and 500r are not configured in the Bayer array described above, but instead one of the imaging elements 500g in the Bayer array is replaced by imaging element 500i. According to the twenty-first variation, this configuration can acquire near-infrared signals in addition to the RGB signals of color information, thus enabling the acquisition of images of the object 800 even in dark environments. Note that in this variation, the wavelength sensitivity of imaging element 500i and light-receiving elements 10a and 10b may be the same or different.

[0239] Furthermore, in the twenty-second variation, such as Figure 33 As shown, multiple light-receiving elements 10a and 10b and multiple imaging elements 500b, 500g and 500r are configured in a column. In the twenty-second variation, this configuration reduces spatial resolution but simplifies the layout. Therefore, wiring design is easy, and the pixel array unit 12 can be easily manufactured.

[0240] (Examples 23 to 28)

[0241] Furthermore, in this embodiment, the imaging element 500 can be disposed on a different semiconductor substrate than the semiconductor substrate on which the light-receiving element 10 is disposed; that is, the pixel array unit 12 can have a stacked structure. This stacked structure allows the pixel array unit 12 to be compact in size. Reference will be made below. Figures 34-39 Explain the twenty-third to twenty-eighth variations with this configuration. Figure 34This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-third modification of this embodiment. Figure 35 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-fourth modification of this embodiment. Furthermore, Figure 36 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-fifth modification of this embodiment. Figure 37 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-sixth modification of this embodiment. Furthermore, Figure 38 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-seventh modification of this embodiment. Figure 39 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-eighth variation of this embodiment.

[0242] First, in the twenty-third variation, such as Figure 34 As shown, the pixel array unit 12 has multiple light-receiving elements 10a and 10b disposed on the semiconductor substrate 200, and multiple imaging elements 500b, 500g, and 500r disposed on the semiconductor substrate 200b stacked on the semiconductor substrate 200. According to the twenty-third modification, stacking two semiconductor substrates 200 and 200b in this manner allows for a more compact size of the pixel array unit 12. Note that... Figure 34 The arrows in the diagram indicate the direction of light (hν) incident, and in this modified example, the light is incident from one direction, thus simplifying the configuration of the focusing lens, etc., that converges the light to the pixel array unit 12. Furthermore, in the twenty-third modified example, as... Figure 34 As shown, light-receiving elements 10a and 10b are configured in a 2×2 configuration in the Bayer array to simplify the layout, thus making it easy to manufacture the pixel array unit 12.

[0243] Next, in the pixel array unit 12 of the twenty-fourth variation, as... Figure 35 As indicated by the arrows, light is incident from both sides of the stacked semiconductor substrates 200 and 200b. In the twenty-fourth variation, the incident direction of light towards the imaging elements 500b, 500g, and 500r is different from the incident direction of light towards the light-receiving elements 10a and 10b. Therefore, the imaging elements 500b, 500g, and 500r, together with the light-receiving elements 10a and 10b, can acquire signals with high sensitivity.

[0244] Next, in the pixel array unit 12 of the twenty-fifth variation, as... Figure 36As shown, a plurality of light-receiving elements 10a and a plurality of light-receiving elements 10b are arranged on the semiconductor substrate 200 in an inclined direction. Furthermore, the inclined columns of the plurality of light-receiving elements 10a and the inclined columns of the plurality of light-receiving elements 10b are arranged alternately. According to the twenty-fifth modification, this arrangement can improve the ranging resolution of the light-receiving elements 10a and 10b.

[0245] Next, in the pixel array unit 12 of the twenty-sixth and twenty-seventh variations, as... Figure 37 and Figure 38 As shown, in addition to multiple light-receiving elements 10a and 10b, multiple imaging elements 500i are disposed on the semiconductor substrate 200. Specifically, in the twenty-sixth modification, as... Figure 37 As shown, the spectral wavelength of each imaging element 500i is longer than that of visible light. Therefore, the imaging element 500i is formed to be larger in size (area) than the other imaging elements 500b, 500g, and 500r, as well as the light-receiving elements 10a and 10b, thereby improving sensitivity. Furthermore, in the twenty-seventh variation, as... Figure 38 As shown, the imaging element 500i, light-receiving element 10a, and light-receiving element 10b are arranged in one direction to simplify the layout, thus making it easy to manufacture the pixel array unit 12. In the twenty-sixth and twenty-seventh modifications, as described above, according to the twenty-sixth and twenty-seventh modifications, near-infrared signals other than RGB signals containing color information can be acquired while improving resolution, so that, for example, an image of the object 800 can be acquired even in a dark environment.

[0246] Next, in the pixel array unit 12 of the twenty-eighth variation, as... Figure 39 As shown, the light-receiving elements 10a and 10b and the imaging element 500i are configured in a 2×2 configuration, thus improving the resolution.

[0247] (Examples 29 to 35)

[0248] Furthermore, in this embodiment, the light-receiving elements 10a and 10b can be formed to have a larger size than the imaging elements 500b, 500g, and 500r. This configuration allows for improved ranging accuracy. (Referring below...) Figures 40-46 Examples of variations with this configuration, from the 29th to the 35th, are explained. Figure 40 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the twenty-ninth variation of this embodiment. Figure 41 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirtieth variation of this embodiment. Figure 42 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-first modification of this embodiment. Figure 43This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-second modification of this embodiment. Furthermore, Figure 44 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-third modification of this embodiment. Figure 45 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-fourth modification of this embodiment. Furthermore, Figure 46 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-fifth modification of this embodiment.

[0249] First, in the pixel array unit 12 of the twenty-ninth variation, as Figure 40 As shown, light-receiving elements 10a and 10b have a larger size (area) than imaging elements 500b, 500g, and 500r. Generally, high resolution is required for imaging elements 500b, 500g, and 500r, but the light-receiving elements 10a and 10b do not need to have the same high resolution as imaging elements 500b, 500g, and 500r. Therefore, in the twenty-ninth variation, by providing light-receiving elements 10a and 10b with such a large size, sensitivity can be improved and ranging accuracy can be further improved, despite the lower resolution.

[0250] Furthermore, in the pixel array unit 12 of the thirtieth and thirty-first variations, such as Figure 41 and Figure 42 As shown, light-receiving elements 10a and 10b are arranged in one direction to simplify the layout, thus making it easy to manufacture the pixel array unit 12.

[0251] Furthermore, also in the stacked configuration, the light-receiving elements 10a and 10b can have a larger size (area) than the imaging elements 500b, 500g, and 500r. Similarly, in the stacked configuration of the pixel array unit 12 according to the thirty-second to thirty-fourth variations, such as... Figures 43-45 As shown, the light-receiving elements 10a and 10b have a larger size (area) than the imaging elements 500b, 500g and 500r.

[0252] Furthermore, in the pixel array unit 12 of the thirty-fifth variation, such as Figure 46 As shown, imaging element 500i has a larger size (area) than imaging elements 500b, 500g, and 500r. According to this modified example, sensitivity can be improved by providing imaging element 500i with such a large size.

[0253] (Examples 36 to 40)

[0254] Furthermore, in this embodiment, the pixel array unit 12 can be configured such that the orientation of the plurality of light-receiving elements 10 is optimized at each location. Referring below... Figures 47-52 Explain the thirty-sixth to fortieth variations with this configuration. Figure 47 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the thirty-sixth to fortieth modifications of this embodiment. Figure 48 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-sixth modification of this embodiment. Figure 49 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-seventh variation of this embodiment. Figure 50 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-eighth modification of this embodiment. Figure 51 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the thirty-ninth variation of this embodiment. Figure 52 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the fortieth variation of this embodiment.

[0255] In the thirty-sixth to fortieth variations described below, it is assumed that the planar configuration of each light-receiving element 10 has, for example, as shown in the following examples. Figure 47 The structure shown. Specifically, Figure 47 The planar composition is similar to Figure 5 The diagram shows a planar configuration example of the light-receiving element 10 according to the first embodiment of this disclosure. To facilitate understanding of the orientation of the light-receiving element 10, in... Figure 47 In the image, the letter "F" is displayed on the light-receiving element 10.

[0256] First, in the pixel array unit 12 of the thirty-sixth variation, as Figure 48 As shown, all of the multiple light-receiving elements 10 are configured to face the same direction. According to the thirty-sixth variation, as described above, all the light-receiving elements 10 are configured to face the same direction, thus reducing performance variations of the light-receiving elements 10 during manufacturing.

[0257] Next, in the thirty-seventh variation, such as Figure 49 As shown, the pixel array unit 12 is divided into two regions, as follows: Figure 49 The pixel array unit 12 has an upper and lower half, and further, in the upper and lower half, multiple light-receiving elements 10 face a defined direction in their respective regions. In other words, the multiple light-receiving elements 10 face different directions between the upper and lower half of the pixel array unit 12. According to the thirty-seventh variation, changing the direction of the light-receiving elements 10 between the upper and lower half of the pixel array unit 12 in this way can mitigate the degradation of ranging accuracy caused by oblique light incident obliquely on the pixel array unit 12.

[0258] Next, in the thirty-eighth variation, such as Figure 50As shown, the pixel array unit 12 is divided into two regions, as follows: Figure 50 The right and left halves of the pixel array unit 12 are further divided into two regions, and in the right and left halves, multiple light-receiving elements 10 face different directions. According to the thirty-eighth variation, changing the direction of the light-receiving elements 10 between the right and left halves of the pixel array unit 12 in this way can mitigate the degradation of ranging accuracy caused by oblique light incident obliquely on the pixel array unit 12.

[0259] Next, in the thirty-ninth variation, such as Figure 51 As shown, the pixel array unit 12 is divided into four regions, such as the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant, and further, the plurality of light-receiving elements 10 face different directions between their respective quadrants. According to the thirty-ninth variation, changing the direction of the light-receiving elements 10 between their respective quadrants in this way (i.e., optimizing the direction of the light-receiving elements 10 according to their positions) can mitigate the degradation of ranging accuracy caused by oblique light incident obliquely on the pixel array unit 12.

[0260] Next, in the pixel array unit 12 of the fortieth variation, as... Figure 52 As shown, Figure 52 The central region and its surrounding region are divided into five regions, such as the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant. Furthermore, multiple light-receiving elements 10 face different directions among the five regions. According to the fortieth variation, optimizing the orientation of the light-receiving elements 10 in this way based on their positions can mitigate the degradation of ranging accuracy caused by oblique light incident obliquely on the pixel array unit 12.

[0261] (Example 41)

[0262] Furthermore, in this embodiment, even when multiple allocation transistors VG are provided, the orientation of the multiple light-receiving elements 10 can be optimized for each position in the pixel array unit 12. (See below for reference.) Figure 53 and Figure 54 This describes the forty-first variation with this configuration. Figure 53 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to the forty-first modification of this embodiment. Figure 54 This is an explanatory diagram showing a planar configuration example of the pixel array unit 12 according to the forty-first variation of this embodiment.

[0263] In the forty-first variation described below, it is assumed that the planar configuration of each light-receiving element 10 has, for example, as shown in the example below. Figure 53 The structure shown. Specifically, Figure 53 The planar composition is similar to Figure 29The image shows a planar configuration example of the light-receiving element 10 according to the eighteenth variation of the first embodiment of this disclosure. To facilitate understanding of the orientation of the light-receiving element 10, in... Figure 53 In the image, the letter "F" is displayed on the light-receiving element 10.

[0264] Next, in the forty-first variation, such as Figure 54 As shown, the pixel array unit 12 is divided into four regions, such as the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant, and further, the plurality of light-receiving elements 10 face different directions between their respective quadrants. In the forty-first modification, for example, among the light-receiving elements 10 located at the corners of the pixel array unit 12, it is preferable to use only the allocation transistor VG located near the corners. According to the forty-first modification, changing the orientation of the light-receiving elements 10 for each quadrant and changing the allocation transistor VG to be used in this way can mitigate the degradation of ranging accuracy caused by oblique light incident obliquely on the pixel array unit 12.

[0265] <<7. Second Implementation Plan>>

[0266] Furthermore, in the first embodiment and its variations described above, the thickness of the insulating films (not shown) of the charge accumulation cells MEM1 and MEM2, and the gate insulating films (not shown) of the amplifying transistors AMP1 and AMP2, can be reduced. This configuration allows for an increase in the capacity of the charge accumulation cells MEM1 and MEM2 without increasing their size. Moreover, the reduction in the influence of crystal defects caused by a decrease in crystal defects within the gate insulating film or an increase in the mutual conductivity gm of the transistors, or the reduction in interface states caused by a reduction in heat treatment time or a reduction in heat treatment temperature, allows for a reduction in the random noise of the amplifying transistors AMP1 and AMP2.

[0267] Here, in the third embodiment of this disclosure, reference will be made to Figure 55 , Figure 56A and Figure 56B This describes charge accumulation cells MEM1 and MEM2 with reduced-thickness insulating films, and amplifying transistors AMP1 and AMP2. Note that... Figure 55 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to this embodiment, wherein the light-receiving element 10 is viewed from above the surface of the semiconductor substrate 200. Figure 55 The light-receiving element 10 is similar to Figure 17 The light-receiving element 10 of the eighth variation of the first embodiment shown. Figure 56A It is along Figure 55 A cross-sectional view of the light-receiving element 10 taken by line C-C' in the diagram. Figure 56B It is along Figure 55A cross-sectional view of the light-receiving element 10 taken by line D-D'. Specifically, in Figure 56A and Figure 56B In each of these figures, the upper side is the surface side of the semiconductor substrate 200, and the lower side is the back side of the semiconductor substrate 200. Figure 56A The contact portion on the gate electrode 160 is not shown in the diagram.

[0268] Specifically, in this implementation scheme, for example, such as Figure 56A As shown, the insulating film 720a located below the gate electrode 160 of the amplifying transistor AMP1, which is covered by the sidewall 730, is made of an oxide film (third oxide film), for example, and its thickness is smaller than that of the insulating film 720 located below the gate electrode 158 of the reset transistor RST1 and the gate electrode 162 of the select transistor SEL1, which is made of an oxide film (third oxide film).

[0269] Furthermore, in this embodiment, the charge accumulation unit MEM1 includes an electrode 154a, an insulating film 720a, and an N-type semiconductor region. Specifically, for example, as Figure 56B As shown, the insulating film 720a located below the electrode 154 covered by the sidewall 730 of the charge accumulation unit MEM1 is, for example, composed of an oxide film (first oxide film), and its thickness is smaller than that of the insulating film 720 located below the gate electrode 156 of the transmission transistor TG1, which is composed of an oxide film (second oxide film).

[0270] Note that in this embodiment, the insulating film 720a located below the gate electrode 160 of the amplifying transistor AMP1 and the insulating film 720a located below the electrode 154 of the charge accumulation unit MEM1 can be oxide films made of the same material, or can have approximately the same film thickness.

[0271] More specifically, in this embodiment, the insulating film 720a located below the gate electrode 160 of the amplifying transistor AMP1 and the insulating film 720a located below the electrode 154 of the charge accumulation unit MEM1 are composed of oxide films such as silicon oxide (SiO2) and silicon nitride (SiN). Furthermore, in this embodiment, considering the effect of reduced random noise due to the reduced thickness and the increased power consumption due to the increased leakage current, the film thickness of each of the insulating film 720a located below the gate electrode 160 of the amplifying transistor AMP1 and the insulating film 720a located below the electrode 154 of the charge accumulation unit MEM1 is preferably approximately half the film thickness of the insulating film 720 located below the gate electrodes 156, 158, and 162 of other elements (transfer transistor TG, reset transistor RST, and select transistor SEL), more preferably, for example, 1.0 nm or more and 5.0 nm or less.

[0272] Furthermore, in this embodiment, when viewed from above the semiconductor substrate 200, the insulating film 720a located below the gate electrode 160 of the amplifying transistor AMP1 and the insulating film 720a located below the electrode 154 of the charge accumulation unit MEM1 are preferably wider than the gate electrode 160 and the electrode 154 to the extent that adjacent elements do not interfere with each other.

[0273] Note that this embodiment is not limited to reducing only the thickness of the insulating film 720a of the charge accumulation units MEM1 and MEM2 and the gate insulating film 720a of the amplifying transistors AMP1 and AMP2. In this embodiment, only the thickness of the insulating film 720a of the charge accumulation units MEM1 and MEM2 can be reduced, and the thickness of the insulating film 720 that contacts the gate electrodes 150, 152, 156, 158, 160 and 162 and electrode 154 of each element (charge accumulation unit MEM, transfer transistor TG, distribution transistor VG, discharge transistor OFG, amplifying transistor AMP, reset transistor RST and select transistor SEL) on the light receiving element 10 can also be reduced.

[0274] As described above, according to this embodiment, reducing the thickness of the insulating film 720a of the charge accumulation unit MEM and the gate insulating film 720a of the amplifying transistor AMP allows for an increase in the capacity of the charge accumulation unit MEM without increasing its size, thereby reducing the random noise of the transistor. Therefore, the configuration of this embodiment is applicable to the configuration of the first embodiment with a symmetrical layout. Therefore, the insulating film 720a to be reduced can be formed accurately. Therefore, in addition to the improved ranging accuracy of the ranging module 1 due to the uniform collection of charge in the charge accumulation units MEM1 and MEM2, the capacity of the charge accumulation units MEM1 and MEM2 increases, and the random noise of the transistor decreases. Therefore, the ranging accuracy of the ranging module 1 can be further improved. Note that this embodiment can be implemented in conjunction with the first embodiment described above and its variations.

[0275] <<8. Third Implementation Plan>>

[0276] Incidentally, in the second embodiment described above, the thickness of the insulating film 720a of each charge accumulation unit MEM and the thickness of the gate insulating film 720a of the amplifying transistor AMP are reduced to increase the capacity of each charge accumulation unit MEM and reduce the random noise of the amplifying transistor AMP. However, while the above-mentioned effects can be achieved by further reducing the thickness of each gate insulating film 720a, leakage current increases, thus limiting the reduction of film thickness. Therefore, the inventors have conceived of using a high-dielectric film with a higher relative permittivity, which can increase the capacity of the charge accumulation unit MEM compared to the oxide film described above, even with the same film thickness, instead of the insulating film 720a. Even with a reduced film thickness, using a high-dielectric film as the insulating film 720a can achieve both an increase in the capacity of the charge accumulation unit MEM and a reduction in the random noise of the amplifying transistor AMP, while avoiding an increase in leakage current.

[0277] Here, we will refer to Figure 57 , Figure 58A and Figure 58B This describes charge accumulation units MEM1 and MEM2 having an insulating film including a high-dielectric film, and amplifying transistors AMP1 and AMP2, according to a third embodiment of this disclosure. Note that... Figure 57 This is an explanatory diagram showing a planar configuration example of the light-receiving element 10 according to this embodiment, wherein the light-receiving element 10 is viewed from above the surface of the semiconductor substrate 200. Figure 57 The light-receiving element 10 is similar to the light-receiving element 10 of the first embodiment. Furthermore, Figure 58A It is along Figure 57 A cross-sectional view of the light-receiving element 10 taken by line E-E' in the diagram. Figure 58B It is along Figure 57 A cross-sectional view of the light-receiving element 10 taken by line F-F'. Specifically, in Figure 58A and Figure 58B In each of them, the upper side in the figure is the surface side of the semiconductor substrate 200, and the lower side in the figure is the back side of the semiconductor substrate 200.

[0278] Specifically, in this implementation scheme, for example, such as Figure 58A As shown, the insulating film (third insulating film) 740 located below the gate electrode 160 of the amplifying transistor AMP1, which is covered by the sidewall 730, contains a high dielectric film. Therefore, the relative dielectric constant of the insulating film 740 is higher than the relative dielectric constant of the insulating film (third insulating film) 720 located below the gate electrode 158 of the reset transistor RST1 and the gate electrode 162 of the select transistor SEL1.

[0279] Furthermore, in this embodiment, for example, such as Figure 58BAs shown, the insulating film (first insulating film) 740 located below the electrode 154 covered by the sidewall 730 of the charge accumulation unit MEM1 contains a high dielectric film. The relative dielectric constant of the insulating film 740 is higher than the relative dielectric constant of the insulating film (second insulating film) 720 located below the gate electrode 156 of the transmission transistor TG1.

[0280] Note that in this embodiment, the insulating film 740 located below the gate electrode 160 of the amplifying transistor AMP1 and the insulating film 740 located below the electrode 154 of the charge accumulation unit MEM1 can be formed of the same material.

[0281] More specifically, in this embodiment, the high-dielectric film comprises a material with a higher relative permittivity than that of silicon oxide (SiO2) (3.9), and preferably a material having a relative permittivity of 4 or higher. In this embodiment, for example, the high-dielectric film is a metal oxide film, and may be formed from materials such as Al2O3, HfSiON, Y2O3, Ta2O5, La2O3, TiO2, HfO2, ZrO2, or HfZrO2.

[0282] When a high-dielectric film is used as the insulating film 740, in order to adjust Vth (threshold voltage), metallic materials such as TiN, TaN or NiSi can be used as the materials for forming the gate electrodes 150, 152, 154, 156, 158, 160 and 162.

[0283] Furthermore, in this embodiment, when viewed from above the semiconductor substrate 200, the insulating film 740 located below the gate electrode 160 of the amplifying transistor AMP1 and the insulating film 740 located below the electrode 154 of the charge accumulation unit MEM1 are preferably wider than the gate electrode 160 and the electrode 154 to the extent that adjacent elements do not interfere with each other.

[0284] Note that this embodiment is not limited to forming only the insulating films 740 of charge accumulation units MEM1 and MEM2 and the gate insulating films 740 of amplification transistors AMP1 and AMP2 using a high-dielectric film. Furthermore, the insulating films 740 of only charge accumulation units MEM1 and MEM2 can be formed of a high-dielectric film, and the insulating film 720 that contacts the gate electrodes 150, 152, 156, 158, 160, and 162 and electrode 154 of each element on the light-receiving element 10 (charge accumulation unit MEM, transfer transistor TG, distribution transistor VG, discharge transistor OFG, amplification transistor AMP, reset transistor RST, and selection transistor SEL) can also be formed of a high-dielectric film.

[0285] As described above, according to this embodiment, by using a high-dielectric film to form the insulating film 740 of the charge accumulation unit MEM and the gate insulating film 740 of the amplifying transistor AMP, it is possible to increase the capacity of the charge accumulation unit MEM and reduce the random noise of the amplifying transistor AMP without reducing their film thickness compared to using SiO2. Therefore, the configuration of this embodiment is applicable to the configuration of the first embodiment with a symmetrical layout. Therefore, the insulating film 720 containing the high-dielectric film can be accurately formed. Therefore, in addition to the effect of improved ranging accuracy of the ranging module 1 caused by the uniform collection of charges in the charge accumulation units MEM1 and MEM2, the capacity of the charge accumulation units MEM1 and MEM2 is increased, and the random noise of the transistor is reduced. Therefore, the ranging accuracy of the ranging module 1 can be further improved. Note that this embodiment can be implemented in conjunction with the first embodiment described above and its variations.

[0286] <<9. Summary>>

[0287] As described above, in the embodiments and variations thereof of this disclosure, the planar configuration of the light-receiving element 10 shows that the gate electrodes of the distribution transistors VG1 and VG2 are positioned at locations that are linearly symmetrical to each other relative to the center line extending through the center of the photodiode PD. In the embodiments of this disclosure, by employing the above-described planar configuration, even with manufacturing deviations, the gate electrodes positioned at the same (approximately the same) distance from the photodiode PD ensure that the charge distribution performance is approximately equal between the distribution transistors VG1 and VG2. Therefore, even with manufacturing deviations, it is easy to uniformly form the distribution transistors VG1 and VG2 in all the light-receiving elements 10, and it is possible to avoid situations where there are differences in performance between the distribution transistors VG1 and VG2 in each light-receiving element 10. Therefore, in the embodiments of this disclosure, the charge collected in the charge accumulation units MEM1 and MEM2 becomes uniform in the light-receiving element 10. Therefore, the ranging module 1 can ensure high ranging accuracy.

[0288] Although this disclosure has described embodiments, variations, and applications, it is not limited to the above embodiments, and various modifications, alterations, or combinations are possible. Note that the effects described in this specification are merely illustrative. The effects of this disclosure are not limited to those described herein. This disclosure may have effects beyond those described herein.

[0289] Note that in the embodiments and variations thereof disclosed above, the conductivity type of each of the semiconductor regions may be reversed. For example, the embodiments and variations thereof are applicable to elements that use holes as charges instead of electrons.

[0290] Furthermore, in the embodiments and variations thereof disclosed above, the semiconductor substrate is not necessarily a silicon substrate, but may be other substrates (e.g., silicon-on-insulator (SOI) substrate, SiGe substrate, etc.). Moreover, the semiconductor substrate may have semiconductor structures formed on such various substrates.

[0291] Furthermore, in the embodiments and variations thereof disclosed above, the light-receiving element 10 may be formed together with the light-emitting unit, processing circuit, etc. on a single chip, or the light-receiving element 10 may be disposed in a package, but is not particularly limited thereto.

[0292] In the embodiments and variations thereof disclosed herein, examples of methods for forming the aforementioned layers, films, and components include physical vapor deposition (PVD) and CVD. Examples of PVD methods include vacuum vapor deposition using resistance heating or high-frequency heating, electron beam (EB) vapor deposition, various sputtering methods (magnetron sputtering, radio frequency (RF)-direct current (DC) coupled-mode bias sputtering, electron cyclotron resonance (ECR) sputtering, directed-target sputtering, high-frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal-organic (MO) CVD, and optical CVD. In addition, other methods include electroplating, electroless plating, and spin coating; immersion coating; casting; microcontact printing; drop casting; various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing; hot stamping; spray coating; and various coating methods such as air knife coating, smear coating, rod coating, doctor blade coating, extrusion coating, reverse roller coating, transfer roller coating, gravure coating, kiss coating, cast coating, spray coating, slotted mesh coating, and calendering coating. Furthermore, examples of patterning methods for each layer include chemical etching such as shadow masking, laser transfer, and photolithography; and physical etching using ultraviolet light, lasers, etc. Furthermore, examples of planarization techniques include chemical mechanical polishing (CMP), laser planarization, and reflow. In other words, components according to embodiments and variations thereof can be easily and inexpensively manufactured using existing semiconductor device manufacturing processes.

[0293] <<10. Examples of Electronic Device Structure>>

[0294] Furthermore, the light-receiving element 10 can be applied not only to the aforementioned ranging module 1, but also to various electronic devices such as cameras with ranging functions and smartphones with ranging functions. (Refer to...) Figure 59 Here is an example of the configuration of a smartphone 900, which is an electronic device to which this technology is applicable. Figure 59This is a block diagram illustrating an example of the configuration of a smartphone 900, which is an electronic device to which the ranging module 1 is applicable according to an embodiment of the present disclosure.

[0295] like Figure 59 As shown, the smartphone 900 includes a central processing unit (CPU) 901, a read-only memory (ROM) 902, and a random access memory (RAM) 903. Furthermore, the smartphone 900 includes a storage device 904, a communication module 905, and a sensor module 907. Additionally, the smartphone 900 includes a ranging module 908 suitable for the ranging module 1 described above, and also includes an imaging device 909, a display device 910, a speaker 911, a microphone 912, an input device 913, and a bus 914. Moreover, instead of the CPU 901, or in addition to the CPU 901, the smartphone 900 may include processing circuitry such as a digital signal processor (DSP).

[0296] The CPU 901 functions as a processing unit and control device, controlling all or part of the operations within the smartphone 900 according to various programs recorded in the ROM 902, RAM 903, and storage device 904. The ROM 902 stores programs and calculation parameters used by the CPU 901. The RAM 903 primarily stores programs used during the execution of the CPU 901 or parameters that change appropriately during program execution. The CPU 901, ROM 902, and RAM 903 are interconnected via a bus 914. Furthermore, the storage device 904 is an example data storage device configured as a storage unit in the smartphone 900. The storage device 904 may include, for example, magnetic storage devices such as hard disk drives (HDDs), semiconductor storage devices, and optical storage devices. The storage device 904 stores programs executed by the CPU 901, various data, and various data acquired from external sources.

[0297] Communication module 905 includes a communication interface, such as a communication device for connecting to communication network 906. Communication module 905 can be, for example, a wired or wireless local area network (LAN), a Bluetooth (registered trademark) communication card, or a wireless USB (WUSB) communication card. Furthermore, communication module 905 can be a router for optical communication, a router for asymmetric digital subscriber line (ADSL), or a modem for various communications. Communication module 905, for example, sends / receives signals to / from the Internet or other communication devices using a predetermined protocol such as TCP / IP. Furthermore, communication network 906 connected to communication module 905 is a network connected in a wired or wireless manner, such as the Internet, a home LAN, infrared communication, or satellite communication.

[0298] The sensor module 907 includes, for example, various sensors such as motion sensors (e.g., accelerometers, gyroscopes, geomagnetic sensors, etc.), bio-information sensors (e.g., pulse sensors, blood pressure sensors, fingerprint sensors, etc.) or position sensors (e.g., Global Navigation Satellite System (GNSS) receivers, etc.).

[0299] A ranging module 908 is disposed on the surface of the smartphone 900 and is configured to acquire, for example, the shape or movement of the user's fingertips, palm, face, etc., facing the surface as a ranging result. Such ranging results can be used for user authentication and recognition of user gestures. Furthermore, the ranging module 908 is also configured to acquire, for example, the distance from the smartphone 900 to the object 800 or three-dimensional shape data about the surface of the object 800.

[0300] An imaging device 909 is disposed on the surface of a smartphone 900 and configured to image an object 800 or similar object located around the smartphone 900. Specifically, the imaging device 909 may include an imaging element (not shown) such as a complementary MOS (CMOS) image sensor and a signal processing circuit (not shown) that performs imaging signal processing on the signal obtained by photoelectric conversion of the imaging element. Furthermore, the imaging device 909 may also include an optical system mechanism (not shown) (which includes an imaging lens, an aperture mechanism, a zoom lens, a focusing lens, etc.) and a drive system mechanism (not shown) that controls the operation of the optical system mechanism. The imaging element then collects incident light from the object 800 as an optical image. The signal processing circuit performs photoelectric conversion on the formed optical image pixel by pixel, reads out the signal of each pixel as an imaging signal, and performs image processing to obtain a captured image.

[0301] Display device 910 is disposed on the surface of smartphone 900, and may be a display device such as liquid crystal display (LCD) or organic electroluminescent display (EL). Display device 910 is configured to display operation screen, captured images obtained by imaging device 909, etc.

[0302] The speaker 911 is configured to output to the user voice such as calling voice, voice of accompanying image content displayed by the display device 910.

[0303] The microphone 912 is configured to collect, for example, the user's voice calls, voice commands including those for activating the functions of the smartphone 900, and sounds from the surrounding environment of the smartphone 900.

[0304] Input device 913 is a user-operated device such as a button, touch panel, or mouse. Input device 913 includes an input control circuit that generates input signals based on user input information and outputs the input signals to CPU 901. The user can operate input device 913 to input various data into smartphone 900 or to give instructions for processing operations.

[0305] The above describes an example of the configuration of a smartphone 900. The aforementioned components can use general-purpose parts, or may include hardware specifically designed for the functions of each component. Such a configuration can be appropriately modified according to the current level of technology.

[0306] <<11. Examples of Applications of Endoscopic Surgical Systems>>

[0307] The technology of this invention (the technology) can be applied to various products; for example, the technology of this invention can be applied to endoscopic surgical systems.

[0308] Figure 60 This is a diagram illustrating an example of a schematic configuration of an endoscopic surgical system to which the technology (the present technology) can be applied.

[0309] Figure 60 The illustration shows a surgeon (physician) 11131 performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgical system 11000. As shown, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy delivery device 11112, a support arm assembly 11120 supporting the endoscope 11100, and a trolley 11200 on which various devices for endoscopic surgery are mounted.

[0310] Endoscope 11100 includes a lens tube 11101 in which a region of a predetermined distance from the distal end is inserted into a body cavity of patient 11132, and a camera 11102 connected to the proximal end of the lens tube 11101. In the example shown, an endoscope 11100 configured as a so-called rigid endoscope with a rigid lens tube 11101 is shown, but endoscope 11100 can be configured as a so-called flexible endoscope with a flexible lens tube.

[0311] The opening into which the objective lens is mounted is located at the distal end of the lens tube 11101. A light source device 11203 is connected to the endoscope 11100. Light generated by the light source device 11203 is guided to the distal end of the lens tube via a light guide extending into the lens tube 11101, and emitted via the objective lens toward the object being observed within the body cavity of the patient 11132. Note that the endoscope 11100 can be a direct-viewing endoscope, an oblique-viewing endoscope, or a lateral-viewing endoscope. Furthermore, the light-emitting unit 20 and the light-receiving unit 30 of the ranging module 1 according to this disclosure embodiment can be built into the distal end of the endoscope tube 11101. Installing such a ranging module 1 allows for further improvement of surgical accuracy by referring to distance information from the ranging module 1, in addition to surgery performed under the doctor's visual supervision.

[0312] For example, as shown in the example of the configuration of endoscope 11100 Figure 61 In this configuration, the iToF sensor 15004, which serves as the light-emitting unit 20 and the light-receiving unit 30 of the ranging module 1 according to this embodiment, is disposed in the camera 11102. Specifically, the reflected light (observation light) from the object being observed passes through the lens barrel 11101, is converged by the lens 15001 within the camera 11102, is reflected by the semi-reflective mirror 15002, and is received by the iToF sensor 15004. The observation light is photoelectrically converted by the iToF sensor 15004 to generate an electrical signal corresponding to the observation light, which is stored in the memory 15005 and then transmitted to the ranging signal processing device 11209 described later.

[0313] In addition, such as Figure 61 As shown, the imaging element 15003 is disposed inside the camera 11102. Reflected light from the observed object (observation light) passes through the lens barrel 11101, is converged by the lens 15001, reflected by the semi-reflective mirror 15002, and received by the imaging element 15003. The observation light is photoelectrically converted by the imaging element 15003, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is temporarily stored in the memory 15005 and then transmitted as RAW data to the camera control unit (CCU) 11201.

[0314] The CCU 11201 comprises a central processing unit (CPU), a graphics processing unit (GPU), and other components, and integrates the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera 11102 and performs various image processing operations on the image signals, such as image processing (de-mosaicing), for displaying images based on those image signals.

[0315] The display device 11202 displays an image based on the image signal processed by the CCU 11201 under the control of the CCU 11201.

[0316] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED) and supplies illumination light for imaging surgical sites to the endoscope 11100.

[0317] Input device 11204 is an input interface for endoscopic surgical system 11000. Users can input various information and commands into endoscopic surgical system 11000 via input device 11204. For example, users can input commands through endoscope 11100 to change imaging conditions (type of illumination light, magnification, focal length, etc.).

[0318] The treatment device control device 11205 controls the drive of the energy treatment device 11112 for purposes such as tissue cauterization and incision, and sealing of blood vessels. The pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to inflate the body cavity, ensuring the field of vision of the endoscope 11100 and ensuring the surgeon's working space. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various forms such as text, images, and graphics. The ranging signal processing device 11209 is a device equipped with a control unit 40 and a processing unit 60 according to the ranging module 1 of this disclosure and configured to acquire distance information.

[0319] Note that the light source device 11203, which supplies illumination light to the endoscope 11100 for imaging the surgical site, can be, for example, an LED, a laser light source, or a white light source having a combination thereof. When the white light source is constructed using a combination of RGB laser light sources, the white balance of the captured image can be adjusted within the light source device 11203 because the output intensity and timing of each color (wavelength) can be controlled with high precision. Furthermore, in this case, by illuminating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the driving of the imaging element of the camera 11102 in synchronization with the illumination timing, images corresponding to each RGB can also be captured in a time-division manner. According to this method, a color image can be obtained without a color filter in the imaging element.

[0320] Furthermore, the drive of the light source device 11203 can be controlled to change the intensity of the light to be output at predetermined intervals. By controlling the drive of the imaging element of the camera 11102 in time-segmented synchronization with the change in light intensity to acquire and synthesize images, high dynamic range images without so-called underexposed shadows and overexposed highlights can be generated.

[0321] Furthermore, the light source device 11203 can be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, so-called narrow-band light observation (narrow-band imaging) is performed, where predetermined tissues, such as blood vessels in the mucosal surface, are imaged with high contrast by using light in a narrower band than the illumination light used in ordinary observation (i.e., white light) by utilizing the wavelength dependence of light absorption in body tissue. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image by irradiating fluorescence generated by excitation light. In fluorescence observation, for example, body tissue can be irradiated with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to supply narrow-band light and / or excitation light corresponding to this special light observation.

[0322] Figure 62 It is shown Figure 60 The block diagram shown illustrates an example of the functional configuration of the camera 11102 and CCU 11201.

[0323] Camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. Camera 11102 and CCU 11201 are communicatively connected to each other via a transmission cable 11400.

[0324] Lens unit 11401 is an optical system disposed at the connection portion with lens barrel 11101. Observation light received from the distal end of lens barrel 11101 is guided to camera 11102 and incident on lens unit 11401. Lens unit 11401 is constructed by combining multiple lenses, including zoom lenses and focal lenses.

[0325] Imaging unit 11402 is composed of imaging elements. The number of imaging elements constituting imaging unit 11402 can be a single element (so-called single-plate type) or multiple elements (so-called multi-plate type). When imaging unit 11402 is constructed as multi-plate type, for example, an image signal corresponding to each RGB can be generated by each imaging element, and a color image can be obtained by combining the image signals. Alternatively, imaging unit 11402 may include a pair of imaging elements for acquiring image signals for the right and left eyes corresponding to three-dimensional (3D) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of body tissue in the surgical site. Note that when imaging unit 11402 is constructed as multi-plate type, multiple lens units 11401 corresponding to each imaging element can be provided.

[0326] Furthermore, the imaging unit 11402 does not necessarily have to be located within the camera 11102. For example, the imaging unit 11402 can be located directly behind the objective lens inside the lens barrel 11101.

[0327] The drive unit 11403 includes an actuator that, under the control of the camera control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0328] Communication unit 11404 includes communication means for transmitting and receiving various information to / from CCU 11201. Communication unit 11404 transmits image signals acquired from imaging unit 11402 as RAW data to CCU 11201 via transmission cable 11400.

[0329] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 for controlling the camera 11102 and supplies the control signals to the camera control unit 11405. The control signals include, for example, information related to imaging conditions, such as information for specifying the frame rate of the captured image, information for specifying the exposure value during imaging, and / or information for specifying the magnification and focus of the captured image.

[0330] Note that imaging conditions such as frame rate, exposure value, magnification, and focus can be appropriately specified by the user, or can be automatically set by the control unit 11413 of CCU 11201 based on the captured image signal. In the latter case, so-called automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions are installed in endoscope 11100.

[0331] The camera control unit 11405 controls the driving of the camera 11102 based on the control signals received from the CCU 11201 via the communication unit 11404.

[0332] The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera 11102. The communication unit 11411 receives image signals transmitted from the camera 11102 via a transmission cable 11400.

[0333] In addition, the communication unit 11411 transmits control signals for controlling the camera 11102 to the camera 11102. Image signals and control signals can be transmitted via electrical communication, optical communication, etc.

[0334] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera 11102.

[0335] The control unit 11413 performs various controls related to imaging of surgical sites, etc., using the endoscope 11100, and displaying the captured images obtained by imaging the surgical sites, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera 11102.

[0336] Furthermore, the control unit 11413 causes the display device 11202 to display captured images of the surgical site, etc., based on image signals processed by the image processing unit 11412. At this time, the control unit 11413 can identify various objects within the captured image using various image recognition technologies. For example, the control unit 11413 can identify surgical instruments such as forceps, specific living sites, bleeding, fog during the use of the energy treatment device 11112, etc., by detecting the edge shape and / or color of objects included in the captured image. When the captured image is displayed on the display device 11202, the control unit 11413 can overlay and display various surgical support information related to the image of the surgical site using the recognition results. Since the surgical support information is overlaid and displayed and presented to the surgeon 11131, the burden on the surgeon 11131 can be alleviated, and the surgeon 11131 can perform the surgery reliably.

[0337] The transmission cable 11400 connecting the camera 11102 and the CCU 11201 is an electrical signal cable corresponding to electrical signal communication, an optical fiber or a composite cable corresponding to optical communication.

[0338] Here, in the example shown, communication is wired using transmission cable 11400, but wireless communication between camera 11102 and CCU 11201 is also possible.

[0339] Examples of endoscopic surgical systems to which the technology according to this disclosure is applicable have been described. The technology according to this disclosure can be applied to the imaging unit 11402 in the above-described configuration. Specifically, the light-receiving element 10 can be applied as part of the configuration of the imaging unit 11402. Applying the technology according to this disclosure as part of the configuration of the imaging unit 11402 allows for high-precision measurement of the distance to the surgical site and the acquisition of clearer images of the surgical site.

[0340] Note that examples of endoscopic surgical systems have been described herein, but the techniques disclosed herein can be further applied to, for example, microscopic surgical systems.

[0341] <<12. Examples of Applications of Moving Bodies>>

[0342] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed on any type of mobile body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, unmanned aerial vehicles, ships, robots, etc.

[0343] Figure 63 This is a block diagram illustrating a schematic configuration example of a vehicle control system, which serves as an example of a mobile body control system to which the technology according to this disclosure is applicable.

[0344] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 63 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as functional components of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0345] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a drive force generating device such as an internal combustion engine or drive motor to generate drive force for the vehicle, a drive force transmission mechanism to transmit drive force to the wheels, a steering mechanism to adjust the vehicle's steering angle, and a control device to generate braking force for the vehicle.

[0346] The main system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves transmitted from a portable device or signals from various switches, used to replace buttons, can be input to the main system control unit 12020. The main system control unit 12020 receives the input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0347] The exterior information detection unit 12030 detects external information of the vehicle on which the vehicle control system 12000 is installed. For example, an imaging unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. The exterior information detection unit 12030 can perform object detection processing such as people, cars, obstacles, signs, and text on the road, or distance detection processing based on the received images. For example, an iToF sensor 12032 is connected to the exterior information detection unit 12030. The iToF sensor 12032 is configured to be used as a ranging module 1 according to an embodiment of the present disclosure.

[0348] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output an electrical signal as an image or as ranging information. Furthermore, the light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0349] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041, which detects the driver's state, is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that images the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is drowsy.

[0350] For example, the microcomputer 12051 can calculate control values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior and exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or mitigation, distance-based tracking, speed maintenance, collision warning, and lane departure warning.

[0351] Furthermore, the microcomputer 12051 can coordinate and control the drive force generating device, steering mechanism, braking device, etc., based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, in order to achieve autonomous driving, where the vehicle drives itself without relying on the driver's operation.

[0352] Furthermore, the microcomputer 12051 can output control commands to the main system control unit 12020 based on information about the exterior of the vehicle obtained by the external information detection unit 12030. For example, the microcomputer 12051 can coordinate the control of the headlights according to the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030 to achieve glare prevention, such as switching the high beams to low beams.

[0353] The audio / image output unit 12052 transmits at least one of the audio and image output signals to an output device capable of visually or audibly informing vehicle occupants or the outside of the vehicle. Figure 63 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0354] Figure 64 This is a diagram showing an example of the mounting location of the imaging unit 12031.

[0355] exist Figure 64 In the vehicle 12100, imaging units 12101, 12102, 12103, 12104 and 12105 are included as imaging units 12031.

[0356] Imaging units 12101, 12102, 12103, 12104, and 12105 are installed at locations such as the front of the vehicle 12100, side mirrors, rear bumper, rear door, and the upper part of the windshield inside the vehicle. Imaging unit 12101 at the front of the vehicle and imaging unit 12105 at the upper part of the windshield inside the vehicle primarily acquire images of the front of the vehicle 12100. Imaging units 12102 and 12103 at the side mirrors primarily acquire images of the sides of the vehicle 12100. Imaging unit 12104 at the rear bumper or rear door primarily acquires images of the rear of the vehicle 12100. Imaging unit 12105 at the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc., ahead. The iToF sensor module 12201, which includes a light-emitting unit 20 and a light-receiving unit 30 of a ranging module 1 according to an embodiment of the present disclosure, is, for example, located at the front of a vehicle 12100.

[0357] also, Figure 64 An example of the imaging range of imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located at the front of the vehicle; imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located in the side mirrors, respectively; and imaging range 12114 represents the imaging range of imaging unit 12104 located in the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view of the vehicle 12100 as seen from above is obtained.

[0358] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0359] For example, based on distance information obtained from imaging units 12101 to 12104, by obtaining the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed relative to vehicle 12100), microcomputer 12051 extracts the closest three-dimensional object on the driving path of vehicle 12100, and identifies the three-dimensional object traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher) as the vehicle ahead. Furthermore, microcomputer 12051 can set a pre-defined distance between vehicles for the vehicle ahead and can perform automatic braking control (including tracking stop control), automatic acceleration control (including tracking start control), etc. As described above, coordinated control for autonomous driving, etc., can be performed, in which the vehicle drives autonomously without relying on driver operation.

[0360] For example, based on distance information obtained from imaging units 12101-12104, microcomputer 12051 can classify three-dimensional object data into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles, extract the three-dimensional object data, and use the three-dimensional object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that can be visually recognized by the driver of vehicle 12100 and obstacles that are difficult to visually recognize. Then, microcomputer 12051 determines the collision risk indicating the degree of danger of colliding with each obstacle, and when the collision risk is equal to or higher than a set value and there is a possibility of collision, it can provide driving assistance for collision avoidance by outputting a warning to the driver via audio speaker 12061 and display unit 12062 or by performing forced deceleration or evasive steering via drive system control unit 12010.

[0361] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. For example, pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / image output unit 12052 causes the display unit 12062 to overlay and display a quadrilateral outline for emphasis on the identified pedestrian. Furthermore, the audio / image output unit 12052 can cause the display unit 12062 to display an icon or similar indicating the pedestrian at a desired location.

[0362] Examples of mobile body control systems to which the technology according to this disclosure is applicable have been described above. The technology according to this disclosure is applicable to the vehicle exterior information detection unit 12030 or the imaging unit 12031. Specifically, the light-receiving element 10 or the ranging module 1 is applicable to the distance detection processing block of the vehicle exterior information detection unit 12030 or the imaging unit 12031. The technology according to this disclosure, applied to the vehicle exterior information detection unit 12030 or the imaging unit 12031, enables the high-precision measurement of distances to objects such as people, cars, obstacles, signs, or text on the road surface, and utilizes the obtained distance information to reduce driver fatigue or improve driver or vehicle safety.

[0363] <13. Supplementary Explanation>

[0364] Preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings. However, the scope of the present disclosure is not limited to such examples. It will be apparent to those skilled in the art that various modifications and variations can be conceived within the scope of the technical concept recited in the claims, and naturally fall within the scope of the present disclosure.

[0365] Furthermore, the effects described in this specification are illustrative or exemplary only, and not restrictive. In other words, in addition to or instead of the effects described above, the technology according to this disclosure may exhibit other effects that are obvious to those skilled in the art from the description herein.

[0366] Note that this technology can also be configured as follows.

[0367] (1) A light-receiving device including a light-receiving unit, the light-receiving unit comprising a plurality of light-receiving elements arranged along a row direction and a column direction on a semiconductor substrate, wherein

[0368] Each of the light-receiving elements includes:

[0369] The first photoelectric conversion unit that converts light into electrical charge;

[0370] The first charge accumulation unit that transfers charge to the first photoelectric conversion unit;

[0371] Distribute charge from the first photoelectric conversion unit to the first distribution gate of the first charge accumulation unit;

[0372] A second charge accumulation unit that transfers charge to the first photoelectric conversion unit; and

[0373] Distributing charge from the first photoelectric conversion unit to the second distribution gate of the second charge accumulation unit, and

[0374] When viewed from above the semiconductor substrate, the first distribution gate and the second distribution gate are positioned in a position that is linearly symmetrical to each other with respect to the first central axis, which extends through the center of the first photoelectric conversion unit along a direction that intersects the column direction at a predetermined angle.

[0375] (2) The light-receiving device according to (1), wherein the predetermined angle is 45 degrees.

[0376] (3) A light-receiving device including a light-receiving unit, the light-receiving unit comprising a plurality of light-receiving elements arranged along a row direction and a column direction on a semiconductor substrate, wherein

[0377] Each of the light-receiving elements includes:

[0378] The first photoelectric conversion unit that converts light into electrical charge;

[0379] The first charge accumulation unit that transfers charge to the first photoelectric conversion unit;

[0380] Distribute charge from the first photoelectric conversion unit to the first distribution gate of the first charge accumulation unit;

[0381] A second charge accumulation unit that transfers charge to the first photoelectric conversion unit; and

[0382] Distributing charge from the first photoelectric conversion unit to the second distribution gate of the second charge accumulation unit, and

[0383] When viewed from above the semiconductor substrate, the first distribution gate and the second distribution gate are positioned in a position that is linearly symmetrical to each other with respect to the first central axis, which extends along the column direction through the center of the first photoelectric conversion unit.

[0384] (4) The light-receiving device according to any one of (1) to (3), wherein

[0385] Each of the light-receiving elements further includes a first discharge gate and a second discharge gate for discharging charge from the first photoelectric conversion unit, and

[0386] When viewed from above the semiconductor substrate, the first discharge gate and the second discharge gate are positioned in a position that is linearly symmetrical to each other with respect to a second central axis that is perpendicular to a first central axis passing through the center of the first photoelectric conversion unit.

[0387] (5) The light-receiving device according to (4), wherein

[0388] The first distribution gate and the second distribution gate, or the first discharge gate and the second discharge gate, are included in one or more buried gate portions in the semiconductor substrate.

[0389] (6) The light-receiving device according to (4), wherein

[0390] When viewed from above the semiconductor substrate, the first charge accumulation unit and the second charge accumulation unit are positioned at points symmetrical to each other with respect to the center of the first photoelectric conversion unit.

[0391] (7) The light-receiving device according to (3), wherein

[0392] Each of the light-receiving elements further includes a third discharge gate for discharging charge from the first photoelectric conversion unit, and

[0393] When viewed from above the semiconductor substrate, the center of the third discharge gate is located on the first central axis.

[0394] (8) The light-receiving device according to (7), wherein

[0395] When viewed from above,

[0396] The first line segment connecting the center of the first distribution gate and the center of the first photoelectric conversion unit, and the second line segment connecting the center of the second distribution gate and the center of the first photoelectric conversion unit, are perpendicular to the first central axis.

[0397] (9) The light-receiving device according to (7), wherein

[0398] When viewed from above,

[0399] The first line segment connecting the center of the first distribution gate and the center of the first photoelectric conversion unit forms an acute angle with the first central axis, and

[0400] The second line segment connecting the center of the second distribution gate and the center of the first photoelectric conversion unit forms an acute angle with the first central axis.

[0401] (10) The light-receiving device according to (9), wherein

[0402] When viewed from above the semiconductor substrate, the first charge accumulation unit and the second charge accumulation unit are positioned at a position that is linearly symmetrical to each other with respect to the first central axis.

[0403] (11) The light-receiving device according to (3), wherein

[0404] Each of the light-receiving elements further includes:

[0405] One or more first floating diffusion regions are disposed within the semiconductor substrate;

[0406] A first transfer gate, disposed on the semiconductor substrate, is used to transfer charge transferred to the first charge accumulation unit to the one or more first floating diffusion regions; and

[0407] A second transfer gate is disposed on the semiconductor substrate to transfer the charge transferred to the second charge accumulation unit to one or more of the first floating diffusion regions.

[0408] (12) The light-receiving device according to (11), wherein

[0409] Each of the light-receiving elements further includes:

[0410] One or more amplifying transistors amplify the charge transferred to the first floating diffusion region and output it as a pixel signal;

[0411] One or more selection transistors, which output the pixel signal according to a selection signal; and

[0412] One or more reset transistors that reset the charge accumulated in the first floating diffusion region.

[0413] (13) The light-receiving device according to (12), wherein each of the first charge accumulation unit and the second charge accumulation unit comprises a stack of electrodes, a first insulating film and a semiconductor layer.

[0414] (14) The light-receiving device according to (13), wherein the first insulating film is composed of an oxide film with a thickness of less than 5.0 nm.

[0415] (15) The light-receiving device according to (13), wherein

[0416] The relative permittivity of the first insulating film is 4 or higher.

[0417] (16) The light-receiving device according to (13), wherein

[0418] The first insulating film is composed of a first oxide film.

[0419] Each of the first and second transmission gates has a second oxide film disposed on the semiconductor substrate, and

[0420] The first oxide film has a smaller thickness than the second oxide film.

[0421] (17) The light-receiving device according to (16), wherein

[0422] Each of the amplifying transistor, the selecting transistor, and the resetting transistor has a third oxide film disposed on the semiconductor substrate, and

[0423] The thickness of the third oxide film of the amplifying transistor is less than the thickness of the third oxide film of the select transistor and the reset transistor.

[0424] (18) The light-receiving device according to (13), wherein

[0425] Each of the first and second transmission gates has a second insulating film disposed on the semiconductor substrate, and

[0426] The first insulating film has a higher relative permittivity than the second insulating film.

[0427] (19) The light-receiving device according to (18), wherein

[0428] Each of the amplifying transistor, the selecting transistor, and the reset transistor has a third insulating film disposed on the semiconductor substrate, and

[0429] The relative permittivity of the third insulating film of the amplifying transistor is higher than that of the third insulating film of the select transistor and the reset transistor.

[0430] (20) The light receiving device according to (12), wherein the one or more amplifying transistors, the one or more selecting transistors and the one or more reset transistors are disposed on the semiconductor substrate.

[0431] (21) The light-receiving device according to (12), wherein the one or more amplifying transistors, the one or more selecting transistors and the one or more reset transistors are disposed on another semiconductor substrate.

[0432] (22) The light-receiving device according to (3), wherein the plurality of light-receiving elements are configured to face the same direction in the light-receiving unit.

[0433] (23) The light-receiving device according to (3), wherein

[0434] The light-receiving unit is divided into multiple regions, and

[0435] In each of the regions, the plurality of light-receiving elements are configured to face a defined direction for each region.

[0436] (24) The light-receiving device according to (3), wherein

[0437] The light-receiving unit also includes multiple imaging elements, and

[0438] Each of the imaging elements includes:

[0439] The second photoelectric conversion unit converts light into electrical charge;

[0440] The second floating diffusion region from which charge is transferred to the second photoelectric conversion unit; and

[0441] The third transfer gate transfers charge from the second photoelectric conversion unit to the second floating diffusion region.

[0442] (25) The light-receiving device according to (24), wherein the plurality of imaging elements includes a first imaging element for detecting red light, a second imaging element for detecting blue light and a third imaging element for detecting green light.

[0443] (26) The light-receiving device according to (25), wherein

[0444] The plurality of imaging elements also includes a fourth imaging element for detecting near-infrared light.

[0445] (27) The light-receiving device according to any one of (24) to (26), wherein the plurality of imaging elements are disposed on the semiconductor substrate.

[0446] List of reference numerals

[0447] 1. Ranging module 10, 10a, 10b; light receiving element

[0448] 12 pixel array units, 20 light-emitting units

[0449] 30 Light receiving unit; 32 Vertical drive circuit unit

[0450] 34-column signal processing circuit unit; 36-column horizontal drive circuit unit

[0451] 38 Output circuit unit 40 Control unit

[0452] 42 pixel drive lines; 44 control circuit units

[0453] 46 Horizontal signal line 48 Vertical signal line

[0454] 50. Transistor drive unit; 52. Signal processing unit

[0455] 54 Data storage units 60 Processing units

[0456] 100, 102a, 102b N-type semiconductor regions

[0457] 150a, 150b, 150c, 150d, 152, 152a, 152b, 156a, 156b, 158a, 158b, 160a, 160b, 162a, 162b Gate electrodes

[0458] 154a, 154b, 306, 406 electrodes

[0459] 200,200b Semiconductor substrate 202 Anti-reflective film

[0460] 204 planarization film; 206 light-blocking film.

[0461] 208 On-chip lens 210a Pixel isolation section

[0462] 300 wiring layers

[0463] 302, 402, 720, 720a, 740 insulating films

[0464] 304,404 metal film 400 substrate

[0465] Imaging elements for models 500, 500b, 500g, 500r, and 500i.

[0466] Center lines 600, 602, 604a, 604b, 612, 614

[0467] 710 via

[0468] 730 sidewall 800 object

[0469] 802a, 802b Area 900 Smartphones

[0470] 901 CPU 902 ROM

[0471] 903 RAM 904 Storage device

[0472] 905 Communication Module; 907 Sensor Module

[0473] 908 Ranging Module; 909 Imaging Device

[0474] 910 Display device 911 Speaker

[0475] 912 Microphone; 913 Input Device

[0476] AMP, AMP1, AMP2 Amplifying Transistors

[0477] FD, FD1, FD2, FD3, FD4, FD5, FD6, FD7, FD8 Floating diffusion regions

[0478] MEM, MEM1, MEM2, MEM3, MEM4, MEM5, MEM6, MEM7, MEM8 Charge accumulation units

[0479] Center point of O, O1a, O1b, O2

[0480] OFG, OFG1, OFG2 discharge transistors

[0481] PD photodiodes RST, RST1, RST2; reset transistors

[0482] SEL, SEL1, SEL2 select transistors

[0483] TG, TG1, TG2, TG3, TG4, TG5, TG6, TG7, TG8 Transmission transistors

[0484] VDD power supply potential

[0485] VG, VG1, VG2, VG3, VG4, VG5, VG6, VG7, VG8 are assigned transistors.

[0486] VSL, VSL1, VSL2 signal lines

Claims

1. A light-receiving device including a light-receiving unit including a plurality of light-receiving elements arranged on a semiconductor substrate along a row direction and a column direction, wherein each of the light-receiving elements includes: a first photoelectric conversion unit that converts light into electric charges; a first charge accumulation unit to which the electric charges are transferred from the first photoelectric conversion unit; a first distribution gate that distributes the electric charges from the first photoelectric conversion unit to the first charge accumulation unit; a second charge accumulation unit to which the electric charges are transferred from the first photoelectric conversion unit; and a second distribution gate that distributes the electric charges from the first photoelectric conversion unit to the second charge accumulation unit, and the first distribution gate and the second distribution gate are disposed at positions that are line-symmetrical to each other with respect to a first central axis that extends through a center of the first photoelectric conversion unit along a direction that intersects the column direction at a predetermined angle when viewed from above the semiconductor substrate, wherein each of the light-receiving elements further includes: one or more first floating diffusion regions provided within the semiconductor substrate; a first transfer gate provided on the semiconductor substrate to transfer the electric charges transferred to the first charge accumulation unit to the one or more first floating diffusion regions; and a second transfer gate provided on the semiconductor substrate to transfer the electric charges transferred to the second charge accumulation unit to the one or more first floating diffusion regions, wherein each of the first charge accumulation unit and the second charge accumulation unit includes a stack of an electrode, a first insulating film, and a semiconductor layer, and the first insulating film is composed of a first oxide film, each of the first transfer gate and the second transfer gate has a second oxide film provided on the semiconductor substrate, and the first oxide film has a film thickness that is smaller than the second oxide film.

2. The light-receiving device according to claim 1, wherein the predetermined angle is 45 degrees.

3. A light-receiving device including a light-receiving unit including a plurality of light-receiving elements arranged on a semiconductor substrate along a row direction and a column direction, wherein each of the light-receiving elements includes: a first photoelectric conversion unit that converts light into electric charges; a first charge accumulation unit to which the electric charges are transferred from the first photoelectric conversion unit; a first distribution gate that distributes the electric charges from the first photoelectric conversion unit to the first charge accumulation unit; a second charge accumulation unit to which the electric charges are transferred from the first photoelectric conversion unit; and a second distribution gate that distributes the electric charges from the first photoelectric conversion unit to the second charge accumulation unit, and the first distribution gate and the second distribution gate are disposed at positions that are line-symmetrical to each other with respect to a first central axis that extends through a center of the first photoelectric conversion unit along the column direction when viewed from above the semiconductor substrate, wherein each of the light-receiving elements further includes: one or more first floating diffusion regions provided within the semiconductor substrate; a first transfer gate provided on the semiconductor substrate to transfer the electric charges transferred to the first charge accumulation unit to the one or more first floating diffusion regions; and a second transfer gate provided on the semiconductor substrate to transfer the electric charges transferred to the second charge accumulation unit to the one or more first floating diffusion regions, wherein each of the first charge accumulation unit and the second charge accumulation unit includes a stack of an electrode, a first insulating film, and a semiconductor layer, and the first insulating film is composed of a first oxide film, each of the first transfer gate and the second transfer gate has a second oxide film provided on the semiconductor substrate, and the first oxide film has a film thickness that is smaller than the second oxide film. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a second transfer gate provided on the semiconductor substrate to transfer the electric charges transferred to the second electric charge accumulation unit to the one or more first floating diffusion regions, wherein each of the first electric charge accumulation unit and the second electric charge accumulation unit includes a stack of an electrode, a first insulating film, and a semiconductor layer, and wherein the first insulating film is composed of a first oxide film, each of the first transfer gate and the second transfer gate has a second oxide film provided on the semiconductor substrate, and the first oxide film has a film thickness smaller than that of the second oxide film.

4. The light-receiving device according to claim 3, wherein each of the light-receiving elements further includes a first drain gate and a second drain gate for draining the electric charges in the first photoelectric conversion unit, and the first drain gate and the second drain gate are provided at positions symmetrical to each other with respect to a second central axis orthogonal to a first central axis passing through the center of the first photoelectric conversion unit, when viewed from above the semiconductor substrate.

5. The light-receiving device according to claim 4, wherein any one of the first distribution gate and the second distribution gate or the first drain gate and the second drain gate includes one or more buried gate portions in the semiconductor substrate.

6. The light-receiving device according to claim 4, wherein the first electric charge accumulation unit and the second electric charge accumulation unit are provided at positions symmetrical to each other with respect to the center of the first photoelectric conversion unit, when viewed from above the semiconductor substrate.

7. The light-receiving device according to claim 3, wherein each of the light-receiving elements further includes a third drain gate for draining the electric charges in the first photoelectric conversion unit, and a center of the third drain gate is located on the first central axis, when viewed from above the semiconductor substrate.

8. The light-receiving device according to claim 7, wherein when viewed from above the semiconductor substrate, a first line segment connecting a center of the first distribution gate and a center of the first photoelectric conversion unit and a second line segment connecting a center of the second distribution gate and the center of the first photoelectric conversion unit are orthogonal to the first central axis.

9. The light-receiving device according to claim 7, wherein when viewed from above the semiconductor substrate, the first line segment connecting the center of the first distribution gate and the center of the first photoelectric conversion unit forms an acute angle with the first central axis, and the second line segment connecting the center of the second distribution gate and the center of the first photoelectric conversion unit forms an acute angle with the first central axis.

10. The light-receiving device according to claim 9, wherein the first electric charge accumulation unit and the second electric charge accumulation unit are provided at positions symmetrical to each other with respect to the first central axis, when viewed from above the semiconductor substrate.

11. The light-receiving device according to claim 3, wherein each of the light-receiving elements further includes: one or more amplification transistors that amplify the electric charges transferred to the first floating diffusion region and output as a pixel signal; one or more selection transistors that output the pixel signal in accordance with a selection signal; and one or more reset transistors that reset the electric charges accumulated in the first floating diffusion region. ​ 12. The light-receiving device according to claim 3, wherein the first insulating film is composed of a first oxide film having a film thickness of 5.0 nm or less.

13. The light-receiving device according to claim 3, wherein a relative dielectric constant of the first insulating film is 4 or more.

14. The light-receiving device according to claim 11, wherein each of the amplification transistor, the selection transistor, and the reset transistor has a third oxide film provided on the semiconductor substrate, and a film thickness of the third oxide film of the amplification transistor is smaller than film thicknesses of the third oxide films of the selection transistor and the reset transistor.

15. The light-receiving device according to claim 3, wherein each of the first transfer gate and the second transfer gate has a second insulating film provided on the semiconductor substrate, and the first insulating film has a higher relative dielectric constant than the second insulating film.

16. The light-receiving device according to claim 11, wherein each of the amplification transistor, the selection transistor, and the reset transistor has a third insulating film provided on the semiconductor substrate, and a relative dielectric constant of the third insulating film of the amplification transistor is higher than relative dielectric constants of the third insulating films of the selection transistor and the reset transistor.

17. The light-receiving device according to claim 11, wherein the one or more amplification transistors, the one or more selection transistors, and the one or more reset transistors are provided on the semiconductor substrate.

18. The light-receiving device according to claim 11, wherein the one or more amplification transistors, the one or more selection transistors, and the one or more reset transistors are provided on another semiconductor substrate.

19. The light-receiving device according to claim 3, wherein the plurality of light-receiving elements are configured to face the same direction in the light-receiving unit.

20. The light-receiving device according to claim 3, wherein the light-receiving unit is divided into a plurality of regions, and in each of the regions, the plurality of light-receiving elements are configured to face a defined direction for each of the regions.

21. The light-receiving device according to claim 3, wherein the light-receiving unit further includes a plurality of imaging elements, and each of the imaging elements includes: a second photoelectric conversion unit that converts light into electric charges; a second floating diffusion region to which electric charges are transferred from the second photoelectric conversion unit; and a third transfer gate that transfers electric charges from the second photoelectric conversion unit to the second floating diffusion region.

22. The light-receiving device according to claim 21, wherein the plurality of imaging elements include a first imaging element that detects red light, a second imaging element that detects blue light, and a third imaging element that detects green light.

23. The light-receiving device according to claim 22, wherein the plurality of imaging elements further include a fourth imaging element that detects near-infrared light.

24. The light-receiving device according to claim 21, wherein the plurality of imaging elements are provided on the semiconductor substrate. ​

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