Data comparison device, data comparison method and chip tester

Abstract

This application relates to the field of chip testing technology. Disclosed are a data comparison device, a data comparison method, and a chip tester. The data comparison device includes: a data comparison module, which includes a first input end, a second input end, and an output end; the second input end is used to connect to an external device and is configured to receive expected data from the external device; the first input end is used to connect to a chip testing device, and the chip testing device is used to test a chip to be tested and output test data of the chip to be tested. The first input end is configured to receive the test data from the chip testing device; wherein, in response to the chip testing device outputting the test data, the first input end receives the test data and compares the test data with the expected data to obtain a data comparison result. Through the above data comparison device, it is possible to compare the test data and the expected data in real time according to the parameters stored in the storage module, ensuring the real-time nature of chip testing and improving the chip testing efficiency.

Description

Technical Field

[0001] This application relates to the technical field of chip testing, and particularly to a data comparison device, a data comparison method, and a chip tester thereof. Background Art

[0002] Wafer CP (Chip Probing) testing is often applied to the functional testing and performance testing of electronic chips to understand whether the chip functions are normal and to screen out faulty chips in the chip wafer. Wafer CP testing mainly includes the process of extracting chip data and the testing process. Among them, in the extraction process, a probe is first used to pierce the chips on the wafer, various signals are input into the chips, and then the data output by the chips is filtered and / or delayed to extract the required chip data, which is then stored through a storage module. In the testing process, a tester is first connected to the storage module to obtain chip data, then the clock frequency of the obtained chip data is adjusted to be the same as the clock frequency of an expected data, and then the expected data is compared and calculated with the chip data to obtain the chip test result.

[0003] Chip testing in the prior art requires two processes, and each process needs to be completed using different instruments, resulting in low efficiency of data comparison, and the data stored in the module to be tested is not real-time, which cannot meet scenarios with high requirements for real-time performance. Summary of the Invention

[0004] To solve the above problems, this application provides a data comparison device that can realize real-time comparison of test data and expected data according to the threshold parameters stored in the device, thereby ensuring the real-time performance of chip testing and improving the chip testing efficiency.

[0005] One technical solution adopted by this application is: to provide a data comparison device, which includes: a data comparison module, the data comparison module includes a first input end, a second input end, and an output end; the second input end is used to connect to an external device and is configured to receive expected data from the external device; the first input end is used to connect to a chip testing device, the chip testing device is used to test a chip to be tested and output test data of the chip to be tested, and the first input end is configured to receive test data from the chip testing device; wherein, in response to the chip testing device outputting test data, the first input end receives the test data and compares the test data with the expected data to obtain a data comparison result.

[0006] Wherein, the device further includes: a register module, the register module stores functional parameters; the data comparison module compares the test data with the expected data based on the functional parameters to obtain a data comparison result.

[0007] Among them, the functional parameters include threshold parameters, configuration parameters, and multiple control instructions; the data comparison module configures data comparison parameters based on the configuration parameters, and according to the first instruction among the multiple control instructions, performs an operation of comparing the test data with the expected data, and obtains a data comparison result in response to the value of the data comparison meeting the threshold parameter; among them, the data comparison parameters include a delay parameter and a comparison parameter.

[0008] Among them, the data comparison module includes: a delay circuit, connected to the register module, the delay circuit configures the delay parameter based on the configuration parameter, and corrects the input delays of the test data and the expected data according to the second instruction among the multiple control instructions to obtain the corrected test data and the corrected expected data; a comparison circuit, connected to the delay circuit and the register module, the comparison circuit configures the comparison parameter based on the configuration parameter, and according to the third instruction among the multiple control instructions, performs an operation of comparing the corrected test data with the corrected expected data, and obtains a data comparison result in response to the value of the data comparison meeting the threshold parameter.

[0009] Among them, the comparison circuit configures the comparison parameter based on the configuration parameter, including: the comparison circuit configures the data bit width of the comparison circuit according to the configuration parameter.

[0010] Among them, the data comparison result includes a test signal and an expected signal; the data comparison device further includes: a signal comparison module, connected to the output end and the register module, configured to receive the test signal and the expected signal output by the data comparison module from the output end; the signal comparison module configures signal comparison parameters based on the configuration parameter, and according to the fourth instruction among the multiple control instructions, performs an operation of comparing the test signal with the expected signal, and obtains a signal comparison result in response to the value of the signal comparison meeting the threshold parameter; among them, the signal comparison parameters include a counting depth.

[0011] Among them, the signal comparison module includes: a counter, connected to the register module, the counter configures the counting depth based on the configuration parameter, and counts according to the counting depth to obtain a count value; a sampler, connected to the register module, the data comparison module, and the counter, the sampler performs an operation of sampling the count value and determining the duration when the data comparison results are different according to the fifth instruction among the multiple control instructions.

[0012] Among them, the signal comparison module includes: an overflow judgment circuit, connected to the data comparison module, the register module, and the counter, the overflow judgment circuit performs an operation of obtaining the judgment starting point of the data comparison module and determining whether the count value overflows according to the sixth instruction among the multiple control instructions to generate a judgment signal.

[0013] Among them, the signal comparison module includes: a comparator, connected to the register module, the sampler, and the overflow judgment circuit. The comparator, according to the seventh instruction among multiple control instructions, performs an operation of using a judgment signal to determine the number of counts corresponding to the count value within a duration, and in response to the number of counts meeting the threshold parameter, obtains a signal comparison result; among them, in response to the number of counts corresponding to the count value within the duration being not greater than the threshold parameter, the signal comparison result is that the test data comparison is the same; in response to the number of counts corresponding to the count value within the duration being greater than the threshold parameter, the signal comparison result is that the test data comparison is different.

[0014] Among them, the device further includes: a clock input module, connected to the signal comparison module and the register module, configured to input a clock signal to the signal comparison module; the clock input module configures clock parameters based on configuration parameters, and according to the eighth instruction among multiple control instructions, performs an operation of inputting a clock signal to the signal comparison module.

[0015] Among them, the clock input module includes: a phase-locked loop, connected to the register module, the counter, and the sampler, and a third input terminal of the phase-locked loop is connected to an external oscillator; among them, in response to the external oscillator outputting an oscillation signal, the third input terminal receives the oscillation signal; the phase-locked loop configures clock parameters based on configuration parameters, and according to the ninth instruction among multiple control instructions, performs an operation of converting the oscillation signal into a first clock signal and transmitting the first clock signal to the counter and the sampler, so as to adjust the counting accuracy of the counter and the sampling frequency of the sampler.

[0016] Among them, the clock input module includes: a crystal oscillator, connected to a fourth input terminal of the phase-locked loop, configured to, when the external oscillator has no output, according to the tenth instruction among multiple control instructions, perform an operation of outputting a second clock signal to the phase-locked loop, so as to correspondingly adjust the counting accuracy of the counter and the sampling frequency of the sampler.

[0017] Among them, the device further includes: a communication interface, connected to the register module and an external device, for receiving a communication signal input by the external device and converting it into a threshold parameter, a configuration parameter, and a control instruction.

[0018] To solve the above technical problems, another technical solution adopted by this application is: to provide a data comparison method, the method includes: obtaining test data and expected data; performing a data comparison on the test data and the expected data to obtain a data comparison result; among them, the data comparison result includes a test signal and an expected signal; performing a signal comparison on the test signal and the expected signal to obtain a signal comparison result.

[0019] Among them, obtaining test data and expected data includes: receiving expected data from an external device, and receiving test data from a chip test device.

[0020] Among them, the test data is compared with the expected data to obtain a data comparison result, including: correcting the input delays of the test data and the expected data to obtain the corrected test data and the corrected expected data; comparing the corrected test data and the corrected expected data, and obtaining a data comparison result in response to the numerical value of the data comparison meeting the threshold parameter.

[0021] Among them, before comparing the corrected test data and the corrected expected data, it further includes: comparing a training sequence to correct the frequency deviation between the signal under test and the expected signal.

[0022] Among them, the test signal is compared with the expected signal to obtain a signal comparison result, including: counting according to a pre-designed counting depth to obtain a count value; sampling the count value and determining the duration when the data comparison results are different; obtaining the judgment start point during data comparison and determining whether the count value overflows according to the judgment start point to generate a judgment signal; determining the number of counting corresponding to the count value within the duration according to the judgment signal; obtaining a signal comparison result in response to the number of counting meeting the preset threshold parameter; among them, in response to the number of counting corresponding to the count value within the duration not being greater than the threshold parameter, the signal comparison result is that the test data is the same; in response to the number of counting corresponding to the count value within the duration being greater than the threshold parameter, the signal comparison result is that the test data is different.

[0023] Among them, the method further includes: obtaining a first clock signal input by a phase-locked loop; adjusting the counting accuracy and sampling frequency based on the first clock signal.

[0024] Among them, the method further includes: obtaining a second clock signal input by a crystal oscillator; adjusting the counting accuracy and sampling frequency based on the second clock signal.

[0025] Among them, the method further includes: obtaining function parameters and a mode signal input by a host computer; storing the function parameters and converting them into corresponding test modes according to the mode signal.

[0026] To solve the above technical problems, another technical solution adopted by this application is: providing a chip tester, which includes a chip test device for testing a chip under test to obtain test data; a data comparison device connected to the chip test device, applying the data comparison method to compare the test data to obtain a data comparison result; among them, the data comparison device is the data comparison device described above; the data comparison method is obtained from the data comparison method described above.

[0027] The beneficial effects of the present application are as follows: The solution of the present application provides a data comparison device, which includes a data comparison module. Among them, the data comparison module includes a first input end, a second input end, and an output end; the second input end of the data comparison module is used to connect to an external device and is configured to receive expected data from the external device in real time. The first input end of the data comparison module is used to connect to a chip testing device; wherein, the chip testing device is used to test a chip to be tested and output test data of the chip to be tested, and the first input end is configured to receive the test data from the chip testing device in real time. Among them, in response to the chip testing device outputting test data, the first input end receives the test data and compares the test data with the expected data to obtain a data comparison result. Compared with the prior art where the test data needs to be stored first and then compared subsequently, through the above data comparison device, the test data of the chip to be tested can be directly received from the chip testing device, and the input test data and expected data can be compared in real time, thereby ensuring the real-time nature of chip testing and improving the efficiency of chip testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the drawings of the present application. Among them:

[0029] Figure 1 is a schematic structural diagram of an embodiment of the data comparison device provided by the present application;

[0030] Figure 2 is a schematic structural diagram of another embodiment of the data comparison device provided by the present application;

[0031] Figure 3 is a schematic structural diagram of an embodiment of the external device provided by the present application;

[0032] Figure 4 is a schematic structural diagram of an embodiment of the data comparison module provided by the present application;

[0033] Figure 5 is a schematic structural diagram of an embodiment of the comparison circuit provided by the present application;

[0034] Figure 6 is a schematic structural diagram of an embodiment of the signal comparison module provided by the present application;

[0035] Figure 7 is a schematic structural diagram of an embodiment of the clock input module provided by the present application;

[0036] Figure 8It is a schematic flowchart of the first embodiment of the data comparison method provided by this application;

[0037] Figure 9 It is a schematic flowchart of an embodiment of step 12 of this application;

[0038] Figure 10 It is a schematic flowchart of an embodiment of step 13 of this application;

[0039] Figure 11 It is a schematic flowchart of the second embodiment of the data comparison method provided by this application;

[0040] Figure 12 It is a schematic flowchart of the third embodiment of the data comparison method provided by this application;

[0041] Figure 13 It is a schematic flowchart of the fourth embodiment of the data comparison method provided by this application;

[0042] Figure 14 It is a schematic structural diagram of an embodiment of the chip tester provided by this application. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. It can be understood that the specific embodiments described herein are only used to explain this application, rather than limiting this application. Additionally, it should be noted that for the sake of description, only parts related to this application rather than all structures are shown in the accompanying drawings. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

[0044] In addition, in the embodiments of this application, there are descriptions involving "first", "second", etc. The descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. Additionally, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0045] As used in this application, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include steps or units not listed, or may optionally further include other steps or units inherent to these processes, methods, products or devices.

[0046] Reference to "an embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0047] To elaborate in detail on the technical content, technical steps, achieved objectives and effects of this application, the following will be described in detail in conjunction with the embodiments and with reference to the accompanying drawings.

[0048] One technical solution of this application provides a data comparison device, which can achieve real-time comparison of test data and expected data according to threshold parameters, thereby ensuring the real-time nature of chip testing and improving chip testing efficiency.

[0049] Figure 1 It is a schematic structural diagram of an embodiment of the data comparison device provided by this application.

[0050] As Figure 1 shown, the data comparison device 10 includes a data comparison module 200. Specifically, the data comparison module 200 is provided with a first input terminal 210, a second input terminal 220 and an output terminal 230. Among them, the second input terminal 220 is used to connect to an external device 20, and the second input terminal 220 is configured to receive expected data from the external device 20 in real time. The first input terminal 210 is used to connect to a chip testing device 30. Among them, the chip testing device 30 is used to test a chip under test 31 and output the test data of the chip under test 31 to the first input terminal 210, and the first input terminal 210 is configured to receive the test data from the chip testing device 30. Among them, in response to the chip testing device 30 outputting test data, the first input terminal 210 receives the test data and compares the test data with the expected data to obtain a data comparison result.

[0051] Specifically, the expected data can be data obtained from an external device or data pre-stored in the data comparison device. It can be understood that if the expected data is data obtained from an external device, the data comparison device 10 further includes a second input terminal 220, which is used to connect to the external device and receive the expected data from the external device. Alternatively, in an embodiment, a predetermined communication protocol can also be set in the data comparison device 10 to obtain the expected data from the external device through the predetermined communication protocol. If the expected data is data pre-stored in the data comparison device, a register can be set in the data comparison device, and the register is used to store the expected data.

[0052] Optionally, the external device 20 can be a host computer, and a preset expected data is configured therein. The preset expected data can be set according to the requirements of data comparison (such as the accuracy and timeliness of data comparison).

[0053] Optionally, the chip under test 31 is a wafer that has not been diced and packaged. Tens of thousands of unpackaged chips are regularly distributed on the wafer. The probes on the chip testing device 30 can be used to pierce the chips on the wafer, so as to output various signals in the chips, so that the first input terminal 210 of the data comparison module 200 can receive the test data input by the chip testing device 30 in real time.

[0054] When the data comparison device 10 is working, the data comparison module 200 obtains the expected data transmitted by the external device 20 from the second input terminal 220 in real time and obtains the test data from the first input terminal 210 in real time. The data comparison module 200 compares the test data and the expected data in real time to obtain the result of data comparison, and outputs the result of data comparison through the output terminal 230, so that the data comparison device 10 can use the result of data comparison to obtain the test result of the chip under test 31.

[0055] Different from the prior art, the solution of the present application provides a data comparison device 10, and the data comparison device 10 includes a data comparison module 200. Among them, the data comparison module 200 includes a first input end 210, a second input end 220 and an output end 230; the second input end 220 of the data comparison module 200 is used to connect to an external device 20 and is configured to receive expected data from the external device 20 in real time. The first input end 210 of the data comparison module 10 is used to connect to a chip test device 30; among them, the chip test device 30 is used to test a chip to be tested 31 and output test data of the chip to be tested 31, and the first input end 210 is configured to receive the test data from the chip test device 30 in real time. Among them, in response to the chip test device 30 outputting test data, the first input end 210 receives the test data and compares the test data with the expected data to obtain a data comparison result. Compared with the prior art in which the test data needs to be stored first and then compared subsequently, through the above data comparison device 10, it is possible to compare the input test data and expected data in real time according to corresponding parameters, thereby ensuring the real-time nature of chip testing and improving the efficiency of chip testing.

[0056] Figure 2 It is a schematic structural diagram of another embodiment of the data comparison device provided by the present application.

[0057] As Figure 2 shown, the data comparison device 10 includes a register module 100, a data comparison module 200, a communication interface 300, a signal comparison module 400 and a clock input module 500. Specifically, the function parameters required by the data comparison module 200 are stored in the register module 100 and are connected to the data comparison module 200. Among them, the data comparison module 200 compares the test data with the expected data based on the function parameters to obtain a data comparison result. Among them, the data comparison module 200 is the same as that in the above embodiment and will not be elaborated here.

[0058] Among them, the function parameters include threshold parameters, configuration parameters and various control instructions.

[0059] Specifically, the data comparison module 200 configures the required data comparison parameters based on the configuration parameters transmitted by the storage module 100, and executes the operation of comparing the test data with the expected data according to the first instruction among the multiple control instructions transmitted by the storage module 100. When the numerical value of the data comparison meets the threshold parameter, a data comparison result is obtained. Among them, the data comparison parameters configured by the data comparison module 200 according to the configuration parameters include a delay parameter and a comparison parameter; the threshold parameters transmitted by the storage module 100 include a first threshold parameter and a second threshold parameter. The first threshold parameter is used for the data comparison process of the data comparison module 200, and the second threshold parameter is used for the signal comparison process of the signal comparison module 400; the multiple control instructions are used to control the data comparison and signal comparison processes of the data comparison module 200, the signal comparison module 400, and the clock input module 500.

[0060] Optionally, the storage module 100 is a register array, which may include general-purpose registers, special-purpose registers, control registers, etc., and can be used to temporarily store instructions, data, and addresses. The storage module 100 can simultaneously transmit data to internal circuits, external circuits, or external software, and the storage module 100 can provide a very high read / write speed, so that the data transmission between the register array and internal circuits, external circuits, or external software can be real-time.

[0061] Please continue to refer to Figure 2 , the external device 20 is respectively connected to the communication interface 300 and the first input end 210, so that the storage module 100 can receive the communication signal transmitted by the external device 20 through the communication interface 300 and the expected signal transmitted by the external device 20 through the first input end 210, for subsequent data comparison.

[0062] Figure 3 is a schematic structural diagram of an embodiment of the external device provided by the present application.

[0063] As Figure 3 shown, the external device 20 includes a human-machine interface 21 and a processor 22. Configuration parameters, threshold parameters, multiple control instructions, etc. can be input through the input end of the human-machine interface 21, and then each parameter or instruction is converted into a communication signal and expected data by the processor 22.

[0064] Furthermore, the communication interface 300 is connected to the external device 20 and the storage module 100, so that the communication interface 300 can obtain the communication signal from the external device 20 and convert it into threshold parameters, configuration parameters, and multiple control instructions, and then can transmit the threshold parameters, configuration parameters, and multiple control instructions to the storage module 100 for storage.

[0065] Optionally, the communication interface 300 includes an SPI interface (Serial Peripheral Interface), an I2C interface (INTER-IC, serial bus interface), a JTAG interface (Joint Test Action Group interface), etc., for connecting different communication protocols and configuring different working modes. Among them, the communication protocol corresponding to the SPI interface is a synchronous serial communication method, which is a three-wire synchronous bus, and the data conversion process is simple and fast. The communication protocol corresponding to the I2C interface is an inter-chip serial transmission bus, which can achieve duplex synchronous data transmission, and has the advantages of fewer interface lines, simplified control method, small device packaging form, and relatively high communication rate. The communication protocol corresponding to the JTAG interface is the Joint Test Action Group, which is an international standard test protocol (compatible with IEEE1149.1), mainly used for in-chip testing. Different test mode outputs, clock signal outputs, data inputs, and data outputs can be selected.

[0066] Figure 4 It is a schematic structural diagram of an embodiment of the data comparison module provided by the present application.

[0067] As Figure 4 shown, the data comparison module 200 includes: a delay circuit 240. Among them, the delay circuit 240 is connected to the register module 100. The delay circuit 240 configures its delay parameters based on the configuration parameters transmitted by the register module 100, and receives and executes the second instruction among the multiple control instructions transmitted by the register module 100. Among them, the second instruction is used to correct the input delay of the test data of the chip 31 to be tested and the expected data of the external device 20, so as to offset the input delay of the two data links, and thus obtain the corrected test data and the corrected expected data.

[0068] Optionally, in one embodiment, the delay circuit 240 may include a plurality of serially connected tri-state buffers and a plurality of transmission gates. Among them, the register module 100 inputs the first control instruction and the delay code to the delay circuit 240. The tri-state terminals of the plurality of serially connected tri-state buffers are connected to the register module 100 to receive the first control instruction and the delay code, and conduct the corresponding number of tri-state buffers according to the delay code and the first control instruction. The plurality of transmission gates then select the corresponding output form according to the corresponding configuration parameters to achieve the delay function. Optionally, the number of tri-state buffers conducted by the plurality of serially connected tri-state buffers according to the first control instruction can be from 0 to all the tri-state buffers.

[0069] Optionally, before the chip test device 30 outputs test data to the delay circuit 240 and the external device 20 outputs expected data to the delay circuit 240, it further includes: inputting a training sequence to the first input terminal 210 and the second input terminal 220 of the data comparison module 200, where the training sequence is used to correct the delay deviation between the data link to be tested and the expected data link. For example, the training sequence can be a regular signal sequence such as 010101 or 101010, so as to ensure that there is only a phase difference between the test data and the expected data input from the first input terminal 210 and the second input terminal 220, and there is no data error. Furthermore, when the test data and the expected data are input into the delay circuit 230, the input delays of the test data and the expected data can be offset.

[0070] As Figure 4 shown, the data comparison module 200 further includes: a comparison circuit 250. Among them, the comparison circuit 250 is connected to the delay circuit 240 and the register module 100, and is used to obtain the configuration parameters transmitted by the register module 100 to configure the comparison parameters of the comparison circuit 250. The comparison parameters include the data bit width, so as to be able to compare the test data and the expected data with different data bit widths. And obtain the third instruction among the multiple control instructions transmitted by the register module 100 and the first threshold parameter among the threshold parameters, so as to perform data comparison on the corrected test data and the corrected expected data output from the delay circuit 240. Among them, in response to the value of the data comparison satisfying the first threshold parameter, a data comparison result is obtained, and then a comparison signal is output.

[0071] In an embodiment, the comparison circuit 250 configures the data bit width to be 6 - 12 bit and the data depth to be 114 - 142 based on the configuration parameters transmitted by the register module 100. For example, the data bit width of the register module 100 is 8 bit and the data depth is 128. Among them, the data bit width and the data depth are used to configure the working mode of the functional modules in the data comparison device 10.

[0072] Figure 5 It is a schematic structural diagram of an embodiment of the comparison circuit provided by this application.

[0073] As Figure 5As shown in the figure, the T-DATA[0]-T-DATA[3] terminals of the comparison circuit 250 are respectively connected to the data output terminals to be tested of the delay circuit 240, and the E-DATA[0]-E-DATA[3] are respectively connected to the expected data output terminals of the delay circuit 240, so as to obtain the data to be tested and the expected data with different data bit widths. The sel[0]-sel[3] terminals of the comparison circuit 250 are connected to the register module 100, and the 1`b0 terminal is connected to the power ground, so as to obtain the configuration parameters transmitted by the register module 100 to configure the data bit width of the comparison circuit 250. The data comparison circuit 250 compares the test data and the expected data output from the delay circuit 240 and obtains the corresponding data comparison result.

[0074] Optionally, if the data comparison result shows that there are different data segments between the corrected test data and the corrected expected data, in response to the different data comparison results, the output of the data comparison circuit 250 is a high-level signal at this time. If the data comparison result shows that the corrected test data and the corrected expected data are exactly the same, in response to the same data comparison results, the output of the data comparison circuit 250 is a low-level signal at this time.

[0075] Please continue to refer to Figure 2 , the data comparison device 10 further includes a signal comparison module 400. The signal comparison module 400 is connected to the comparison circuit 250 (i.e., the output terminal 230 of the data comparison module 200) and the register module 100, so as to receive the second threshold parameter, various control instructions and configuration parameters sent by the register module 100. Furthermore, the signal comparison module 400 can analyze and process the level signal output by the comparison circuit 240 according to the second threshold parameter and obtain the signal comparison result.

[0076] In another embodiment, the output terminal 230 of the data comparison module 200 can input a test signal and an expected signal to the signal comparison module 400. The comparison circuit 250 configures the signal comparison parameters based on the configuration parameters transmitted by the register module 100, and performs the operation of comparing and analyzing the test signal and the expected signal according to the fourth instruction in the various control instructions. In response to the numerical value of the signal comparison satisfying the second threshold parameter in the threshold parameter, the signal comparison result is obtained. Among them, the first threshold parameter obtained by the data comparison module 200 from the register module 100 and the second threshold parameter obtained by the signal comparison module 400 from the register module 100 can be flexibly configured according to the actual application scenario. In this application, the threshold parameters stored in the register module 100 are not specifically limited.

[0077] Figure 6 is a schematic structural diagram of an embodiment of the signal comparison module provided by the present application.

[0078] As Figure 6As shown, the signal comparison module 400 includes: a counter 410 and a sampler 420. Among them, the counter 410 is connected to the storage module 100, and is used to obtain the configuration parameters of the storage module 100, and configure the counting depth of the counter 410 based on the configuration parameters, so that the counter 410 can count according to the counting depth to obtain a count value. Among them, the signal comparison parameters of the signal comparison module 400 include the counting depth.

[0079] The sampler 420 is connected to the storage module 100, the data comparison module 200, and the counter 410, and is used to obtain the comparison result signal output by the data comparison module 200, and according to the signal corresponding to the data comparison result output by the data comparison module 200, execute sampling of the count value of the counter 410 at the corresponding moment according to the fifth instruction in a variety of control instructions, so as to determine the duration when the signals corresponding to different data comparison results are output by the data comparison module 200.

[0080] Optionally, the counter 410 is a cyclic counter, and its configuration depth can be configured by receiving the corresponding configuration parameters sent by the storage module 100. For example, the depth of the counter 410 can be configured as 8, 10, 16, etc., and no specific limitation is made in this application. The counting method of the counter 410 is cyclic counting, that is, the counter 410 starts counting from the starting count value 1, and completes a cycle of counting when it reaches the last count value of its depth. The sampler 420 is a numerical sampler, and is used to count at the corresponding moment according to the signal corresponding to the data comparison result to obtain the corresponding count value.

[0081] When the data comparison device 10 is working, the counter 410 receives the corresponding configuration parameters sent by the storage module 100, and configures its counting depth to 16 according to the configuration parameters. The sampler 420 receives the output result (i.e., the level signal) of the data comparison module 200. When the data comparison module 200 outputs a high-level signal, the sampler 420 starts sampling, and when the data comparison module 200 outputs a low-level signal, the sampler 420 stops sampling. Among them, the sampling values of the sampler 420 include the first count value of the counter 410 when the data comparison module 200 outputs different data comparison results (i.e., the test signal and the expected signal are different), the second count value of the counter 410 when the data comparison module 200 outputs the same data comparison result (i.e., the test signal and the expected signal are restored to be the same), and the count value between the different and restored same comparison results output by the data comparison module 200. If the number of counts between the first count value and the second count value is within the number of counts corresponding to the threshold parameter, the signal comparison result obtained by the signal comparison module 400 is that the test data comparison is the same. If the number of counts between the first count value and the second count value is outside the number of counts corresponding to the threshold parameter, the signal comparison result obtained by the signal comparison module 400 is that the test data comparison is different.

[0082] Please continue to refer to Figure 6 Figure 6 , the signal comparison module 400 further includes: an overflow judgment circuit 430 and a comparator 440. Optionally, the overflow judgment circuit 430 is connected to the register module 100, the data comparison module 200, and the counter 410, and is configured to receive the corresponding comparison result sent by the data comparison module 200, and execute the operation of obtaining the judgment starting point of the data comparison module 200 according to the sixth instruction among the multiple control instructions transmitted by the register module 100, and monitor in real time whether the count value of the counter 410 overflows according to the judgment starting point, so as to generate a judgment signal.

[0083] Specifically, if the first count value and the second count value of the counter 410 are within the same counting cycle, the overflow judgment circuit 430 responds to the first count value and the second count value being valid values, and determines that the count value does not overflow. At this time, the obtained judgment signal is the corresponding non-overflow signal. If the first count value and the second count value of the counter 410 are not within the same counting cycle, the overflow judgment circuit 430 responds to the first count value and the second count value being invalid values, and determines that the count value overflows. At this time, the obtained judgment signal is the corresponding overflow signal. Among them, when the output of the data comparison module 200 is at a high level, the overflow judgment circuit 430 records the count value of the counter 410 at this time, and before the output of the data comparison module 200 becomes low, the overflow judgment circuit 430 compares the count values of all counters 410 in each clock cycle with the count value it records. If the count value of the counter 410 is equal to the recorded count value, it is determined to overflow. If the count value of the counter 410 is not equal to the recorded count value, this overflow judgment ends, and the judgment result is non-overflow.

[0084] Optionally, the comparator 440 is respectively connected to the overflow judgment circuit 430, the register module 100, and the sampler 420, and is configured to execute the operation of determining the number of counts corresponding to the count value of the counter 410 during the duration when the data comparison results are different by using the judgment signal transmitted by the overflow judgment circuit 430 according to the seventh instruction among the multiple control instructions transmitted by the register module 100, so as to determine whether the number of counts between the first count value and the second count value sampled by the sampler 420 corresponding to the duration when the data comparison module 200 outputs different data comparison results is greater than the second threshold parameter in the threshold parameter. If it responds that the number of counts satisfies being greater than the second threshold parameter, the corresponding signal comparison result is obtained, that is, the test result of the chip to be tested.

[0085] Among them, within the duration when the data comparison results are different, if the number of counts of the counter 410 corresponding to the first count value and the second count value is not greater than the second threshold parameter, the test result is that the test signals are compared as the same; within the duration when the data comparison results are different, if the number of counts of the counter 410 corresponding to the first count value and the second count value is greater than the threshold parameter, the test result is that the test signals are compared as different.

[0086] Optionally, the comparator 440 is connected to the external device 20. When the comparator 440 obtains the test result, it is used to output a judgment signal, the compared test signal, the compared expected signal, the signal comparison result, the first count value sampled by the sampler 420 (i.e., the count value of the counter 410 when the test signal and the expected signal are different), and the second count value (i.e., the count value of the counter 410 when the test signal and the expected signal return to be the same), as well as the count difference between the first count value and the second count value to the external device 20. In another embodiment, the comparator 440 may only output a judgment signal to the external device 20.

[0087] Please continue to refer to Figure 2 , the data comparison device 10 further includes a clock input module 500. The clock input module 500 is connected to the signal comparison module 400 and the register module 100, and is used to receive the configuration parameters sent by the register module 100, so as to be able to configure the frequency of its clock input according to the configuration parameters, and then execute the operation of outputting a clock signal with a corresponding clock frequency to the signal comparison module 400 according to the eighth instruction among the multiple control instructions transmitted by the register module 100. Furthermore, the signal comparison module 400 performs real-time signal analysis on the level signal output by the comparison circuit 240 according to the input clock signal, and obtains the corresponding signal comparison result.

[0088] Figure 7 is a schematic structural diagram of an embodiment of the clock input module provided by the present application.

[0089] As Figure 7As shown, the clock input module 500 includes a phase-locked loop 510 and a crystal oscillator 520. Among them, the phase-locked loop 510 is connected to the register module 100, the counter 410, and the sampler 420. The third input terminal 511 of the phase-locked loop 510 is also connected to an external oscillator. In response to the oscillation signal output by the external oscillator, the third input terminal 511 receives the oscillation signal emitted by the external oscillator, configures the output clock frequency using the configuration parameters transmitted by the register module 100, and according to the ninth instruction among multiple control instructions, performs the operation of converting the clock signal output by the external oscillator into a first clock signal and transmitting the first clock signal to the counter 410 and the sampler 420, so as to adjust the counting accuracy of the counter 410 and the sampling frequency of the sampler 420. The crystal oscillator 520 is connected to the fourth input terminal 512 of the phase-locked loop 510, and is configured to, when the external oscillator does not output a clock signal to the phase-locked loop 510, according to the tenth instruction among multiple control instructions, perform the operation of outputting a second clock signal to the phase-locked loop 510. Furthermore, the phase-locked loop 510 can convert the second clock signal into a first clock signal to correspondingly adjust the counting accuracy of the counter 410 and the sampling frequency of the sampler 420.

[0090] In one embodiment, the external oscillator oscillates to generate an oscillation signal with a corresponding frequency. The phase-locked loop 510 receives the oscillation signal through the third input terminal 511, configures its own clock frequency using the configuration parameters of the obtained register module 100, then converts the clock signal generated by the oscillation of the external oscillator into a first clock signal, and transmits the first clock signal to the signal comparison module 400. The counter 410 receives the first clock signal and performs a counting process with a corresponding counting accuracy according to the first clock signal. The sampler 420 receives the first clock signal and performs a sampling process with a corresponding sampling frequency according to the first clock signal.

[0091] In another embodiment, when the external oscillator does not oscillate and thus does not generate a corresponding clock signal, the phase-locked loop 510 receives the second clock signal emitted by the crystal oscillator through the fourth input terminal 512, configures its own clock frequency using the configuration parameters of the obtained register module 100, then can convert the second clock signal into a first clock signal, and transmits the first clock signal to the signal comparison module 400. The counter 410 receives the first clock signal and performs a counting process with a corresponding counting accuracy according to the first clock signal. The sampler 420 receives the first clock signal and performs a sampling process with a corresponding sampling frequency according to the first clock signal.

[0092] Optionally, the higher the clock frequency of the first clock signal, the higher the counting accuracy of the counter 410 and the sampling frequency of the sampler 420, and thus the higher the accuracy of signal comparison. In this application, the clock frequency of the first clock signal can be configured according to the actual application scenario through the configuration parameters of the register module 100, and the numerical value of the clock frequency of the first clock signal is not specifically limited here.

[0093] Different from the prior art, the solution of the present application provides a data comparison device, which includes a storage module, a data comparison module, a signal comparison module, and a clock input module. Among them, the storage module stores threshold parameters for comparing two data chains. The data comparison module is connected to the storage module, the chip under test, and the host computer to input test data and expected data in real time, and perform real-time data comparison on the test data and the expected data according to the threshold parameters to obtain the compared test signal, the compared expected signal, and their corresponding data comparison results. Then, the compared test signal, the compared expected signal, and / or the corresponding level signal are input into the signal comparison module, and the first count value when the test signal and the expected signal are different, the second count value when they return to the same, and the corresponding judgment signal are obtained through a counter, an overflow judgment circuit, and a sampler. Furthermore, the comparator can compare the corresponding signal comparison result according to the threshold parameters. Thus, the data comparison device can compare the test data and the expected data in real time, ensuring the real-time nature of chip testing and improving the efficiency of chip testing. In addition, each functional module in the data comparison device can receive the corresponding configuration parameters sent by the storage module for corresponding settings, and adjust the clock frequency of the phase-locked loop or crystal oscillator in the clock input module, so as to adjust the counting accuracy of the counter and the sampling frequency of the sampler, and then adjust the comparison accuracy of the signal comparison module. Therefore, the data comparison device can implement configurable comparison data to obtain comparison results with different comparison accuracies.

[0094] Figure 8 It is a schematic flowchart of the first embodiment of the data comparison method provided by the present application.

[0095] Among them, the data comparison method in this embodiment is applied to the data comparison device as described above.

[0096] Step 11: Obtain test data and expected data.

[0097] Specifically, the data comparison device receives the expected data from an external device and the test data from a chip testing device.

[0098] Optionally, the external device can be a host computer, where the host computer is configured with preset expected data. The preset expected data can be set according to the requirements of data comparison (such as the accuracy and timeliness of data comparison).

[0099] Optionally, the chip testing device is connected to a chip to be tested, which is a wafer that has not been diced and packaged. There are thousands of unpackaged chips regularly distributed on the wafer. The chips on the wafer can be probed through the probes on the chip testing device, so as to output various signals inside the chips, enabling the data comparison device to receive the test data input by the chip testing device in real time.

[0100] Step 12: Compare the test data with the expected data to obtain a data comparison result; wherein, the data comparison result includes a test signal and an expected signal.

[0101] Refer to Figure 9 , Figure 9 which is a schematic flowchart of an embodiment of step 12 of the present application. Step 12 specifically includes the following:

[0102] Step 121: Calibrate the input delays of the test data and the expected data to obtain the calibrated test data and the calibrated expected data.

[0103] Specifically, the data comparison device configures its delay parameters according to the stored configuration parameters, and calibrates the input delays of the test data and the expected data according to the delay parameters, thereby offsetting the input delays of the two data links to obtain the calibrated test data and the calibrated expected data. Optionally, the configuration parameters are stored in the register module of the data comparison device. The register module is the same as that in the above embodiment and will not be elaborated here.

[0104] Step 122: Compare the calibrated test data and the calibrated expected data, and in response to the numerical value of the data comparison satisfying the threshold parameter, obtain a data comparison result.

[0105] Specifically, the data comparison device executes the instruction to compare the calibrated test data and the calibrated expected data, and according to the stored first threshold parameter, determines that when the numerical value of the data comparison is greater than the first threshold parameter, a data comparison result is obtained, and then a comparison signal is output.

[0106] Optionally, if the data comparison result shows that there are different data segments between the calibrated test data and the calibrated expected data, in response to the different data comparison results, the data comparison circuit 250 outputs a high-level signal at this time. If the data comparison result shows that the calibrated test data and the calibrated expected data are exactly the same, in response to the same data comparison results, the data comparison circuit 250 outputs a low-level signal at this time.

[0107] Optionally, before comparing the calibrated test data and the calibrated expected data, it further includes:

[0108] Compare a training sequence to correct the frequency deviation between the signal to be measured and the expected signal.

[0109] Specifically, the data comparison device first obtains a pair of training sequences from an external device and performs data comparison on the pair of training sequences to correct the delay deviation between the data link to be tested and the expected data link. For example, the training sequence can be a regular signal sequence such as 010101 or 101010, etc., so as to ensure that when the data comparison device compares the data to be tested and the expected data, there is only a phase difference and no data error. Furthermore, the data comparison device then corrects the data to be tested and the expected data to offset the input delay of the data to be tested and the expected data.

[0110] Step 13: Compare the test signal with the expected signal to obtain a signal comparison result.

[0111] Refer to Figure 10 , Figure 10 is a schematic flowchart of an embodiment of step 13 of the present application. Step 13 specifically includes the following:

[0112] Step 131: Perform counting according to a pre-designed counting depth to obtain a count value.

[0113] Specifically, during the process of the data comparison device comparing the test signal with the expected signal, the data comparison device performs counting according to the pre-designed counting depth to obtain the count value during the signal comparison process. Among them, the pre-designed counting depth can be configured as 8, 10, 16, etc., which is not specifically limited in the present application. The counting method is cyclic counting, that is, starting from the starting count value 1, counting is completed when reaching the last count value of its depth to complete a cycle of counting.

[0114] Step 132: Sample the count value and determine the duration when the data comparison results are different.

[0115] Specifically, when it is determined that the data comparison results are different, the data comparison device starts to collect the count value. When it is determined that the data comparison results return to the same, the data comparison device stops collecting the count value. The collected count value can be used to determine the duration when the data comparison results are different.

[0116] Step 133: Obtain the judgment starting point during data comparison and determine whether the count value overflows according to the judgment starting point to generate a judgment signal.

[0117] Specifically, the first count value collected by the data comparison device is the judgment starting point, and the last count value collected by the data comparison device is the judgment ending point. If the judgment starting point and the judgment ending point are within the same counting cycle, in response to the judgment starting point and the judgment ending point being valid values and determining that the count value has not overflowed, the obtained judgment signal is the corresponding non-overflow signal at this time. If the judgment starting point and the judgment ending point are not within the same counting cycle, in response to the judgment starting point and the judgment ending point being invalid values and determining that the count value has overflowed, the obtained judgment signal is the corresponding overflow signal at this time.

[0118] Step 134: According to the judgment signal, determine the number of counts corresponding to the count value within the duration.

[0119] Step 135: In response to the number of counts meeting the preset threshold parameter, obtain the signal comparison result.

[0120] Specifically, in response to the number of counts corresponding to the count value within the duration being not greater than the threshold parameter, the signal comparison result is that the test data is compared as the same; in response to the number of counts corresponding to the count value within the duration being greater than the threshold parameter, the signal comparison result is that the test data is compared as different.

[0121] Optionally, the threshold parameter is the second threshold parameter stored in the data comparison device, which can be flexibly configured according to the actual application scenario, and the threshold parameter stored in the data comparison device in this application is not specifically limited.

[0122] Refer to Figure 11 , Figure 11 is the schematic flowchart of the second embodiment of the data comparison method provided by this application.

[0123] Step a1: Obtain the first clock signal input by a phase-locked loop.

[0124] Specifically, the data comparison device is connected to the phase-locked loop and obtains the first clock signal input by the phase-locked loop in real time. Optionally, the phase-locked loop is also connected to an external oscillator. Among them, in response to the external oscillator outputting an oscillation signal, the phase-locked loop receives the oscillation signal sent by the external oscillator, configures the output clock frequency using its own stored configuration parameters, converts the clock signal output by the external oscillator into the first clock signal, and transmits the first clock signal to the data comparison device.

[0125] Step a2: Based on the first clock signal, adjust the counting accuracy and sampling frequency.

[0126] Specifically, the data comparison device adjusts the counting accuracy and sampling frequency according to the first clock signal. For example, adjust from a counting depth of 16 to 24; and adjust from a sampling frequency of 500 ms to 100 ms.

[0127] Refer toFigure 12 , Figure 12 is a schematic flowchart of the third embodiment of the data comparison method provided by this application.

[0128] Step b1: Obtain a second clock signal input by a crystal oscillator.

[0129] Specifically, the data comparison device is connected to the crystal oscillator, and the crystal oscillator is configured to output the second clock signal to the phase-locked loop when the external oscillator does not output a clock signal to the phase-locked loop, and the phase-locked loop transmits the second clock signal to the data comparison device.

[0130] Step b2: Adjust the counting accuracy and sampling frequency based on the second clock signal.

[0131] Specifically, the data comparison device adjusts the counting accuracy and sampling frequency according to the second clock signal.

[0132] Optionally, in other embodiments, the phase-locked loop can convert the received second clock signal into a first clock signal and transmit the second clock signal to the data comparison device to adjust the counting accuracy of the counter and the sampling frequency of the sampler.

[0133] Refer to Figure 13 , Figure 13 is a schematic flowchart of the fourth embodiment of the data comparison method provided by this application.

[0134] Step c1: Obtain function parameters and mode signals input by a host computer.

[0135] Specifically, the data comparison device is connected to the host computer through a communication interface and receives the function parameters and mode signals transmitted by the host computer. Among them, the function parameters include threshold parameters, configuration parameters, and various control instructions. The threshold parameters include the first threshold parameter and the second threshold parameter in the above embodiments. The first threshold parameter is used for the data comparison process, and the second threshold parameter is used for the signal comparison process; the various control instructions are used to control the data comparison device and the clock module to perform the data comparison and signal comparison processes.

[0136] Among them, the communication interface includes an SPI interface (Serial Peripheral Interface), an I2C interface (INTER-IC, serial bus interface), and a JTAG interface (Joint Test Action Group interface), etc., for connecting different communication protocols and configuring different working modes.

[0137] Step c2: Store the function parameters and convert to the corresponding test mode according to the mode signal.

[0138] Figure 14It is a schematic structural diagram of an embodiment of the chip tester provided by the present application.

[0139] The present application also provides another technical solution, including providing a chip tester 40. As Figure 14 shown, the chip tester 40 includes: a chip testing device 50 and a data comparison device 10. Among them, the chip testing device 50 tests the chip to be tested to obtain test data. The data comparison device 10 is connected to the chip testing device 50, and is used to obtain the data to be tested, and apply the data comparison method to perform data comparison and signal comparison on the test data to obtain a data comparison result and a signal comparison result. Among them, the data comparison device 10 is the same as the above embodiment.

[0140] When the chip tester 40 is working, the chip tester 40 inputs the data to be tested to the data comparison device 10, and an external device inputs the expected data to the data comparison device 10. The data comparison device 10 compares the test data and the expected data to obtain a data comparison result. The data comparison device 10 compares the test signal corresponding to the data comparison result and the expected signal according to the data comparison result to obtain a signal comparison result.

[0141] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the description and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A data comparison device, characterized in that, the data comparison device includes: a data comparison module, the data comparison module includes a first input end and an output end; the first input end is used to connect to a chip test device, the chip test device is used to test a chip to be tested and output test data of the chip to be tested, and the first input end is configured to receive the test data from the chip test device; wherein, in response to the chip test device outputting the test data, the first input end receives the test data and compares the test data with expected data to obtain a data comparison result; the data comparison result includes a test signal and an expected signal; the data comparison device further includes: a signal comparison module, connected to the output end and a storage module, and configured to receive the test signal and the expected signal output by the data comparison module from the output end; the signal comparison module configures signal comparison parameters based on configuration parameters, and according to a fourth instruction among multiple control instructions, performs an operation of comparing the test signal with the expected signal, and in response to the value of the signal comparison satisfying a threshold parameter, obtains a signal comparison result; wherein, the signal comparison parameters include a counting depth; the signal comparison module includes: a counter, connected to the storage module, the counter configures the counting depth based on the configuration parameters and counts according to the counting depth to obtain a count value; a sampler, connected to the storage module, the data comparison module and the counter, the sampler performs an operation of sampling the count value according to a fifth instruction among the multiple control instructions and determining the duration when the data comparison results are different; the signal comparison module includes: an overflow judgment circuit, connected to the data comparison module, the storage module and the counter, the overflow judgment circuit performs an operation of obtaining a judgment starting point of the data comparison module according to a sixth instruction among the multiple control instructions and determining whether the count value overflows according to the judgment starting point to generate a judgment signal; the signal comparison module includes: a comparator, connected to the storage module, the sampler and the overflow judgment circuit, the comparator performs an operation of using the judgment signal to determine the number of counts corresponding to the count value within the duration according to a seventh instruction among the multiple control instructions, and in response to the number of counts satisfying the threshold parameter, obtains the signal comparison result; wherein, in response to the number of counts corresponding to the count value within the duration not being greater than the threshold parameter, the signal comparison result is that the test data is the same; in response to the number of counts corresponding to the count value within the duration being greater than the threshold parameter, the signal comparison result is that the test data is different.

2. The data comparison device according to claim 1, characterized in that, the storage module stores function parameters; the data comparison module compares the test data with the expected data based on the function parameters to obtain a data comparison result.

3. The data comparison device according to claim 2, wherein, the function parameters include threshold parameters, configuration parameters, and multiple control instructions; the data comparison module configures data comparison parameters based on the configuration parameters, and according to the first instruction among the multiple control instructions, performs an operation of comparing the test data with the expected data, and obtains the data comparison result in response to the numerical value of the data comparison satisfying the threshold parameter; wherein, the data comparison parameters include a delay parameter and a comparison parameter.

4. The data comparison device according to claim 3, wherein, the data comparison module includes: a delay circuit, connected to the storage module, the delay circuit configures the delay parameter based on the configuration parameter, and corrects the input delays of the test data and the expected data according to the second instruction among the multiple control instructions to obtain corrected test data and corrected expected data; a comparison circuit, connected to the delay circuit and the storage module, the comparison circuit configures the comparison parameter based on the configuration parameter, and according to the third instruction among the multiple control instructions, performs an operation of comparing the corrected test data with the corrected expected data, and obtains the data comparison result in response to the numerical value of the data comparison satisfying the threshold parameter.

5. The data comparison device according to claim 4, wherein, the comparison circuit configures the comparison parameter based on the configuration parameter, including: the comparison circuit configures the data bit width of the comparison circuit according to the configuration parameter.

6. The data comparison device according to claim 3, wherein, the data comparison device further includes: a communication interface, connected to the storage module and an external device, for receiving a communication signal input by the external device and converting it to form the threshold parameter, the configuration parameter, and the multiple control instructions.

7. The data comparison device according to claim 1, wherein, the data comparison device further includes: a clock input module, connected to the signal comparison module and the storage module, configured to input a clock signal to the signal comparison module; the clock input module configures clock parameters based on the configuration parameter, and according to the eighth instruction among the multiple control instructions, performs an operation of inputting a clock signal to the signal comparison module.

8. The data comparison device according to claim 7, wherein, the clock input module includes: a phase-locked loop, connected to the storage module, the counter, and the sampler, a third input terminal of the phase-locked loop is connected to an external oscillator; wherein, in response to the external oscillator outputting an oscillation signal, the third input terminal receives the oscillation signal; the phase-locked loop configures clock parameters based on the configuration parameter, and according to the ninth instruction among the multiple control instructions, performs an operation of converting the oscillation signal into a first clock signal and transmitting the first clock signal to the counter and the sampler to adjust the counting accuracy of the counter and the sampling frequency of the sampler.

9. The data comparison device according to claim 8, wherein, The clock input module includes: A crystal oscillator, connected to the fourth input terminal of the phase-locked loop, and configured to, when the external oscillator has no output, perform an operation of outputting a second clock signal to the phase-locked loop according to the tenth instruction among the multiple control instructions, so as to correspondingly adjust the counting accuracy of the counter and the sampling frequency of the sampler.

10. A data comparison method Characterized in that The data comparison method includes: Obtaining test data and expected data; Performing data comparison on the test data and the expected data to obtain a data comparison result; wherein, the data comparison result includes a test signal and an expected signal; Performing signal comparison on the test signal and the expected signal to obtain a signal comparison result; The performing signal comparison on the test signal and the expected signal to obtain a signal comparison result includes: Performing counting according to a preset counting depth to obtain a count value; Sampling the count value and determining the duration when the data comparison results are different; Obtaining a judgment starting point during the data comparison and determining whether the count value overflows according to the judgment starting point to generate a judgment signal; According to the judgment signal, determining the number of counts corresponding to the count value within the duration; Responding to the number of counts meeting a preset threshold parameter to obtain the signal comparison result; Wherein, in response to the number of counts corresponding to the count value within the duration being not greater than the threshold parameter, the signal comparison result is that the test data is compared as the same; In response to the number of counts corresponding to the count value within the duration being greater than the threshold parameter, the signal comparison result is that the test data is compared as different.

11. The data comparison method according to claim 10 Characterized in that The performing data comparison on the test data and the expected data to obtain a data comparison result includes: Calibrating the input delays of the test data and the expected data to obtain calibrated test data and calibrated expected data; Comparing the calibrated test data and the calibrated expected data, and in response to the numerical values of the data comparison meeting the threshold parameter, obtaining the data comparison result.

12. The data comparison method according to claim 11 Characterized in that Before comparing the calibrated test data and the calibrated expected data, it further includes: Comparing a training sequence to correct the frequency deviation between the test signal and the expected signal.

13. The data comparison method according to claim 10 Characterized in that The method further includes: Obtaining a first clock signal input by a phase-locked loop; Based on the first clock signal, adjusting the counting accuracy and the sampling frequency.

14. The data comparison method according to claim 10 Characterized in that The method further includes: Obtaining a second clock signal input by a crystal oscillator; Based on the second clock signal, adjusting the counting accuracy and the sampling frequency.

15. The data comparison method according to claim 10 Characterized in that The method further includes: Obtain the function parameters and mode signals input by a host computer; Store the function parameters and convert them into corresponding test modes according to the mode signals.

16. A chip tester, the chip tester comprises: A chip test device for testing a chip to be tested to obtain test data; A data comparison device connected to the chip test device, applying a data comparison method to compare the test data to obtain a data comparison result; wherein, the data comparison device is the data comparison device according to any one of claims 1-9; the data comparison method is obtained by the data comparison method according to any one of claims 10-15.

Images