A method and router for clock synchronization, validation circuit devices

Abstract

The present specification provides a method for clock synchronization, verification circuit device and router, the method comprises: obtaining the first clock signal sent by CPU, sending the first clock signal to system complex programmable logic device (CPLD) and service complex programmable logic device (CPLD) through clock buffer (Buffer). Through the method, the clock synchronization of system CPLD and service CPLD can be ensured.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of communication technology, and in particular to a method for clock synchronization and verification of a circuit device and a router. BACKGROUND

[0002] The CPU of the X86 server architecture generally has a relatively large number of peripheral interfaces, such as PCIE, USB, SPI, LPC, SATA, Ethernet, etc., and can support a large number of external devices. In a single board of a high-density and high-complexity operator backbone network level router, due to the complexity of functions and the large number of peripherals, a plurality of CPLDs are often used as adhesion logic to manage and monitor the peripherals of the single board. At the same time, the collected information is uniformly sent to the CPU for processing. The communication between the CPU and the CPLD is generally implemented by using a parallel localbus bus. However, the X86 CPU does not have a localbus bus, so a CPLD needs to be used as a dedicated decoding CPLD (which can be referred to as SYS_CPLD, i.e., system CPLD) to perform decoding operation on the LPC bus of the CPU inside the SYS_CPLD to convert it into a localbus bus, and perform localbus communication with a plurality of downstream peripheral CPLDs (i.e., business CPLD). SUMMARY

[0003] The present disclosure provides a method for clock synchronization and verification of a circuit device and a router, which can ensure the clock synchronization of the system CPLD and the business CPLD.

[0004] The present disclosure provides a method for clock synchronization, which comprises the following steps:

[0005] obtaining a first clock signal sent by a CPU;

[0006] sending the first clock signal to a system complex programmable logic device (CPLD) and a business complex programmable logic device (CPLD) through a clock buffer Buffer;

[0007] The system complex programmable logic device (CPLD) is used to perform LPC bus to localbus bus decoding of each business CPLD.

[0008] Through the method, the clock synchronization of the system CPLD and the business CPLD can be ensured.

[0009] The embodiment of the present disclosure further provides a method for verifying a circuit device, the circuit device comprising a CPU, a system CPLD, a service CPLD and a clock buffer Buffer, the CPU sending a clock signal to the system CPLD and the service CPLD through the clock buffer Buffer, wherein the system CPLD is used for performing LPC bus to local bus decoding of each service CPLD.

[0010] Obtaining clock delay difference information of the service CPLD relative to the system CPLD for obtaining the clock signal from the clock buffer Buffer.

[0011] Obtaining data wire delay information of the service CPLD for receiving the data signal sent by the system CPLD.

[0012] Determining whether the sum of the clock delay difference information, the data wire delay information, a clock output delay Tco and a clock setup time Tsu is less than a clock period.

[0013] If the sum is less than the clock period, it is determined that the circuit device meets the bus communication requirement, and if the sum is greater than the clock period, it is determined that the circuit device does not meet the bus communication requirement.

[0014] The method can guide the wiring design of PCB development to meet the requirement of bus communication.

[0015] The clock delay difference information of the service CPLD relative to the system CPLD for obtaining the clock signal from the clock buffer Buffer comprises the following steps.

[0016] Obtaining the PCB wire delay difference of the service CPLD relative to the system CPLD for obtaining the clock signal from the clock buffer Buffer, and the phase deviation of the clock signal output by the clock buffer Buffer.

[0017] Determining the clock delay difference information of the clock signal according to the PCB wire delay difference of the clock signal and the phase deviation of the clock signal.

[0018] The data wire delay information of the service CPLD for receiving the data signal sent by the system CPLD comprises the following steps.

[0019] Obtaining the PCB data wire delay information of the service CPLD for receiving the data signal sent by the system CPLD, and taking the PCB data wire delay information as the data wire delay information.

[0020] The embodiment of the present disclosure further provides a circuit device, which comprises a CPU, a system CPLD, a service CPLD and a clock buffer Buffer, wherein the system CPLD is used for performing LPC bus to local bus decoding of each service CPLD.

[0021] The clock buffer Buffer is connected with the CPU at one end and connected with the system CPLD and the service CPLD at the other end respectively;

[0022] The first clock signal sent by the CPU is acquired;

[0023] The first clock signal is sent to the system CPLD and the service CPLD through the clock buffer Buffer.

[0024] The circuit device provided by the embodiment of the present disclosure comprises a CPU, a system CPLD, a service CPLD and a clock buffer Buffer, wherein the CPU sends a clock signal to the system CPLD and the service CPLD through the clock buffer Buffer, the system CPLD is used for performing LPC bus to localbus bus decoding of each service CPLD, and the circuit device further comprises:

[0025] The acquisition module is used for acquiring clock time delay difference information of the service CPLD relative to the system CPLD for acquiring the clock signal from the clock buffer Buffer;

[0026] The acquisition module is further used for acquiring data line time delay information of the service CPLD for receiving the data signal sent by the system CPLD;

[0027] The judgment module is used for judging whether the sum of the clock time delay difference information, the data line time delay information, the clock output time delay Tco and the clock establishment time Tsu is less than a clock period;

[0028] The judgment module is further used for judging that if the sum is less than the clock period, it is determined that the circuit device meets the bus communication requirement, and if the sum is greater than the clock period, it is determined that the circuit device does not meet the bus communication requirement.

[0029] The acquisition module is specifically used for acquiring a PCB line time delay difference of the service CPLD relative to the system CPLD for acquiring the clock signal from the clock buffer Buffer and a phase deviation of the clock signal output by the clock buffer Buffer.

[0030] The clock time delay difference information of the clock signal is determined according to the PCB line time delay difference of the clock signal and the phase deviation of the clock signal.

[0031] The acquisition module is specifically used for acquiring PCB data line time delay information of the service CPLD for receiving the data signal sent by the system CPLD, and the PCB data line time delay information is used as the data line time delay information.

[0032] The embodiment of the present disclosure further provides a router, wherein the router is configured with the circuit device in any of the above-mentioned embodiments.

[0033] The embodiment of the present disclosure further provides a router, which comprises a memory, a processor and a program stored in the memory and capable of running on the processor, and the program implements the method steps in any of the above-mentioned embodiments when executed by the processor. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present specification and serve to explain the principles of the present specification.

[0035] Figure 1 A logic schematic diagram of a circuit device provided by the embodiment of the present disclosure.

[0036] Figure 2 A flowchart of a clock synchronization method provided by the embodiment of the present disclosure.

[0037] Figure 3 A logic schematic diagram of a circuit device provided by the embodiment of the present disclosure.

[0038] Figure 4 A flowchart of a method for verifying a circuit device provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The following description is only exemplary and is not intended to limit the scope, applicability or configuration of the present disclosure. Rather, the exemplary embodiments are presented as illustration of the principles of the present disclosure and the features shown therein are by way of illustration only and are not intended to limit the scope of the claims.

[0040] The terms used in the present specification are merely for the purpose of describing particular embodiments and are not intended to limit the present specification. As used in the present specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0041] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one piece of information from another piece of information of the same type. For example, without departing from the scope of the present specification, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining".

[0042] In the embodiment, the LPC bus includes an address data multiplexing signal LAD[3:0], a bus 33Mhz clock LCLK, and the like. When communicating using the LPC, the CPU sends the LCLK clock signal to synchronize the SYS_CPLD device. The SYS_CPLD internally uses the LCLK as a reference clock to perform LPC-localbus decoding operations.

[0043] As shown in Figure 1 In an embodiment, after receiving the LPC signal sent by the CPU and decoding into the localbus bus, the SYS_CPLD simultaneously sends the address signal Address[11:0] and the data signal [7:0] of the localbus to the N downstream peripheral CPLDs. Each of the peripheral CPLDs has its own independent clock source, which is usually a 25Mhz crystal oscillator. The clock source is used as a reference clock to sample the localbus signal.

[0044] In this embodiment, the SYS_CPLD completes the decoding from the LPC bus of the CPU to the localbus bus of the downstream CPLD. However, since the clock LCLK of the LPC and the clock crystal oscillator of the downstream CPLD are not the same clock, and the frequencies are inconsistent, it is easy to cause communication failures such as data signal sampling errors due to the clock edge not being aligned during the bus communication. At the same time, since the lengths of the wires of the localbus to each downstream CPLD are not equal, the time of the data signal transmitted to each CPLD is also inconsistent, and it is more likely to cause errors due to the data signal not meeting the setup time.

[0045] To solve the above technical problems, the embodiment of the present disclosure provides a clock synchronization method, as shown in Figure 2 The method comprises the following steps:

[0046] S201 acquiring a first clock signal sent by a CPU;

[0047] S202 sending the first clock signal to a system complex programmable logic device (CPLD) and a service complex programmable logic device (CPLD) through a clock buffer;

[0048] The system complex programmable logic device (CPLD) is used to perform LPC bus to local bus decoding of each service CPLD.

[0049] In combination Figure 3 As shown in the figure, the CPU (i.e. X86 CPU) is connected with the system CPLD and each service CPLD through a clock buffer Buffer (hereinafter referred to as ClockBuffer or Buffer), the Buffer receives a first clock signal from the CPU and sends it to the system CPLD and each service CPLD in parallel.

[0050] That is, the Buffer copies the input clock signal into multiple identical clock signals and outputs them to the system CPLD and each service CPLD, which are used as the logic reference clock of the system CPLD and each service CPLD, so that the system CPLD and each service CPLD have the same frequency of the same source clock, and the possibility of clock edge alignment is guaranteed in frequency.

[0051] The inventor found in the related experiments that, in order to avoid the problem of abnormal bus communication, the data setup time and hold time of the device should be met when designing the circuit device. The setup time refers to the time when the data is stable before the rising edge of the clock signal of the flip-flop arrives, if the setup time is not enough, the data cannot be punched into the flip-flop at this clock rising edge; the hold time refers to the time when the data is stable after the rising edge of the clock signal of the flip-flop arrives, if the hold time is not enough, the data cannot be punched into the flip-flop.

[0052] In order to guarantee the clock synchronization, in addition to the frequency synchronization, the synchronization of the clock phase is also needed. That is, to guarantee that the data signal meets the setup time requirement when it arrives at each CPLD (service CPLD and system CPLD). Due to the difference in the layout and wiring of the devices on the board, the lengths of the lines of each output clock of the clock buffer Buffer to each CPLD are inconsistent; and the lengths of the lines of the local bus to each service CPLD are also inconsistent. Moreover, due to the internal manufacturing process of the device, the phases of each output clock of the clock buffer Buffer cannot be consistent. Therefore, the time of each CLK clock edge to each CPLD cannot be guaranteed to be the same. In order to guarantee the normal local bus communication of each service CPLD, a method for verifying the length of the PCB line is needed to realize the synchronization of the clock phase, and then to meet the setup time and hold time requirement of the local bus communication.

[0053] Based on the above description, the disclosure embodiment further provides a method for verifying the circuit device, like Figure 4As shown, the circuit device includes a CPU, a system CPLD, a service CPLD and a clock buffer Buffer, the CPU sends a clock signal to the system CPLD and the service CPLD through the clock buffer Buffer, wherein the system CPLD is used to perform LPC bus to localbus bus decoding of each service CPLD;

[0054] S401 acquiring clock delay difference information of the service CPLD relative to the system CPLD from the clock buffer Buffer;

[0055] S402 acquiring data line delay information of the service CPLD receiving data signals sent by the system CPLD;

[0056] S403 judging whether the sum of the clock delay difference information, the data line delay information, the clock output delay Tco and the clock setup time Tsu is less than a clock period;

[0057] S404 if less than the clock period, determining that the circuit device meets the bus communication requirement, and if greater than the clock period, determining that the circuit device does not meet the bus communication requirement.

[0058] In the embodiment, the acquiring of the clock delay difference information of the service CPLD relative to the system CPLD from the clock buffer Buffer includes:

[0059] acquiring a clock signal PCB line delay difference of the service CPLD relative to the system CPLD from the clock buffer Buffer, and a phase deviation of the clock signal output by the clock buffer Buffer;

[0060] determining the clock delay difference information of the clock signal according to the clock signal PCB line delay difference and the phase deviation of the clock signal.

[0061] In step S401, the clock delay difference information=A1 (each clock PCB line delay difference)+A2 (each output phase deviation of the clock buffer). In order to facilitate the description, the clock is set to 33M clock in the embodiment (here, it is not limited to only 33M clock signal, and other frequency clock signals are still applicable).

[0062] That is, the clock delay difference information A=each 33M clock PCB line delay difference A1+each output phase deviation A2 of the clock buffer.

[0063] In step S402, the data line delay information B=PCB data line delay B1.

[0064] For the convenience of understanding, examples are described.

[0065] In this example, the 33M clock from the clock buffer arrives at the service CPLD 1 earlier than the system CPLD by a delay A; while the data signal from the system CPLD decoding needs to go through a flight time delay B to arrive at the service CPLD 1.

[0066] The data signal from the system CPLD decoding is delayed by Tco from the rising edge of the system CPLD clock due to the inherent property of the system CPLD.

[0067] The clock period of the 33M clock is 1 / 33M = 30ns, and the data signal from the system CPLD decoding needs to be stable for the setup time before the next clock rising edge.

[0068] Therefore, A + Tco + B + Tsu < 30ns, where Tsu is the clock setup time, and Tsu > 0 in the general CPLD manual.

[0069] According to A = A1 + A2, B = B1, and A + Tco + B + Tsu < 30ns, we have

[0070] A1 (the difference in the length of the 33M clock PCB traces) + A2 (the difference in the phase of the clock buffer outputs) + Tco + B1 (the length of the PCB data traces) + Tsu < 30ns.

[0071] Generally, the PCB signal transmission rate in FR4 board is about 6 inch / ns. The difference in the phase of the clock buffer outputs is in the order of ps, which can be ignored.

[0072] Tco is about 7.5ns in the general CPLD manual.

[0073] Therefore, A1' (the difference in the length of the 33M clock PCB traces (inch)) / 6ns + 7.5ns + B1' (the length of the PCB data traces (inch)) / 6ns < 30ns.

[0074] The above formula can be simplified to A1' (the difference in the length of the 33M clock PCB traces) + B1' (the length of the PCB data traces) < 135 inch.

[0075] Therefore, when designing a circuit, the relevant parameters can be input into the above formula, and if it is less than 135 inch, it is considered that the designed circuit meets the system requirements, otherwise, if it is greater than 135 inch, it is considered that the designed circuit does not meet the system requirements.

[0076] Based on the above embodiments, the circuit device comprises a CPU, a system CPLD, a service CPLD and a clock buffer Buffer, wherein the system CPLD is configured to perform LPC bus to localbus bus decoding of each service CPLD.

[0077] One end of the clock buffer Buffer is connected with the CPU, and the other end is connected with the system CPLD and the service CPLD respectively.

[0078] The first clock signal sent by the CPU is acquired.

[0079] The first clock signal is sent to the system complex programmable logic device CPLD and the service complex programmable logic device CPLD through the clock buffer Buffer.

[0080] Based on the above embodiments, the circuit device comprises a CPU, a system CPLD, a service CPLD and a clock buffer Buffer, wherein the system CPLD is configured to perform LPC bus to localbus bus decoding of each service CPLD.

[0081] The acquisition module is configured to acquire clock delay difference information of the service CPLD relative to the system CPLD from the clock buffer Buffer.

[0082] The acquisition module is further configured to acquire data line delay information of the service CPLD receiving the data signal sent by the system CPLD.

[0083] The judgment module is configured to judge whether the sum of the clock delay difference information, the data line delay information, the clock output delay Tco and the clock setup time Tsu is less than the clock period.

[0084] The judgment module is further configured to determine that the circuit device meets the bus communication requirement if the sum is less than the clock period, and determine that the circuit device does not meet the bus communication requirement if the sum is greater than the clock period.

[0085] The acquisition module is specifically configured to acquire the PCB line delay difference of the service CPLD relative to the system CPLD from the clock buffer Buffer, and the phase deviation of the clock signal output by the clock buffer Buffer.

[0086] The clock delay difference information of the clock signal is determined according to the PCB line delay difference of the clock signal and the phase deviation of the clock signal.

[0087] The acquisition module is specifically configured to acquire PCB data trace delay information of a data signal received by the service CPLD from the system CPLD, and take the PCB data trace delay information as the data trace delay information.

[0088] The circuit device in any of the above embodiments can be applied to a router.

[0089] The circuit device in any of the above embodiments can be applied to a router.

[0090] In this embodiment, the router can be an X86 server.

[0091] The above describes specific embodiments of the present specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different than the order in which they are recited, and still achieve desirable results. In addition, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0092] Other embodiments of this specification will be readily apparent to those skilled in the art upon considering the specification in its entirety. This specification is intended to cover any variations, uses, or adaptations of the specification following the general principles thereof and including such departures from the present disclosure as come within known use or customary practice in the art to which this specification pertains or relates. The specification and examples are to be considered exemplary only, with the true scope and spirit of the specification being indicated by the following claims.

[0093] It should be understood that the present specification is not limited to the precise structures as set forth above and shown in the attached drawings and that various modifications and changes can be made without departing from the scope thereof. The scope of the present specification is limited only by the claims that follow.

[0094] The above only describes preferred embodiments of the present specification and does not limit the present specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of protection of the present specification.

Claims

1. A method of verifying a circuit device, characterized by, The circuit device includes a CPU, a system CPLD, a service CPLD and a clock buffer Buffer, the CPU sends a clock signal to the system CPLD and the service CPLD through the clock buffer Buffer, wherein the system CPLD is used to execute LPC bus to localbus bus decoding of each service CPLD; obtain clock delay difference information of the service CPLD relative to the system CPLD from the clock buffer Buffer to obtain the clock signal; obtain data trace delay information of the service CPLD receiving the data signal sent by the system CPLD; determine whether the sum of the clock delay difference information, the data trace delay information, a clock output delay Tco and a clock setup time Tsu is less than a clock period; if less than the clock period, determine that the circuit device meets the bus communication requirement, and if greater than the clock period, determine that the circuit device does not meet the bus communication requirement; wherein the obtaining clock delay difference information of the service CPLD relative to the system CPLD from the clock buffer Buffer to obtain the clock signal includes: obtaining PCB trace delay difference of the service CPLD relative to the system CPLD from the clock buffer Buffer to obtain the clock signal, and phase deviation of the clock signal output by the clock buffer Buffer; determining the clock delay difference information of the clock signal according to the PCB trace delay difference of the clock signal and the phase deviation of the clock signal; wherein the obtaining data trace delay information of the service CPLD receiving the data signal sent by the system CPLD includes: obtaining PCB data trace delay information of the service CPLD receiving the data signal sent by the system CPLD, and taking the PCB data trace delay information as the data trace delay information.

2. A circuit device, characterized by, The circuit device includes a CPU, a system CPLD, a service CPLD and a clock buffer Buffer, the CPU sends a clock signal to the system CPLD and the service CPLD through the clock buffer Buffer, wherein the system CPLD is used to execute LPC bus to localbus bus decoding of each service CPLD, and the circuit device further includes: an obtaining module, configured to obtain clock delay difference information of the service CPLD relative to the system CPLD from the clock buffer Buffer to obtain the clock signal; the obtaining module is further configured to obtain data trace delay information of the service CPLD receiving the data signal sent by the system CPLD; a judging module, configured to determine whether the sum of the clock delay difference information, the data trace delay information, a clock output delay Tco and a clock setup time Tsu is less than a clock period; the judging module is further configured to determine that the circuit device meets the bus communication requirement if less than the clock period, and determine that the circuit device does not meet the bus communication requirement if greater than the clock period; wherein the obtaining module is specifically configured to obtain PCB trace delay difference of the service CPLD relative to the system CPLD from the clock buffer Buffer to obtain the clock signal, and phase deviation of the clock signal output by the clock buffer Buffer; The clock delay difference information of the clock signal is determined based on the PCB trace delay difference of the clock signal and the phase deviation of the clock signal; Specifically, the acquisition module is used to acquire the PCB data trace delay information of the data signal sent by the CPLD of the business CPLD receiving system, and to use the PCB data trace delay information as the data trace delay information.

3. A router, characterized in that, The router includes the circuit device as described in claim 2.

4. A router, characterized in that The router includes: a memory, a processor, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the method as described in claim 1.

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