Metal grid support groove manufacturing method and metal grid structure

Abstract

The present invention provides a method for manufacturing support grooves for metal gates. The method comprises providing a substrate, on which first and second device regions are formed, wherein the first device region has multiple first gates, and the second device region has at least one second gate larger than the first gate; etching the second gate to form at least one support groove; forming a first mask layer on the substrate to cover the first and second gates; forming a second mask layer on the substrate to cover the first mask layer so that the support grooves are filled with the second mask layer; etching the second mask layer to remove the second mask layer outside the support grooves; and etching the first mask layer to expose the upper surfaces of the first and second gates. By adding additional support grooves to the large-area gate, the present invention increases the abrasion resistance of the metal gate, thereby ensuring that high-voltage devices can operate normally under the metal gate process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a support groove of a metal gate and a metal gate structure. Background Art

[0002] As the size of transistors continues to shrink, HKMG (including high-k insulating layer and metal gate) gradually replaces the original configuration of silicon dioxide insulating layer and polysilicon gate, becoming an indispensable part of the process below 28nm.

[0003] The metal gate process usually begins with depositing metal using PVD (atomic vapor deposition) or CVD (chemical vapor deposition), and then uses chemical mechanical polishing (CMP) to remove excess metal, leaving the required metal gate portion.

[0004] See also Figure 1 During the chemical mechanical polishing process, different metal gate sizes produce different polishing effects (pattern loading). Oversized metal gates will be polished excessively, resulting in a bowl-shaped structure with a low thickness (dishing). Therefore, in the HKMG process, there are usually certain restrictions on the metal gate size to avoid excessive metal gate area.

[0005] In the high-voltage device manufacturing process, due to the special requirements of high voltage, the metal gate will inevitably have the problem of being too large and the size cannot be limited by design rules.

[0006] To this end, a specially designed metal gate structure is required. By adding additional support grooves in the large-area gate of the high-voltage device, the metal gate's anti-grinding ability is increased, thereby ensuring that the high-voltage device can operate normally under the metal gate process. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for manufacturing a support groove for a metal gate and a metal gate structure, which are used to solve the problem in the prior art that an oversized metal gate will be excessively ground, resulting in a low bowl-shaped thickness. Usually, in the HKMG process, there are certain restrictions on the size of the metal gate to avoid an excessively large metal gate area. However, in the high-voltage device process, due to the special requirements of high voltage, the metal gate will inevitably have a problem of being too large in area, and the size cannot be restricted by design rules.

[0008] To achieve the above-mentioned and other related objectives, the present invention provides a method for manufacturing a support groove of a metal grid, comprising:

[0009] Step 1: providing a substrate, wherein a first device region and a second device region are formed on the substrate, wherein a plurality of first gates are formed in the first device region, and at least one second gate having a size larger than the first gate is formed in the second device region;

[0010] Step 2: etching the second gate to form a supporting groove;

[0011] Step 3: forming a first mask layer covering the first gate and the second gate on the substrate;

[0012] Step 4: forming a second mask layer on the substrate to cover the first mask layer, so that the supporting groove is filled with the second mask layer;

[0013] Step 5: etching the second mask layer to remove the second mask layer except for the portion filled in the supporting groove;

[0014] Step six: Etch the first mask layer to expose the upper surfaces of the first gate and the second gate.

[0015] Preferably, the method further includes step seven, forming an interlayer dielectric layer on the substrate covering the first gate, the second gate, the first mask layer and the second mask layer, and then grinding the interlayer dielectric layer to expose the first gate and the second gate.

[0016] Preferably, the grinding in step seven is chemical mechanical grinding.

[0017] Preferably, the substrate in step 1 is a silicon substrate.

[0018] Preferably, the first device region in step 1 is a low-voltage device region.

[0019] Preferably, the second device region in step 1 is a high-voltage device region.

[0020] Preferably, the first gate and the second gate in step 1 are both metal gates.

[0021] Preferably, the width of the supporting groove in step 2 is smaller than the minimum distance between two adjacent first grid electrodes.

[0022] Preferably, the etching in step 2 is dry etching.

[0023] Preferably, the material of the first mask layer in step three is SiCN.

[0024] Preferably, the material of the second mask layer in step 4 is silicon dioxide.

[0025] Preferably, the etching in step five is wet etching.

[0026] Preferably, the etching in step six is ​​dry etching.

[0027] Preferably, the material of the interlayer dielectric layer in step seven is silicon dioxide.

[0028] A metal gate structure, comprising:

[0029] A substrate having a first device region and a second device region formed thereon, wherein a plurality of first gates are formed in the first device region, and at least one second gate having a size larger than the first gate is formed in the second device region; wherein,

[0030] At least one supporting groove is formed on the second gate;

[0031] A filling layer is formed in the supporting groove.

[0032] Preferably, the substrate is a silicon substrate.

[0033] Preferably, the first device region is a low-voltage device region.

[0034] Preferably, the second device region is a high-voltage device region.

[0035] Preferably, the first gate and the second gate are both metal gates.

[0036] Preferably, the filling layer includes a first mask layer formed on the surface of the supporting groove and a second mask layer filled in the first mask layer.

[0037] Preferably, the material of the first mask layer is SiCN.

[0038] Preferably, the second mask layer is made of silicon dioxide.

[0039] Preferably, the first mask is also formed on side walls of the first gate and the second gate.

[0040] Preferably, an interlayer dielectric layer is formed between the first mask on the sidewalls of the first gate and the second gate.

[0041] Preferably, the material of the interlayer dielectric layer is silicon dioxide.

[0042] Preferably, the width of the supporting groove is smaller than the minimum distance between two adjacent first grids.

[0043] As described above, the metal grid support groove manufacturing method and metal grid structure of the present invention have the following beneficial effects:

[0044] The present invention increases the anti-grinding capability of the metal gate by adding additional supporting grooves in the large-area gate, thereby ensuring that the high-voltage device can work normally under the metal gate process. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Shown is a schematic diagram of a large-size gate after grinding in the prior art;

[0046] Figure 2 Shown is a schematic top view of a substrate structure forming a support groove according to the present invention;

[0047] Figure 3 Shown is a schematic cross-sectional view of a substrate structure forming a support groove according to the present invention;

[0048] Figure 4 Shown is a schematic diagram of forming a first mask layer according to the present invention;

[0049] Figure 5 Shown is a schematic diagram of forming a second mask layer according to the present invention;

[0050] Figure 6 Shown is a schematic diagram of etching the second mask layer according to the present invention;

[0051] Figure 7 Shown is a schematic diagram of forming an interlayer dielectric layer after polishing according to the present invention;

[0052] Figure 8 Shown is a schematic diagram of the process flow of the present invention. DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] See also Figure 8 The present invention provides a method for manufacturing a support groove of a metal grid, comprising:

[0055] Step 1: providing a substrate 10, on which a first device region and a second device region are formed. The first device region is formed with a plurality of first gates 12, and the second device region is formed with at least one second gate 11 having a size larger than the first gate 12. Excessively large metal gates will be excessively ground, resulting in a bowl-shaped structure with a low thickness.

[0056] In one possible embodiment, the substrate 10 in step one is a silicon substrate 10, and the devices on the first device region and the second device region are formed on the substrate 10. Alternatively, after an epitaxial layer is formed on the substrate 10, the devices on the first device region and the second device region are formed on the epitaxial layer.

[0057] In a possible implementation manner, the first device region in step 1 is a low-voltage device region.

[0058] In one possible implementation, the second device region in step one is a high-voltage device region. In the high-voltage device manufacturing process, due to the special requirements of high voltage, the metal gate will inevitably have an area that is too large and cannot be limited in size by design rules.

[0059] It should be understood that the first device region and the second device region may also be other types of device regions including large-sized metal gates.

[0060] In a possible implementation, the first gate 12 and the second gate 11 in step 1 are both metal gates.

[0061] Step 2, please refer to Figure 2 and Figure 3 , etching the second gate 11 to form at least one supporting groove;

[0062] In a possible implementation manner, the width of the supporting groove in step 2 is smaller than the minimum distance between two adjacent first gates 12 .

[0063] In a possible implementation manner, the etching in step 2 is dry etching, and anisotropic dry etching can form relatively vertical supporting grooves.

[0064] In one possible embodiment, the support groove in step 2 and the second gate 11 are formed in the same etching step, that is, the areas of the first gate 12 and the second gate 11 and the area of ​​the support groove are simultaneously defined by photolithography, and then etching is performed, which can save process manufacturing time.

[0065] Step 3, please refer to Figure 4 , forming a first mask layer 13 covering the first gate 12 and the second gate 11 on the substrate 10 to protect the first gate 12 and the second gate 11 thereunder;

[0066] In a possible implementation manner, the material of the first mask layer 13 in step three is SiCN.

[0067] Step 4, please refer to Figure 5 , forming a second mask layer 14 covering the first mask layer 13 on the substrate 10 so that the supporting groove is filled with the second mask layer 14;

[0068] In a possible implementation, the material of the second mask layer 14 in step 4 is silicon dioxide.

[0069] Step 5, please refer to Figure 6 , etching the second mask layer 14 so that the second mask layer 14 filled outside the supporting groove is removed, that is, the second mask layer 14 is retained in the supporting groove;

[0070] In a possible implementation, the etching in step five is wet etching. Wet etching can remove the second mask layer 14 made of silicon dioxide, while having a relatively small etching selectivity for the first mask layer 13 made of SiCN.

[0071] Step six: etching the first mask layer 13 to expose the upper surfaces of the first gate 12 and the second gate 11 .

[0072] In a possible embodiment, the etching in step six is ​​dry etching, and the anisotropic dry etching can remove the first mask layer 13 at the bottom of the trench between the first gate 12 and the second gate 11 and the first mask layer 13 on the upper surface of the first gate 12 and the second gate 11.

[0073] In one possible implementation, see Figure 7 The method further includes step seven, forming an interlayer dielectric layer covering the first gate 12, the second gate 11, the first mask layer 13 and the second mask layer 14 on the substrate 10, and then grinding the interlayer dielectric layer so that the first gate 12 and the second gate 11 are exposed. Figure 1 The gate structure after the middle grinding has a support groove formed on the larger second gate 11, and the support groove is filled with the second mask layer 14. Therefore, when the interlayer dielectric layer is ground, the grinding resistance of the metal gate is greatly increased, thereby ensuring that the devices in the first device area can work normally under the metal gate process.

[0074] In one possible implementation, the material of the interlayer dielectric layer in step seven is silicon dioxide.

[0075] In a possible implementation manner, the polishing in step seven is a chemical mechanical planarization process.

[0076] A metal gate structure can be manufactured by any of the above methods, comprising:

[0077] A substrate 10 is provided, on which a first device region and a second device region are formed. The first device region is provided with a plurality of first gates 12, and the second device region is provided with at least one second gate 11 having a size larger than that of the first gate 12.

[0078] At least one supporting groove is formed on the second gate 11;

[0079] A filling layer is formed in the supporting groove.

[0080] In one possible embodiment, the substrate 10 is a silicon substrate 10, and the devices on the first device region and the second device region are formed on the substrate 10. Alternatively, after an epitaxial layer is formed on the substrate 10, the devices on the first device region and the second device region are formed on the epitaxial layer.

[0081] In a possible implementation manner, the first device region is a low-voltage device region.

[0082] In a possible implementation, the second device region is a high-voltage device region.

[0083] In a possible implementation, the first gate 12 and the second gate 11 are both metal gates.

[0084] In a possible implementation, the filling layer includes a first mask layer 13 formed on the surface of the supporting groove and a second mask layer 14 filled in the first mask layer 13 .

[0085] In a possible implementation, the material of the first mask layer 13 is SiCN.

[0086] In one possible implementation, the material of the second mask layer 14 is silicon dioxide.

[0087] In a possible implementation manner, the first mask is also formed on the sidewalls of the first gate 12 and the second gate 11 .

[0088] In a possible implementation, an interlayer dielectric layer is formed between the first mask on the sidewalls of the first gate 12 and the second gate 11 .

[0089] In one possible implementation, the material of the interlayer dielectric layer is silicon dioxide.

[0090] In a possible implementation manner, the width of the supporting groove is smaller than the minimum distance between two adjacent first gates 12 .

[0091] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0092] In summary, the present invention enhances the metal gate's anti-grinding capability by adding additional support grooves to the large-area gate, thereby ensuring the normal operation of high-voltage devices under the metal gate manufacturing process. Therefore, the present invention effectively overcomes the shortcomings of the existing technology and has high industrial application value.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a metal grid with a support groove, characterized in that: At least: Step 1: providing a substrate, wherein a first device region and a second device region are formed on the substrate, wherein a plurality of first gates are formed in the first device region, and at least one second gate having a size larger than the first gate is formed in the second device region; Step 2: etching the second gate to form a supporting groove, wherein the width of the supporting groove is smaller than the minimum distance between two adjacent first gates; Step 3: forming a first mask layer covering the first gate and the second gate, wherein the material of the first mask layer is SiCN; Step 4: forming a second mask layer covering the first mask layer so that the supporting groove is filled with the second mask layer, wherein the material of the second mask layer is silicon dioxide; Step 5: etching the second mask layer to remove the second mask layer except for the portion filled in the supporting groove; Step 6: etching the first mask layer to expose the upper surfaces of the first gate and the second gate; Step seven: forming an interlayer dielectric layer covering the first and second gates and the first and second mask layers, and then polishing the interlayer dielectric layer to expose the first and second gates.

2. The manufacturing method according to claim 1, wherein: The polishing in step seven is chemical mechanical polishing.

3. The manufacturing method according to claim 1, wherein: The substrate in step 1 is a silicon substrate.

4. The manufacturing method according to claim 1, wherein: The first device region in step 1 is a low-voltage device region.

5. The manufacturing method according to claim 1, wherein: The second device region in step one is a high-voltage device region.

6. The manufacturing method according to claim 1, wherein: In step 1, the first gate and the second gate are both metal gates.

7. The manufacturing method according to claim 1, wherein: The etching in step 2 is dry etching.

8. The manufacturing method according to claim 1, wherein: The etching in step five is wet etching.

9. The manufacturing method according to claim 1, wherein: The etching in step six is ​​dry etching.

10. The manufacturing method according to claim 1, wherein: The material of the interlayer dielectric layer in step seven is silicon dioxide.

11. A metal gate structure manufactured by the method for manufacturing a metal gate with support grooves according to claim 1, characterized in that: include: a substrate having a first device region and a second device region formed thereon, wherein a plurality of first gates are formed in the first device region, and at least one second gate having a size larger than the first gate is formed in the second device region; wherein at least one supporting groove is formed in the second gate, and the width of the supporting groove is smaller than the minimum spacing between two adjacent first gates; A filling layer is formed in the supporting groove.

12. The metal gate structure according to claim 11, wherein: The substrate is a silicon substrate.

13. The metal gate structure according to claim 11, wherein: The first device region is a low-voltage device region.

14. The metal gate structure according to claim 11, wherein: The second device region is a high-voltage device region.

15. The metal gate structure according to claim 11, wherein: The first gate and the second gate are both metal gates.

16. The metal gate structure according to claim 11, wherein: The filling layer includes a first mask layer formed on the surface of the supporting groove and a second mask layer filled in the first mask layer.

17. The metal gate structure according to claim 16, wherein: The material of the first mask layer is SiCN.

18. The metal gate structure according to claim 16, wherein: The material of the second mask layer is silicon dioxide.

19. The metal gate structure according to claim 16, wherein: The first mask layer is also formed on sidewalls of the first gate and the second gate.

20. The metal gate structure according to claim 19, wherein: An interlayer dielectric layer is formed between the first mask layer on the sidewall of the first gate and the first mask layer on the sidewall of the second gate.

21. The metal gate structure according to claim 20, wherein: The material of the interlayer dielectric layer is silicon dioxide.

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