A synaptic transistor with long-term synaptic plasticity and a method for preparing the same

Abstract

The present invention is a synaptic transistor with long-term synaptic plasticity and a preparation method thereof. The structure of the transistor is: a semiconductor layer is on a substrate, electrodes are provided at both ends of the semiconductor layer, and an ion glue layer is covered on the semiconductor layer between the electrodes; wherein the electrodes are spaced source and drain electrodes; the semiconductor layer is an indium zinc oxide nanowire array and a nafion-graphene quantum dot blended layer covered thereon; during the preparation, graphene quantum dots are added to the nafion film to form a blended structure of graphene quantum dots and nafion, which greatly increases the long-term plasticity of the device. The present invention is a synaptic transistor with long-term synaptic plasticity, which enriches the selection of functional layer materials of synaptic transistors with bionic functions.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic materials and devices, and specifically relates to a synaptic transistor with long-term synaptic plasticity and a preparation method thereof. The method can be used to regulate the synaptic plasticity of the synaptic transistor, etc. Background Art

[0002] With the rapid growth of information in human society, neuromorphic engineering that simulates the structure, function and computing principles of the human brain has developed rapidly. Synapse is an important structure that connects two neuron cells. It realizes the conversion between chemical signals and electrical signals by controlling the ion concentration between synapses. It is the basic functional unit for human brain perception, recognition, learning and decision-making. Therefore, when building large-scale neural networks and developing cognitive computers with similar structures to the human brain, it is necessary to realize the functional simulation of synaptic bionic electronic devices.

[0003] The regulation of synaptic plasticity is the key to simulating the function of biological synapses. Synaptic plasticity mainly includes short-term synaptic plasticity and long-term synaptic plasticity, which are considered to be the biological basis of learning and memory activities at the cellular level. Among them, long-term synaptic plasticity plays a vital role in the brain's memory function and neural connections. Therefore, it is crucial to prepare a suitable and simple device structure to simulate the long-term plasticity of synapses. Synaptic transistors are three-terminal synaptic bionic devices made of semiconductor materials. Compared with traditional two-terminal synaptic devices such as memristors, phase change memories, and atomic switches, synaptic transistors have the advantages of low power consumption, high integration, and similarity to biological neural architectures. However, due to the many unknowns in the device structure and semiconductor layer materials of synaptic transistors, research on the long-term plasticity of synaptic transistors is still at a basic level. Summary of the invention

[0004] The purpose of the present invention is to provide a synaptic transistor with long-term synaptic plasticity and a preparation method thereof in view of the deficiencies in the current technology. The transistor can enhance the long-term synaptic plasticity of the device by adding a nafion-graphene quantum dot film; in the preparation method, graphene quantum dots are added to the nafion film to form a blended structure of graphene quantum dots and nafion, which greatly increases the long-term plasticity of the device. The present invention is a synaptic transistor with long-term synaptic plasticity, which enriches the selection of functional layer materials of synaptic transistors with bionic functions.

[0005] After the indium zinc oxide nanowires prepared by the present invention are printed, the long-term synaptic plasticity of the device can be enhanced by spin coating a nafion-graphene quantum dot blend solution.

[0006] The technical solution of the present invention is:

[0007] A synaptic transistor with long-term synaptic plasticity, the structure of the transistor is: a semiconductor layer is on the substrate, electrodes are provided at both ends of the semiconductor layer, and an ion gel layer is covered on the semiconductor layer between the electrodes;

[0008] The electrodes are spaced source and drain electrodes; the semiconductor layer is an indium zinc oxide nanowire array and a nafion-graphene quantum dot mixed layer covering the indium zinc oxide nanowire array.

[0009] The metal is gold or aluminum, with a thickness of 50 to 200 nm;

[0010] In the nanowire array, the diameter of the nanowire is 50 to 5000 nm; the length is 0.5 to 5 cm; the array spacing is 50 to 500 μm;

[0011] The material of the ion gel film is [PVDF-HFP] [EMIM], PEO-Li or sodium alginate; the thickness is 100-500 μm;

[0012] The substrate is a silicon wafer or glass;

[0013] In the nafion-graphene quantum dot mixed layer, the mass ratio of nafion to graphene quantum dots is 20-80:1; and the thickness ranges from 20 to 500 nm.

[0014] The method for preparing the synaptic transistor with long-term synaptic plasticity comprises the following steps:

[0015] 1) cleaning the substrate;

[0016] 2) polyvinyl pyrrolidone, zinc acetate dihydrate and indium nitrate hydrate in a mass ratio of 5-10:10-20:1 are mixed and dissolved in a mixed solution of N,N-dimethylformamide and trichloroethylene in a mass ratio of 2-4:1, and stirred at room temperature for 0.5-24 hours to prepare a precursor solution;

[0017] Wherein, the mass concentration of polyvinyl pyrrolidone is 10-20%;

[0018] 3) On the cleaned substrate, the precursor solution prepared in step 2) is printed into a nanowire array using an electrofluidic printing device. After printing, the nanowire array is placed in a muffle furnace, calcined, and then cooled to room temperature to obtain an IZO nanowire array;

[0019] 4) mixing the nafion solution with the graphene quantum dot solution to prepare a mixed solution;

[0020] The volume ratio is nafion solution: graphene quantum dot solution = 1:1-1:2; the graphene quantum dot solvent is water with a concentration of 0.5-2 mg / mL; the concentration of the nafion solution is 10-100 mg / mL;

[0021] 5) After cleaning the IZO nanowire array obtained in step 3), the mixed solution obtained in the previous step is added dropwise to the nanowire array region on the substrate and spin-coated to obtain a nafion-graphene quantum dot blend / IZO film;

[0022] 6) using a mask plate, evaporating a metal electrode on the surface of the thin film obtained in step 5) to prepare a thin film transistor device;

[0023] 7) attaching the ion gel film to the thin film transistor device obtained in step 6) to prepare a synaptic transistor device;

[0024] The cleaning described in step 1) is to ultrasonically clean the substrate in acetone, then ultrasonically clean it in isopropyl alcohol IPA, then heat the IPA to boiling, fumigate the surface of the substrate with IPA hot steam, and then blow dry the surface with a N2 gun;

[0025] Step 3) is to use an electrofluidic printing device to print the precursor solution prepared in step 2) into a nanowire array, the voltage between the syringe needle and the receiving surface is 0.5-2.5 kV, the distance between the syringe needle and the substrate is 1-6 mm, the syringe needle outlet flow rate is set to 1-50 nL / min, and the substrate movement speed is set to 300-1000 mm / s;

[0026] The calcination in step 3) is calcined at 300-500° C. for 30-120 minutes;

[0027] In step 5), the IZO nanowire array obtained in step 3) is placed in a UV ozone cleaning machine for treatment, and then the mixed solution prepared in step 4) is added dropwise to the obtained nanowires at 3500-5000 r·min. -1 The nafion-graphene quantum dot blend / IZO film was obtained by spin coating at a rotation speed of 30-50s.

[0028] Preparation method of ion gel film in step 7): PVDF-HFP and EMIM-TFSI in a mass ratio of 1:3-5:6 are mixed in acetone to prepare a mixed solution with a total mass fraction of the two substances of 10-20%, and the mixture is stirred at room temperature and condensed to obtain an ion gel film.

[0029] The synaptic transistor with long-term synaptic plasticity prepared by the present invention is prepared by digital controllable nanowire printing technology, and the steps are simple, the manufacturing cost is reduced, the process flow is simplified, and large-scale production can be achieved. The long-term synaptic plasticity of the device is greatly increased by nafion-graphene quantum dot blending modification, and excitatory postsynaptic current, double pulse facilitation, spike voltage-dependent plasticity, spike number-dependent plasticity and spike frequency-dependent plasticity are achieved. The present invention effectively prepares a synaptic transistor with long-term synaptic plasticity by reasonably controlling the concentration ratio of the nafion-graphene quantum dot blending solution, the rotation speed and time in the spin coating process, and other parameters, which is of great significance to the development of neuromorphic engineering and humanoid robots.

[0030] The essential features of the present invention are:

[0031] After printing indium zinc oxide nanowires, the present invention can enhance the long-term synaptic plasticity of the device by spin coating a nafion-graphene quantum dot blend solution. The addition of graphene quantum dots is equivalent to the introduction of a floating gate structure. After a positive voltage is applied to the gate of the device, cations in the ion colloid are injected into the semiconductor layer and captured by the graphene quantum dots. After the positive voltage is removed, the cations cannot return to the ion colloid, which can slightly increase the long-term synaptic plasticity of the device. However, compared to simply adding graphene quantum dots, the blending of graphene quantum dots and nafion film increases the contact area between graphene quantum dots and ions, allowing more cations to be captured by graphene quantum dots, thereby greatly increasing the long-term plasticity of the device.

[0032] The present invention can realize large-scale manufacturing of devices by utilizing high-precision nanowires, and can greatly optimize device performance by spin coating a blended solution to obtain a synaptic transistor with long-term synaptic plasticity.

[0033] The beneficial effects of the invention are:

[0034] 1. The preparation method of the synaptic transistor with long-term synaptic plasticity provided by the present invention is simple and easy, low in cost, and can be mass-produced;

[0035] 2. The blending of graphene quantum dots and nafion film increases the contact area between graphene quantum dots and ions in ion colloid, allowing more cations to be captured by graphene quantum dots, thereby greatly increasing the long-term plasticity of the device. The method of the present invention can greatly enhance the long-term synaptic plasticity of synaptic transistors and has a beneficial effect on artificial intelligence learning and computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Schematic diagram of biological synapse structure.

[0037] Figure 2It is a schematic diagram of the structure of the synaptic transistor with long-term synaptic plasticity of the present invention.

[0038] Figure 3 This is the long-term synaptic plasticity based on a single IZO nanowire synaptic transistor obtained in Example 1. The pulse amplitude is 4V, and the reading voltage is 1V.

[0039] Figure 4 This is the long-term synaptic plasticity based on the nafion-graphene quantum dot blend / IZO nanowire synaptic transistor obtained in Example 1. The pulse amplitude is 4V, and the reading voltage is 1V. DETAILED DESCRIPTION

[0040] The present invention is described below in conjunction with examples, but the present invention is not limited to the scope of the examples.

[0041] Embodiment 1:

[0042] 1) 1.5×1.5cm 2 The silicon wafer was ultrasonically cleaned with acetone solution and isopropanol IPA solution for 15 minutes, the isopropanol solution was heated to boiling, the substrate surface was fumigated with isopropanol hot vapor, and then the surface was blown dry with N2;

[0043] 2) polyvinyl pyrrolidone, zinc acetate dihydrate and indium nitrate hydrate in a mass ratio of 10:20:1 are mixed and dissolved in a mixed solution of N,N-dimethylformamide and trichloroethylene in a mass ratio of 2:1, wherein the mass concentration of polyvinyl pyrrolidone is 11.7%, and stirred at room temperature for 1 hour to prepare a precursor solution;

[0044] 3) Printing the precursor solution into a nanowire array using an electrofluidic printing device, controlling the voltage between the syringe needle and the receiving surface to be 1 kV, the distance between the syringe needle and the substrate to be 5 mm, setting the syringe needle outlet flow rate to 20 nL / min, and setting the substrate movement speed to 1000 mm / s. After printing, placing the nanowire array in a muffle furnace, calcining at 500° C. for 60 minutes and then cooling to room temperature to obtain an IZO nanowire array, wherein the diameter of a single nanowire is 250 nm;

[0045] 4) Mixing a nafion solution and a graphene quantum dot solution in a volume ratio of 1:1 to prepare a mixed solution; wherein the graphene quantum dot solvent is water with a concentration of 1 mg / mL; the nafion solution is a commercially available product with a concentration of 50 mg / mL; (i.e., the mass ratio of nafion to graphene quantum dots is 50:1;)

[0046] 5) Place the IZO nanowire array in a UV-ozone cleaning machine, use a pipette to take 50 μL of the nafion solution and the graphene quantum dot mixed solution onto the resulting nanowires, and clean the nanowires at 3500 r·min. -1 The nafion-graphene quantum dot blend / IZO film was obtained by spin coating at a speed of 30 s; the thickness was 200 nm;

[0047] 6) Using a mask, evaporating gold electrodes with a thickness of 80 nm and a spacing of 100 microns on the surface of the film to prepare a thin film transistor device;

[0048] 7) PVDF-HFP, EMIM-TFSI and acetone in a mass ratio of 1:4:7 were mixed and placed on a magnetic stirrer, heated and stirred at 50°C and 600 r / min for 12 h until a clear state was obtained, and condensed after stirring at room temperature to prepare an ion gel film with a thickness of 200 μm;

[0049] 8) attaching the ion gel film on the semiconductor layer between two gold electrodes to prepare a synaptic transistor device;

[0050] 9) Use a semiconductor analyzer to test the electrical performance of the synaptic transistor device, and adjust the input pulse signal to achieve the simulation of the functional behavior of the biological synapse by the artificial synapse.

[0051] Figure 1 This is a schematic diagram of the structure of biological synapses. When the presynaptic membrane is stimulated by electrical signals, the synaptic vesicles fuse with the presynaptic membrane and release the neurotransmitters stored in the synaptic vesicles. When the postsynaptic membrane is stimulated by neurotransmitters, electrical signals are generated. When the stimulation signal is removed, the electrical signal does not return to its initial position in a short period of time, which is called long-term plasticity. Figure 2 Schematic diagram of the structure of a synaptic transistor with long-term synaptic plasticity, in which the metal probe serves as the gate, simulating the presynaptic membrane. The ion gel layer contains a large number of anions and cations, simulating the neurotransmitters stored in synaptic vesicles. The indium zinc oxide nanowire and nafion / graphene quantum dot blend layer serve as the semiconductor layer, simulating the postsynaptic membrane. When the gate voltage is applied, the cations in the ion gel are injected into the semiconductor layer and captured by the graphene quantum dots. This process simulates the release of neurotransmitters from the presynaptic membrane to the postsynaptic membrane. After the voltage is removed, the ions cannot return to the ion gel, and the current of the synaptic transistor cannot return to the baseline level in a short time. This process simulates long-term synaptic plasticity. Figure 3 and Figure 4They are respectively the long-term synaptic plasticity based on a single IZO nanowire synaptic transistor and a nafion-graphene quantum dot blend / IZO nanowire synaptic transistor obtained in Example 1. Electrical testing was performed using a Keithley 4200 semiconductor analyzer, and it can be seen that after applying the same voltage stimulus (gate voltage 4V, reading voltage 1V), the current of the nafion-graphene quantum dot blend / IZO nanowire synaptic transistor did not decrease relatively in a short period of time, and had excellent long-term synaptic plasticity.

[0052] Embodiment 2:

[0053] 1) 1.5×1.5cm 2 The silicon wafer was ultrasonically cleaned with acetone solution and isopropanol IPA solution for 15 minutes, the isopropanol solution was heated to boiling, the substrate surface was fumigated with isopropanol hot vapor, and then the surface was blown dry with N2;

[0054] 2) polyvinyl pyrrolidone, zinc acetate dihydrate and indium nitrate hydrate in a mass ratio of 10:15:1 are mixed and dissolved in a mixed solution of N,N-dimethylformamide and trichloroethylene in a mass ratio of 2:1, wherein the mass concentration of polyvinyl pyrrolidone is 11.7%, and stirred at room temperature for 1 hour to prepare a precursor solution;

[0055] 3) Using an electrofluidic printing device to print the precursor solution into a nanowire array, controlling the voltage between the syringe needle and the receiving surface to be 1 kV, the distance between the syringe needle and the substrate to be 5 mm, the syringe needle outlet flow rate to be set to 20 nL / min, and the substrate movement speed to be set to 1000 mm / s. After printing, the nanowire array is placed in a muffle furnace, calcined at 500° C. for 60 minutes, and then cooled to room temperature to obtain an IZO nanowire array, wherein the diameter of a single nanowire is 300 nm;

[0056] 4) Mixing a nafion solution and a graphene quantum dot solution in a volume ratio of 1:1 to prepare a mixed solution; wherein the graphene quantum dot solvent is water with a concentration of 1 mg / mL; the nafion solution is a commercially available product with a concentration of 50 mg / mL; (i.e., the mass ratio of nafion to graphene quantum dots is 50:1;)

[0057] 5) Place the IZO nanowire array in a UV-ozone cleaning machine, use a pipette to take 50 μL of the nafion solution and the graphene quantum dot mixed solution onto the resulting nanowires, and clean the array at 4000 r·min. -1 The nafion-graphene quantum dot blend / IZO film was obtained by spin coating at a speed of 30 s; the thickness was 150 nm;

[0058] 6) Using a mask, evaporating gold electrodes with a thickness of 80 nm and a spacing of 100 microns on the surface of the film to prepare a thin film transistor device;

[0059] 7) PVDF-HFP, EMIM-TFSI and acetone in a mass ratio of 1:4:7 were mixed and placed on a magnetic stirrer, heated and stirred at 50° C. and 600 r / min for 12 h until a clear state was obtained, and condensed after stirring at room temperature to prepare an ion gel film with a thickness of 300 μm;

[0060] 8) attaching the ion gel film to the thin film transistor device to prepare a synaptic transistor device;

[0061] 9) Use a semiconductor analyzer to test the electrical performance of the synaptic transistor device, and adjust the input pulse signal to achieve the simulation of the functional behavior of the biological synapse by the artificial synapse.

[0062] Matters not covered by the present invention are known technologies.

Claims

1. A method for preparing a synaptic transistor with long-term synaptic plasticity, characterized in that The following steps are involved: 1) Cleaning the substrate; 2) Mix polyvinyl pyrrolidone, zinc acetate dihydrate and indium nitrate hydrate in a mass ratio of 5-10:10-20:1, dissolve in a mixed solution of N,N-dimethylformamide and trichloroethylene in a mass ratio of 2-4:1, stir at room temperature for 0.5-24 hours, and prepare a precursor solution; wherein the mass concentration of polyvinyl pyrrolidone is 10-20%; 3) On the cleaned substrate, the precursor solution prepared in step 2) is printed into a nanowire array using an electrofluidic printing device. After printing, the nanowire array is placed in a muffle furnace, calcined, and then cooled to room temperature to obtain an IZO nanowire array; 4) mixing the nafion solution with the graphene quantum dot solution to prepare a mixed solution; The volume ratio is nafion solution: graphene quantum dot solution = 1:1-1:2; the graphene quantum dot solvent is water, and the concentration is 0.5-2 mg / mL; the concentration of nafion solution is 10-100 mg / mL; 5) After cleaning the IZO nanowire array obtained in step 3), the mixed solution obtained in the previous step is dripped onto the nanowire array region on the substrate and spin-coated to obtain a nafion-graphene quantum dot blend / IZO film; 6) using a mask to evaporate a metal electrode on the surface of the thin film obtained in step 5) to prepare a thin film transistor device; 7) Attaching the ion gel film to the thin film transistor device obtained in step 6) to prepare a synaptic transistor device.

2. The method for preparing a synaptic transistor with long-term synaptic plasticity according to claim 1, characterized in that The cleaning described in step 1) is to ultrasonically clean the substrate in acetone, then ultrasonically clean it in isopropyl alcohol IPA, then heat the IPA to boiling, fumigate the surface of the substrate with IPA hot steam, and then blow dry the surface with a N2 gun.

3. The method for preparing a synaptic transistor with long-term synaptic plasticity according to claim 1, characterized in that Step 3) is to use an electrofluidic printing device to print the precursor solution prepared in step 2) into a nanowire array, the voltage between the syringe needle and the receiving surface is 0.5~2.5 kV, the distance between the syringe needle and the substrate is 1-6 mm, the syringe needle outlet flow rate is set to 1-50 nL / min, and the substrate movement speed is set to 300-1000 mm / s.

4. The method for preparing a synaptic transistor with long-term synaptic plasticity according to claim 1, characterized in that The calcination in step 3) is carried out at 300-500°C for 30-120 minutes.

5. The method for preparing a synaptic transistor with long-term synaptic plasticity according to claim 1, characterized in that In step 5), the IZO nanowire array obtained in step 3) is placed in a UV ozone cleaning machine for treatment, and then the mixed solution prepared in step 4) is added dropwise to the obtained nanowires at 3500-5000 r·min. -1 The film was spin coated at a rotation speed of 30-50 s to obtain a nafion-graphene quantum dot blend / IZO film.

6. The method for preparing a synaptic transistor with long-term synaptic plasticity according to claim 1, characterized in that Preparation method of ion gel film in step 7): PVDF-HFP and EMIM-TFSI in a mass ratio of 1:3-5:6 are mixed in acetone to prepare a mixed solution with a total mass fraction of the two substances of 10-20%, and the mixture is stirred at room temperature and condensed to obtain an ion gel film.

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