A high-side soft switch control system for a step-down synchronous rectifier circuit under light load conditions

Abstract

The present invention discloses a high-side soft switch control system under light-load conditions of a buck synchronous rectifier circuit, wherein a high-side dead zone control circuit 006 is provided to replace the fixed dead zone generating circuit 001 of the prior art, and the high-side dead zone control circuit 006 includes a current zero-crossing detection circuit 007, a high-side zero-crossing detection circuit 008, a buck level shift circuit 009, a setting delay circuit module 010, and an SR trigger SR1 and an SR trigger SR2. The high-side dead zone control circuit 006 automatically adjusts the CCM and FCCM control modes according to the changes of the input voltage VIN and the load current through the cooperation of the current zero-crossing detection circuit 007, the high-side zero-crossing detection circuit 008, and the buck level shift circuit 009, thereby realizing low diode conduction loss under the CCM control mode and soft opening of the power tube MH under the FCCM mode to avoid switching loss, thereby significantly improving the power conversion efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply, and in particular to a high-side soft switch control system of a step-down synchronous rectification circuit under light-load conditions. Background Art

[0002] At present, environmental protection, full integration and high efficiency have become the inevitable trend of power technology development, which makes high-density and high-efficiency power converters the mainstream technology of power conversion. The buck synchronous rectifier circuit uses a synchronous rectifier power tube with a small on-resistance to replace the diode with a high on-voltage drop in the traditional non-synchronous rectifier circuit, so it is more suitable for application in high power density and high efficiency scenarios. In the control of the buck synchronous rectifier circuit, there are three current control modes, namely: CCM (continuous current mode) control mode; DCM (discontinuous current mode) control mode; FCCM (forced continuous current mode) control mode.

[0003] Since the CCM control mode has the smallest inductor current ripple, and its power factor PF (power factor) and electromagnetic interference EMI (electromagnetic interference) are better than the DCM control mode, it is widely used in rectifier circuits in the field of power supply technology. However, when the load is light, the load current is small and there is a backflow phenomenon in the inductor current, CCM becomes FCCM control mode. When the synchronous rectifier power tube is turned off, the backflow inductor current charges the parasitic capacitance of the switch node, so that the switch node voltage VS rises to equal the input voltage VIN, and then the power tube MH is turned on, thereby realizing high-side soft switching to improve power conversion efficiency.

[0004] like Figure 1 , which is a structural schematic diagram of a fixed dead zone circuit provided by the prior art. The fixed dead zone circuit is generally set to work in a CCM current control mode. However, if the current control mode changes to FCCM or DCM due to changes in the input voltage VIN and the load current, then this fixed dead zone circuit will produce more losses. Figure 1 It includes a fixed dead zone generating circuit 001, a high voltage level shifting circuit 002, a driving stage circuit 003, a high and low side power tube 004 and a load circuit 005. The high side power tube MH and the low side power tube ML can be GaN (gallium nitride) or MOSFET (field effect transistor). In order to improve the power conversion efficiency of the step-down synchronous rectification circuit. Figure 1Under the condition of light load (i.e., small load current), the opening condition of the power tube MH of the fixed dead zone circuit structure is specifically analyzed. The input signal VPWM passes through the fixed dead zone generating circuit 001, then passes through the high voltage level shifting circuit 002, and finally passes through the high side driving circuit GH in the driving stage circuit 003 to the gate end of the power tube MH. Since the rising and falling slopes of the node voltage VS change with the changes of the input voltage VIN and the load current, when the input voltage VIN increases or the load current decreases, the rising slope of the node voltage VS decreases accordingly, resulting in a large switching loss when the power tube MH is turned on; when the input voltage VIN decreases or the load current increases, the rising slope of the node voltage VS increases accordingly, resulting in a large reverse conduction loss when the power tube MH is turned on. Therefore, how to improve the power conversion efficiency of the buck synchronous rectification circuit has become an urgent problem to be solved. Summary of the invention

[0005] In view of the problem of low power conversion efficiency of the buck synchronous rectifier circuit under light load conditions in the above-mentioned prior art, the present invention proposes a high-side soft switching control system of the buck synchronous rectifier circuit under light load conditions, which can adaptively adjust the dead time according to the change of the input voltage VIN or the load current, thereby realizing soft switching of the high-side power tube MH, and significantly improving the power conversion efficiency of the buck synchronous rectifier circuit under light load conditions.

[0006] To achieve the above-mentioned invention object, the technical solution adopted by the present invention is: a high-side soft switch control system of a step-down synchronous rectification circuit under light load conditions, comprising a fixed dead zone generating circuit (001), a high-voltage level shifting circuit (002), a driving stage circuit (003), a high-side and low-side power tube circuit (004) and a load circuit (005), wherein the driving stage circuit (003) is provided with a high-side driving circuit GH and a low-side driving circuit GL; the high-side and low-side power tube circuit (004) is provided with a power supply VIN and a high-side power tube MH and a low-side power tube ML; the load circuit (005) is provided with an inductor L, a capacitor CO and a resistor R; an input signal VPWM is sequentially connected to the input end of the high-side driving circuit GH in the driving stage circuit (003) after passing through the fixed dead zone generating circuit (001) and the high-voltage level shifting circuit (002); and the high-side driving circuit GH is connected to the input end of the high-side driving circuit GH in the driving stage circuit (003). The output of the driving circuit GH is connected to the gate of the high-side power tube MH in the high-low-side power tube circuit (004), the drain of the high-side power tube MH is connected to the positive end of the input power supply VIN, and the negative end of the input power supply VIN is grounded. The pulse control signal generated by the previous MCU chip or controller is used as the input signal VPWM to connect the input end of the low-side driving circuit GL in the driving stage circuit (003), the output of the low-side driving circuit GL is connected to the gate of the low-side power tube ML in the high-low-side power tube circuit (004), the source of the low-side power tube ML is grounded, the source of the high-side power tube MH and the drain of the low-side power tube ML are connected to one end of the inductor L in the load circuit (005) to generate a floating ground voltage VS, the other end of the inductor L is connected to one end of the capacitor CO and one end of the resistor R, and the other end of the capacitor CO and the other end of the resistor R are both grounded;

[0007] The invention is characterized in that: a high-side dead zone control circuit (006) is provided to replace the fixed dead zone generating circuit (001); the high-side dead zone control circuit (006) comprises a current zero-crossing detection circuit (007), a high-side zero-crossing detection circuit (008), a voltage step-down level shift circuit (009), a setting delay circuit module (010), a low-level effective SR trigger SR1, a high-level effective SR trigger SR2, and a three-input OR gate OR; the input end of the current zero-crossing detection circuit (007) and the input end of the high-side zero-crossing detection circuit (008) are both connected to a floating ground voltage VS; the output control signal V1 of the current zero-crossing detection circuit (007) is connected to a set input end S of the SR trigger SR1; the reset input end R of the SR trigger SR1 is connected to an input signal VPWM; the output of the SR trigger SR1 is connected to a reset input end R of the SR trigger SR1; and the output of the SR trigger SR1 is connected to a reset input end S of the SR trigger SR1. The output signal H_CCM at the Q end is connected to one input end of the three-input OR gate OR; the output control signal V2 of the high-side zero-crossing detection circuit (008) is connected to the input end of the step-down level shift circuit (009), the output control signal V3 of the step-down level shift circuit (009) is connected to the set input end S of the SR trigger SR2, the reset input end R of the SR trigger SR2 is connected to the input signal VPWM, and the output signal H_FCCM at the output end Q of the SR trigger SR2 is connected to the other input end of the three-input OR gate OR; the input end of the setting delay circuit module (010) is connected to the input signal VPWM, the output of the setting delay circuit module (010) is connected to the third input end of the three-input OR gate OR, and the output signal H_DRH of the three-input OR gate OR is used as the input signal of the high-voltage level shift circuit (002);

[0008] The current zero-crossing detection circuit (007) comprises a constant current source Idc1, PMOS tubes MP1, MP2, MP3 and MP4, NMOS tubes MN1, MN2, MN3, MN4, MN5 and MNH1; the input end of the constant current source Idc1 is connected to a chip power supply VCC, and the output end of the constant current source Idc1 is connected to the drain and gate of the NMOS tube MN1, the gate of the NMOS tube MN2 and the gate of the NMOS tube MN3; the source of the NMOS tube MN1 and the source of the NMOS tube MN2 are both grounded, the drain of the NMOS tube MN2 is connected to the drain and gate of the PMOS tube MP1, the gate of the PMOS tube MP2 and the gate of the NMOS tube MP3, and the source of the PMOS tube MP1, the source of the PMOS tube MP2, the source of the PMOS tube MP3 and the source of the PMOS tube MP4 are all connected The chip power supply VCC, the drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN3 and the gate of the NMOS tube MN4, the source of the NMOS tube MN3 is connected to the source of the NMOS tube MNH1, the drain of the NMOS tube MNH1 is connected to the floating ground voltage VS, the gate of the NMOS tube MNH1 is connected to the input signal VPWM, the sources of the PMOS tube MP3 and the PMOS tube MP4 are both connected to the chip power supply voltage VCC, the drain of the PMOS tube MP3 is interconnected with the gate of the PMOS tube MP4, the drain of the NMOS tube MN4 and the gate of the NMOS tube MN5, the source of the NMOS tube MN4 and the source of the NMOS tube MN5 are both grounded, and the drain of the PMOS tube MP4 and the drain of the NMOS tube MN5 are interconnected as the output end of the current zero-crossing detection circuit (007) to output the control signal V1;

[0009] The high-side zero-crossing detection circuit (008) comprises a constant current source Idc2, a PMOS tube MP5, an NMOS tube MN6, MN7 and MNH2 and a comparator CMP; the input end of the constant current source Idc2 and the source of the PMOS tube MP5 are both connected to a chip floating power supply VB, the output end of the constant current source Idc2 is connected to the drain and gate of the NMOS tube MN6 and the gate of the NMOS tube MN7, the source of the NMOS tube MN6 and the source of the NMOS tube MN7 are both connected to a floating ground voltage VS, the drain of the NMOS tube MN7 is connected to the gate and drain of the PMOS tube MP5 and the negative end of the comparator CMP and the source of the NMOS tube MNH2, the gate of the NMOS tube MNH2 and the positive end of the comparator CMP are both connected to the floating ground voltage VS, the drain of the NMOS tube MNH2 is connected to the input voltage VIN, and the output end of the comparator CMP serves as the output end of the high-side zero-crossing detection circuit (008) outputting a control signal V2.

[0010] In the above system, the current zero-crossing detection circuit (007), the high-side zero-crossing detection circuit (008), the step-down level shift circuit (009), the setting delay circuit module (010), the SR trigger SR1, the high-level effective SR trigger SR2 and the three-input OR gate OR in the high-side dead zone control circuit (006) cooperate with each other to realize automatic adjustment of the CCM and FCCM control modes according to the changes of the input voltage VIN and the load current, thereby realizing low diode conduction loss under the CCM control mode and soft opening of the power tube MH under the FCCM mode; according to whether the current of the inductor L has a backflow phenomenon, that is, whether the inductor current crosses zero, the current zero-crossing detection circuit The circuit (007) and the high-side zero-crossing detection circuit (008) output different control signals V1 and V2; the control signal V1 is converted into a gate control signal VGH for turning on the power tube MH in the CCM mode after passing through the SR trigger SR1, the three-input OR gate OR, the high-voltage level shift circuit (002) and the high-side driving circuit GH in the output stage circuit (003); similarly, the control signal V2 is converted into a gate control signal VGH for turning on the power tube MH in the FCCM mode after passing through the step-down level shift circuit (009), the SR trigger SR2, the three-input OR gate OR, the high-voltage level shift circuit (002) and the high-side driving circuit GH in the output stage circuit (003).

[0011] The control process of the system is as follows:

[0012] CCM control process: when the output is under heavy load condition, the output load current is very large, and there is no backflow phenomenon of the inductor current. After the power tube MH is not turned on and the power tube ML is turned off, the current zero-crossing detection circuit (007) determines whether the inductor current has a backflow phenomenon by detecting whether the VS voltage has a negative voltage; if the VS voltage has a negative voltage, it means that the body diode of the power tube ML is performing a freewheeling function, so the inductor current will not have a backflow phenomenon, and the rectifier circuit is in a CCM control mode; the current zero-crossing detection circuit (007) detects the falling edge of the negative voltage VS when the body diode of the power tube ML is freewheeling as the control signal V1 for controlling the power tube MH to turn on, the input signal VPWM is connected to the reset terminal R of the SR trigger SR1, and is used as the control signal for controlling the power tube MH to turn off, and the output terminal Q of the SR trigger SR1 outputs the control signal H_CCM, which is converted into the gate control signal VGH of the power tube MH through the three-input OR gate OR, the high-voltage level shift circuit (002) and the high-side drive circuit GH in the drive stage circuit (003);

[0013] FCCM control process 1: When the output is under light load condition, the output load current is small, and the inductor current will have a backflow phenomenon. After the power tube MH is not turned on and the power tube ML is turned off, the current zero-crossing detection circuit (007) determines whether the inductor current has a backflow phenomenon by detecting whether the VS voltage has a negative voltage; if the VS voltage does not have a negative voltage, it means that the inductor current has a backflow phenomenon, and the backflow current charges the node parasitic capacitance, and the node voltage VS begins to rise. Then the rectifier circuit is in FCCM control mode, and the high-side zero-crossing detection circuit (008) will detect whether the node voltage VS is charged to a level greater than the input voltage VIN, and at the same time, the detection node When the voltage VS is equal to the input voltage VIN, the corresponding rising edge is used as the control signal V2 for controlling the power tube MH to turn on; the control signal V2 in the high-voltage domain is converted into the control signal V3 in the low-voltage domain through the step-down level shift circuit (009); the input signal VPWM is connected to the reset terminal R of the SR trigger SR2 as the control signal for controlling the power tube MH to turn off, and the output terminal Q of the SR trigger SR2 outputs the control signal H_FCCM which is converted into the gate control signal VGH for turning on the power tube MH through the SR trigger SR2, the three-input OR gate OR, the high-voltage level shift circuit (002) and the high-side drive circuit GH in the drive stage circuit (003);

[0014] FCCM control process 2: When the output is under light load conditions, the output load current is very small, that is, the time required for the node voltage VS to rise to the input voltage VIN is greater than the load current corresponding to 200ns set according to different system frequencies, and the inductor current will have a backflow phenomenon. After the power tube MH has not yet turned on and the power tube ML is turned off, the current zero-crossing detection circuit (007) determines whether the inductor current has a backflow phenomenon by detecting whether there is a negative voltage in the VS voltage; if there is no negative voltage in the VS voltage, it means that the inductor current has a backflow phenomenon, and the backflow current charges the node parasitic capacitance, and the node voltage VS starts to rise, then the rectifier circuit is in FCCM control mode; however, when the output load current is very small, the backflow current will also be very small, resulting in a small rising slope of the node voltage VS, so the node voltage VS rises to The time required to be equal to the input voltage VIN will be longer, resulting in the output signal V2 of the high-side zero-crossing detection circuit (008) flipping from a low level to a high level later than the control signal H_FD output by the setting delay circuit module 010. Due to the limitation of the operating frequency of the rectifier circuit system, it is necessary to set a limit on the rise time of the node voltage VS. The setting delay circuit module 010 delays the input signal VPWM to ts=200ns set according to different system frequencies, and outputs the control signal H_FD. The reset signal of the SR trigger SR2 is determined by the input signal VPWM. The control signal H_FD is converted into the gate control signal VGH for turning on the power tube MH through the three-input OR gate OR, the high-voltage level shift circuit (002) and the high-side drive circuit GH in the drive stage circuit (003);

[0015] Furthermore, MP1, MP2, MP3 and MP4 in the current zero-crossing detection circuit (007) are all low-voltage PMOS tubes, MN1, MN2, MN3, MN4 and MN5 are all low-voltage NMOS tubes, and MNH1 is a high-voltage NMOS tube.

[0016] Furthermore, MP5 in the high-side zero-crossing detection circuit (008) is a low-voltage PMOS tube, MN6 and MN7 are both low-voltage NMOS tubes, and MNH2 is a high-voltage NMOS tube.

[0017] Compared with the prior art, the present invention has the following advantages and significant effects:

[0018] (1) The present invention detects the node voltage VS and outputs a control signal through the current zero-crossing detection circuit 007 and the high-side zero-crossing detection circuit 008, so that the circuit can adaptively adjust the dead time according to the changes of the input voltage VIN and the load current. Compared with the existing technical solutions, the application range is wider.

[0019] (2) The present invention can automatically adjust the CCM and FCCM control modes according to the changes in the input voltage VIN and the load current through the current zero-crossing detection circuit 007, thereby achieving low diode conduction loss under the CCM control mode and soft turning on of the power tube MH in the FCCM mode to avoid switching loss, thereby significantly improving the power conversion efficiency.

[0020] (3) The present invention realizes soft-start of the power tube MH under light load conditions, significantly reduces the influence of dv / dt on the high-voltage level shift circuit 002, and improves the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of a fixed dead zone circuit structure provided by the prior art;

[0022] Figure 2 This is a schematic diagram of a high-side soft switch circuit structure under light load conditions proposed by the present invention;

[0023] Figure 3 yes Figure 2 An implementation circuit of the current zero-crossing detection circuit 007;

[0024] Figure 4 yes Figure 2 An implementation circuit of the mid-high side zero-crossing detection circuit 008;

[0025] Figure 5 It is a working waveform diagram of a fixed dead zone generating circuit provided by the prior art;

[0026] Figure 6 It is a comparison diagram of the working waveforms of CCM and FCCM control within the set delay range of the present invention;

[0027] Figure 7 It is a comparison diagram of the working waveforms of the FCCM control within the set delay range and the FCCM control beyond the set delay range of the present invention. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings.

[0029] See also Figure 2 , is a schematic diagram of the structure of a high-side soft switch control system under light-load conditions of a step-down synchronous rectifier circuit proposed in the present invention. Figure 1On the basis of the prior art, the fixed dead zone generating circuit 001 is removed and a high-side dead zone control circuit 006 is provided. The high-side dead zone control circuit 006 includes a current zero-crossing detection circuit 007, a high-side zero-crossing detection circuit 008, a step-down level shift circuit 009, a setting delay circuit module 010, and a low-level effective SR trigger SR1 and a high-level effective SR trigger SR2. In the high-side dead zone control circuit 006, except for the current zero-crossing detection circuit 007 and the high-side zero-crossing detection circuit 008, the step-down level shift circuit 009, the setting delay circuit module 010, the SR triggers SR1, SR2 and the three-input OR gate OR can all adopt the prior art. The high-side dead-zone control circuit 006 mainly cooperates with the current zero-crossing detection circuit 007, the high-side zero-crossing detection circuit 008 and the step-down level shift circuit 009 to automatically adjust the CCM and FCCM control modes according to the changes in the input voltage VIN and the load current, thereby achieving low diode conduction loss under the CCM control mode and soft-start of the power tube MH under the FCCM mode to avoid switching loss, thereby significantly improving the power conversion efficiency.

[0030] The input end of the current zero-crossing detection circuit 007 and the input end of the high-side zero-crossing detection circuit 008 are both connected to the floating ground voltage VS, the current zero-crossing detection circuit (007) outputs a control signal V1 connected to the set input end S of the SR trigger SR1, the reset input end R of the SR trigger SR1 is connected to the input signal VPWM, the output end Q of the SR trigger SR1 outputs a signal H_CCM connected to one input end of a three-input OR gate OR; the high-side zero-crossing detection circuit (008) outputs a control signal V2 connected to the input end of the step-down level shift circuit (009), the step-down level shift circuit The circuit 009 outputs a control signal V3 connected to the set input terminal S of the SR flip-flop SR2, the reset input terminal R of the SR flip-flop SR2 is connected to the input signal VPWM, the output terminal Q of the SR flip-flop SR2 outputs a signal H_FCCM connected to another input terminal of the three-input OR gate OR; the input terminal of the setting delay circuit module (010) is connected to the input signal VPWM, the output of the setting delay circuit module (010) is connected to the third input terminal of the three-input OR gate OR, and the three-input OR gate OR outputs a signal H_DRH as the input signal of the high-voltage level shift circuit 002.

[0031] The working principle of the high-side dead zone control circuit 006 is as follows: after the power tube MH is not turned on and the power tube ML is turned off, the current zero-crossing detection circuit 007 is used to detect whether the VS voltage has a negative voltage to determine whether the inductor current has a backflow phenomenon, thereby determining whether the rectifier circuit is in CCM control mode or FCCM control mode, and then the power tube MH is controlled to be turned on at different time points through two subsequent different loops, thereby ensuring that the circuit operates stably, reliably and efficiently within a wide load range. The output signal V1 of the current zero-crossing detection circuit 007 is a judgment signal for whether the VS voltage has a negative voltage, that is, a judgment signal for CCM control and FCCM control, and also a detection signal for CCM control. If the VS voltage has a negative voltage, it means that the body diode of the power tube ML is performing a freewheeling function, and the inductor current will not have a backflow phenomenon, then the rectifier circuit needs to be in CCM control mode. When the VS voltage has a negative voltage, the output control signal V1 of the current zero-crossing detection circuit 007 will flip from a high level to a low level, and the falling edge of the control signal V1 will be used as the set signal of the SR trigger. The reset signal of the SR trigger is determined by the input signal VPWM. The control signal V1 is converted into the gate control signal VGH for turning on the power tube MH through the subsequent processing circuit. If the VS voltage does not have a negative voltage, it means that the inductor current will be backflowing, and the backflow current will charge the node parasitic capacitance, and the node voltage VS will start to rise, then the rectifier circuit needs to perform FCCM control. The high-side zero-crossing detection circuit 008 will detect whether the node voltage VS is charged to be equal to the input voltage VIN. When the node voltage VS is equal to the input voltage VIN, the output signal V2 of the high-side zero-crossing detection circuit 008 will flip from a low level to a high level, and the control signal V2 of the high-voltage domain will be converted into the control signal V3 of the low-voltage domain through the step-down level shift circuit 009, and the rising edge of the control signal V3 will be used as the set signal of the SR trigger. The reset signal of the SR trigger is determined by the input signal VPWM. The control signal V3 is converted into a gate control signal VGH for turning on the power tube MH through a subsequent processing circuit.

[0032] The CCM control process is as follows: when the output is under heavy load conditions, the output load current is very large, and there is no backflow phenomenon in the inductor current. After the power tube MH has not been turned on and the power tube ML is turned off, the current zero-crossing detection circuit 007 determines whether the inductor current has a backflow phenomenon by detecting whether the VS voltage has a negative voltage; if the VS voltage has a negative voltage, it means that the body diode of the power tube ML is performing a freewheeling function, so the inductor current will not have a backflow phenomenon, and the rectifier circuit is a CCM control mode; the current zero-crossing detection circuit 007 will detect the falling edge of the negative voltage VS when the body diode of the power tube ML is freewheeling as the control signal V1 to control the power tube MH to turn on, and the input signal VPWM is connected to the reset terminal R of the SR trigger as the control signal to control the power tube MH to turn off. The output terminal Q of the SR trigger outputs the control signal H_CCM, which is converted into the gate control signal VGH of the power tube MH through the OR gate logic circuit, the high-voltage level shift circuit 002 and the high-side drive circuit GH in the drive stage circuit 003.

[0033] The FCCM control process 1 is as follows: when the output is under light load conditions, the output load current is small, and the inductor current will have a backflow phenomenon. After the power tube MH has not been turned on and the power tube ML is turned off, the current zero-crossing detection circuit 007 determines whether the inductor current has a backflow phenomenon by detecting whether there is a negative voltage in the VS voltage. If there is no negative voltage in the VS voltage, it means that the inductor current will have a backflow phenomenon, and the backflow current charges the node parasitic capacitance, and the node voltage VS begins to rise, then the rectifier circuit is in the FCCM control mode. The high-side zero-crossing detection circuit 008 will detect whether the node voltage VS is charged to a value greater than the input voltage VIN, and at the same time, the corresponding rising edge when the detection node voltage VS is equal to the input voltage VIN is used as the control signal V2 for controlling the power tube MH to turn on. The set signal V2 of the high-voltage domain is converted into the control signal V3 of the low-voltage domain through the step-down level shift current circuit 009, and the input signal VPWM is connected to the reset terminal R of the SR trigger as the control signal for controlling the power tube MH to turn off. The output terminal Q of the SR trigger outputs a control signal H_FCCM which is converted into a gate control signal VGH of the power tube MH through an OR gate logic circuit, a high-voltage level shift circuit 002 and a high-side drive circuit GH in the drive stage circuit 003 .

[0034] FCCM control process 2 is as follows: when the output is under light load conditions, the output load current is very small, that is, the time required for the node voltage VS to rise to the input voltage VIN is greater than 200ns (set according to different system frequency) corresponding to the load current, and the inductor current will have a backflow phenomenon. After the power tube MH has not been turned on and the power tube ML is turned off, the current zero-crossing detection circuit 007 determines whether the inductor current has a backflow phenomenon by detecting whether there is a negative voltage in the VS voltage. If there is no negative voltage in the VS voltage, it means that the inductor current will have a backflow phenomenon, and the backflow current charges the node parasitic capacitance, and the node voltage VS begins to rise, then the rectifier circuit is a FCCM control mode. However, when the output load current is very small, the backflow current will also be very small, resulting in a small slope of the node voltage VS rising, so the time required for the node voltage VS to rise to equal the input voltage VIN will be longer, resulting in a late time for the output signal V2 of the high-side zero-crossing detection circuit 008 to flip from a low level to a high level (later than the control signal H_FD output by the setting delay circuit module 010). Due to the limitation of the operating frequency of the rectifier circuit system, it is necessary to limit the node voltage VS rise time. The delay circuit module 010 is set to delay the input signal VPWM by ts=200ns (set according to the system frequency) and output the control signal H_FD. The reset signal of the SR trigger is determined by the input signal VPWM. The control signal H_FD is converted into the gate control signal VGH for turning on the power tube MH through the OR gate logic circuit, the high-voltage level shift circuit 002 and the high-side drive circuit GH in the drive stage circuit 003.

[0035] See also Figure 3The current zero-crossing detection circuit 007 includes a constant current source Idc1, four low-voltage PMOS tubes MP1, MP2, MP3 and MP4, five low-voltage NMOS tubes MN1, MN2, MN3, MN4 and MN5, and a high-voltage NMOS tube MNH1. The input end of the constant current source Idc1 is connected to the chip power supply voltage VCC, and the output end of the constant current source Idc1 is connected to the drain and gate of the NMOS tube MN1 and the gates of the NMOS tubes MN2 and MN3; the source of the NMOS tube MN1 and the source of the NMOS tube MN2 are both connected to the chip logic ground, the drain of the NMOS tube MN2 is connected to the drain and gate of the PMOS tube MP1 and the gate of the PMOS tube MP2 and the gate of the NMOS tube MP3, the source of the PMOS tube MP1 and the source of the PMOS tube MP2 are both connected to the chip power supply VCC, the drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN3 and the gate of the NMOS tube MN4; the source of the NMOS tube MN3 is connected to the chip logic ground, the drain of the NMOS tube MN2 is connected to the drain and gate of the PMOS tube MP1 and the gate of the PMOS tube MP2 and the gate of the NMOS tube MP3, the source of the PMOS tube MP1 and the source of the PMOS tube MP2 are both connected to the chip power supply VCC, the drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN3 and the gate of the NMOS tube MN4; The source is connected to the source of the high-voltage NMOS tube MNH1, the drain of the high-voltage NMOS tube MNH1 is connected to the node voltage VS, and the gate of the high-voltage NMOS tube MNH1 is connected to the input signal VPWM; the sources of the PMOS tube MP3 and the PMOS tube MP4 are both connected to the chip power supply voltage VCC, the drain of the PMOS tube MP3, the gate of the PMOS tube MP4, the drain of the NMOS tube MN4 and the gate of the NMOS tube MN5 are connected to each other, the source of the NMOS tube MN4 and the source of the NMOS tube MN5 are both connected to the chip logic ground, and the drain of the PMOS tube MP4 and the drain of the NMOS tube MN5 are connected as the output end of the current zero-crossing detection circuit 007 to output the control signal V1.

[0036] Working principle of current zero-crossing detection circuit 007: Under CCM control mode, VS voltage has three stages of transformation process. The first stage is that the initial condition VS voltage is not negative voltage, that is, zero voltage. In the second stage, due to the freewheeling effect of the body diode of power tube ML, VS voltage becomes negative voltage. In the third stage, after power tube MH is turned on, VS voltage rises and finally equals input voltage VIN. At this time, VS voltage is not negative voltage. When VS is not negative voltage, the pull-up current capability of PMOS tube MP2 is greater than the pull-down current capability of NMOS tube MN3, so that the middle potential VX of the two MOS tubes is pulled up to equal to VCC voltage. Since the gate of PMOS tube MP3 is biased at a fixed potential, the pull-down current capability of NMOS tube MN4 is greater than the pull-up current capability of PMOS tube MP3, so that the middle potential VY of the two MOS tubes is pulled down to close to logic ground. Finally, the output control signal V1 is obtained as high level through the inverter composed of PMOS tube MP4 and NMOS tube MN5. Due to the freewheeling effect of the body diode of the power tube ML, when VS becomes a negative voltage, the VX potential is also pulled down to a negative voltage. At this time, the NMOS tube MN4 is in a closed state, and the VY potential is pulled up by the PMOS tube MP3 to a voltage close to the chip power supply voltage VCC. After passing through the inverter composed of the PMOS tube MP4 and the NMOS tube MN5, the output control signal V1 is flipped to a low level. Finally, when VS becomes a non-negative voltage, the current zero-crossing detection circuit 007 outputs a control signal V1 that flips to a high level. Similarly, under the FCCM control mode, the VS voltage is not a negative voltage, so the current zero-crossing detection circuit 007 outputs a control signal V1 that is always a high level. The withstand voltage effect of the body diode of the high-voltage tube MNH1 is used to prevent the VS voltage in the high-voltage domain from affecting the low-voltage tube above.

[0037] See also Figure 4 The high-side zero-crossing detection circuit 008 includes a constant current source Idc2, a low-voltage PMOS tube MP5, two low-voltage NMOS tubes MN6 and MN7, a high-voltage NMOS tube MNH2 and a comparator CMP; the upper end of the constant current source Idc2 is connected to the chip floating power supply VB, and the lower end of the constant current source Idc2 is connected to the drain and gate of the NMOS tube MN6 and the gate of the NMOS tube MN7; the source of the NMOS tube MN6 and the source of the NMOS tube MN7 are both connected to the floating ground VS, the drain of the NMOS tube MN7 is connected to the gate and drain of the PMOS tube MP5, the out-of-phase end of the comparator CMP and the source of the high-voltage NMOS tube MNH2, the gate of the high-voltage NMOS tube MNH2 and the in-phase end of the comparator CMP are both connected to the floating ground VS, and the drain of the high-voltage NMOS tube MNH2 is connected to the input voltage VIN; the source of the PMOS tube MP5 is connected to the chip floating power supply VB, and the output end of the comparator CMP outputs the control signal V2 as the output end of the high-side zero-crossing detection circuit 008.

[0038] The working principle of the high-side zero-crossing detection circuit 008 is as follows: Under the initial condition, the floating ground potential VS is equal to the chip logic ground, and the floating power supply VB is equal to the chip power supply voltage VCC. The voltage VZ is biased at a high potential close to VCC by the constant current source Idc2 and the diode-connected PMOS tube MP5. At this time, the VZ voltage is greater than the VS voltage, so the output of the comparator CMP, that is, the output control signal V2 of the high-side zero-crossing detection circuit 008 is low. When the body diode of the power tube MH is freewheeling, the floating ground potential VS changes from the chip logic ground to a voltage greater than the input voltage VIN, and the NMOS tube MN7 performs freewheeling, and the VZ potential becomes a negative voltage. At this time, the VZ voltage is less than the VS voltage, so the output of the comparator CMP, that is, the output control signal V2 of the high-side zero-crossing detection circuit 008, flips to a high level. When the circuit is stable, the floating ground potential VS changes from the chip logic ground to a level greater than the input voltage VIN, and the body diode of the high-voltage NMOS tube MNH2 begins to conduct, and the VZ-VS potential becomes the forward conduction voltage drop of the body diode of the high-voltage NMOS tube MNH2, which is about 0.7V. At this time, the VZ voltage is greater than the VS voltage, so the output of the comparator CMP, that is, the output control signal V2 of the high-side zero-crossing detection circuit 008, is flipped to a low level.

[0039] See also Figure 5 , which is a working waveform diagram of the fixed dead zone generation circuit provided by the prior art. It can be seen from the two different load currents corresponding to different VS slopes that after the power tube MH of the fixed dead zone generation circuit has not been turned on and the power tube ML is turned off, if the VS slope is small, the fixed dead zone will cause the opening of the power tube MH to produce large switching losses; if the VS slope is large, the fixed dead zone will cause the body diode of the power tube MH to continue to flow and produce large diode conduction losses. Therefore, the fixed dead zone generation circuit seriously affects the power conversion efficiency of the rectifier circuit, which is particularly serious in the high-frequency application of GaN power tubes.

[0040] See also Figure 6, is a comparison diagram of the working waveforms of CCM control and FCCM control within the set delay range of the present invention. The left part of the figure is the working waveform diagram of CCM control, and the right part of the figure is the working waveform diagram of FCCM control. It can be seen from the working waveform diagram of the left part of CCM control that the inductor current IL is always greater than zero. At the moment 0-t0, VGH is at a low level and VGL is at a high level, that is, the power tube MH is in the off state, and the power tube ML is in the on-state. Since the on-state voltage drop of the power tube ML is very small, the node voltage VS is approximately equal to zero potential (not a negative voltage) at this time, so the current zero-crossing detection circuit 007 outputs a control signal V1 of a high level; at the moment t0-t1, VGH and VGL are both low levels, that is, the power tube MH and the power tube ML are both in the off state, then the body diode of the power tube ML is in the on-state. effect, at this time the node voltage VS flips to a negative voltage, then the current zero-crossing detection circuit 007 outputs a control signal V1 that flips to a low level, and the falling edge, as a detection signal under the CCM control mode, becomes a rising edge of the drive signal VGH of the power tube MH after a transmission delay ts1; at t1-t2, VGH is a high level and VGL is a low level, that is, the power tube MH is in the on state and the power tube ML is in the off state. At this time, the node voltage VS (not a negative voltage) starts to rise and eventually equals the input voltage VIN, then the current zero-crossing detection circuit 007 outputs a control signal V1 that flips to a high level. From the working waveform of the right part of FCCM control, it can be seen that the inductor current IL is less than zero. At t3-t4, VGH is low and VGL is high, that is, the power tube MH is in the off state, and the power tube ML is in the on-state. Since the on-state voltage drop of the power tube ML is approximately zero, it means that the node voltage VS is approximately equal to zero potential. At this time, the VZ potential is biased at a high potential close to VCC, so the VZ voltage is greater than the VS voltage. Therefore, the output of the comparator CMP, that is, the output control signal V2 of the high-side zero-crossing detection circuit 008 is low, and the control signal V2 is converted into the control signal V3 of low level through the step-down level shift circuit 009.At the moment t4-t5, VGH and VGL are both low level, that is, the power tube MH and the power tube ML are both in the off state. Due to the backflow phenomenon of the inductor current (the current is less than zero), and the backflow current charges the node parasitic capacitance, the node voltage VS begins to rise but is still less than the input voltage VIN, then the high-side zero-crossing detection circuit 008 outputs the control signal V2 which is converted into the control signal V3 through the step-down level shift circuit 009 and is still low level; at the moment t5-t6, VGH and VGL are both low level, that is, the power tube MH and the power tube ML are both in the off state. In the off state, since the backflow current continues to charge the node parasitic capacitance and the body diode of the power tube MH starts to perform freewheeling, when the node voltage VS starts to rise to be greater than the input voltage VIN, the NMOS tube MN7 in the high-side zero-crossing detection circuit 008 also performs freewheeling, and the VZ potential becomes a negative voltage. At this time, the VZ voltage is less than the VS voltage. Therefore, the output of the comparator CMP, that is, the output control signal V2 of the high-side zero-crossing detection circuit 008 is flipped to a high level, and the control signal V2 is converted into the control signal V3 through the step-down level shift current 009 and flipped to a high level. This rising edge is used as a detection signal under the FCCM control mode and is transformed into a rising edge of the driving signal VGH of the power tube MH through a transmission delay ts2; at time t6-t7, VGH is at a high level and VGL is at a low level, that is, the power tube MH is in the on state, the power tube ML is in the off state, the floating ground potential VS becomes equal to the input voltage VIN, the body diode of the high-voltage NMOS tube MNH2 begins to conduct, and the VZ-VS potential becomes the forward conduction voltage drop of the body diode of the high-voltage NMOS tube MNH2, which is about 0.7V. At this time, the VZ voltage is greater than the VS voltage, so the output of the comparator CMP, that is, the output control signal V2 of the high-side zero-crossing detection circuit 008 is flipped to a low level, and the control signal V2 is transformed into the control signal V3 through the step-down level shift circuit 009 and flipped to a low level.

[0041] See also Figure 7 , which is a comparison diagram of the working waveforms of the FCCM control within the set delay range and the FCCM control beyond the set delay range of the present invention. The left part of the figure is the working waveform of the FCCM control (within the set delay range), and the right part of the figure is the working waveform of the FCCM control (outside the set delay range). The working waveform principle analysis and Figure 6The working waveform of the right part of FCCM control is the same and will not be repeated here. From the working waveform of the right part of FCCM control (outside the set delay range), it can be seen that when the inductor current backflow current is very small, the node voltage VS rise slope is very small, resulting in a long time required for the node voltage VS to rise to equal the input voltage VIN, which seriously limits the system operating frequency of the rectifier circuit. Therefore, it is necessary to set a limit on the rise time of the node voltage VS. Set the delay circuit module 010 to delay the input signal VPWM by ts=200ns (set according to the system frequency). At time t3-t4, Figure 6 The principle analysis of the t3-t4 moment is the same as that of the t4-t5 moment, which will not be repeated here. Figure 6 The principle analysis of the t4-t5 moment is the same, the only difference is that, because the inductor current backflow is a small current, the node voltage VS has not reached the input voltage VIN after the set delay ts, and the VZ voltage is greater than the VS voltage at this time, so the output of the comparator CMP, that is, the output control signal V2 of the high-side zero-crossing detection circuit 008 is still at a low level, and the control signal V2 is converted to the control signal V3 after the step-down level shift circuit 009 and is still at a low level. At t5-t6, the output control signal H_FD of the delay circuit module is set to flip from a low level to a high level. This rising edge is used as a detection signal under the FCCM control mode (outside the set delay range) and is converted into the rising edge of the drive signal VGH of the power tube MH after a transmission delay ts3. The transmission delay is equal to ts3. When the drive signal VGH flips to a high level, the node voltage VS is quickly pulled up to equal the input voltage VIN. At the moment t6-t7, VGH is at a high level and VGL is at a low level, that is, the power tube MH is in the on state, the power tube ML is in the off state, the floating ground potential VS becomes equal to the input voltage VIN, the body diode of the high-voltage NMOS tube MNH2 begins to conduct, and the VZ-VS potential becomes the forward conduction voltage drop of the body diode of the high-voltage NMOS tube MNH2, which is about 0.7V. At this time, the VZ voltage is greater than the VS voltage, so the output of the comparator CMP, that is, the output control signal V2 of the high-side zero-crossing detection circuit 008 is still at a low level, and the control signal V2 is converted into the control signal V3 through the step-down level shift circuit 009, which is still at a low level.

[0042] The above is a detailed introduction to an embodiment of a high-side soft switch control system under light-load conditions of a step-down synchronous rectifier circuit provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. For general technicians in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope, but any changes made under the idea of ​​the present invention should be within the protection scope of the present invention.

Claims

1. A high-side soft switch control system for a step-down synchronous rectification circuit under light load conditions, comprising a fixed dead zone generation circuit (001), a high-voltage level shift circuit (002), a drive stage circuit (003), a high-side and low-side power tube circuit (004) and a load circuit (005), in, The driving stage circuit (003) is provided with a high-side driving circuit GH and a low-side driving circuit GL; the high-side and low-side power tube circuit (004) is provided with a power supply VIN and a high-side power tube MH and a low-side power tube ML; the load circuit (005) is provided with an inductor L, a capacitor CO and a resistor R; the input signal VPWM is connected to the input end of the high-side driving circuit GH in the driving stage circuit (003) after passing through the fixed dead zone generating circuit (001) and the high-voltage level shifting circuit (002) in sequence, the output of the high-side driving circuit GH is connected to the gate of the high-side power tube MH in the high-side and low-side power tube circuit (004), the drain of the high-side power tube MH is connected to the positive end of the input power supply VIN, The negative end of the input power supply VIN is grounded, and the pulse control signal generated by the previous stage MCU chip or controller is used as the input signal VPWM to connect the input end of the low-side driving circuit GL in the driving stage circuit (003). The output of the low-side driving circuit GL is connected to the gate of the low-side power tube ML in the high-low side power tube circuit (004). The source of the low-side power tube ML is grounded. The source of the high-side power tube MH and the drain of the low-side power tube ML are connected to one end of the inductor L in the load circuit (005) to generate a floating ground voltage VS. The other end of the inductor L is connected to one end of the capacitor CO and one end of the resistor R. The other end of the capacitor CO and the other end of the resistor R are both grounded. The invention is characterized in that: a high-side dead zone control circuit (006) is provided to replace the fixed dead zone generating circuit (001); the high-side dead zone control circuit (006) comprises a current zero-crossing detection circuit (007), a high-side zero-crossing detection circuit (008), a voltage step-down level shift circuit (009), a setting delay circuit module (010), a low-level effective SR trigger SR1, a high-level effective SR trigger SR2, and a three-input OR gate OR; the input end of the current zero-crossing detection circuit (007) and the input end of the high-side zero-crossing detection circuit (008) are both connected to a floating ground voltage VS; the output control signal V1 of the current zero-crossing detection circuit (007) is connected to a set input end S of the SR trigger SR1; the reset input end R of the SR trigger SR1 is connected to an input signal VPWM; the output of the SR trigger SR1 is connected to a reset input end R of the SR trigger SR1; and the output of the SR trigger SR1 is connected to a reset input end S of the SR trigger SR1. The output signal H_CCM at the Q end is connected to one input end of the three-input OR gate OR; the output control signal V2 of the high-side zero-crossing detection circuit (008) is connected to the input end of the step-down level shift circuit (009), the output control signal V3 of the step-down level shift circuit (009) is connected to the set input end S of the SR trigger SR2, the reset input end R of the SR trigger SR2 is connected to the input signal VPWM, and the output signal H_FCCM at the output end Q of the SR trigger SR2 is connected to the other input end of the three-input OR gate OR; the input end of the setting delay circuit module (010) is connected to the input signal VPWM, the output of the setting delay circuit module (010) is connected to the third input end of the three-input OR gate OR, and the output signal H_DRH of the three-input OR gate OR is used as the input signal of the high-voltage level shift circuit (002); The current zero-crossing detection circuit (007) comprises a constant current source Idc1, PMOS tubes MP1, MP2, MP3 and MP4, NMOS tubes MN1, MN2, MN3, MN4, MN5 and MNH1; the input end of the constant current source Idc1 is connected to a chip power supply VCC, and the output end of the constant current source Idc1 is connected to the drain and gate of the NMOS tube MN1, the gate of the NMOS tube MN2 and the gate of the NMOS tube MN3; the source of the NMOS tube MN1 and the source of the NMOS tube MN2 are both grounded, the drain of the NMOS tube MN2 is connected to the drain and gate of the PMOS tube MP1, the gate of the PMOS tube MP2 and the gate of the NMOS tube MP3, and the source of the PMOS tube MP1, the source of the PMOS tube MP2, the source of the PMOS tube MP3 and the source of the PMOS tube MP4 are all connected The chip power supply VCC, the drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN3 and the gate of the NMOS tube MN4, the source of the NMOS tube MN3 is connected to the source of the NMOS tube MNH1, the drain of the NMOS tube MNH1 is connected to the floating ground voltage VS, the gate of the NMOS tube MNH1 is connected to the input signal VPWM, the sources of the PMOS tube MP3 and the PMOS tube MP4 are both connected to the chip power supply voltage VCC, the drain of the PMOS tube MP3 is interconnected with the gate of the PMOS tube MP4, the drain of the NMOS tube MN4 and the gate of the NMOS tube MN5, the source of the NMOS tube MN4 and the source of the NMOS tube MN5 are both grounded, and the drain of the PMOS tube MP4 and the drain of the NMOS tube MN5 are interconnected as the output end of the current zero-crossing detection circuit (007) to output the control signal V1; The high-side zero-crossing detection circuit (008) comprises a constant current source Idc2, a PMOS tube MP5, an NMOS tube MN6, MN7 and MNH2 and a comparator CMP; the input end of the constant current source Idc2 and the source of the PMOS tube MP5 are both connected to a chip floating power supply VB, the output end of the constant current source Idc2 is connected to the drain and gate of the NMOS tube MN6 and the gate of the NMOS tube MN7, the source of the NMOS tube MN6 and the source of the NMOS tube MN7 are both connected to a floating ground voltage VS, the drain of the NMOS tube MN7 is connected to the gate and drain of the PMOS tube MP5 and the negative end of the comparator CMP and the source of the NMOS tube MNH2, the gate of the NMOS tube MNH2 and the positive end of the comparator CMP are both connected to the floating ground voltage VS, the drain of the NMOS tube MNH2 is connected to the input voltage VIN, and the output end of the comparator CMP serves as the output end of the high-side zero-crossing detection circuit (008) outputting a control signal V2.

2. The high-side soft switch control system of the buck synchronous rectifier circuit under light load conditions according to claim 1, Features: The current zero-crossing detection circuit (007), the high-side zero-crossing detection circuit (008), the step-down level shift circuit (009), the setting delay circuit module (010), the low-level effective SR trigger SR1, the high-level effective SR trigger SR2 and the three-input OR gate OR in the high-side dead zone control circuit (006) cooperate with each other to realize automatic adjustment of the CCM and FCCM control modes according to the changes of the input voltage VIN and the load current, thereby realizing low diode conduction loss under the CCM control mode and soft opening of the power tube MH under the FCCM mode; according to whether the current of the inductor L has a backflow phenomenon, that is, whether the inductor current crosses zero, the current zero-crossing detection circuit The circuit (007) and the high-side zero-crossing detection circuit (008) output different control signals V1 and V2; the control signal V1 is converted into a gate control signal VGH for turning on the power tube MH in the CCM mode after passing through the SR trigger SR1, the three-input OR gate OR, the high-voltage level shift circuit (002) and the high-side driving circuit GH in the output stage circuit (003); similarly, the control signal V2 is converted into a gate control signal VGH for turning on the power tube MH in the FCCM mode after passing through the step-down level shift circuit (009), the SR trigger SR2, the three-input OR gate OR, the high-voltage level shift circuit (002) and the high-side driving circuit GH in the output stage circuit (003).

3. The high-side soft switch control system of the buck synchronous rectifier circuit under light load conditions according to claim 2, Features: The control process of the system is as follows: CCM control process: When the output is under heavy load condition, the output load current is large, and there is no backflow phenomenon of the inductor current. After the power tube MH is not turned on and the power tube ML is turned off, the current zero-crossing detection circuit (007) determines whether the inductor current has a backflow phenomenon by detecting whether the VS voltage has a negative voltage; If the VS voltage has a negative voltage, it means that the body diode of the power tube ML is performing a freewheeling function, so the inductor current will not flow back, and the rectifier circuit is in CCM control mode; the current zero-crossing detection circuit (007) detects the falling edge of the negative voltage VS when the body diode of the power tube ML is freewheeling as the control signal V1 for controlling the power tube MH to turn on, the input signal VPWM is connected to the reset terminal R of the SR trigger SR1, and is used as the control signal for controlling the power tube MH to turn off, and the output terminal Q of the SR trigger SR1 outputs the control signal H_CCM, which is converted into the gate control signal VGH of the power tube MH through the three-input OR gate OR, the high-voltage level shift circuit (002) and the high-side drive circuit GH in the drive stage circuit (003); FCCM control process 1: When the output is under light load condition, the output load current is small, and the inductor current will have a backflow phenomenon. After the power tube MH is not turned on and the power tube ML is turned off, the current zero-crossing detection circuit (007) determines whether the inductor current has a backflow phenomenon by detecting whether the VS voltage has a negative voltage; If there is no negative voltage in the VS voltage, it means that the inductor current will flow back, and the flow back current charges the node parasitic capacitance, and the node voltage VS starts to rise, then the rectifier circuit is in FCCM control mode, the high-side zero-crossing detection circuit (008) detects whether the node voltage VS is charged to a level greater than the input voltage VIN, and uses the corresponding rising edge when the node voltage VS is equal to the input voltage VIN as the control signal V2 for controlling the power tube MH to turn on; the control signal V2 in the high-voltage domain is converted into the control signal V3 in the low-voltage domain through the step-down level shift circuit (009); the input signal VPWM is connected to the reset terminal R of the SR trigger SR2 as the control signal for controlling the power tube MH to turn off, and the output terminal Q of the SR trigger SR2 outputs the control signal H_FCCM through the SR trigger SR2, the three-input OR gate OR, the high-voltage level shift circuit (002) and the high-side drive circuit GH in the drive stage circuit (003) to become the gate control signal VGH for turning on the power tube MH; FCCM control process 2: When the output is under light load condition, the output load current is very small, that is, the time required for the node voltage VS to rise to the input voltage VIN is greater than the load current corresponding to 200ns set according to different system frequencies, and the inductor current will have a backflow phenomenon. After the power tube MH is not turned on and the power tube ML is turned off, the current zero-crossing detection circuit (007) determines whether the inductor current has a backflow phenomenon by detecting whether the VS voltage has a negative voltage; If there is no negative voltage in the VS voltage, it means that the inductor current will flow back, and the flow back current will charge the node parasitic capacitance, and the node voltage VS will start to rise, and the rectifier circuit is in FCCM control mode; however, when the output load current is very small, the flow back current will also be very small, resulting in a very small rising slope of the node voltage VS, so the time required for the node voltage VS to rise to equal the input voltage VIN will be longer, resulting in the output signal V2 of the high-side zero-crossing detection circuit (008) switching from a low level to a high level later than the control signal H_FD output by the setting delay circuit module 010. Due to the limitation of the operating frequency of the rectifier circuit system, it is necessary to set a limit on the node voltage VS rising time. The setting delay circuit module 010 delays the input signal VPWM to ts=200ns set according to different system frequencies, and outputs the control signal H_FD. The reset signal of the SR trigger SR2 is determined by the input signal VPWM. The control signal H_FD is converted into the gate control signal VGH for turning on the power tube MH through the three-input OR gate OR, the high-voltage level shift circuit (002) and the high-side drive circuit GH in the drive stage circuit (003).

4. The high-side soft switch control system of the buck synchronous rectifier circuit under light load conditions according to claim 1, Features: MP1, MP2, MP3 and MP4 in the current zero-crossing detection circuit (007) are all low-voltage PMOS tubes, MN1, MN2, MN3, MN4 and MN5 are all low-voltage NMOS tubes, and MNH1 is a high-voltage NMOS tube.

5. The high-side soft switch control system of the buck synchronous rectifier circuit under light load conditions according to claim 1, Features: MP5 in the high-side zero-crossing detection circuit (008) is a low-voltage PMOS tube, MN6 and MN7 are both low-voltage NMOS tubes, and MNH2 is a high-voltage NMOS tube.

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