Semiconductor structure, method for manufacturing the same, and method for detecting abnormal resistance value

Abstract

The application provides a semiconductor structure, a preparation method thereof and a resistance abnormality detection method. In the semiconductor structure provided by the application, the third conductive layer in the substrate is connected with the first conductive layer, and the third conductive layer is extended, so that the extended third conductive layer and the second conductive layer are respectively connected to the first signal end and the second signal end, and the first conductive layer and the second conductive layer are connected in series during the detection process. At this time, when any one of the first conductive layer and the second conductive layer has resistance abnormality, the resistance abnormality can be reflected in the series resistance with the same amplitude, and can be detected, so that the detection sensitivity of the resistance abnormality is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure, a preparation method thereof and a resistance abnormality detection method. BACKGROUND

[0002] In the process of semiconductor devices, a corresponding semiconductor structure (for example, a detection structure) is usually prepared in the process of device manufacturing or after the completion of device manufacturing, so as to perform detection according to the semiconductor structure, so that whether the formed device structure meets the process requirements can be judged based on the obtained detection result. Specifically, one evaluation item for the performance of a film layer is whether the resistance thereof is abnormal, and for this purpose, a corresponding semiconductor structure can be set to perform resistance judgment. However, the existing semiconductor structure for performing resistance judgment is relatively cumbersome when the stacked structure has two or more conductive layers. SUMMARY

[0003] The purpose of the present application is to provide a semiconductor structure, so as to conveniently and sensitively detect whether the conductive layer in the stacked structure is abnormal in resistance.

[0004] To solve the above technical problems, the present application provides a semiconductor structure, comprising: a first conductive layer and a second conductive layer, which are stacked on the surface of a substrate; a third conductive layer formed in a recess of the substrate, the third conductive layer is located below the end of the first conductive layer and connected with the first conductive layer, and the third conductive layer also extends out of the first conductive layer. Wherein, the part of the third conductive layer extending out is used to connect a first signal terminal, and the second conductive layer is used to connect a second signal terminal.

[0005] The present application also provides another semiconductor structure, comprising: a substrate; a recess in the substrate; a third conductive layer in the recess; a first conductive layer and a second conductive layer, which are stacked on the surface of the substrate from bottom to top and partially cover the third conductive layer, the first conductive layer is connected with the third conductive layer; and a first contact plug and a second contact plug, the first contact plug is connected with the third conductive layer, and the second contact plug is connected with the second conductive layer.

[0006] Optionally, the semiconductor structure further comprises a barrier layer, the barrier layer partially covers the third conductive layer, and the part of the third conductive layer not covered by the barrier layer is connected with the first conductive layer.

[0007] Optionally, the sidewall of the first conductive layer and the sidewall of the second conductive layer are aligned.

[0008] Optionally, the materials of the first conductive layer and the third conductive layer are the same.

[0009] Optionally, the material of the first conductive layer comprises polysilicon, and the material of the second conductive layer comprises metal.

[0010] Optionally, the semiconductor structure further comprises a first contact plug and a second contact plug, a bottom of the first contact plug is connected to the third conductive layer, and a bottom of the second contact plug is connected to the second conductive layer.

[0011] Optionally, an isolation structure is formed in the substrate, the third conductive layer is formed in the isolation structure, and the first conductive layer and the second conductive layer are stacked above the isolation structure.

[0012] Optionally, at least part of a top surface of the third conductive layer is lower than a top surface of the substrate.

[0013] Optionally, a top of the third conductive layer has a recess, an end of the first conductive layer extends into the recess of the third conductive layer to be connected to the third conductive layer, and a top surface of the first conductive layer appears as an uneven surface.

[0014] The present application also provides a resistance abnormality detection method, comprising: providing the semiconductor structure as described above, and applying a test voltage between the first signal end and the second signal end to obtain a corresponding test current; or applying a test current between the first signal end and the second signal end to obtain a corresponding test voltage; and obtaining the resistance between the first signal end and the second signal end according to the obtained test voltage and test current.

[0015] Optionally, the resistance abnormality detection method further comprises: comparing the measured resistance between the first signal end and the second signal end with a standard resistance value to determine whether there is a resistance abnormality.

[0016] The present application also provides a semiconductor structure preparation method, comprising: forming a recess in a substrate, and filling a third conductive layer in the recess; and stacking a first conductive layer and a second conductive layer on a surface of the substrate, an end of the first conductive layer partially covers the third conductive layer to be connected to the third conductive layer, and the third conductive layer further extends from below the end of the first conductive layer.

[0017] Optionally, before forming the first conductive layer and the second conductive layer, a barrier layer is formed on the surface of the substrate, and an opening is formed in the barrier layer to expose the surface of the substrate and part of the third conductive layer. The method for forming the first conductive layer and the second conductive layer comprises: sequentially forming a first conductive material layer and a second conductive material layer, the first conductive material layer filling the opening; and etching the second conductive material layer and the first conductive material layer sequentially and stopping on the barrier layer.

[0018] Optionally, the method for preparing the semiconductor structure further comprises: forming a first contact plug and a second contact plug, the first contact plug being above the third conductive layer and connected to the third conductive layer, and the second contact plug being above the second conductive layer and connected to the second conductive layer.

[0019] The application further provides a method for preparing a semiconductor device, comprising: providing a substrate, the substrate having a device region and a test region; forming a recess in the substrate in the test region and filling the recess with a third conductive layer; and simultaneously forming a first conductive layer and a second conductive layer stacked in the device region and the test region. In the device region, the first conductive layer and the second conductive layer are stacked to form bit lines of a memory. In the test region, an end portion of the first conductive layer covers the third conductive layer to be connected to the third conductive layer, and the third conductive layer further extends from below the end portion of the first conductive layer.

[0020] Optionally, before forming the first conductive layer and the second conductive layer, a barrier layer is formed on the surface of the substrate, and a first opening and a second opening are formed in the barrier layer, the first opening being in the device region and defining a bit line contact window, and the second opening exposing part of the third conductive layer. The first conductive layer in the device region further fills the bit line contact window, and the first conductive layer in the test region covers the region of the second opening and is connected to the third conductive layer.

[0021] Optionally, the method for forming the first conductive layer and the second conductive layer comprises: sequentially forming a first conductive material layer and a second conductive material layer on the substrate, and etching the second conductive material layer and the first conductive material layer sequentially and stopping on the barrier layer.

[0022] In the semiconductor structure provided by the present application, by arranging the third conductive layer in the substrate and connecting the first conductive layer in the stack structure on the surface of the substrate with the third conductive layer, the third conductive layer extends out of the first conductive layer, so that the extended third conductive layer and the second conductive layer are respectively connected to the first signal terminal and the second signal terminal, so that the conductive layers in the stack structure are connected in series during the test process (i.e., the first conductive layer and the second conductive layer are connected in series during the test process), and the total resistance between the first signal terminal and the second signal terminal detected at this time is the series resistance of the conductive layers in the stack structure. When any conductive layer in the stack structure has abnormal resistance (for example, any of the first conductive layer and the second conductive layer has abnormal resistance), it can be reflected in the series resistance with the same amplitude, so that it can be detected sensitively. Therefore, when the semiconductor structure provided by the present application is used for resistance abnormality detection, whether any conductive layer in the stack structure has abnormal resistance can be inferred sensitively. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 It is a schematic diagram of a semiconductor structure.

[0024] Figure 2 It is a schematic diagram of a semiconductor structure in an embodiment of the present application.

[0025] Figure 3 It is a schematic diagram of another semiconductor structure in an embodiment of the present application.

[0026] Figures 4a-4f It is a schematic diagram of a semiconductor structure in an embodiment of the present application in the preparation process.

[0027] Figures 5a-5d It is a schematic diagram of another semiconductor structure in an embodiment of the present application in the preparation process.

[0028] Among them, the reference signs are as follows:

[0029] 10 / 100 - substrate;

[0030] 110 - isolation structure;

[0031] 21 / 210 - first conductive layer;

[0032] 22 / 220 - second conductive layer;

[0033] 230 - top cover layer;

[0034] 240 - side wall;

[0035] 300 - third conductive layer;

[0036] 410 - first conductive plug;

[0037] 420 - second conductive plug;

[0038] 500 - barrier layer;

[0039] 600 - dielectric layer. DETAILED DESCRIPTION

[0040] As described in the background, the existing semiconductor structure for resistance determination is relatively complicated when there are two or more conductive layers in the stacked structure. For example, each conductive layer can be detected separately, so that the detection structure needs to be set one by one, and the detection determination needs to be performed one by one, which is not only high in cost but also complicated in process.

[0041] Therefore, a semiconductor structure is provided for determining whether there is a resistance abnormality of the conductive layer in the stacked structure. For example Figure 1 As shown, the detection structure includes a stacked structure with a first conductive layer 21 and a second conductive layer 22 formed on a substrate 10, and a first signal end V- and a second signal end V+ connected to both ends of the stacked structure. When determining the resistance abnormality, a voltage signal is applied between the first signal end V- and the second signal end V+, and a feedback signal (for example, a current signal) between the first signal end V- and the second signal end V+ is obtained, and then the resistance value between the first signal end V- and the second signal end V+ can be obtained according to the voltage-current information.

[0042] However Figure 1 In the semiconductor structure shown, the total resistance between the first signal end V- and the second signal end V+ corresponds to the parallel resistance between the first conductive layer 21 and the second conductive layer 22, that is, 1 / R = 1 / R1 + 1 / R2, where R is the total resistance, R1 is the resistance of the first conductive layer 21, and R2 is the resistance of the second conductive layer 22. Therefore, when any one of the first conductive layer 21 and the second conductive layer 22 has a resistance abnormality, the influence on the parallel total resistance is not great, so that the obtained parallel resistance cannot sensitively capture the resistance change of the first conductive layer 21 and the second conductive layer 220.

[0043] Therefore, the present application provides a novel semiconductor structure, which comprises: a first conductive layer and a second conductive layer stacked; and a third conductive layer formed below the end of the first conductive layer and connected to the first conductive layer. The third conductive layer extends from the first conductive layer for connecting a first signal end, and the top surface of the second conductive layer is used for connecting a second signal end.

[0044] That is, the semiconductor structure provided by the present application uses the third conductive layer in the substrate to laterally lead out the first conductive layer in the stacked structure, so that the third conductive layer and the second conductive layer can be connected to the first signal end and the second signal end respectively, and thus the conductive layers in the stacked structure are connected in series when detection is performed, so that the total resistance between the first signal end and the second signal end obtained by detection is the total series resistance in the stacked structure. When any conductive layer in the stacked structure has abnormal resistance (for example, any of the first conductive layer and the second conductive layer has abnormal resistance), it can be reflected in the series resistance, so that it can be sensitively detected.

[0045] The semiconductor structure provided by the present application and the preparation method and the abnormal resistance judgment method thereof will be further described in detail below in combination with the drawings and specific embodiments. According to the following description, the advantages and characteristics of the present application will be more apparent. It should be noted that the drawings are very simplified and use non-precise proportions, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. It should be recognized that relative terms such as "above", "below", "top", "bottom", "upper" and "lower" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of the elements in addition to the orientations depicted in the drawings. For example, if the device is inverted with respect to the view in the drawing, the element described as "above" another element will now be "below" the element.

[0046] Figure 2 A schematic diagram of a semiconductor structure in an embodiment of the present application is shown in FIG. 1. Figure 2 As shown in FIG. 1, the semiconductor structure includes a stacked structure disposed on the surface of a substrate 100, and the stacked structure includes at least two conductive layers stacked and electrically connected.

[0047] Specifically, the at least two conductive layers in the stacked structure can include a first conductive layer 210 and a second conductive layer 220. In this embodiment, the first conductive layer 210 and the second conductive layer 220 are in contact connection, that is, the top surface of the first conductive layer 210 and the bottom surface of the second conductive layer 220 are in contact. However, in other embodiments, other conductive layers can be disposed between the first conductive layer and the second conductive layer, and the first conductive layer, the other conductive layers and the second conductive layer are sequentially stacked and electrically connected.

[0048] Further, at least two conductive layers in the stack structure can be formed based on a same patterning process. For example, the first conductive layer 210 and the second conductive layer 220 can be formed based on a same patterning process, and the sidewall of the first conductive layer 210 and the sidewall of the second conductive layer 220 are arranged in alignment. In this embodiment, the stack structure further includes a top cover layer 230 covering the conductive layers thereunder. In a specific example, the conductive layers thereunder can be etched based on the top cover layer 230 as a mask to complete the patterning process, and the top cover layer 230 is retained after the patterning to cover the conductive layers thereunder. The material of the first conductive layer 210 includes, for example, polysilicon, the material of the second conductive layer 220 can include metal (e.g., tungsten), and the material of the top cover layer 230 can include silicon nitride and / or silicon oxide.

[0049] With reference to the foregoing Figure 2 As shown, the semiconductor structure further includes a third conductive layer 300 formed in a recess of the substrate 100. The width dimension of the third conductive layer 300 can be smaller than the width dimension of the first conductive layer 210. In a specific scheme, the material of the third conductive layer 300 can be the same as the material of the first conductive layer 210, for example, both of which include polysilicon.

[0050] In this embodiment, an isolation structure 110 can be formed in the substrate 100, and the third conductive layer 300 can be formed in the isolation structure 110, and the stack structure can be arranged above the isolation structure 110.

[0051] Further, the bottommost conductive layer in the stack structure is connected to the third conductive layer 300. Specifically, the third conductive layer 300 is located below the end of the stack structure and extends from the end of the stack structure, so that the third conductive layer 300 extends out of the stack structure. In this embodiment, the bottommost conductive layer in the stack structure is the first conductive layer 210, and the third conductive layer 300 is located below the end of the first conductive layer 210, so that the end of the first conductive layer 210 covers the third conductive layer 300 to connect the first conductive layer 210, and the part of the third conductive layer 300 not covered by the first conductive layer 210 extends out of the first conductive layer 210.

[0052] The third conductive layer 300 extends to connect a first signal terminal, and a top surface of the second conductive layer 220 is used to connect a second signal terminal, so that a signal can be applied to the first signal terminal and the second signal terminal, and a resistance state between the first signal terminal and the second signal terminal can be obtained according to a feedback signal fed back. In the embodiment, the first signal terminal and the second signal terminal can be connected to a negative electrode and a positive electrode of a power supply, respectively.

[0053] Further, the semiconductor structure can further include a barrier layer 500, the barrier layer 500 partially covers the third conductive layer 300, and another part of the third conductive layer 300 is exposed from the barrier layer 500. The part of the third conductive layer 300 not covered by the barrier layer 500 is located below the stack structure to connect the bottommost conductive layer (i.e., the first conductive layer 210) of the stack structure. In the embodiment, the stack structure also partially covers the barrier layer 500, so that the end of the stack structure is located on the barrier layer 500, so that the barrier layer 500 can be used as an etching stop layer when the stack structure is prepared, and the patterning accuracy of the stack structure is improved. In particular, when the material of the first conductive layer 210 in the stack structure is the same as the material of the third conductive layer 300, the third conductive layer 300 extending out can be protected by the barrier layer 500 from being affected.

[0054] Further, a side wall 240 is also formed on the sidewall of the stack structure. In the embodiment, the side wall 240 covers the sidewall of the first conductive layer 210, the second conductive layer 220, and the top covering layer 230. In addition, the bottom of the side wall 240 is located on the barrier layer 500, so that the substrate 100 can be protected during the preparation of the side wall 240.

[0055] Continuing to refer to Figure 2 The semiconductor structure also includes a first contact plug 410 and a second contact plug 420. The bottom of the first contact plug 410 is connected to the third conductive layer 300, and the bottom of the first contact plug 410 is connected to the part of the third conductive layer extending out. The bottom of the second contact plug 420 is connected to the second conductive layer 220. The first contact plug 410 is used to connect the first signal terminal, and the second contact plug 420 is used to connect the second signal terminal.

[0056] In this embodiment, the bottom of the first conductive plug 410 extends into the third conductive layer 300 to connect with the third conductive layer 300, so as to reduce the contact resistance between the first conductive plug 410 and the third conductive layer 300. In an alternative embodiment, a metal silicide layer is further provided under the bottom of the first conductive plug 410 to further reduce the contact resistance between the first conductive plug 410 and the third conductive layer 300. In addition, the bottom of the second conductive plug 420 can also extend into the second conductive layer 220 to connect with the second conductive layer 220.

[0057] In addition, a dielectric layer 600 is further formed on the substrate 100, which covers the stack structure and the third conductive layer 300, wherein the material of the dielectric layer 600 includes, for example, silicon oxide. In addition, the second conductive plug 420 penetrates the dielectric layer 600 and the top cover layer 230 in sequence to connect with the second conductive layer 220, and the first conductive plug 421 penetrates the dielectric layer 600 and the barrier layer 500 in sequence to connect with the third conductive layer 300.

[0058] In Figure 2 In the example shown, the third conductive layer 300 fills in the substrate 100, and the top surface of the third conductive layer 300 is flush with the top surface of the substrate 100. In other examples, at least part of the top surface of the third conductive layer 300 is further sunken relative to the top surface of the substrate 100, for example Figure 3 As shown, the top of the third conductive layer 300 has a recess, which is located below the stack structure, and the recess can be formed on the top of the third conductive layer 300 by a back etching process.

[0059] Continuing to refer to Figure 3 As shown, the end of the first conductive layer 210 also extends into the recess of the third conductive layer 300 to connect with the third conductive layer 300. In this embodiment, the first conductive layer 210 conformally covers the third conductive layer 300, so that the end of the first conductive layer 210 is sunken, and in turn, the top surface of the first conductive layer 210 is correspondingly sunken to present an uneven surface, and the second conductive layer 220 and the top cover layer 230 are also sunken to conformally cover the top surface of the first conductive layer 210. In this embodiment, the barrier layer 500 covers the recessed part of the third conductive layer 300, and the end of the first conductive layer 210 is located on the barrier layer in the recess.

[0060] The semiconductor structure as described above can be used for resistance abnormality detection of the conductive layers (including the first conductive layer 210 and the second conductive layer 220) in the stack structure.

[0061] Specifically, the method for detecting resistance abnormality using the semiconductor structure as described above includes: applying a test voltage between the first signal terminal and the second signal terminal, and obtaining a corresponding test current, and then the total resistance between the first signal terminal and the second signal terminal can be obtained according to the obtained test voltage and test current. Alternatively, the method for detecting resistance abnormality using the semiconductor structure as described above includes: applying a test current between the first signal terminal and the second signal terminal, and obtaining a corresponding test voltage, and then the total resistance between the first signal terminal and the second signal terminal can be obtained according to the obtained test voltage and test current.

[0062] The total resistance between the first signal terminal and the second signal terminal is specifically the series resistance of the conductive layers in the stacked structure, that is, the connection between at least two conductive layers in the stacked structure is based on the series connection mode, for example Figure 2 and Figure 3 In the scheme shown in Figure 2 and Figure 3 When the first conductive layer 210 or the second conductive layer 220 has resistance abnormality, it will cause a large abnormal fluctuation of the series resistance between the first signal terminal and the second signal terminal and be detected.

[0063] In further schemes, the measured resistance between the first signal terminal and the second signal terminal can be compared with a standard resistance value to determine whether there is resistance abnormality. The standard resistance is specifically the series resistance between the first signal terminal and the second signal terminal when all the conductive layers in the stacked structure have no resistance abnormality.

[0064] The preparation method of the semiconductor structure as described above will be described in detail below. For example, the semiconductor structure shown in Figure 2 will be described in detail, and the semiconductor structure shown in Figures 4a-4f may be specifically referred to. Figures 4a-4f is a structure diagram of a semiconductor structure in the preparation process in an embodiment of the present application.

[0065] First, referring to Figure 4a , a recess is formed in a substrate 100, and a third conductive layer 300 is filled in the recess. The third conductive layer 300 will be connected with the conductive layer located at the bottom layer in the subsequent formed stacked structure, and the material of the third conductive layer 300 includes, for example, polysilicon. In this embodiment, an isolation structure 110 is also formed in the substrate 100, and the recess can be formed in the isolation structure 110, so that the third conductive layer 300 is also located in the isolation structure 110.

[0066] Among the optional solutions, refer to Figure 4b As shown, prior to forming the stacked structure, the process further includes forming a barrier layer 500 on the surface of the substrate 100, wherein an opening is formed in the barrier layer 500, the opening exposing the substrate surface and a portion of the third conductive layer 300. In subsequent processes, the stacked structure can cover the opening area, thereby allowing the bottom conductive layer in the stacked structure to connect to the third conductive layer 300 exposed within the opening.

[0067] Next, refer to Figure 4c and Figure 4d As shown, a stacked structure is formed on the surface of the substrate. Specifically, this includes: firstly, forming a first conductive material layer 210a, a second conductive material layer 220a, and a dielectric material layer 230a sequentially on the surface of the substrate 100; then, performing a patterning process to form the stacked first conductive layer 210, the second conductive layer 220, and a top cover layer 230, with the first conductive layer 210 corresponding to the bottom layer of the stacked structure. Furthermore, the first conductive layer 210 partially covers and connects to the third conductive layer 300, and the third conductive layer 300 extends below the end of the first conductive layer 210. The patterning process may include: forming a patterned photoresist layer (not shown) on the dielectric material layer 230a; then, using the photoresist layer as a mask, sequentially etching the dielectric material layer, the second conductive material layer, and the first conductive material layer, stopping the etching on the barrier layer 500 to form the stacked structure.

[0068] It should be noted that during the etching process of the conductive material layer, the barrier layer 500 can be used to effectively protect the third conductive layer 300. In particular, when the bottom conductive material layer and the third conductive layer 300 are made of the same material, the barrier layer 500 can effectively prevent the third conductive layer 300 from being consumed.

[0069] Next, refer to Figure 4e As shown, after forming the stacked structure, the method further includes forming a sidewall 240 on the sidewall of the stacked structure. The sidewall 240 is correspondingly formed on the barrier layer 500.

[0070] Next, refer to Figure 4fAs shown, the method for preparing the semiconductor structure further comprises: forming a first contact plug 410 and a second contact plug 420, the first contact plug 410 is above and connected to the third conductive layer 300, and the second contact plug 420 is above and connected to the second conductive layer 220. In this embodiment, the bottom of the first conductive plug 410 further extends into the third conductive layer 300, and the bottom of the second conductive plug 420 further extends into the second conductive layer 220.

[0071] Specifically, before forming the first contact plug 410 and the second contact plug 420, the method further comprises: forming a dielectric layer 600 on the surface of the substrate 100, the dielectric layer 600 covers the stack structure and the substrate surface. And the first contact plug 410 connects the third conductive layer 300 by penetrating the dielectric layer and the barrier layer 500; the second contact plug 420 connects the second conductive layer 220 by penetrating the dielectric layer and the top cover layer 230.

[0072] Next, the semiconductor structure shown in Figure 3 The semiconductor structure shown in Figures 5a-5d The method for preparing the semiconductor structure is described, wherein Figures 5a-5d is a schematic diagram of another semiconductor structure in the preparation process of an embodiment of the present application.

[0073] First, referring to Figure 5a As shown, a recess is formed in a substrate 100, and a third conductive layer 300 is filled in the recess. Among them, the third conductive layer 300 will be connected to the conductive layer located at the bottom layer in the subsequent formed stack structure, and the material of the third conductive layer 300 includes, for example, polysilicon. In this embodiment, an isolation structure 110 is also formed in the substrate 100, and the recess can be formed in the isolation structure 110, so that the third conductive layer 300 is also located in the isolation structure 110.

[0074] Further, the top of the third conductive layer 300 also forms a recess, so that part of the top surface of the third conductive layer 300 is recessed relative to the substrate surface. Specifically, the recess can be formed on the top of the third conductive layer 300 by etching process.

[0075] In an optional scheme, referring to Figure 5b As shown, before forming the stack structure, the method further comprises: forming a barrier layer 500 on the surface of the substrate 100, the barrier layer 500 forms an opening, and the opening exposes the substrate surface and part of the third conductive layer 300. In this embodiment, the barrier layer 500 covers part of the surface of the recess of the third conductive layer 300.

[0076] Next, refer to Figure 5c As shown, a stacked structure is formed on the surface of the substrate. Specifically, this includes: firstly, forming a first conductive material layer, a second conductive material layer, and a dielectric material layer sequentially on the surface of the substrate 100; then, performing a patterning process to form a stacked first conductive layer 210, a second conductive layer 220, and a top cover layer 230, with the first conductive layer 210 corresponding to the bottom layer of the stacked structure. Furthermore, the first conductive layer 210 partially covers and connects to the third conductive layer 300, and the third conductive layer 300 extends from below the end of the first conductive layer 210.

[0077] The patterning process may include: forming a patterned photoresist layer (not shown in the figure) on a dielectric material layer; then, using the photoresist layer as a mask, sequentially etching the underlying film layers, stopping the etching on the barrier layer 500 to form the stacked structure. It should be noted that the barrier layer 500 can effectively protect the third conductive layer 300 during the etching of the conductive material layer. In particular, when the bottom conductive material layer and the third conductive layer 300 are made of the same material, the barrier layer 500 can effectively prevent the third conductive layer 300 from being consumed.

[0078] Furthermore, after forming the stacked structure, the method further includes forming a sidewall 240 on the sidewall of the stacked structure. The sidewall 240 is correspondingly formed on the barrier layer 500.

[0079] Next, refer to Figure 5d As shown, the method for fabricating the semiconductor structure further includes: forming a first contact plug 410 and a second contact plug 420, wherein the first contact plug 410 is located above and connected to the third conductive layer 300, and the second contact plug 420 is located above and connected to the second conductive layer 220. In this embodiment, the bottom of the first conductive plug 410 further extends into the third conductive layer 300, and the bottom of the second conductive plug 420 further extends into the second conductive layer 220.

[0080] Specifically, before forming the first contact plug 410 and the second contact plug 420, the method further includes: forming a dielectric layer 600 on the surface of the substrate 100, the dielectric layer 600 covering the stacked structure and the substrate surface. Furthermore, the first contact plug 410 penetrates the dielectric layer and the barrier layer 500 to connect to the third conductive layer 300; the second contact plug 420 penetrates the dielectric layer and the top cover layer 230 to connect to the second conductive layer 220.

[0081] In addition, the embodiment also provides a semiconductor device manufacturing method, part of the manufacturing process of the semiconductor device coincides with the manufacturing process of the semiconductor structure, and the parameters of the formed film layers in the same process are generally the same.

[0082] For example, the stack structure in the semiconductor structure and the bit line in the semiconductor device are simultaneously prepared in the same process, so that the parameters of the film layers of the stack structure in the semiconductor structure and the parameters of the film layers of the conductive lines in the semiconductor device are the same or close. In this way, when the resistance abnormality detection is performed on the conductive layer in the stack structure, it can be directly judged whether the bit line in the semiconductor device has resistance abnormality. Specifically, the semiconductor device manufacturing method comprises the following steps.

[0083] The first step is to provide a substrate, and the substrate has a device area and a test area. The device area is the formation area of the semiconductor device, and the test area is the formation area of the semiconductor structure.

[0084] The second step is to form a recess in the substrate in the test area, and fill the third conductive layer in the recess.

[0085] The third step is to simultaneously stack structures in the device area and the test area, including simultaneously forming the first conductive layer and the second conductive layer in the device area and the test area.

[0086] Taking a memory as an example, in the device area, the first conductive layer and the second conductive layer can constitute the bit line of the memory. In the test area, the end part of the first conductive layer covers the third conductive layer to connect the third conductive layer, and the third conductive layer also extends from below the end part of the first conductive layer.

[0087] Further, before forming the first conductive layer and the second conductive layer, it also includes forming a barrier layer on the surface of the substrate, the barrier layer has a first opening and a second opening, the first opening is located in the device area and defines a bit line contact window, and the second opening exposes part of the third conductive layer. When the first conductive layer and the second conductive layer are formed, the first conductive layer in the device area also fills the bit line contact window to form a bit line contact, and the first conductive layer in the test area covers the area of the second opening to connect the third conductive layer.

[0088] Specifically, the method for forming the first conductive layer and the second conductive layer comprises: sequentially forming a first conductive material layer and a second conductive material layer on the substrate; and performing an etching process to sequentially etch the second conductive material layer and the first conductive material layer, and to stop etching on the barrier layer. In this way, the first conductive layer and the second conductive layer are simultaneously formed in the device region and the test region.

[0089] In summary, in the semiconductor structure provided by the embodiment, the third conductive layer connected to the bottommost conductive layer is arranged in the substrate, and the third conductive layer extends out, so that the extended third conductive layer and the second conductive layer can be respectively connected to the first signal end and the second signal end, and the conductive layers in the stacked structure are connected in series during the testing process, and then the existence of abnormality of the conductive layers in the stacked structure can be inferred more sensitively according to the detected series resistance.

[0090] Specifically, the first conductive layer and the second conductive layer in the semiconductor structure are connected in series during the testing process, so that the total resistance detected is the series resistance of the first conductive layer and the second conductive layer, and when any conductive layer in the stacked structure has abnormal resistance, it will directly affect the series resistance. Therefore, the semiconductor structure provided by the embodiment can sensitively infer whether the resistance of any conductive layer is abnormal.

[0091] It should be noted that although the present application has been disclosed with the preferred embodiments as above, the above embodiments are not intended to limit the present application. For any person skilled in the art, many possible changes and modifications or equivalent embodiments of the above disclosed technical content can be made without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the present application without departing from the content of the technical solution of the present application shall still fall within the scope of protection of the technical solution of the present application.

[0092] It should also be noted that the references to "one embodiment", "an embodiment", "certain embodiments", "some embodiments" and the like in the specification indicate that the described embodiment can include a particular feature, structure or characteristic, but not necessarily every embodiment. In addition, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure or characteristic is described in connection with an embodiment, it is within the knowledge of those skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. In addition, the terms "first", "second", "third" and the like in the specification do not necessarily indicate any logical relationship or sequential relationship between the components, elements, steps and the like described in the specification, unless specifically stated or indicated otherwise.

[0093] It should also be appreciated that, unless otherwise indicated herein, the singular forms "a", "an", and "the" include plural referents. For example, reference to "a step" or "the step" can mean one or more steps, and can include sub-steps and sub- devices. All conjunctions used herein should be understood to be inclusive, unless the context clearly dictates otherwise. Further, the word "or" should be understood to have the definition as the logical "or" rather than the logical "exclusive or" unless the context clearly dictates otherwise.

Claims

1. A semiconductor structure, characterized by, comprising: a first conductive layer and a second conductive layer, stacked on a surface of a substrate; a third conductive layer formed in a recess of the substrate, the third conductive layer being located below an end portion of the first conductive layer and connected to the first conductive layer, the third conductive layer also extending out of the first conductive layer; wherein the portion of the third conductive layer extending out is used to connect a first signal terminal, and the second conductive layer is used to connect a second signal terminal; and a top covering layer covering the second conductive layer; a side wall covering sidewalls of the first conductive layer, the second conductive layer, and the top covering layer; a barrier layer partially covering the third conductive layer, and allowing the portion of the third conductive layer not covered by the barrier layer to be connected to the first conductive layer; an isolation structure covering a bottom surface of the third conductive layer, and covering a bottom surface of the first conductive layer not in contact with the third conductive layer, and the third conductive layer being formed in the isolation structure.

2. The semiconductor structure of claim 1, wherein, sidewalls of the first conductive layer and the second conductive layer are aligned.

3. The semiconductor structure of claim 1, wherein, the first conductive layer and the third conductive layer are made of the same material.

4. The semiconductor structure of claim 1, wherein, the first conductive layer is made of polysilicon, and the second conductive layer is made of metal.

5. The semiconductor structure of claim 1, wherein, further comprising a first contact plug and a second contact plug, a bottom of the first contact plug being connected to the third conductive layer, and a bottom of the second contact plug being connected to the second conductive layer.

6. The semiconductor structure of claim 1, wherein, the third conductive layer is formed in the isolation structure, and the first conductive layer and the second conductive layer are stacked above the isolation structure.

7. The semiconductor structure of claim 1, wherein, at least a portion of a top surface of the third conductive layer is lower than a top surface of the substrate.

8. The semiconductor structure of claim 7, wherein, a top portion of the third conductive layer has a recess, and an end portion of the first conductive layer extends into the recess of the third conductive layer to be connected to the third conductive layer, and a top surface of the first conductive layer appears as an uneven surface.

9. A semiconductor structure, characterized by comprising: a first conductive layer and a second conductive layer, stacked on a surface of a substrate; a third conductive layer formed in a recess of the substrate, the third conductive layer being located below an end portion of the first conductive layer and connected to the first conductive layer, the third conductive layer also extending out of the first conductive layer; wherein the portion of the third conductive layer extending out is used to connect a first signal terminal, and the second conductive layer is used to connect a second signal terminal; a top portion of the third conductive layer has a recess, and an end portion of the first conductive layer extends into the recess of the third conductive layer; and a top covering layer covering the second conductive layer; a side wall covering sidewalls of the first conductive layer, the second conductive layer, and the top covering layer; an isolation structure covering a bottom surface of the third conductive layer, and covering a bottom surface of the first conductive layer not in contact with the third conductive layer, and the third conductive layer being formed in the isolation structure.

10. A semiconductor structure, characterized by comprising: a substrate; a recess in the substrate; a third conductive layer in the recess; a first conductive layer and a second conductive layer, stacked on a surface of the substrate from bottom to top and partially covering the third conductive layer, the first conductive layer being connected to the third conductive layer; and a top covering layer covering the second conductive layer. a first contact plug connected to the third conductive layer, and a second contact plug connected to the second conductive layer; and, a top covering layer covering the second conductive layer; a side wall covering the side wall of the first conductive layer, the second conductive layer, and the top covering layer; a barrier layer partially covering the third conductive layer, and connecting the part of the third conductive layer not covered by the barrier layer to the first conductive layer; an isolation structure covering the bottom surface of the third conductive layer, and covering the bottom surface of the first conductive layer not in contact with the third conductive layer, and the third conductive layer is formed in the isolation structure.

11. The semiconductor structure of claim 10, wherein, The side wall of the first conductive layer and the side wall of the second conductive layer are aligned.

12. The semiconductor structure of claim 10, wherein, The material of the first conductive layer and the third conductive layer is the same.

13. The semiconductor structure of claim 10, wherein, The material of the first conductive layer includes polysilicon, and the material of the second conductive layer includes metal.

14. The semiconductor structure of claim 10, wherein, The third conductive layer is formed in the isolation structure, and the first conductive layer and the second conductive layer are stacked above the isolation structure.

15. The semiconductor structure of claim 10, wherein, At least part of the top surface of the third conductive layer is lower than the top surface of the substrate.

16. The semiconductor structure of claim 15, wherein, The top of the third conductive layer has a recess, and the end of the first conductive layer extends into the recess of the third conductive layer to connect with the third conductive layer, and the top surface of the first conductive layer presents an uneven surface.

17. A method of detecting abnormal resistance value, characterized by, including: providing a semiconductor structure as claimed in any one of claims 1-8; applying a test voltage between the first signal terminal and the second signal terminal, and obtaining the corresponding test current; or, applying a test current between the first signal terminal and the second signal terminal, and obtaining the corresponding test voltage; and, obtaining the resistance between the first signal terminal and the second signal terminal according to the obtained test voltage and test current.

18. The resistance abnormality detection method according to claim 17, wherein Further including: comparing the measured resistance between the first signal terminal and the second signal terminal with a standard resistance value to determine whether there is a resistance abnormality.

19. A method of fabricating a semiconductor structure, the method comprising: including: forming a recess in a substrate, and filling the recess with a third conductive layer; and, stacking a first conductive layer and a second conductive layer on the surface of the substrate, the end of the first conductive layer partially covering the third conductive layer to connect with the third conductive layer, and the third conductive layer also extending from below the end of the first conductive layer; wherein, before forming the first conductive layer and the second conductive layer, a barrier layer is also formed on the surface of the substrate, and the barrier layer has an opening formed therein, and the opening exposes the surface of the substrate and part of the third conductive layer; and, the method for forming the first conductive layer and the second conductive layer includes: sequentially forming a first conductive material layer and a second conductive material layer, the first conductive material layer filling the opening and covering part of the barrier layer; and etching the second conductive material layer and the first conductive material layer in sequence, and stopping etching on the barrier layer; forming a top covering layer, a side wall, and an isolation structure, respectively; wherein, the top covering layer covers the second conductive layer; the side wall covers the side wall of the first conductive layer, the second conductive layer, and the top covering layer; The isolation structure covers the bottom surface of the third conductive layer and covers the bottom surface of the first conductive layer which is not in contact with the third conductive layer, and the third conductive layer is formed in the isolation structure.

20. The method of producing a semiconductor structure according to claim 19, wherein Further comprising: forming a first contact plug and a second contact plug, the first contact plug being above the third conductive layer and connecting the third conductive layer, and the second contact plug being above the second conductive layer and connecting the second conductive layer.

21. A method of fabricating a semiconductor device, characterized by, Comprising: providing a substrate, the substrate having a device region and a test region; forming a recess in the substrate in the test region, and filling the recess with a third conductive layer; simultaneously forming a first conductive layer and a second conductive layer in a stacked arrangement in the device region and the test region; wherein in the device region, the first conductive layer and the second conductive layer are in a stacked arrangement to constitute bit lines of a memory; and in the test region, an end portion of the first conductive layer covers the third conductive layer to connect with the third conductive layer, and the third conductive layer further extends from below the end portion of the first conductive layer; before forming the first conductive layer and the second conductive layer, further comprising: forming a barrier layer on the surface of the substrate, the barrier layer having a first opening and a second opening formed therein, the first opening being in the device region and defining a bit line contact window, and the second opening being in the test region and exposing a portion of the third conductive layer; and the first conductive layer in the device region further fills the bit line contact window, the first conductive layer in the test region covers the region of the second opening and connects the third conductive layer, and covers a portion of the barrier layer; forming a top cover layer, a sidewall and an isolation structure, respectively; wherein the top cover layer covers the second conductive layer; the sidewall covers the sidewall of the first conductive layer, the second conductive layer and the top cover layer; the isolation structure covers the bottom surface of the third conductive layer and covers the bottom surface of the first conductive layer which is not in contact with the third conductive layer, and the third conductive layer is formed in the isolation structure.

22. The method of producing a semiconductor device according to Claim 21, wherein The method for forming the first conductive layer and the second conductive layer comprises: sequentially forming a first conductive material layer and a second conductive material layer on the substrate, and etching the second conductive material layer and the first conductive material layer in sequence, and etching stops on the barrier layer.

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