Semiconductor structure and method of fabrication

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a preparation method, the semiconductor structure comprises: a substrate, the substrate comprises an active region; a channel layer, the channel layer is located on the substrate surface of the active region; a gate structure, the gate structure is located on the surface of the channel layer; a barrier layer, the barrier layer is located on the substrate surface of the active region, the side surface of the barrier layer is in contact with the side surface of the channel layer, and the lattice constant of the material of the channel layer is greater than the lattice constant of the materials of the barrier layer and the substrate. The semiconductor structure provided by the embodiment of the present disclosure can at least prevent the stress relaxation phenomenon of the channel layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of integrated circuit technology and process technology, the feature size of transistor (MOS) devices is constantly shrinking in order to improve the integration density of integrated circuits. At process nodes such as high-dielectric metal gate (HKMG) and FinFET, while improving the operating speed of MOS devices and reducing their power consumption, a series of problems need to be addressed.

[0003] How to prevent stress relaxation in the channel layer due to thermal effects and improve the stability of semiconductor structures has become an important problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and fabrication method that at least helps prevent stress relaxation problems in the channel layer.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising: a substrate, the substrate including an active region; a channel layer, the channel layer being located on the substrate surface of the active region; a gate structure, the gate structure being located on the surface of the channel layer; and a barrier layer, the barrier layer being located on the substrate surface of the active region, the side of the barrier layer being in contact with the side of the channel layer, and the lattice constant of the material of the channel layer being greater than the lattice constant of the materials of the barrier layer and the substrate.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including an active region; forming a channel layer, the channel layer being located on the substrate surface of the active region; forming a gate structure, the gate structure being located above the channel layer; forming a barrier layer, the barrier layer being located on the substrate surface and contacting the side of the channel layer with the side of the barrier layer, wherein the lattice constant of the material of the channel layer is greater than the lattice constant of the materials of the barrier layer and the substrate.

[0007] The technical solutions provided in this disclosure have at least the following advantages:

[0008] In the semiconductor structure provided in this embodiment, a barrier layer is provided on the substrate surface, and the sidewalls of the channel layer are in contact with the sidewalls of the barrier layer. Barrier layers are formed on both sides of the channel layer to fix the lattice boundaries of the channel layer material, preventing deformation of the channel layer and thus preventing stress relaxation in the channel layer. Furthermore, the difference in lattice constant between the channel layer material and the barrier layer material is used to compress the channel layer under the gate structure. The compressive stress generated by the difference in lattice constants can offset some of the stress relaxation caused by thermal effects in the channel layer, thereby ensuring that the lattice of the channel layer material does not relax outwards. Attached Figure Description

[0009] One or more embodiments are illustrated by way of example with corresponding accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the accompanying drawings are not to be limited in scale. To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0011] Figures 2-4 This is a schematic diagram of the structure corresponding to each step in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0012] Figures 5-10 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0013] As is known from the background art, existing semiconductor structures may exhibit channel layer stress relaxation.

[0014] Analysis revealed that one of the reasons for stress relaxation in the channel layer is that, in gate structures, the channel layer is typically formed on the surface of the active region's substrate, and the lattice constant of the channel layer material is greater than that of the substrate material. Therefore, due to this difference in lattice constants, the substrate can exert biaxial compressive stress on the channel layer, resulting in compressive deformation. This increases the mobility of holes (pMOSFETs) or electrons (nMOSFETs) within the channel layer, and also increases the offset between the valence band apex of the channel layer material and the valence band apex of the substrate material, which is beneficial for improving the performance of pMOSFETs or nMOSFETs. However, the DRAM process following channel layer formation involves several steps of high-temperature thermal annealing exceeding 1000°C and heat treatment lasting several hours. Heat treatment can affect the mobility of holes or electrons, which in turn affects the stress between the channel layer and the substrate. In other words, long-term or high-temperature heat treatment will make the stress in the channel layer easier to release, causing the channel layer deformation to disappear partially or completely. At the same time, the benefits of increased mobility brought about by the deformation of the channel layer will also disappear.

[0015] This disclosure provides a semiconductor structure and fabrication method. A barrier layer is formed on the side of the channel layer to prevent stress relaxation due to thermal effects. The barrier layer, located on the side of the channel layer, can prevent the epitaxial growth of the channel layer material, avoiding deformation of the channel layer and improving the stability of the semiconductor structure. Furthermore, the lattice constant of the barrier layer material is smaller than that of the channel layer material. The barrier layer can generate biaxial compressive stress towards the channel layer, i.e., the barrier layer exerts compressive deformation on the channel layer, which can offset some of the stress relaxation caused by thermal effects in the channel layer, thus helping to prevent stress relaxation in the channel layer.

[0016] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. Figure 1 This is a schematic diagram of a semiconductor structure provided in one embodiment of the present disclosure.

[0017] According to some embodiments of this disclosure, reference is made to Figure 1This disclosure provides a semiconductor structure, including: a substrate 100, the substrate 100 including an active region (not shown); a channel layer 102, the channel layer 102 being located on the surface of the active region of the substrate 100; a gate structure 110, the gate structure 110 being located on the surface of the channel layer 102; and a barrier layer 104, the barrier layer 104 being located on the surface of the active region of the substrate 100, the side of the barrier layer 104 being in contact with the side of the channel layer 102, and the lattice constant of the material of the channel layer 102 being greater than the lattice constant of the materials of the barrier layer 104 and the substrate 100.

[0018] In some embodiments, the substrate 100 is made of a semiconductor material, which may include any one of silicon, germanium, silicon carbide, or silicon germanium. This disclosure uses silicon as an example to illustrate the use of silicon as the material of the substrate 100. The lattice constant of silicon is... The substrate 100 is doped with a P-type dopant element, i.e., the semiconductor structure is a P-type transistor (pMOSFET). In other embodiments, the substrate 100 is doped with an N-type dopant element, i.e., the semiconductor structure is an N-type transistor (nMOSFET). Specifically, the N-type dopant element can be a group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type dopant element can be a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0019] In some embodiments, the channel layer 102 can serve as the channel region of a semiconductor structure. The lattice constant of the material of the channel layer 102 is greater than that of the material of the substrate 100. The material of the channel layer 102 is germanium-silicon, and germanium has a higher carrier mobility. Furthermore, the lattice constant of germanium-silicon is greater than that of silicon. Due to this difference in lattice constant, the substrate 100 generates compressive stress on the square shape of the channel layer 102, thereby increasing the mobility of carriers (electrons or holes) within the channel layer 102 and improving the driving current and the speed of the transistor composed of the active region, the channel layer 102, and the gate structure 110. The increase in mobility can offset the decrease in mobility caused by the vertical electric field generated by forming multiple transistors on the surface of the substrate 100. That is, the semiconductor structure can be transformed from 2D to 3D, which is beneficial for improving the storage density of the semiconductor structure. In other embodiments, the material of the channel layer can be silicon, and the electron mobility can be improved by implanting germanium ions into the channel layer. In still other embodiments, the material of the channel layer can be germanium, which has a higher carrier mobility.

[0020] In some embodiments, the gate structure 110 includes a gate insulating layer 111, a gate conductive layer 112, a gate cap 113, and a gate sidewall 114. The gate insulating layer 111, the gate conductive layer 112, and the gate cap 113 are sequentially stacked on the surface of the channel layer 102, and the gate sidewall 114 is located on the sides of the gate insulating layer 111, the gate conductive layer 112, and the gate cap 113. The gate insulating layer 111 is used to isolate the gate conductive layer 112 from the channel layer 102, while reducing the direct tunneling current between the gate conductive layer 112 and the channel layer 102, and avoiding leakage current caused by parasitic capacitance. The gate conductive layer 112 can be made of tungsten, copper, tantalum, or silver, that is, the gate structure 110 is a high-dielectric metal gate (HKMG). The metal gate can overcome the depletion effect of the polysilicon gate structure and eliminate the boron penetration effect. At the same time, the resistivity of the metal itself is low, and the gate resistance is small, which is beneficial to reducing the resistance of the gate structure 110. The gate sidewall 114 has doped elements, and the type of doped elements is the same as that in the substrate 100. In some embodiments, the gate conductive layer 112 can be doped polysilicon, and the band gap of the polysilicon is the same as or similar to the band gap of the channel layer 102 located at the bottom of the gate structure 110. That is, the work function of the polysilicon is the same as or similar to the work function of the channel layer 102, which reduces the threshold voltage of the pMOSFET or nMOSFET. Moreover, the work function of the polysilicon can be controlled by changing the concentration of the doped elements, thereby controlling the difference in work function between the polysilicon layer and the channel layer 102 and reducing the threshold voltage of the pMOSFET or nMOSFET. Furthermore, the melting point of polysilicon is higher than that of most metals, which can affect the upper temperature limit of high-temperature deposition of gate materials in semiconductor manufacturing processes, which is beneficial to improving the device performance of the gate structure 110.

[0021] In some embodiments, the gate insulating layer 111 may be made of silicon nitride, silicon oxide, or other materials with high dielectric constants. Materials with high dielectric constants may include silicon dioxide, silicon nitride, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide, hafnium dioxide, lanthanum oxide, zirconium dioxide, strontium titanate, and zirconium silicate oxide. The gate cap 113 may be made of silicon oxide, silicon carbide, or silicon nitride, and the gate sidewall 114 may be made of amorphous silicon, silicon, or polycrystalline silicon.

[0022] In some embodiments, the lattice constant of the material of the barrier layer 104 is smaller than that of the channel layer 102. The barrier layer 104 is located on the side of the channel layer 102 and can block the lattice epitaxy of the material of the channel layer 102. At the same time, the barrier layer 104 squeezes the channel layer 102 under the gate structure 110 due to the difference in lattice constant. The squeezing stress squeezes the side of the channel layer 102, further preventing the lattice epitaxy of the material of the channel layer 102.

[0023] In some embodiments, the lattice constant of the material of the barrier layer 104 is less than or equal to the lattice constant of the material of the substrate 100 in the active region. The barrier layer 104 can generate compressive stress on the substrate 100 to prevent deformation of the substrate 100. At the same time, the difference in lattice constant between the material of the barrier layer 102 and the material of the channel layer 102 is greater than or equal to the difference in lattice constant between the material of the substrate 100 and the material of the channel layer 102. Therefore, the compressive stress generated by the barrier layer 104 is greater than the compressive stress of the substrate 100 on the channel layer 102. When the channel layer 102 experiences stress relaxation, the lattice of the material of the channel layer 102 tends to relax towards the substrate 100 where the compressive stress is smaller, further preventing the lattice of the material of the channel layer 102 from relaxing to both sides and causing deformation of the channel layer 102.

[0024] In some embodiments, the barrier layer 104 includes an epitaxial semiconductor layer, and the material of the barrier layer 104 is the same as the material of the substrate 100 of the active region, that is, the barrier layer 104 can be formed by an epitaxial process on the surface of the substrate 100. Specifically, the material of the barrier layer 104 includes silicon or silicon carbide.

[0025] In some embodiments, the barrier layer 104 contains doped elements, which can be N-type or P-type doped elements. The region where the barrier layer 104 is located can serve as part of the source or drain of a subsequently formed transistor, and the doped elements can act as charge carriers.

[0026] In some embodiments, the substrate 100 of the active region includes a source end and a drain end; along the arrangement direction of the source end and the drain end, the side surface of the channel layer 102 contacts the side surface of the barrier layer 101. In other embodiments, a fine gap exists between the side surface of the barrier layer 104 and the side surface of the channel layer 102, the width of which is... The barrier layer 104 surrounds the side of the channel layer 102.

[0027] In some embodiments, the top surface of the barrier layer 104 away from the substrate 100 is higher than the top surface of the channel layer 102 away from the substrate 100, ensuring that the side surfaces of the channel layer 102 and the barrier layer 104 are in complete contact. The barrier layer 104 can provide complete protection for the channel layer 102, preventing stress relaxation caused by thermal effects. The height difference m between the top surface of the barrier layer 104 and the top surface of the channel layer 102 is... m can specifically be... or

[0028] In some embodiments, the bottom surface of the barrier layer 104 is lower than the bottom surface of the channel layer 102; the height difference n between the bottom surface of the barrier layer 104 and the bottom surface of the channel layer 102 is 3nm to 5nm, specifically 3nm, 4.2nm, 4.8nm, or 5nm. On the one hand, it can completely protect the side surface of the channel layer 102, preventing stress relaxation caused by thermal effects; on the other hand, it is beneficial to the integrity of the epitaxially formed barrier layer 104 and the fact that the height of the barrier layer 104 is higher than that of the channel layer 102, reducing lattice defects and resistance of the barrier layer 104, and improving the electrical connection performance of the semiconductor structure.

[0029] In some embodiments, the semiconductor structure further includes a shallow trench isolation (STI) 120, which surrounds the gate structure 110 and also surrounds the substrate 100 of the active region. The shallow trench isolation 120 can be used to prevent leakage current between adjacent gate structures 110. The sidewalls of the shallow trench isolation 120 that contact the substrate 100 are beveled, which is beneficial to the compactness of the filling material forming the shallow trench isolation 120 and the electrical performance of the shallow trench isolation 120.

[0030] In some embodiments, the depth of the shallow trench isolation structure 120 is 10nm to 100nm. Specifically, the depth of the shallow trench isolation structure 120 can be 12nm, 50nm, 70nm or 100nm. The depth range of the shallow trench isolation structure 120 is used to prevent leakage current between adjacent gate structures 110, and also to eliminate loss regions on the surface of the substrate 100 and shorten the spacing of semiconductor structures.

[0031] In some embodiments, the shallow trench isolation structure 120 includes an isolation layer 121 and a buffer layer 122. The buffer layer 122 is located between the isolation layer 121 and the substrate 100. The buffer layer 122 serves to prevent oxygen atoms in the isolation layer 121 from diffusing into the active region of the substrate 100, while also improving the interface characteristics between the substrate 100 and the isolation layer 121. The thickness of the buffer layer 122 can be [missing information]. The thickness of the buffer layer 122 can be specifically... or The material of the isolation layer 121 can be silicon oxide or silicon oxynitride, and the material of the buffer layer 122 can be silicon oxide, silicon carbide or other insulating materials.

[0032] In the semiconductor structure provided in this embodiment, the substrate 10 has a barrier layer 104 on its surface. The sidewalls of the channel layer 102 are in contact with the sidewalls of the barrier layer 104. The barrier layer 104 is formed on both sides of the channel layer 102 to fix the lattice boundary of the material of the channel layer 102, thereby preventing deformation of the channel layer 102 and thus preventing stress relaxation of the channel layer 102. In addition, the difference between the lattice constant of the material of the channel layer 102 and the material of the barrier layer 104 is used to achieve the purpose of compressing the channel layer 102 under the gate structure 110. The compressive stress generated by the difference in lattice constants can offset part of the stress relaxation phenomenon of the channel layer 102 caused by thermal effects, thereby ensuring that the lattice of the material of the channel layer 102 does not relax outward.

[0033] Accordingly, according to some embodiments of this disclosure, another aspect of this disclosure provides a method for preparing a semiconductor structure, used to prepare the semiconductor structure provided in the above embodiments.

[0034] Figures 2-4 This is a schematic diagram of the structure corresponding to each step in a method for preparing a semiconductor structure according to an embodiment of this disclosure.

[0035] refer to Figures 2 to 3 A substrate 100 is provided, the substrate 100 including an active region; a channel layer 102 is formed, the channel layer 102 is located on the surface of the substrate 100 of the active region; and a gate structure 100 is formed, the gate structure is located above the channel layer 102.

[0036] Specifically, refer to Figure 2 An initial substrate 105 is provided, and a semiconductor film 101 and a gate structure 110 are sequentially formed on the surface of the initial substrate 102.

[0037] The initial substrate 105 is made of a semiconductor material, which may include any one of silicon, germanium, silicon carbide, or germanium-silicon. The initial substrate 105 is doped with a P-type dopant or an N-type dopant, that is, the semiconductor structure is a P-type transistor (pMOSFET) or an N-type transistor (nMOSFET).

[0038] In some embodiments, the lattice constant of the semiconductor film 101 is greater than the lattice constant of the initial substrate 105. The semiconductor film 101 is formed using selective epitaxy or chemical vapor deposition, and the etching selectivity ratio of the semiconductor film 101 to the initial substrate 102 is 0.8:1 to 1:1.2. Specifically, the etching selectivity ratio can be 0.8:1, 1:1, 1:1.1, or 1:1.2. The material of the semiconductor film 101 can be germanium-silicon, germanium, or silicon.

[0039] In some embodiments, a gate insulating layer 111, a gate conductive layer 112, a gate cap 113, and a gate sidewall 114 are sequentially formed using chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). The gate insulating layer 111, the gate conductive layer 112, the gate cap 113, and the gate sidewall 114 together constitute the gate structure 110. The gate insulating layer 111, the gate conductive layer 112, and the gate cap 113 are sequentially stacked on the surface of the channel layer 102, and the gate sidewall 114 is located on the side of the gate insulating layer 111, the gate conductive layer 112, and the gate cap 113.

[0040] In some embodiments, after forming the gate sidewall 114 of the gate structure 110, a shallow trench isolation structure 120 is further formed, the shallow trench isolation structure 120 surrounds the gate structure 110, and the shallow trench isolation structure 120 also surrounds the substrate 100 of the active region; the depth of the shallow trench isolation structure 120 is 10 nm to 100 nm.

[0041] In some embodiments, the shallow trench isolation structure 120 includes an isolation layer 121 and a buffer layer 122, wherein the buffer layer 122 is located between the isolation layer 121 and the substrate 100, and the thickness of the buffer layer 122 can be [missing information]. The thickness of the buffer layer 122 can be specifically... or The material of the isolation layer 121 can be silicon oxide or silicon oxynitride, and the material of the buffer layer 122 can be silicon oxide, silicon carbide or other insulating materials.

[0042] Specifically, after the gate sidewall 114 is formed, an isolation oxide layer is formed on the surface of the substrate 100 and the conductor film 101 to protect the active region substrate 100 from damage during the removal of the subsequently formed nitride layer.

[0043] A nitride mask layer with grooves is formed on the surface of the isolation oxide layer. The position of the grooves corresponds to the position of the shallow trench isolation structure formed subsequently. The nitride mask layer has high strength, which is beneficial to protect the substrate 100 of the active region when forming the shallow trench isolation structure. It can also avoid damage to the substrate 100 caused by the planarization of the formed shallow trench isolation structure.

[0044] Using a nitride mask layer as a mask, the isolation oxide layer and a portion of the substrate 100 are etched along the trench to form a trench; a buffer layer 122 and an isolation layer 122 are formed, and the remaining isolation oxide layer and nitride mask layer are removed. In some embodiments, a photolithography process is used to form the trench. A chemical mechanical polishing process is used to planarize the shallow trench isolation structure 120.

[0045] In some embodiments, the material of the isolation oxide layer can be silicon oxide or aluminum oxide, and the material of the nitride mask layer can be silicon nitride, titanium nitride, aluminum nitride, gallium nitride, or indium nitride.

[0046] refer to Figure 3 Etching removes the semiconductor film 101 exposed outside the gate structure 100 (reference). Figure 2 ), the initial substrate 105 of the etched portion thickness (reference) Figure 2 The first groove 103 is formed, and the remaining initial base 105 (refer to) Figure 2 As substrate 100, the remaining semiconductor film 101 (reference) Figure 2 ) as channel layer 102.

[0047] In some embodiments, a dry etching process is used to etch and remove the semiconductor film 101 (reference). Figure 2 The dry etching process can be any one of isotropic plasma etching, reverse ion etching (RIE), or physical sputtering and ion milling.

[0048] In some embodiments, the depth of the first groove 103 along the direction perpendicular to the surface of the substrate 100 can be 3 nm to 5 nm, ensuring that the semiconductor film 101 exposed outside the gate structure 110 (see reference) Figure 2 All of the material is etched to match the lattice constant of the material of the barrier layer to that of the substrate 100. Moreover, the exposed surface area of ​​the substrate 100 is large, which is beneficial for the subsequent epitaxial formation of the barrier layer, ensuring the integrity of the barrier layer and that the top surface of the barrier layer is higher than the top surface of the channel layer 102.

[0049] Understandably, due to the isotropic nature of the etching, the bottom of the first groove 103 is arc-shaped.

[0050] refer to Figure 4 A barrier layer 104 is formed, located on the side of the channel layer 102 on the surface of the substrate 100 and in contact with the side of the barrier layer 102. The lattice constant of the material of the channel layer 102 is greater than the lattice constant of the material of the barrier layer 104. The barrier layer 104 also fills the first groove 103 (reference). Figure 3 ).

[0051] In some embodiments, a barrier layer 104 is formed using a selective epitaxial growth process. The source material used in the selective epitaxial growth process includes a source gas and a dopant source gas, wherein the dopant source gas is used to provide the dopant element. The source gas can be a silicon source gas, specifically silane, silane, dichlorosilane, or trichlorosilane; the dopant source gas includes an N-type element source gas or a P-type element source gas, specifically phosphine, arsine, or antimony hydride; the P-type element source gas can specifically be borane. In other embodiments, the source gas can also be a germanium source gas, specifically germanane. The temperature of the selective epitaxial growth process is 800°C to 850°C, specifically 800°C, 825°C, or 849°C.

[0052] The above embodiments involve forming a gate structure first and then forming a barrier layer. Other embodiments of this disclosure may also involve forming a barrier layer first and then forming a gate structure to prepare a semiconductor structure. Figures 5-10 This is a schematic diagram of the structure corresponding to each step in a method for fabricating a semiconductor structure according to another embodiment of this disclosure. The following will be combined with... Figures 5 to 10 The method for preparing a semiconductor structure according to another embodiment of this disclosure will be described in detail. The parts that are the same as those in the above embodiments will not be repeated.

[0053] refer to Figures 5 to 7 A substrate 200 is provided, the substrate 200 including an active region; a channel layer 202 is formed, the channel layer 202 being located on the surface of the substrate 200 in the active region.

[0054] Specifically, refer to Figure 5 A substrate 205 is provided, wherein the substrate 205 includes an active region.

[0055] The substrate 205 may be made of any one of silicon, germanium, silicon carbide, or germanium-silicon. The substrate 205 is doped with P-type or N-type dopant elements, that is, the semiconductor structure is a P-type transistor (pMOSFET) or an N-type transistor (nMOSFET).

[0056] refer to Figure 6 A substrate 205 with a patterned portion thickness is formed in which a second groove 201 is formed.

[0057] Specifically, a second groove 201 is formed in a portion of the active region of the substrate. The second groove 201 is formed by a dry etching process or a wet etching process. The second groove 201 is used to form a channel layer in the future.

[0058] refer to Figure 7 This forms a channel layer 202, which is located in the second groove 201 (reference). Figure 6Within the substrate 205, and along the direction perpendicular to the surface of the substrate 205, the height of the channel layer 202 is less than or equal to the depth of the second groove 201.

[0059] In some embodiments, the height of the channel layer 202 is less than the depth of the second groove 201, and the height difference between the top surface of the channel layer 202 and the top surface of the substrate 205 is [missing information]. The lattice constant of the material of the channel layer 202 is greater than that of the material of the substrate 202.

[0060] refer to Figure 8 A barrier layer 204 is formed, located on the side of the channel layer 202 on the substrate surface, and the side of the channel layer 202 is in contact with the side of the barrier layer 204. The lattice constant of the material of the channel layer 202 is greater than that of the material of the barrier layer 204. The bottom surface of the barrier layer 204 is lower than the bottom surface of the channel layer 202, and the height difference m between the bottom surface of the barrier layer 204 and the bottom surface of the channel layer 202 is 3nm to 5nm.

[0061] Specifically, a portion of the substrate 205 is doped to form a barrier layer 204. The doping process can be in-situ doping or ion doping.

[0062] refer to Figure 9 A gate structure 210 is formed, which is located above the channel layer 202. The gate structure 210 includes a gate insulating layer 211, a gate conductive layer 212, a gate cap 213, and a gate sidewall 214. The gate insulating layer 211, the gate conductive layer 212, and the gate cap 213 are stacked sequentially on the surface of the channel layer 202, and the gate sidewall 214 is located on the side of the gate insulating layer 211, the gate conductive layer 212, and the gate cap 213.

[0063] refer to Figure 10 The substrate 205 with etched portion thickness (reference) Figure 9 The top surface of the remaining substrate is flush with the top surface of the channel layer 202, forming a shallow trench isolation structure 220. The shallow trench isolation structure 220 surrounds the gate structure 210 and also surrounds the substrate 200 of the active region. The depth of the shallow trench isolation structure 220 is 10nm to 100nm. The shallow trench isolation structure 220 includes an isolation layer 221 and a buffer layer 222, with the buffer layer 222 located between the isolation layer 221 and the substrate 200.

[0064] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including an active region; A channel layer, wherein the channel layer is located on the substrate surface of the active region; A gate structure located on the surface of the channel layer; A barrier layer is located on the substrate surface of the active region, the side of the barrier layer is in contact with the side of the channel layer, and the lattice constant of the material of the channel layer is greater than the lattice constant of the materials of the barrier layer and the substrate. Wherein, the top surface of the barrier layer away from the substrate is higher than the top surface of the channel layer away from the substrate; the height difference between the top surface of the barrier layer and the top surface of the channel layer is 10Å~100Å; The bottom surface of the barrier layer is lower than the bottom surface of the channel layer; the height difference between the bottom surface of the barrier layer and the bottom surface of the channel layer is 3nm~5nm.

2. The semiconductor structure according to claim 1, characterized in that, The lattice constant of the material of the barrier layer is less than or equal to the lattice constant of the material of the substrate in the active region.

3. The semiconductor structure according to claim 1, characterized in that, The barrier layer includes an epitaxial semiconductor layer.

4. The semiconductor structure according to claim 3, characterized in that, The material of the barrier layer is the same as the material of the substrate of the active region.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The barrier layer is made of silicon or silicon carbide.

6. The semiconductor structure according to claim 1, characterized in that, The barrier layer contains doped elements, which are either N-type or P-type.

7. The semiconductor structure according to claim 1, characterized in that, The substrate of the active region includes a source end and a drain end; along the arrangement direction of the source end and the drain end, the side of the channel layer is in contact with the side of the barrier layer.

8. The semiconductor structure according to claim 1, characterized in that, The barrier layer surrounds the side of the channel layer.

9. The semiconductor structure according to claim 1, characterized in that, The material of the channel layer includes germanium-silicon or germanium.

10. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an active region; A channel layer is formed, the channel layer being located on the substrate surface of the active region; A gate structure is formed above the channel layer; a barrier layer is formed on the surface of the substrate, the side of the channel layer is in contact with the side of the barrier layer, and the lattice constant of the material of the channel layer is greater than the lattice constant of the materials of the barrier layer and the substrate. Wherein, the top surface of the barrier layer away from the substrate is higher than the top surface of the channel layer away from the substrate; the height difference between the top surface of the barrier layer and the top surface of the channel layer is 10Å~100Å; The bottom surface of the barrier layer is lower than the bottom surface of the channel layer; the height difference between the bottom surface of the barrier layer and the bottom surface of the channel layer is 3nm~5nm.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The process steps for forming the channel layer and the barrier layer include: An initial substrate is provided, and a semiconductor film and the gate structure are sequentially formed on the surface of the initial substrate; Etching removes the semiconductor film exposed outside the gate structure; The barrier layer is formed on the surface of the initial substrate and the side of the semiconductor film, the remaining initial substrate is used as the substrate, and the remaining semiconductor film is used as the channel layer.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, While etching away the semiconductor film exposed outside the gate structure, a portion of the initial substrate is etched to form a first groove; the barrier layer also fills the first groove.

13. The method for preparing a semiconductor structure according to any one of claims 10 to 12, characterized in that, The barrier layer is formed using a selective epitaxial growth process; the temperature of the selective epitaxial growth process is 800°C to 850°C.

14. The method for preparing a semiconductor structure according to claim 10, characterized in that, The process steps for forming the channel layer and the barrier layer include: Provide substrate; The substrate with a patterned portion thickness has a second groove formed within it. The trench layer is formed within the second groove, and the height of the trench layer is less than or equal to the depth of the second groove in a direction perpendicular to the surface of the substrate. The barrier layer is formed by doping a portion of the substrate thickness.

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