A low kickback noise synthesizable dynamic voltage comparator

Abstract

The application belongs to the technical field of semiconductor, and particularly relates to a low-kickback-noise comprehensive dynamic voltage comparator. The comprehensive dynamic voltage comparator comprises a clock delay module, an input comparison stage and an output latch stage circuit. The dynamic voltage comparator works in two phases: a reset phase and a comparison phase. In the reset phase, input voltages and latched comparison results are simultaneously sampled, and in the comparison phase, the difference between the two input voltages is amplified to logic 1 and logic 0 potentials. The dynamic voltage comparator is composed of digital standard units, is compatible with automatic process design, shortens the circuit design time, and is convenient for process migration.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a low-kick noise synthesizable dynamic voltage comparator circuit in an integrated circuit. BACKGROUND

[0002] Most of the traditional complementary metal oxide semiconductor (CMOS) analog circuits are realized by custom-sized MOS transistors, and the layout design of the analog circuit is completed by manual layout and wiring. The layout and design iteration time is relatively long. When the analog circuit completed under a specific CMOS process is migrated to other CMOS processes, the circuit needs to be rebuilt and the layout layout and wiring are completed. The traditional analog circuit is difficult to realize the rapid migration between CMOS processes.

[0003] The synthesizable analog circuit refers to an analog circuit realized by a digital standard cell and automatically generated by a digital layout tool. The synthesizable analog circuit needs to use a digital standard cell to replace the CMOS transistor in the traditional analog circuit, and the digital circuit layout generation tool can be used for automatic layout and wiring in the layout generation stage, which greatly improves the layout design speed. In addition, the digital standard cells of different processes are less different, and the same cell can be used to quickly replace the original circuit during process migration, realizing the rapid migration of the analog circuit between different processes.

[0004] The voltage comparator is used for comparing the size of two input voltages, and the output value is logic 1 or logic 0, which is an indispensable module in the successive approximation type analog-to-digital converter. Compared with the static comparator, the dynamic comparator does not have static power consumption, and due to the positive feedback, it has faster speed, so the application range is more widely. At the same time, compared with the static comparator, the dynamic comparator is more easily synthesized. The kick noise is one of the non-ideal factors affecting the performance of the comparator. Therefore, it is very attractive to design a low-kick noise synthesizable dynamic voltage comparator. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a low-kick noise synthesizable dynamic voltage comparator which is completely built by digital standard cells, shortens the circuit design time and facilitates process migration.

[0006] The low-kick noise synthesizable dynamic voltage comparator provided by the present application comprises a clock delay module, an input comparison stage circuit and an output latch stage circuit; the input port is a pair of positive and negative signal ports and a clock port; the output port is a pair of complementary logic signal output ports; wherein:

[0007] (1) the clock delay module is composed of a delay unit; the ports of the delay unit include a signal input end and a signal output end; the signal input end of the delay unit is connected with the clock input, and the signal output end is connected with the delayed clock signal;

[0008] (2) the input comparison stage circuit is composed of a pair of input units; the ports of each input unit include four signal input ends and a signal output end; the first signal input end of the pair of signal input units is respectively connected with the positive input and the negative input, the second signal input end is connected with the delayed clock signal, the fourth signal input end is connected with the input clock signal, and the third signal input end of one input unit is respectively connected with the signal output end of the other input unit; the signal output ends are respectively connected to the intermediate regeneration signals;

[0009] (3) the output latch stage circuit is composed of a pair of inverters and a pair of NAND gates; the ports of the NAND gates include two signal input ends and a signal output end; wherein the signal input ends of one NAND gate are respectively connected with the signals after the intermediate regeneration signals are inverted by the pair of inverters, and the other signal input end is respectively connected with the signal output end of the other NAND gate; the signal output ends are respectively connected to the latch output ports.

[0010] The low kickback noise synthesizable dynamic voltage comparator provided by the application has a pair of input units working in two modes under the control of an input clock signal: a reset mode and a comparison mode; in the reset mode, the input clock signal resets the intermediate regeneration signals to the power supply voltage; in the comparison mode, the input comparison stage circuit exhibits a positive feedback function, so that the intermediate regeneration signals compete with each other and finally converge to logic 0 and logic 1 voltages.

[0011] The low kickback noise synthesizable dynamic voltage comparator provided by the application has an output latch stage circuit (i.e. an SR latch) working in two modes under the control of an input clock signal: a latch mode and an update mode; in the latch mode, the intermediate regeneration signals are the power supply voltage, and after being inverted, they are all zero level (VSS), so that the output signal remains unchanged; in the update mode, if S is high level and R is low level, the output signal is low level and high level respectively; otherwise, if S is low level and R is high level, the output signal is high level and low level respectively.

[0012] The low kickback noise synthesizable dynamic voltage comparator provided by the application has a circuit working in two phases;

[0013] (1) the reset phase: the reset clock is off level; the intermediate regeneration signals are reset to the power supply voltage; the input signals are sampled at this time; the output latch stage circuit is in the latch mode, and the output signal remains unchanged;

[0014] (2) comparison phase: the reset clock is a conductive level; the input comparison stage circuit is in a comparison mode, and the intermediate regeneration signal starts to discharge at different speeds according to the size of the input signal, when the fast end discharges to make the PMOS tube of the other end conductive, the positive feedback mechanism is triggered, and finally due to the cross positive feedback, it converges to different logic levels 0 or 1.

[0015] The low kickback noise synthesizable dynamic voltage comparator provided by the application comprises a clock delay module, an input comparison stage circuit and an output latch stage circuit, and all of them can be realized by digital standard units. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 The circuit diagram of the conventional synthesizable dynamic voltage comparator based on NAND gate.

[0017] Figure 2 The circuit block diagram of the low kickback noise synthesizable dynamic voltage comparator.

[0018] Figure 3 The gate level circuit diagram of the embodiment of the low kickback noise synthesizable dynamic voltage comparator.

[0019] Figure 4 The transistor level circuit diagram of a pair of input units in the embodiment of the low kickback noise synthesizable dynamic voltage comparator.

[0020] Figure 5 The transistor level circuit of two NAND gates in the output latch stage circuit in the embodiment of the low kickback noise synthesizable dynamic voltage comparator.

[0021] Figure 6 The transistor level circuit diagram of the clock delay module and the inverter in the embodiment of the low kickback noise synthesizable dynamic voltage comparator. DETAILED DESCRIPTION

[0022] As Figure 1As shown, in the conventional synthesizable dynamic voltage comparator based on NAND gate, VINP and VINN are input signals, control input pair of MNA1_1, MNA1_2, MPA1_1 and MPA1_2 gate end; CLK is a comparison enable signal, control MNA3_1, MNA3_2, MPA3_1 and MPA3_2 gate end. When CLK is logic 0, MNA3_1 and MNA3_2 are off, MPA3_1 and MPA3_2 are on, node POUT_NAND3 and NOUT_NAND3 are charged to the power supply voltage, so that MNA2_1 and MNA2_2 are on. When CLK is logic 1, MNA3_1 and MNA3_2 are on, MPA3_1 and MPA3_2 are off, at this time node POUT_NAND3 and NOUT_NAND3 start to discharge at different speeds according to the size of VINP and VINN, when POUT_NAND3 drops to make MPA2_2 conductive or NOUT_NAND3 drops to make MPA1_2 conductive, the positive feedback structure composed of MPA2_1, MNA2_1 and MPA2_2, MNA2_2 two inverters starts to work, finally makes NOUT_NAND3 converge to logic 1, POUT_NAND3 converges to logic 0 or the opposite situation. The result of this convergence is then latched by the SR latch to get the final VOUTP and VOUTN.

[0023] The conventional synthesizable dynamic voltage comparator based on NAND gate is precharged by PMOS and discharged by NMOS. But the discharge node is located at the drain end of the input pair transistor, and the voltage change of this node will be coupled to the input node through the gate-drain parasitic capacitance of the input pair transistor, thereby causing disturbance to the input node voltage, which is called kickback noise. The conventional MOS-based dynamic voltage comparator can reduce kickback noise by inserting an isolation tube between the drain end of the input pair transistor and the regeneration node, but the synthesizable comparator is based on standard cells, so it cannot directly insert MOS tubes.

[0024] Figure 2 The application discloses a low-kickback-noise synthesizable dynamic voltage comparator. Figure 3 The application discloses a low-kickback-noise synthesizable dynamic voltage comparator.

[0025] (1) The clock delay module is composed of a delay unit (100); the ports of the delay unit include a signal input end (IN) and a signal output end (OUT); the signal input end of the delay unit is connected with a clock input (CLK), and the signal output end is connected with a delayed clock signal (CLKD).

[0026] (2) The input comparison stage circuit (200) is composed of a pair of input units (210 and 220); the ports of each input unit include four signal input ends (A1, A2, A3 and A4) and a signal output end (OUT); in the pair of signal input units (112 and 120), the first signal input end (A1) is connected with positive and negative inputs (VINP and VINN) respectively, the second signal input end (A2) is connected with the delayed clock signal (CLKD), the fourth signal input end (A4) is connected with the input clock signal (CLK), and the third signal input end (A3) of one input unit is connected with the signal output end (NOUT or POUT) of the other input unit respectively; the signal output end (OUT) is connected to the intermediate regeneration signals (POUT and NOUT) respectively.

[0027] (3) The output latch stage circuit (300) is composed of an SR latch (310); the ports of the SR latch include two signal input ends (S and R) and two signal output ends (Q and QN); the two signal input ends (S and R) are connected after being connected with the intermediate regeneration signals (POUT and NOUT) respectively; the two signal output ends (Q and QN) are connected to the output ports (VOUTP and VOUTN) of the comparator respectively.

[0028] Figure 4 The transistor level circuit is a pair of input units of the low kickback noise synthesizable dynamic voltage comparator applied to the application; the input comparison stage circuit works in two modes under the control of the input clock signal; in the reset mode, the input clock signal resets the intermediate regeneration signals to the power supply voltage; in the comparison mode, the input comparison stage circuit behaves as a positive feedback function, so that the intermediate regeneration signals compete with each other and finally converge to the logic 0 and logic 1 voltages respectively.

[0029] Figure 5 The transistor level circuit is two NAND gates in the output latch stage of the dynamic voltage comparator applied to the application; the SR latch works in two modes; in the latch mode, the output signal remains unchanged; in the update mode, the output signal changes accordingly with the input change and is latched.

[0030] The synthesizable dynamic voltage comparator, the circuit of which works in two phases;

[0031] (1) Reset phase: the reset clock is off level; the intermediate regeneration signal is reset to power voltage; the input signal is sampled at this time; the output latch circuit is in latch mode, and the output signal remains unchanged;

[0032] (2) Comparison phase: the reset clock is on level; the input comparison circuit is in comparison mode, and the intermediate regeneration signal starts to discharge at different speeds according to the size of the input signal. When the fast discharging end discharges to the PMOS tube of the other end, the positive feedback mechanism is triggered, and finally converges to different logic levels 0 or 1 due to cross positive feedback.

[0033] Figure 6 An example circuit of the delay module and the inverter used.

[0034] The above embodiments are only for illustrating the technical concept and characteristics of the present application. The clock delay module, the input comparison stage and the output latch stage can all be implemented by other circuit structures to achieve the same function. The purpose is to enable those skilled in the art to understand the content of the present application and to implement it, and cannot limit the protection scope of the present application. Any modification made according to the spirit and essence of the main technical solution of the present application should be covered within the protection scope of the present application.

Claims

1. A low kickback noise integrable dynamic voltage comparator, characterized by, The application relates to a clock delay module, which comprises a clock delay module (100), an input comparison stage circuit (200) and an output latch stage circuit (300); the input ports of the clock delay module are a pair of positive and negative signal ports (VINP and VINN) and a clock port (CLK); the output ports of the clock delay module are a pair of complementary logic signal output ports (VOUTN and VOUTP); wherein: (1) the clock delay module is composed of a delay unit; the ports of the delay unit include a signal input end (IN) and a signal output end (OUT); the signal input end of the delay unit is connected with the clock input (CLK), and the signal output end is connected with a delayed clock signal (CLKD); (2) the input comparison stage circuit (200) is composed of a pair of input units (210 and 220); the ports of the input units include four signal input ends (A1, A2, A3 and A4) and a signal output end (OUT); the first signal input ends (A1) of the pair of signal input units (210 and 220) are respectively connected with the positive and negative inputs (VINP and VINN), the second signal input ends (A2) are connected with the delayed clock signal (CLKD), the fourth signal input ends (A4) are connected with the input clock signal (CLK), the third signal input ends (A3) of one input unit are respectively connected with the signal output ends of the other input unit, and the signal output end (OUT) is connected to intermediate regeneration signals (POUT and NOUT); (3) the output latch stage circuit (300) is composed of an SR latch (310); the ports of the SR latch include two signal input ends (S and R) and two signal output ends (Q and QN); the two signal input ends (S and R) are respectively connected after being inverted with the intermediate regeneration signals (POUT and NOUT); and the two signal output ends (Q and QN) are respectively connected to the output ports (VOUTP and VOUTN) of the comparator.

2. The low kickback noise integrable dynamic voltage comparator of claim 1, wherein, The pair of input units (210 and 220) work in two modes under the control of the input clock signal (CLK), namely a reset mode and a comparison mode; In the reset mode, the input clock signal (CLK) resets the intermediate regeneration signals (POUT and NOUT) to the power supply voltage (VDD); In the comparison mode, the input comparison stage circuit (200) behaves as a positive feedback function, so that the intermediate regeneration signals (POUT and NOUT) compete with each other and finally converge to logic 1 and logic 0 voltages respectively.

3. The low kickback noise programmable dynamic voltage comparator of claim 1, wherein, The SR latch (310) works in two modes under the control of the input clock signal (CLK), namely a latch mode and an update mode; In the latch mode, the intermediate regeneration signals (POUT and NOUT) are the power supply voltage (VDD), and after being inverted, both are zero level (VSS), so that the output signals (VOUTN and VOUTP) remain unchanged. When the update mode is in progress, if S is high and R is low, the output signals (VOUTN and VOUTP) are low and high respectively; otherwise, if S is low and R is high, the output signals (VOUTN and VOUTP) are high and low respectively.

4. The low kickback noise programmable dynamic voltage comparator of claim 1, wherein, The dynamic voltage comparator works in two phases: reset phase and comparison phase. In the reset phase, the reset clock (CLK) is off; the intermediate regeneration signals (POUT and NOUT) are reset to the power supply voltage (VDD); the input signals (VINP and VINN) are sampled at this time; the output latch stage circuit (300) is in the latch mode, and the output signals (VOUTP and VOUTN) remain unchanged. In the comparison phase, the reset clock (CLK) is on; the input comparison stage circuit (200) is in the comparison mode; the intermediate regeneration signals (POUT and NOUT) start to discharge at different speeds according to the size of the input signals (VINP and VINN); when the fast discharging end discharges to the level that makes the PMOS transistor of the other end conduct, the positive feedback mechanism is triggered; finally, due to the cross positive feedback, it converges to different logic levels 0 or 1.

5. The low kickback noise integratable dynamic voltage comparator of claim 1, wherein, The clock delay module (100), the input comparison stage circuit (200) and the output latch stage circuit (300) are all realized by digital standard cells.

Images