Memory Device and Method for Detecting Error Bits

Abstract

The present invention provides a memory device and a method for detecting error bits. The memory device includes a syndrome generation circuit and a plurality of latch circuits. The syndrome generation circuit includes a plurality of input terminals and a plurality of logic circuits. The latch circuits are coupled to the syndrome generation circuit and configured to set the input terminals of the syndrome generation circuit to a predetermined logic state according to a precharge reset signal. The latch circuits are configured to provide a plurality of data bits to the input terminals of the syndrome generation circuit after setting the input terminals of the syndrome generation circuit to the predetermined logic state. The syndrome generation circuit is configured to generate a syndrome bit based on the data bits through the logic circuits, where the syndrome bit indicates whether there is an error bit among the data bits.

Description

Technical Field

[0001] The present invention relates to a memory device, and more particularly, to a memory device and a method capable of improving error detection performance in the memory device. Background Art

[0002] Error detection schemes such as error correction code (ECC) and cyclic redundancy check (CRC) are widely used in memory devices to detect errors that may potentially occur in the memory device. In an error detection scheme, data bits stored in a memory device may include original data and check codes (such as spare data) for detecting errors. To detect the presence of an error in the data bits, the error detection scheme may use an exclusive OR (XOR) gate to perform a comparison between the original data and the spare data. Since a large number of comparisons must be performed to detect an error in the data bits, the speed of the error detection scheme mainly depends on the delay of the XOR gate. Therefore, there is an urgent need to improve the speed at which the memory device performs the error detection scheme. Summary of the Invention

[0003] The present invention introduces a memory device and a method capable of improving error detection performance in the memory device.

[0004] In an embodiment of the present invention, a method for detecting an error bit includes the steps of: setting a plurality of input terminals of a syndrome generation circuit to a predetermined logic state according to a precharge reset signal; after setting the plurality of input terminals of the syndrome generation circuit to the predetermined logic state, providing a plurality of data bits to the plurality of input terminals of the syndrome generation circuit; and generating a syndrome bit based on the plurality of data bits by a plurality of logic circuits of the syndrome generation circuit, wherein the syndrome bit indicates whether there is an error bit among the plurality of data bits.

[0005] In an embodiment of the present invention, a memory device includes a syndrome generation circuit and a plurality of latch circuits. The syndrome generation circuit includes a plurality of input terminals and a plurality of logic circuits. The plurality of latch circuits are coupled to the syndrome generation circuit and configured to set the plurality of input terminals of the syndrome generation circuit to a predetermined logic state according to a precharge reset signal. After setting the input terminals of the syndrome generation circuit to the predetermined logic state, the plurality of latch circuits provide a plurality of data bits to the plurality of input terminals of the syndrome generation circuit. The syndrome generation circuit is configured to generate a syndrome bit based on the plurality of data bits by the plurality of logic circuits, wherein the syndrome bit indicates whether there is an error bit among the plurality of data bits. Brief Description of the Drawings

[0006] Figure 1 is a schematic diagram showing a memory device according to an embodiment of the present invention;

[0007] Figure 2 is a schematic diagram showing an error detection circuit of a memory device according to an embodiment of the present invention;

[0008] Figure 3 is a schematic diagram showing a latch circuit according to an embodiment of the present invention;

[0009] Figures 4A to 4B show the logic states of XOR gates in a syndrome generation circuit without a precharge scheme;

[0010] Figures 5A to 5B show the logic states of XOR gates in a syndrome generation circuit with a precharge scheme according to an embodiment of the present invention;

[0011] Figures 6A to 6C shows an XOR gate according to an embodiment of the present invention;

[0012] Figure 7 is a waveform diagram showing signals in an error detection circuit according to an embodiment of the present invention;

[0013] Figure 8 is a flowchart showing a method for detecting an error bit in a memory device according to an embodiment of the present invention.

[0014] Description of Reference Numerals in the Drawings

[0015] 100: Memory device;

[0016] 110, 210: Error detection circuit;

[0017] 112, 212: Syndrome generation circuit;

[0018] 120: Input / output circuit;

[0019] 130: Memory array;

[0020] 140: Controller;

[0021] 214, 214a: Latch circuit;

[0022] 801, 802, 803: Steps;

[0023] 2141: NAND gate;

[0024] 2142, 2143, 2144: NOT gate;

[0025] A, N11, N21, N31: Nodes;

[0026] CLK: Latch clock signal;

[0027] H: High logic state;

[0028] IN: Data bit;

[0029] L: Low logic state;

[0030] OUT: Output;

[0031] P0, P1, P2, N0, N1, N2: Transistors;

[0032] P1, P2, P3, P4: Pulses;

[0033] PRE: Precharge reset signal;

[0034] Q: Output terminal;

[0035] S1, S2, S3, S4, S5, S6: Stages;

[0036] SB: Syndrome bit;

[0037] t1, t2, t3: Time;

[0038] T1 to Tn: Input terminals;

[0039] Vdd: Supply voltage;

[0040] VP, VN: Terminals;

[0041] Wr_CMD: Write command;

[0042] X11 to X1m, X21 to X2k, X31 to X3p, X41, X42, X43, X51, X60, X61: Exclusive - OR gates;

[0043] CLK: Inverted latch clock signal. Detailed implementation manners

[0044] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals are used in the drawings and the description to refer to the same or similar parts.

[0045] Reference Figure 1, the memory device 100 includes an error detection circuit 110, an input / output (IO) circuit 120, a memory array 130, and a controller 140. The memory array 130 may include a plurality of memory cells (not shown) configured to store data. In some embodiments, the memory array 130 is a double data rate synchronous dynamic random access memory (DDR SDRAM) or a low power DDR SDRAM, but the present invention is not limited thereto. The memory array 130 may be a volatile memory array (e.g., a static random-access memory (SRAM) array or a dynamic random access memory (DRAM) array), or a non-volatile memory array (e.g., a flash memory array).

[0046] In some embodiments, the IO circuit 120 is coupled to the error detection circuit 110 and configured to provide data bits to the error detection circuit 110, and the error detection circuit 110 is used to detect errors in the data bits. In some embodiments, the IO circuit 120 provides the function of a connection interface configured to connect the error detection circuit 110 to other circuits of the memory device 100.

[0047] The error detection circuit 110 is configured to detect whether there is an error in the data bits based on an error detection code added to the data bits during an encoding operation. After the encoding operation, the encoded data bits may include the original data and the error detection code (e.g., a parity bit), and the encoded data bits are stored at a specified address in the memory array 130, where the original data refers to the payload data or the actual data containing the stored information; and the addition of the error detection code to the original data is used to detect possible errors in the data bits. Examples of error detection codes are Hamming codes, but the present invention is not limited to any specific algorithm or method for generating or adding error detection codes. The error detection circuit 110 may compare the original data in the data bits with the error detection code to detect errors in the data bits. In some embodiments, the error detection circuit 110 includes a syndrome generation circuit 112 configured to perform a comparison with the bits in the data bits to generate syndrome bits. The syndrome bits may indicate the presence of errors in the data bits. For example, when the syndrome bits are in a first logic state (e.g., a high logic state or a logic state "1"), they can be used to indicate that there is at least one error in the data bits. When the syndrome bits are in a second logic state (e.g., a low logic state or a logic state "0"), they can be used to indicate that there is no error in the data bits.

[0048] The controller 140 includes logic circuitry configured to control the operation of the memory device 100. For example, the controller 140 may be coupled to the error detection circuit 110 to send control commands to the error detection circuit 110 to control the operation of the error detection circuit 110. The controller 140 may also be coupled to the IO circuit 120 to send control commands to the IO circuit 120 and other circuits of the memory device 100 to control the operation of the IO circuit 120 and other circuits. The structure and architecture of the controller 140 are not intended to limit the present invention.

[0049] Figure 2 The error detection circuit 210 in Figure 1 may be the same as the error detection circuit 110 of the memory device 100 in Figure 2 . Referring to

[0050] , the error detection circuit 210 includes a syndrome generation circuit 212 and a latch circuit 214 coupled to the syndrome generation circuit 212. The syndrome generation circuit 212 may include a plurality of input terminals T1 to Tn configured to receive data bits IN from the latch circuit 214, where n is a positive integer. In some embodiments, n is equal to the number of bits of the data bits IN. For example, if the data bits IN are 64-bit data, then the syndrome generation circuit 212 includes 64 input terminals for receiving 64-bit data.

[0051] The XOR gates X11 to X1m of stage S1 are coupled to the latch circuit 214 to receive data bits from the latch circuit 214, and are configured to perform an XOR operation on the received data bits IN to generate a first logical output at the output terminals of the XOR gates X11 to X1m. The output terminals of the XOR gates X11 to X1m of stage S1 are coupled to the input terminals of the XOR gates X21 to X2k of stage S2. The XOR gates X21 to X2k of stage S2 are configured to receive the first logical output from the output terminals of the XOR gates X11 to X1m, and perform an XOR logical operation on the received first logical output to generate a second logical output at the output terminals of the XOR gates X21 to X2k. Similarly, the XOR gates X31 to X3p in stage S3 perform an XOR logical operation on the second logical output from the XOR gates X21 to X2k to generate a third logical output at the output terminals of the XOR gates X31 to X3p. The XOR gates X41 to X43 receive the third logical output from the XOR gates X31 to X3p and perform an XOR logical operation on the third logical output to generate a fourth logical output at the output terminals of the XOR gates X41 to X43. The XOR gate X51 in stage S5 receives the third logical output from the XOR gates X41 and X42 and performs an XOR logical operation to generate a fifth logical output. The XOR gate X61 in stage 6 performs an XOR logical operation on the outputs of the XOR gates X43 and X51 to generate a syndrome bit SB. It should be noted that the number of XOR stages in the syndrome generation circuit 210 is not limited to the six stages S1 to S6 as shown in Figures 6A to 6C . The number of XOR stages in the syndrome generation circuit 210 is determined according to design requirements. For example, the number of XOR stages is determined according to the number of bits in the data bit IN.

[0052] In some embodiments, the value of the syndrome bit SB may indicate the presence of an error in the data bit IN. For example, when the syndrome bit SB value is in the first logical state (e.g., "1"), it indicates that there is an error in the data bit. A correction procedure may be executed when an error is detected to correct the error bit. When the syndrome bit SB value is in the second logical state (e.g., "0"), it indicates that there is no error in the data bit IN.

[0053] In some embodiments, the latch circuit 214 is coupled to input terminals T1 to Tn of the syndrome generation circuit 212 and is configured to set the input terminals T1 to Tn of the syndrome generation circuit 212 to a predetermined logic state based on a precharge reset signal PRE. In some embodiments, the predetermined logic state is a high logic state, but in some alternative embodiments, the predetermined logic state may be a low logic state. To set the input terminals T1 to Tn of the syndrome generation circuit 212 to the predetermined logic state, the latch circuit 214 may precharge the input terminals T1 to Tn of the syndrome generation circuit 212 to a predetermined voltage level (e.g., supply voltage Vdd) equal to the high logic state. It should be noted that the memory device may further include a precharge circuit (not shown) and / or a voltage generation circuit (not shown) configured to assist the latch circuit 214 in precharging the input terminals T1 to Tn to the predetermined voltage level (or predetermined logic state).

[0054] In some embodiments, the latch circuit 214 is further configured to latch data bits IN received from an IO circuit (e.g., Figure 1 the IO circuit 120 in

[0055] Figure 3 FIG. shows a latch circuit 214a including a node A, a NAND gate 2141, and NOT gates 2142, 2143, and 2144 according to some embodiments. Figure 2 The latch circuit 214 in Figure 3A plurality of latch circuits 214a as shown, and each latch circuit 214a may correspond to one of the input terminals T1 to Tn. In some embodiments, the NAND gate 2141 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is coupled to node A, the second input terminal is coupled to receive a precharge reset signal PRE, and the output terminal is coupled to the NOT gate 2142. The NAND gate 2141 is configured to perform a NAND operation on the signal at node A and the precharge reset signal PRE to generate an output result at the output terminal of the NAND gate 2141. In some embodiments, when the precharge reset signal PRE is in a low logic state, the NAND gate 2141 is configured to output a low logic state at the output terminal of the NAND gate 2141.

[0056] The NOT gate 2142 is coupled between the NAND gate 2141 and node A and operates according to an inverted latch clock signal / CLK. In some embodiments, when the inverted latch clock signal / CLK is in a high logic state, the NOT gate 2142 is enabled to perform a NOT operation on the output result from the NAND gate 2141. When the inverted latch clock signal / CLK is in a low logic state, the NOT gate 2142 is disabled. In some embodiments, when the precharge reset signal PRE is enabled, the NOT gate 2142 is enabled to perform a NOT operation on the output result of the NAND gate 2141, thereby setting node A to a low logic state. When node A is set to a low logic state, due to the operation of the NOT gate 2144, the output OUT of the latch circuit 214a is set to a high logic state (e.g., a predetermined logic state).

[0057] In some embodiments, the NOT gate 2143 includes an input terminal and an output terminal, where the input terminal is coupled to an IO circuit (e.g., Figure 1 the IO circuit 120 therein) to receive a data bit IN, and the output terminal is coupled to node A of the latch circuit 214a. In some embodiments, the NOT gate 2143 is operated with a latch clock signal CLK. In other words, when the latch clock signal CLK is in a high logic state, the NOT gate 2143 is enabled to perform a NOT operation on the data bit IN, and when the latch clock signal CLK is in a low logic state, the NOT gate 2143 is disabled. In some embodiments, after setting the output OUT of the latch circuit 214a to a predetermined logic state, the NOT gate 2143 is enabled to latch the data bit IN to the output OUT of the latch circuit 214a. Since the output terminal of the latch circuit 214a is coupled to the input terminal of a syndrome generation circuit (e.g., Figure 2 the syndrome generation circuit 212 therein), before latching the data bit IN to the input terminal of the syndrome generation circuit, the input terminal of the syndrome generation circuit is set to a predetermined logic state.

[0058] Figures 4A and 4B illustrate an example of a syndrome generation circuit, in which input terminals T1 to T8 are not precharged to a predetermined logic state (e.g., high logic state H) before data bits IN are provided to input terminals T1 to T8. Referring to FIG. 4A, since the input terminals are not precharged to a predetermined logic state, the logic states at input terminals T1 to T8 are random between the high logic state H and the low logic state L. In FIG. 4B, when data bits IN are provided to input terminals T1 to T8, the logic states at input terminals T1 to T8 randomly change from the low logic state to the high logic state and from the high logic state to the low logic state. Accordingly, the logic states of the XOR gates in subsequent stages S1 to S3 randomly change from the high logic state to the low logic state and from the low logic state to the high logic state. For example, the logic state at terminal T2 changes from the high logic state to the low logic state due to data bits IN; node N11 in stage S1 has a low logic state; node N21 in stage S2 has a low logic state; and node N31 in stage S3 has a high logic state. Since the comparison speed of an XOR gate depends on its input logic state, the randomly changing input logic states may render the speed of the XOR gates in the syndrome generation circuit unpredictable.

[0059] Figure 5A and Figure 5B illustrates an example of a syndrome generation circuit 212 according to some embodiments, in which input terminals T1 to T8 are precharged to a predetermined logic state before data bits IN are provided to input terminals T1 to T8. Referring Figure 5A to, before data bits IN are latched into input terminals T1 to T8, input terminals T1 to T8 of the syndrome generation circuit 212 are set to the high logic state H based on a precharge reset signal PRE. All of the XOR gates in stages S1 to S3 are in the low logic state L. Referring Figure 5B to, when data bits IN are latched into input terminals T1 to T8 of the syndrome generation circuit 212, the change in the logic states at input terminals T1 to T8 is limited to a high-to-low transition. For Figure 5A the Figure 5B example shown in and, when data bits IN are latched into input terminals T1 to T8, the logic state at input terminal T1 changes from the high logic state H to the low logic state L, and the logic states at the other input terminals T2 to T8 remain unchanged in the high logic state H. Since the change in the logic states at input terminals T1 to T8 is limited to a high-to-low transition, the XOR gates can have the speed of the XOR operations performed by the XOR gates designed in an optimized manner.

[0060] Figures 6A to 6C An XOR gate X60 having an input terminal T61, an input terminal T62, and an output terminal Q is shown in accordance with some embodiments. Figures 6A to 6C The XOR gate X60 shown in Figure 2 may be one of the XOR gates of the syndrome generation circuit 212 shown in

[0061] Refer to Figure 6A , the input terminals T61 and T62 of the XOR gate X60 are in a high logic state H. In this embodiment, the high logic state H at the input terminals T61 and T62 of the XOR gate X60 is set by a latch circuit (such as Figure 2 the latch circuit 214 in

[0062] Refer to Figure 6B , when the input terminal T61 has a low logic state L and the input terminal T62 has a high logic state H, compared with Figure 6A , the transistor P0 is turned on and the transistor N0 is turned off to output a high logic state H to the output terminal Q of the XOR gate X60. Thus, when the input terminal T61 has a low logic state L and the input terminal T62 has a high logic state H, the operation speed of the XOR gate X60 mainly depends on the turn-on speed of the turned-on transistor P0. Refer to Figure 2 , Figure 6A and Figure 6B , when the logic state at the input terminal T61 changes from the high logic state H to the low logic state L and the logic state of the input terminal T62 remains at the high logic state H (for example, when receiving a data bit IN), the operation speed of the XOR gate X60 mainly depends on the switching speed of the transistor P0. Thus, the transistor P0 can be designed in such a way as to increase the switching speed of the transistor P0.

[0063] Reference Figure 6C , when the input terminal T61 has a high logic state H and the input terminal T62 has a low logic state L, compared with Figure 6A , the transistor P1, the transistor P2, and the transistor N1 are turned on and the transistor N2 is turned off to output a high logic state H at the output terminal of the XOR gate X60. When the input terminal T61 has a high logic state H and the input terminal T62 has a low logic state L, the operation speed of the XOR gate X60 depends on the turn-on speed of the transistor P1. Reference Figure 2 , Figure 6A and Figure 6C , when the logic state at the input terminal T61 remains at the high logic state H and the logic state of the input terminal T62 changes from the high logic state H to the low logic state L (for example, when receiving the data bit IN), the operation speed of the XOR gate X60 depends on the switching speed of the transistor P1. Therefore, the transistor P1 can be designed in a way that increases the switching speed of the transistor P1.

[0064] In some embodiments, the transistors P0 and P1 of the XOR gate X60 are designed such that the switching speeds of the transistors P0 and P1 are faster than the switching speeds of the other transistors (such as transistors N0, N1, N2, and P2) of the XOR gate X60. Since the switching speed of a transistor depends on the size of the transistor, the sizes of the transistors P0 and P1 of the XOR gate X60 can be designed to be larger than the sizes of the other transistors N0, N1, N2, and P2 in the XOR gate X60. The size of a transistor can be determined based on the length and / or width of the transistor. In some embodiments, the widths of the transistors P0 and P1 in the XOR gate X60 are greater than the widths of the transistors N0, N1, N2, and P2 in the XOR gate X60. It should be noted that any technique that makes the switching speeds of the transistors P0 and P1 in the XOR gate X60 faster than the switching speeds of the other transistors in the XOR gate X60 falls within the scope of the present invention.

[0065] Figure 7 Shows exemplary waveforms of signals in an error detection circuit according to some embodiments. Reference Figure 3 and Figure 7 , the precharge reset signal PRE is configured to set the input terminal of the syndrome generation circuit to a predetermined logic state (such as a high logic state H) before latching the data bit IN to the input terminal of the syndrome generation circuit. When the precharge reset signal changes from the high logic state to the low logic state (such as pulse P1) at time t1, Figure 3 the latch circuit 214a in

[0066] After a short delay after time t1, the signal at node A (e.g., the node in Figure 3 ) changes from a high logic state to a low logic state (e.g., pulse P2) at time t2, thereby setting the output terminal OUT of the latch circuit (e.g., the latch circuit 214a in Figure 3 ) to a predetermined logic state (e.g., pulse P3). Since the output terminal OUT of the latch circuit is coupled to the input terminal of the syndrome generation circuit, the input terminal of the syndrome generation circuit is set to a predetermined logic state based on the precharge reset signal PRE.

[0067] After setting the input terminal of the syndrome generation circuit to a predetermined logic state, the latch clock CLK (e.g., pulse P4) is enabled at time t3 to latch the data bit IN into the input terminal of the syndrome generation circuit. In other words, after setting the input terminal of the syndrome generation circuit to a predetermined logic state, the data bit IN is latched into the input terminal of the syndrome generation circuit by the latch circuit.

[0068] Figure 7 Further shown is the column-to-column delay (tCCD), which is the minimum time delay for accessing another memory column of the memory array after accessing one memory column. The access operation may include a write operation configured to write data to the memory array (e.g., memory array 130), and a read operation configured to read data stored in the memory array. In some embodiments, the precharge reset signal PRE is enabled in response to an access command (e.g., a write command or a read command). In other words, an error detection operation is performed to detect an error in the data bits during a read operation or a write operation. In Figure 7 , the write command Wr_CMD may trigger the precharge reset signal PRE. In another example, a read command (not shown in the figure) may also trigger the precharge reset signal PRE.

[0069] Figure 8 A flowchart of a method for detecting error bits according to an embodiment of the present invention is shown. In step 801, a plurality of input terminals of the syndrome generation circuit are set to a predetermined logic state according to the precharge reset signal. In step 802, after setting the plurality of input terminals of the syndrome generation circuit to a predetermined logic state, a plurality of data bits are provided to the plurality of input terminals of the syndrome generation circuit. In step 803, a plurality of logic circuits of the syndrome generation circuit generate syndrome bits based on the plurality of data bits, where the syndrome bits indicate whether there are error bits among the plurality of data bits. For example, when the syndrome bit is in a high logic state, it indicates that there is an error in the data bits; and when the syndrome bit is in a low logic state, it indicates that there is no error in the data bits.

[0070] In the above embodiments, before latching data bits to the input terminals of the syndrome generation circuit, a plurality of input terminals of the syndrome generation circuit in the error detection circuit are precharged to a predetermined logic state. In this way, the change in the logic state of the input terminals of the syndrome generation circuit is restricted to a specific transition (e.g., a transition from high to low). Since the change in the logic state is restricted to a specific transition rather than a random transition, the XOR gate can be configured to optimize the operation speed of the XOR gate. For example, the size of the transistors in the XOR gate can be configured to increase the operation speed of the XOR gate. Consequently, the delay time caused by the comparison performed by the XOR gate is reduced, and the performance of error detection in the memory device is improved.

[0071] It will be apparent to those skilled in the art that various modifications and variations can be made to the described embodiments of the invention without departing from the scope or spirit of the invention. Given the foregoing, it is intended that the invention cover the modifications and variations provided they come within the scope of the appended claims and their equivalents.

Claims

1. A method for detecting an error bit, comprising: setting a plurality of input terminals of a syndrome generation circuit to a predetermined logic state according to a precharge reset signal; after setting the plurality of input terminals of the syndrome generation circuit to the predetermined logic state, providing a plurality of data bits to the plurality of input terminals of the syndrome generation circuit; and generating a syndrome bit by a plurality of logic circuits of the syndrome generation circuit based on the plurality of data bits, wherein the syndrome bit is configured to indicate whether there is an error bit among the plurality of data bits, wherein setting the plurality of input terminals of the syndrome generation circuit to the predetermined logic state according to the precharge reset signal includes: providing a plurality of latch circuits coupled to the plurality of input terminals of the syndrome generation circuit, each of the plurality of latch circuits including a first logic circuit, a second logic circuit, a third logic circuit, and a fourth logic circuit, an output terminal of the first logic circuit being coupled to an input terminal of the second logic circuit, an output terminal of the third logic circuit being coupled to an input terminal of the fourth logic circuit via a node, and an output terminal of the second logic circuit being coupled to the node; performing a first logic operation on the precharge reset signal and a signal on the node by the first logic circuit to generate a first intermediate bit; when a reverse latch clock signal is in a high logic state, enabling the second logic circuit to perform a second logic operation on the first intermediate bit to generate a second intermediate bit; when a latch clock signal is in the high logic state, enabling the third logic circuit to perform a third logic operation on one of the plurality of data bits to output a third intermediate bit to the node; and performing a fourth logic operation on the signal on the node to set one of the plurality of input terminals of the syndrome generation circuit to the predetermined logic state, and providing one of the plurality of data bits to one of the plurality of input terminals of the syndrome generation circuit.

2. The method for detecting an error bit according to claim 1, wherein each of the plurality of data bits has a low logic state or a high logic state, and the predetermined logic state is the high logic state.

3. The method for detecting an error bit according to claim 2, wherein generating the syndrome bit based on the plurality of data bits comprises: inputting a first data bit and a second data bit among the plurality of data bits through each of the plurality of logic circuits; performing a logic operation on the first data bit and the second data bit by each of the plurality of logic circuits to generate an output bit; and generating the syndrome bit based on the output bit.

4. The method for detecting an error bit according to claim 3, wherein the plurality of logic circuits are exclusive-OR logic circuits, and the logic operation is an exclusive-OR operation.

5. The method for detecting an error bit according to claim 3, wherein Each of the plurality of logic circuits includes a plurality of transistors, the plurality of transistors including a first transistor and a second transistor, a gate terminal of the first transistor being coupled to receive the first data bit, and a gate terminal of the second transistor being coupled to receive the second data bit, When the first data bit is different from the second data bit, one of the first transistor and the second transistor is turned on during the logic operation, When the first data bit is different from the second data bit, the other of the first transistor and the second transistor is turned off during the logic operation, and The switching speed of one of the first transistor and the second transistor is faster than the switching speed of the other of the first transistor and the second transistor.

6. The method of detecting an error bit according to claim 5, wherein a size of one of the first transistor and the second transistor is larger than a size of the other of the first transistor and the second transistor.

7. The method of detecting an error bit according to claim 1, further comprising: Receiving a write command signal configured to enable a write operation to write the data bit to the memory, wherein the precharge reset signal is enabled in response to receiving the write command signal to precharge the plurality of input terminals to the predetermined logic state.

8. A memory device for detecting an error bit, comprising: A syndrome generation circuit including a plurality of input terminals and a plurality of logic circuits; and A plurality of latch circuits coupled to the syndrome generation circuit and configured to set the plurality of input terminals of the syndrome generation circuit to a predetermined logic state according to a precharge reset signal, and after setting the plurality of input terminals of the syndrome generation circuit to the predetermined logic state, provide a plurality of data bits to the plurality of input terminals of the syndrome generation circuit, wherein the syndrome generation circuit is configured to generate a syndrome bit based on the plurality of data bits through the plurality of logic circuits, and the syndrome bit indicates whether there is an error bit among the plurality of data bits, wherein each of the plurality of latch circuits includes an input terminal, a first logic circuit, a second logic circuit, a third logic circuit, a fourth logic circuit, and an output terminal, An input terminal of each of the plurality of latch circuits is coupled to receive one of the plurality of data bits, An output terminal of each of the plurality of latch circuits is coupled to one of the plurality of input terminals of the syndrome generation circuit, The first logic circuit is configured to perform a first logic operation on a signal at a node between the third logic circuit and the fourth logic circuit and the precharge reset signal to generate a first intermediate bit, The second logic circuit is coupled between the first logic circuit and the node and is configured to perform a second logic operation on the first intermediate bit when the reverse latch clock signal is in a high logic state to generate a second intermediate bit, The third logic circuit is coupled between the input terminal and the node, and is configured to perform a third logic operation on one of the plurality of data bits to output a third intermediate bit to the node when the latch clock signal is in the high logic state. The fourth logic circuit is coupled between the node and the output terminal, and is configured to perform a fourth logic operation on the signal on the node to set the plurality of input terminals of the syndrome generation circuit to the predetermined logic state, and to provide one of the plurality of data bits to one of the plurality of input terminals of the syndrome generation circuit.

9. The memory device for detecting an error bit according to claim 8, wherein each of the plurality of data bits has a low logic state or a high logic state, and the predetermined logic state is the high logic state.

10. The memory device for detecting an error bit according to claim 9, wherein the plurality of logic circuits are exclusive - OR logic circuits, and the exclusive - OR logic circuits are configured to perform an exclusive - OR operation on the plurality of data bits to generate the syndrome generation bit.

11. The memory device for detecting an error bit according to claim 10, wherein each of the plurality of logic circuits includes a first input terminal for receiving a first data bit among the plurality of data bits and a second input terminal for receiving a second data bit among the plurality of data bits, and each of the plurality of logic circuits is configured to perform a logic operation on the first data bit and the second data bit to generate an output bit, and generate the syndrome bit based on the output bit.

12. The memory device for detecting an error bit according to claim 11, wherein each of the plurality of logic circuits includes a plurality of transistors, the plurality of transistors including a first transistor and a second transistor, a gate terminal of the first transistor is coupled to receive the first data bit, and a gate terminal of the second transistor is coupled to receive the second data bit, when the first data bit is different from the second data bit, one of the first transistor and the second transistor is turned on during the logic operation, when the first data bit is different from the second data bit, the other of the first transistor and the second transistor is turned off during the logic operation, and a switching speed of one of the first transistor and the second transistor is faster than that of the other of the first transistor and the second transistor.

13. The memory device for detecting an error bit according to claim 12, wherein a size of one of the first transistor and the second transistor is larger than a size of the other of the first transistor and the second transistor.

14. The memory device for detecting an error bit according to claim 10, wherein the plurality of logic circuits are arranged in a multi - stage binary tree structure, the multi - stage binary tree structure includes a plurality of stages, the plurality of stages including a first stage and a second stage, the first stage includes a plurality of first exclusive - OR logic circuits among the plurality of logic circuits. The second stage includes a plurality of second exclusive-OR logic circuits among the plurality of logic circuits, and output terminals of the plurality of first exclusive-OR logic circuits in the first stage are coupled to input terminals of the plurality of second exclusive-OR logic circuits in the second stage.

15. The memory device for detecting error bits according to claim 8, further comprising: a memory array configured to store data, wherein the precharge reset signal is enabled in response to receiving a write command signal to set the plurality of input terminals of the syndrome generation circuit to the predetermined logic state, and the write command signal is configured to enable a write operation to write the data bit into the memory array.

16. The memory device for detecting error bits according to claim 15, further comprising: an input / output circuit coupled to the plurality of latch circuits and configured to provide the data bit to the plurality of latch circuits.

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