Bonded assemblies formed by using hybrid wafer bonding with selective deposition of metal liners

Abstract

A nucleation-inhibiting layer including a self-assembling material can be formed on a surface of a bonding dielectric layer without depositing the self-assembling material on a physically exposed surface of a first metal bonding pad of a first semiconductor die. A metal liner including a second metal can be formed on the physically exposed surface of the metal bonding pad without depositing the second metal on the nucleation-inhibiting layer. The first semiconductor die can be bonded to a second semiconductor die by inducing a metal-to-metal bond between a mating pair of the first metal bonding pad and the second metal bonding pad of the second semiconductor die.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductor devices, and in particular, to bonded assemblies employing selectively grown metal liners for hybrid wafer bonding and methods for forming the same. BACKGROUND

[0002] A memory die containing a three-dimensional memory device including three- dimensional vertical NAND strings having one bit per cell is disclosed in T. Endoh et al., "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell," IEDM Proc. (2001) 33-36. SUMMARY

[0003] According to embodiments of the present disclosure, a method of forming a bonded assembly includes providing a first semiconductor die including a first semiconductor device, a first bonding dielectric layer, and a first metal bonding pad including a first metal, the first metal bonding pad electrically connected to a respective node of the first semiconductor device and embedded in the first bonding dielectric layer; selectively depositing a first nucleation-inhibiting layer including a self-assembly material on a surface of the first bonding dielectric layer without depositing the self-assembly material on a physically exposed surface of the first metal bonding pad; selectively depositing a first metal liner including a second metal on the physically exposed surface of the first metal bonding pad without depositing the second metal on the first nucleation-inhibiting layer; providing a second semiconductor die including a second semiconductor device, a second bonding dielectric layer, and a second metal bonding pad electrically connected to a respective node of the second semiconductor device and embedded in the second bonding dielectric layer; and bonding the second metal bonding pad with the first metal bonding pad by inducing a metal-to-metal bond between each mating pair of the first metal bonding pad and the second metal bonding pad.

[0004] According to another embodiment, a bonded assembly includes: a first semiconductor die including first semiconductor devices, first metal interconnect structures embedded in a first dielectric material layer, and first metal bonding pads including a first metal and embedded in a first bonding dielectric layer; a second semiconductor die including second semiconductor devices, second metal interconnect structures embedded in a second dielectric material layer, and second metal bonding pads including the first metal and embedded in a second bonding dielectric layer and bonded to respective ones of the first metal bonding pads; an interfacial alloy region including an alloy of the first metal and a second metal different from the first metal, the interfacial alloy region located between each of the first metal bonding pads and each of the second metal bonding pads bonded to a respective one of the first metal bonding pads; and an interfacial dielectric region located at an interface between the first bonding dielectric layer and the second bonding dielectric layer, wherein the interfacial dielectric region includes carbon atoms at an average atomic concentration that is greater than twice an average atomic concentration of carbon in the first bonding dielectric layer and greater than twice an average atomic concentration of carbon in the second bonding dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a schematic vertical cross-sectional view of a first semiconductor die after formation of a first bonding dielectric layer and first metal bonding pads according to an embodiment of the disclosure.

[0006] Figure 2 is a schematic vertical cross-sectional view of a first semiconductor die after selective deposition of a first nucleation inhibition layer according to an embodiment of the disclosure.

[0007] Figure 3 is a zoomed-in view of a region of the first nucleation inhibition layer of Figure 2

[0008] Figure 4 is a schematic vertical cross-sectional view of a first semiconductor die after selective deposition of a first metal liner according to an embodiment of the disclosure.

[0009] Figure 5 is a schematic vertical cross-sectional view of a second semiconductor die according to an embodiment of the disclosure.

[0010] Figure 6 is a schematic vertical cross-sectional view of a second semiconductor die after selective deposition of a second nucleation inhibition layer according to an embodiment of the disclosure.

[0011] Figure 7 is a schematic vertical cross-sectional view of a second semiconductor die after selective deposition of a second metal liner according to an embodiment of the disclosure. ​

[0012] Figure 8 is a schematic vertical cross-sectional view of an exemplary structure including a first semiconductor die and a second semiconductor die after disposing a second metal bonding pad over a first metal bonding pad according to embodiments of the present disclosure.

[0013] Figure 9 is a schematic vertical cross-sectional view of an exemplary structure after bonding a second semiconductor die to a first semiconductor die according to embodiments of the present disclosure.

[0014] Figure 10A is a zoomed-in view of an interface alloy region within the exemplary structure of Figure 9 is a zoomed-in view of a bonding pair of a first metal pad and a second metal pad within the exemplary structure of Figure 10B is a zoomed-in view of an interface alloy region within the exemplary structure of Figure 10A is a zoomed-in view of an interface alloy region within the exemplary structure of

[0015] Figure 11 is a schematic vertical cross-sectional view of an exemplary structure after thinning a first substrate and forming a through-substrate via structure through the first substrate according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Metal-to-metal wafer bonding or die-to-die bonding can be used to attach a logic die including peripheral (i.e., driver) circuitry to a memory die. Oxidation of copper metal on the bonding surface reduces the quality of the metal-to-metal bond, and increases the temperature and duration of the bonding process. This adversely affects the quality of the metal-to-metal bond and increases processing costs.

[0017] Embodiments of the present disclosure relate to bonding assemblies employing selectively grown metal liners for hybrid wafer bonding and methods for forming the same, various aspects of which are described in detail herein. Hybrid bonding and selectively grown metal liners allow for lower bonding temperatures and / or bonding process durations, which improve the quality of the bonding assemblies.

[0018] The drawings are not drawn to scale. Where multiple instances of an element are shown in the drawings, multiple instances of the element can be repeated unless explicitly described or otherwise clearly indicated otherwise. Numerical designations such as “first,” “second,” and “third” are merely used to identify like elements and different numerical designations can be employed throughout the specification and claims of the present disclosure. The term “at least one” element means all possibilities including the possibility of a single element and the possibility of multiple elements.

[0019] Like reference numbers indicate like or similar elements throughout. Elements having the same reference numbers are assumed to have the same composition and the same function unless otherwise indicated. “Contact” between elements means direct contact between elements that share an edge or surface unless otherwise indicated. Two or more elements are “separated” from one another if they are not in direct contact with one another or are not directly in contact with one another. As used herein, a first element positioned “on” a second element can be positioned on an outer side of a surface of the second element or on an inner side of the second element. As used herein, a first element is “directly” positioned on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there is an electrically conductive path between the first element and the second element that is comprised of at least one electrically conductive material. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0020] As used herein, a “layer” refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of uniform or non-uniform thickness that is less than the thickness of a continuous structure. For example, a layer can be positioned between or at any pair of horizontal planes between a top surface and a bottom surface of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers thereon, thereabove, and / or therebelow.

[0021] As used herein, first and second surfaces are “vertically coincident” with one another if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first and second surfaces. A substantially vertical plane is a plane that extends linearly along a direction that deviates from a vertical direction by less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction and can or can not include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.

[0022] As used herein, a “memory level” or a “memory array level” refers to a level that corresponds to a general region between a first horizontal plane that includes a topmost surface of an array of memory elements (i.e., a plane that is parallel to a top surface of a substrate) and a second horizontal plane that includes a bottommost surface of the array of memory elements. As used herein, a “through-penetration stack” element refers to an element that extends vertically through a memory level.

[0023] As used herein, a “semiconductor material” refers to a material having a charge carrier concentration of 1.0 x 10-5 S / m to 1.0 x 10 5 S / m. As used herein, a“semiconductor material” refers to a material having electrical conductivity in the range from 1.0 x 10 -5 S / m to 1.0 S / m, and is capable of producing, upon suitable doping with an electrical dopant, a doped material having electrical conductivity in the range from 1.0 S / m to 1.0 x 10 5 S / m. As used herein, an“electrical dopant” refers to a p-type dopant that adds holes to a valence band within a band structure, or an n-type dopant that adds electrons to a conduction band within a band structure. As used herein, a“conductive material” refers to a material having electrical conductivity greater than 1.0 x 10 5 S / m. As used herein, an“insulator material” or a“dielectric material” refers to a material having electrical conductivity less than 1.0 x 10 -5 S / m. As used herein, a“heavily doped semiconductor material” refers to a semiconductor material that is doped with an electrical dopant at a sufficiently high atomic concentration to become a conductive material (i.e., having electrical conductivity greater than 1.0 x 10 5 S / m) when formed as a crystalline material or converted into a crystalline material (e.g., starting from an initial amorphous state) by an annealing process. A“doped semiconductor material” can be a heavily doped semiconductor material, or can be a semiconductor material including an electrical dopant at a concentration providing electrical conductivity in the range from 1.0 x 10 -5 S / m to 1.0 x 10 5 S / m. As used herein, an“insulator material” or a“dielectric material” refers to a material having electrical conductivity less than 1.0 x 10 -5 S / m. As used herein, a“heavily doped semiconductor material” refers to a semiconductor material that is doped with an electrical dopant at a sufficiently high atomic concentration to become a conductive material (i.e., having electrical conductivity greater than 1.0 x 10 5 S / m) when formed as a crystalline material or converted into a crystalline material (e.g., starting from an initial amorphous state) by an annealing process. A“doped semiconductor material” can be a heavily doped semiconductor material, or can be a semiconductor material including an electrical dopant at a concentration providing electrical conductivity in the range from 1.0 x 10 -5 S / m to 1.0 x 10 5 S / m. As used herein, an“insulator material” or a“dielectric material” refers to a material having electrical conductivity less than 1.0 x 10

[0024] Generally, a semiconductor package (or“package”) refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package can include one or more semiconductor chips (or“chips”) that are through-bonded, for example, through flip-chip bonding or another chip-to-chip bonding. A package or chip can include a single semiconductor die (or“die”) or multiple semiconductor dies. A die is the smallest unit that can independently execute an external command or report a status. Typically, a package or chip with multiple dies is capable of executing as many external commands concurrently as the total number of planes in it. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there can be some limitations. In the case where a die is a memory die (i.e., a die that includes memory elements), a concurrent read operation, a concurrent write operation, or a concurrent erase operation can be performed in each plane within the same memory die. In a memory die, each plane contains a plurality of memory blocks (or“blocks”), which are the smallest units that can be erased by a single erase operation. Each memory block contains a plurality of pages, which are the smallest units that can be selected for programming. Pages are also the smallest units that can be selected for read operations.

[0025] Reference Figure 1 FIG. 1 illustrates a first semiconductor die 900 according to embodiments of the present disclosure. The first semiconductor die 900 includes a first substrate 908, a first semiconductor device 920 overlying the first substrate 908, a first dielectric material layer (290, 960, 970) overlying the first semiconductor device, and a first metal interconnect structure 980 embedded in the first dielectric material layer (290, 960, 970). In one embodiment, the first substrate 908 can be a commercially available silicon wafer with a thickness in a range from 500 microns to 1 mm.

[0026] Generally, the first semiconductor device 920 can include any semiconductor device known in the art. In one embodiment, the first semiconductor die 900 includes a memory die and can include a memory device, such as a three-dimensional NAND memory device. In an illustrative example, the first semiconductor device 920 can include a vertically alternating stack of insulating layers 32 and conductive layers 46, and an array of two-dimensional memory openings extending vertically through the vertically alternating stack (32, 46). The conductive layers 46 can include word lines of a three-dimensional NAND memory device.

[0027] Memory opening fill structures 58 can be formed within each memory opening. The memory opening fill structures 58 can include a memory film and a vertical semiconductor channel contacting the memory film. The memory film can include a blocking dielectric, a tunneling dielectric, and a charge storage material located between the blocking dielectric and the tunneling dielectric. The charge storage material can include a charge trapping layer, such as a silicon nitride layer, or a plurality of discrete charge trapping regions, such as floating gates or discrete portions of a charge trapping layer. In this case, each memory opening fill structure 58 and an adjacent portion of the conductive layer 46 constitute a vertical NAND string. Alternatively, the memory opening fill structures 58 can include any type of non-volatile memory element, such as a resistive memory element, a ferroelectric memory element, a phase change memory element, etc. The memory device can include an optional horizontal semiconductor channel layer 10 connected to a bottom end of each vertical semiconductor channel, and an optional dielectric spacer layer 910 providing electrical isolation between the first substrate 908 and the horizontal semiconductor channel layer 10.

[0028] The conductive layer 46 can be patterned to provide a platform region in which each overlying conductive layer 46 has a smaller lateral extent than any underlying conductive layer 46. Contact via structures (not shown) can be formed in the platform region on the conductive layer 46 to provide electrical connections to the conductive layer 46. Dielectric material portions 65 can be formed around each vertical alternating stack (32, 46) to provide electrical isolation between adjacent vertical alternating stacks (32, 46).

[0029] The first dielectric material layers (290, 960, 970) can include a first contact level dielectric layer 290 embedding contact via structures and bit lines 982, a first interconnect level dielectric layer 960 located above the first contact level dielectric layer 290 embedding a subset of the first metal interconnect structures 980, and a first bonding dielectric layer 970 formed above the first interconnect level dielectric layer 960. The bit lines 982 are a subset of the first metal interconnect structures 980 and can electrically contact drain regions above the semiconductor channels at the top of the memory opening fill structures 58. The contact via structures contact various nodes of the first semiconductor device. Interconnect metal lines and interconnect metal via structures, which are a subset of the first metal interconnect structures 980, can be embedded in the first interconnect level dielectric layer 960. The first metal interconnect structures 980 can be located within the first interconnect level dielectric layer 960 or within the first bonding dielectric layer 970.

[0030] Each of the first contact-level dielectric layers 290 and the first interconnect-level dielectric layers 960 can include a dielectric material, such as an undoped silicate glass, a doped silicate glass, an organosilicate glass, silicon nitride, a dielectric metal oxide, or a combination thereof. The first bonding dielectric layer 970 includes and / or consists essentially of a dielectric material that can be bonded to another dielectric material through a dielectric-to-dielectric bond. For example, the first bonding dielectric layer 970 can include and / or consist essentially of a silicon oxide material, such as an undoped silicate glass (e.g., silicon oxide), silicon nitride, or a doped silicate glass, or a silicon carbonitride (i.e., silicon carbonitride, “SiCN”). The first bonding dielectric layer 970 can have a thickness in a range from 100 nm to 3,000 nm, although lesser and greater thicknesses can also be employed. The first bonding dielectric layer 970 can have a planar top surface, which can be provided, for example, through a planarization process such as a chemical-mechanical polishing (CMP) process. The topmost layer of the first interconnect-level dielectric layers 960 can be a dielectric diffusion barrier layer (not explicitly shown), which can be a silicon nitride layer having a thickness in a range from 10 nm to 300 nm. Alternatively, the diffusion barrier layer can be omitted.

[0031] For example, the first metal bonding pads 988 are formed in the first bonding dielectric layer 970 by forming pad cavities in the first bonding dielectric layer 970 and filling the pad cavities with at least one electrically conductive material that includes the first metal. Alternatively, the metal bonding pads 988 are first formed on the first metal interconnect structures 980, then the first bonding dielectric layer 970 is formed over and around the first metal bonding pads 988, then the first bonding dielectric layer 970 is planarized to expose top surfaces of the first metal bonding pads 988. The at least one electrically conductive material can be a metal (i.e., a metal or metal alloy) material that can be bonded to the same metal material or another metal material through a metal-to-metal or hybrid bond. In one embodiment, each of the first metal bonding pads 988 can include an optional metal liner that includes TiN, TaN, and / or WN, and a metal fill material portion that includes the first metal that can be bonded to another portion of the first metal or another metal material through a metal-to-metal bond. In one embodiment, the first metal can be copper or any other metal that is capable of providing a metal-to-metal bond. For example, the metal fill material portion can include and / or consist essentially of any material selected from Cu, a copper alloy (including copper at an atomic concentration greater than 70%, which can be greater than 90% and / or 95%).

[0032] Generally, the first metal bond pads 988 include a first metal that is electrically connected to a respective node of the first semiconductor device 920 and embedded in the first bond dielectric layer 970. Each of the first metal bond pads 988 is surrounded by the first bond dielectric layer 970 and contacts a respective underlying structure in the first metal interconnect structure 980.

[0033] Referring to Figure 2 and Figure 3 , a first nucleation inhibition layer 992 can be formed on a physically exposed surface (e.g., a top surface) of the first bond dielectric layer 970. The first nucleation inhibition layer 992 includes a material that inhibits nucleation of a metal material thereon during a subsequent metal deposition process. Generally, the dielectric material of the first bond dielectric layer 970, such as silicon oxide or silicon carbonitride, does not provide sufficient inhibition of metal material deposition thereon. The function of the first nucleation inhibition layer 992 is to provide inhibition of metal material nucleation during a subsequent metal material deposition process and thereby prevent metal material deposition over areas of the first bond dielectric layer 970. The first nucleation inhibition layer 992 is selectively deposited on the physically exposed surface of the first bond dielectric layer 970 without depositing the first nucleation inhibition material on the physically exposed surface of the first metal bond pads 988. Thus, the first nucleation inhibition layer 992 can be formed as a discrete portion of material on the top surface of the first bond dielectric layer 970.

[0034] In one embodiment, the nucleation inhibition material can be an organic material, such as an organic self-assembled material (SAM), also referred to as a self-assembled monolayer if the material is about one monolayer thick. The organic nucleation inhibition material can be carbon-based and can include silicon atoms. In one embodiment, the nucleation inhibition material molecules can optionally include at least one silicon atom per molecule, can optionally include at least one hydrogen atom per molecule, and / or can optionally include at least one chlorine atom per molecule. In one embodiment, the first nucleation inhibition layer 992 can be formed by a selective deposition process in which the first nucleation inhibition material chemically bonds to the physically exposed surface of the first bond dielectric layer 970 without attaching to the physically exposed surface of the first metal bond pads 988.

[0035] In one embodiment, the first nucleation inhibition layer 992 can include a monolayer of a self-assembled material. In one embodiment, the self-assembled material can include a silicon-containing carbon-based self-assembled material, such as octadecyltrichlorosilane (“ODTS”) (C 18 H 37 Cl3Si), decyltrichlorosilane (“DTS”) (C 10 H 21 Cl3Si), or octylsilane (“OTS”) (C8H 20Si). Thus, by depositing a suspension containing a SAM precursor onto the first metal bonding pad 988 and the first bonding dielectric layer 970, the self-assembling material can be self-assembled onto the physically exposed surface of the first bonding dielectric layer 970 without being attached to the first metal bonding pad 988. Figure 3 In some embodiments shown, each molecule of the SAM material may include a head group having affinity for the dielectric material of the first bonding dielectric layer 970 but not for the first metal bonding pad 988, and a tail group having no affinity for the dielectric material of the first bonding dielectric layer 970 and the first metal bonding pad 988.

[0036] refer to Figure 4 , an atomic layer deposition (ALD) process may be performed to selectively deposit the second metal on the physically exposed metal surface of the first metal bond pad 988 without depositing the second metal on the surface of the first nucleation inhibition layer 992. The second metal is different from the first metal. Typically, the second metal comprises a metal that is more resistant to oxidation than the first metal. In one embodiment, the first metal is copper and the second metal is a noble metal. In illustrative examples, the second metal comprises an element selected from palladium, platinum, iridium, osmium, ruthenium, gold, or silver.

[0037] During the atomic layer deposition process, a metal-organic precursor gas comprising a second metal may be flowed into the processing chamber comprising first semiconductor die 900. The type of metal-organic precursor gas may be selected based on the material of the second metal and first nucleation inhibition layer 992 (i.e., the self-assembling material). The metal-organic precursor gas may be selected so that molecules of the metal-organic precursor gas are selectively adsorbed on the physically exposed surface of first metal bond pad 988 and decompose thereon to form first metal liner 998 consisting essentially of the second metal. Thus, the metal-organic precursor gas nucleates on the surface of the first metal and not on the surface of first nucleation inhibition layer 992. The metal-organic precursor gas does not adsorb on the surface of first nucleation inhibition layer 992, and therefore, first metal liner 998 is not formed over first nucleation inhibition layer 992. Generally, first metal liner 998 comprising the second metal may be selectively deposited on the physically exposed surface of first metal bond pad 988 without depositing the second metal on first nucleation inhibition layer 992. The thickness of the first metal liner 998 may be selected so that during a subsequent annealing process, the first metal of the first metal bond pad 988 may diffuse through the first metal liner 998. For example, the thickness of the first metal liner 998 may be in a range of 2 nm to 15 nm, such as 5 nm to 10 nm, although lesser and greater thicknesses may also be employed.

[0038] refer to Figure 5FIG. 7 shows a second semiconductor die 700. The second semiconductor die 700 includes a second substrate 708, second semiconductor devices 720 overlying the second substrate 708, second dielectric material layers (740, 760, 770) overlying the second semiconductor devices 720, and second metal interconnect structures 780 embedded in the second dielectric material layers (740, 760, 770). In one embodiment, the second semiconductor devices 720 can include at least one complementary metal-oxide-semiconductor (CMOS) circuit including field effect transistors. In one embodiment, the second substrate 708 can be a commercially available silicon substrate having a thickness in a range from 500 microns to 1 mm.

[0039] In general, the second semiconductor devices can include any semiconductor devices that can operate in conjunction with the first semiconductor devices in the first semiconductor die 900 to provide enhanced functionality. In one embodiment, the first semiconductor die 900 includes a memory die, and the second semiconductor die 700 includes a logic die including support circuitry (i.e., peripheral circuitry) for operating memory devices (such as a three-dimensional array of memory elements) within the memory die. In one embodiment, the first semiconductor die 900 can include a three-dimensional memory device including a three-dimensional array of memory elements, word lines (which can include a subset of the conductive lines 46) and bit lines 982, and the second semiconductor devices 720 of the second semiconductor die 700 can include peripheral circuitry for operating the three-dimensional array of memory elements. The peripheral circuitry can include one or more word line driver circuits to drive the word lines of the three-dimensional array of memory elements of the first semiconductor die 900, one or more bit line driver circuits to drive the bit lines 982 of the first semiconductor die 900, one or more word line decoder circuits to decode addresses of the word lines, one or more bit line decoder circuits to decode addresses of the bit lines 982, one or more sense amplifier circuits to sense states of the memory elements within the memory opening fill structures 58 of the first semiconductor die 900, source power circuitry to provide power to the horizontal semiconductor channel layer 10 in the first semiconductor die 900, data buffers and / or latches, and / or any other semiconductor circuitry that can be used to operate the three-dimensional memory device of the first semiconductor die 900.

[0040] The second dielectric material layers (740, 760, 770) can include: a proximal interconnect level dielectric layer 740 that embeds a proximal subset of the second metal interconnect structures 780 that are located proximal to the second substrate 708; a distal interconnect level dielectric layer 760 that embeds a distal subset of the second metal interconnect structures 780 that are located distal to the second substrate 708; and a second bonding dielectric layer 770 that is formed over the distal interconnect level dielectric layer 760. The second metal interconnect structures 780 can be located within the proximal interconnect level dielectric layer 740, within the distal interconnect level dielectric layer 760, or within the second bonding dielectric layer 770.

[0041] The proximal and distal interconnect level dielectric layers 740, 760 can include a dielectric material such as an undoped silicate glass (e.g., silicon oxide), a doped silicate glass, an organosilicate glass, silicon nitride, a dielectric metal oxide, or a combination thereof. The second bonding dielectric layer 770 can include an undoped silicate glass, a doped silicate glass (e.g., a doped or undoped silicon oxide material), silicon nitride, or silicon carbonitride (i.e., silicon carbonitride). The second bonding dielectric layer 770 can have a thickness in a range from 100 nm to 3,000 nm, although lesser and greater thicknesses can also be employed. The second bonding dielectric layer 770 can have a planar top surface that can be provided, for example, by a planarization process such as a chemical mechanical polishing (CMP) process.

[0042] The second metal bonding pads 788 are formed in the second bonding dielectric layer 770, for example, by forming pad cavities in the second bonding dielectric layer 770 and filling the pad cavities with at least one electrically conductive material that includes the first metal. Alternatively, the metal bonding pads 788 are first formed on the second metal interconnect structures 780, then the second bonding dielectric layer 770 is formed over and around the second metal bonding pads 788, then the second bonding dielectric layer 770 is planarized to expose top surfaces of the second metal bonding pads 788. The at least one electrically conductive material can be a metal (i.e., a metallic or metal alloy) material that can be bonded to the same metal material or another metal material by metal-to-metal or hybrid bonding. In one embodiment, each of the first metal bonding pads 988 can include an optional metal liner that includes TiN, TaN, and / or WN, and a metal fill material portion that includes a metal material that can be bonded to the same metal material or another metal material by metal-to-metal bonding. For example, the metal fill material portion can include and / or consist essentially of any material selected from Cu, a copper alloy (including copper at an atomic concentration greater than 70%, which can be greater than 90% and / or 95%). The material of the second metal bonding pads 788 can be the same as or can be different from the material of the first metal bonding pads 988.

[0043] Generally, the second metal bond pads 788 include the first metal, are electrically connected to respective nodes of the second semiconductor device 720, and are embedded in the second bond dielectric layer 770. Each of the second metal bond pads 788 is embedded in the second bond dielectric layer 770 and contacts a respective underlying structure in the second metal interconnect structure 780.

[0044] The types of devices of the first semiconductor die 900 and the second semiconductor die 700 can be selected in any manner such that the devices 920 of the first semiconductor die 900 and the devices 720 of the second semiconductor die 700 can communicate with each other and control or be controlled by devices in the other semiconductor die. In one embodiment, one of the first semiconductor die 900 and the second semiconductor die 700 includes a memory die including memory elements such as a three-dimensional array of memory cells, and the other of the first semiconductor die 900 and the second semiconductor die 700 includes a logic die including peripheral circuitry configured to operate the memory elements such as the three-dimensional array of memory cells.

[0045] Referring to Figure 6 The second nucleation inhibition layer 792 can be formed on a physically exposed surface (e.g., a top surface) of the second bond dielectric layer 770. The second nucleation inhibition layer 792 includes a material that inhibits nucleation of a metal material thereon during a subsequent metal deposition process. Generally, the dielectric material of the second bond dielectric layer 770 such as silicon oxide, silicon nitride, or silicon carbonitride does not provide sufficient inhibition of metal material deposition thereon. The function of the second nucleation inhibition layer 792 is to provide inhibition of metal material nucleation during a subsequent metal material deposition process and thereby prevent metal material deposition over the region of the second bond dielectric layer 770. The second nucleation inhibition layer 792 is selectively deposited on the physically exposed surface of the second bond dielectric layer 770 without depositing the second nucleation inhibition material on the physically exposed surface of the second metal bond pad 788. Thus, the second nucleation inhibition layer 792 can be formed as a discrete portion of material on the top surface of a respective one of the second metal bond pads 788.

[0046] In one embodiment, the nucleation inhibition material of the second nucleation inhibition layer 792 can also be a SAM such as a SAM monolayer, e.g., ODTS, DTS, or OTS. The nucleation inhibition material of the second nucleation inhibition layer 792 can be the same as or different from the nucleation inhibition material of the first nucleation inhibition layer 992.

[0047] Referring to Figure 7 An atomic layer deposition (ALD) process can be performed to selectively deposit the third metal on the physically exposed metal surfaces of the second metal bond pads 788 without depositing the third metal on the surface of the second nucleation inhibition layer 792, similar to the above with respect toFigure 4 The described method. The third metal is different than the first metal and can be the same or can be different than the second metal. Typically, the third metal comprises a more oxidation resistant metal compared to the first metal. In one embodiment, the first metal is copper and the third metal is a noble metal. In an illustrative example, the third metal comprises an element selected from palladium, platinum, iridium, osmium, ruthenium, gold, or silver.

[0048] During the atomic layer deposition process, a metal organic precursor gas comprising the third metal can flow into the processing chamber including the second semiconductor die 700. The species of the metal organic precursor gas can be selected based on the third metal and the material of the second nucleation inhibition layer 792 (i.e., the self-assembly material). The metal organic precursor gas can be selected such that molecules of the metal organic precursor gas are selectively adsorbed on and decomposed over the physically exposed surfaces of the second metal bonding pad 788 to form a second metal liner 798 consisting essentially of the third metal. Thus, the metal organic precursor gas nucleates on the surface of the first metal without nucleating on the surface of the second nucleation inhibition layer 792. The metal organic precursor gas does not adsorb on the surface of the second nucleation inhibition layer 792 and thus the second metal liner 798 is not formed over the second nucleation inhibition layer 792. Typically, the second metal liner 798 comprising the third metal can be selectively deposited on the physically exposed surfaces of the second metal bonding pad 788 without depositing the third metal on the second nucleation inhibition layer 792. The thickness of the second metal liner 798 can be selected such that during a subsequent anneal process, the first metal of the second metal bonding pad 788 can diffuse through the second metal liner 798. For example, the thickness of the second metal liner 798 can be in a range from 2 nm to 15 nm, such as 5 nm to 10 nm, although lesser and greater thicknesses can also be employed.

[0049] Reference Figure 8The first semiconductor die 900 and the second semiconductor die 700 are oriented such that the first bonding dielectric layer 970 faces the second bonding dielectric layer 770. The first semiconductor die 900 and the second semiconductor die 700 can be laterally aligned such that each second metal bonding pad 788 faces a respective one of the first metal bonding pads 988. In one embodiment, the pattern of the second metal bonding pads 788 can be a mirror image of the pattern of the first metal bonding pads 988, with optional differences in the size of the metal bonding pads between the first semiconductor die 900 and the second semiconductor die 700. In one embodiment, the first metal bonding pads 988 and the corresponding second metal bonding pads 788 can have the same size (i.e., lateral width). In another embodiment, the first metal bonding pads 988 and the corresponding second metal bonding pads 788 can have different sizes. In one embodiment, the area overlap between each facing pair of the first metal bonding pads 988 and the second metal bonding pads 788 can be at least 70% and / or at least 80%, such as at least 90%, for example 90% to 100%, of the area of the smaller one of the first metal bonding pads 988 and the second metal bonding pads 788.

[0050] The second semiconductor die 700 and the first semiconductor die 900 are brought into contact such that each of the first metal pads 998 contacts a respective one of the second metal pads 798. The pattern of the second metal bonding pads 788 can be a mirror image pattern of the pattern of the first metal bonding pads 988. The area of the second nucleation inhibition layer 792 can overlap within the area of the first nucleation inhibition layer 992.

[0051] Referring to Figure 9 , Figure 10A and Figure 10B The second metal bonding pads 788 can be bonded to the first metal bonding pads 988 by performing an anneal process that induces metal-to-metal bonding between the second metal bonding pads 788 and the first metal bonding pads 988. Optionally, dielectric bonding between the first bonding dielectric layer 970 and the second bonding dielectric layer 770 can be performed prior to or concurrently with the bonding of the first metal bonding pads 988 and the second metal bonding pads 788. In general, the second metal bonding pads 788 can be bonded to the first metal bonding pads 988 by inducing metal-to-metal bonding between each mating pair of the first metal bonding pads 988 and the second metal bonding pads 788.

[0052] According to one aspect of the disclosure, the first metal liner 998 and the second metal liner 798 comprise a metal material that is more oxidation resistant than the first metal of the first metal bond pad 988 and the second metal of the second metal bond pad 788. For example, the first metal can be copper, and the second metal of the first metal liner 998 and the third metal of the second metal liner 798 can comprise palladium, platinum, iridium, osmium, ruthenium, gold, and / or silver, which are more oxidation resistant than copper. Thus, in comparison to conventional metal-to-metal bonding processes, the atomic diffusion of the first metal through the stacked metal-to-metal bond of the first metal liner 998 and the second metal liner 798 is reduced during the anneal process. For example, if the first metal is copper, the metal-to-metal bond temperature can be in the range of 150 degrees Celsius to 300 degrees Celsius, such as 225 degrees Celsius to 275 degrees Celsius, including 250 degrees Celsius, in comparison to the conventional copper-to-copper bond temperature of about 350 degrees Celsius to 400 degrees Celsius.

[0053] According to another aspect of the disclosure, a dielectric-to-dielectric bond can be performed between the first bond dielectric layer 970 and the second bond dielectric layer 770 at the same time as the metal-to-metal bond between the first metal bond pad 988 and the second metal bond pad 788. In conventional hybrid bonding processes, the dielectric-to-dielectric bond is performed first at a lower temperature, and the metal-to-metal bond is performed at a higher temperature in a two-step anneal process. According to one aspect of the disclosure, due to the presence of the first metal liner 998 and the second metal liner 798, the metal-to-metal bond temperature can be reduced, and the dielectric-to-dielectric bond and the metal-to-metal bond can occur simultaneously. For example, if the first metal is copper, and the second metal and the third metal of the liners are noble metals, the elevated temperature of the single-step hybrid bond anneal process can be in the range of 150 degrees Celsius to 300 degrees Celsius, and have a duration of 1 to 3 hours, such as 2 hours. Thus, the duration of the single-step hybrid bond anneal process can be reduced by about half in comparison to the prior art two-step sequential hybrid bond anneal process.

[0054] The second metal of the first metal liner 998 and the third metal of the second metal liner 798 diffuse into the first metal bond pad 988 and into the second metal bond pad 788, while the first metal of the first metal bond pad and the second metal bond pad diffuses into and through the liners (798, 998). Thus, as shown in FIG. 9, an interfacial alloy region 999 is formed between each bond pair of the first metal bond pad 988 and the second metal bond pad 788. Figure 10A

[0055] In Figure 10B ​In one embodiment shown, a first metal (e.g., copper) may be diffused from respective bond pads (788, 988) through respective precious metal liners (798, 998) to form a copper-rich intermediate region 999T between a bottom precious metal-rich region 999B and a top precious metal-rich region 999T in the interface alloy region 999. The copper content of the copper-rich intermediate region 999M is higher than the copper content of both the bottom precious metal-rich region 999B and the top precious metal-rich region 999T. In contrast, the precious metal content of the copper-rich intermediate region 999M is lower than the precious metal content of both the bottom precious metal-rich region 999B and the top precious metal-rich region 999T. For example, the copper-rich intermediate region 999M may include 75 atomic % to 95 atomic % (e.g., 80 atomic % to 90 atomic %) of copper and 5 atomic % to 25 atomic % (e.g., 10 atomic % to 20 atomic %) of precious metal. The bottom noble metal-rich region 999B and the top noble metal-rich region 999T may include 50 atomic % to 70 atomic % (such as 55 atomic % to 65 atomic %) of copper and 30 atomic % to 50 atomic % (such as 35 atomic % to 45 atomic %) of the noble metal. The interfaces between the copper-rich middle region 999M and the noble metal-rich region 999B and the top noble metal-rich region 999T, as well as the interfaces between the noble metal-rich regions (999B, 999T) and the corresponding copper bonding pads (788, 988) may be graded in terms of copper and noble metal concentrations, rather than being abrupt in terms of copper and noble metal concentrations.

[0056] like Figure 10A As shown, in one embodiment, grains of the first metal (in the case where the first metal is copper, they are copper grains) near the bonding interface between the first semiconductor die 900 and the second semiconductor die 700 can extend across the interface alloy region 999. Typically, a subset of the crystal grains can extend vertically through the interface alloy region 999 into a proximal portion of a respective one of the first metal bond pads 988 and into a respective one of the second metal bond pads 788. In addition, a plurality of smaller grains can be formed at the bonding interface. The grain boundaries GB at Figure 10A It is shown schematically in FIG.

[0057] The first nucleation suppression layer 992 and the second nucleation suppression layer 792 may be thermally decomposed during the bonding process to form an interfacial doped dielectric material layer 997. The interfacial doped dielectric material layer 997 may be present at the bonding interface between the first bonding dielectric layer 970 and the second bonding dielectric layer 770. The interfacial doped dielectric material layer 997 may include SAM residues, such as residual carbon atoms and optionally residual chlorine atoms. In one embodiment, the integrated area density of carbon atoms at the bonding interface (i.e., the amount obtained by integrating the density of carbon atoms in the vertical direction across the bonding interface) may be between 3×10 13 / cm 2 to 3×10 15 / cm2 / cm 13 / cm 2 / cm 15 / cm 2 / cm

[0058] Generally, a dielectric-to-dielectric bond can be induced between the first bonding dielectric layer 970 and the second bonding dielectric layer 770 during an anneal process that induces a metal-to-metal bond between each mating pair of the first metal bonding pad 988 and the second metal bonding pad 788.

[0059] Referring to Figure 11 , the backside of the first substrate 908 and the second substrate 708 can be optionally thinned. The optional through-substrate contact via structures 714 can be formed through the second substrate 708 or through the first substrate 908. The second substrate 708 (or the first substrate 908) can be thinned from the backside by grinding, polishing, anisotropic etching, or isotropic etching. A backside insulating layer 702 can be formed on the backside of the second substrate 708. A photoresist layer (not shown) can be applied on the backside of the second substrate 708 and can be lithographically patterned to form openings therethrough. The locations of the openings through the patterned photoresist layer can be selected so that each of the openings through the photoresist layer is located entirely within the area of a respective one of the second metal interconnect structures 780.

[0060] An anisotropic etch process can be performed using the patterned photoresist layer as an etch mask layer. The anisotropic etch process can etch through unmasked regions of the second substrate 708 and through the proximal interconnect level dielectric material layers 740. The etch chemistries of the individual steps of the anisotropic etch process can be selected to etch through various unmasked material portions, and a final step of the anisotropic etch process can include an etch chemistry that selectively anisotropically etches one of the proximal interconnect level dielectric material layers 740 relative to the metal material of the second metal interconnect structures.

[0061] A via cavity can be formed extending at least through the second substrate 708 and the proximal interconnect level dielectric material layer 740. The via cavities are referred to herein as straight-through substrate via cavities. Each of the straight-through substrate via cavities can include a respective vertical or substantially vertical sidewall and extend vertically from a backside surface of the second substrate 708 to a proximal surface of a respective one of the second metal interconnect structures 780, which can be a metal pad. Thus, the proximal surfaces of the second metal interconnect structures 780, such as the proximal surfaces of the metal bonding pads, are physically exposed at the bottom of each straight-through substrate via cavity.

[0062] At least one electrically conductive material, such as at least one metallic material, can be deposited in the straight-through substrate via cavities. For example, the at least one electrically conductive material can include a metal nitride liner material, such as TiN, TaN, and / or WN, and a metal fill material, such as W, Co, Cu, Ru, and / or Mo. The at least one electrically conductive material can be deposited by physical vapor deposition or chemical vapor deposition or atomic layer deposition or electrochemical deposition or electroless plating deposition or a combination thereof. The at least one electrically conductive material can be patterned into discrete portions to provide straight-through substrate via structures 714. An upper portion of each straight-through substrate via structure 714 that protrudes above the backside insulating layer 702 includes a metal pad structure that can be used as an external metal bonding pad. Each straight-through substrate via structure 714 can include a metal nitride liner 714L and a metal fill material portion 714C.

[0063] Referring to all of the drawings and in accordance with various embodiments of the present disclosure, a bonded assembly includes a first semiconductor die 900 including a first semiconductor device 720; first metal interconnect structures 980 embedded in a first dielectric material layer 960; and first metal bonding pads 988 including a first metal and embedded in a first bonding dielectric layer 970; a second semiconductor die 700 including a second semiconductor device 720; second metal interconnect structures 780 embedded in a second dielectric material layer 760; and second metal bonding pads 788 including the first metal and embedded in a second bonding dielectric layer 770 and bonded to a respective one of the first metal bonding pads 988. The bonded assembly further includes an interfacial alloy region 999 including an alloy of the first metal and a second metal different from the first metal between each of the first metal bonding pads 988 and each of the second metal bonding pads 788 bonded to a respective one of the first metal bonding pads 988; and an interfacial dielectric region 997 at an interface between the first bonding dielectric layer 970 and the second bonding dielectric layer 770. The interfacial dielectric region 997 includes carbon atoms at an average atomic concentration that is greater than twice an average atomic concentration of carbon in the first bonding dielectric layer 970 and greater than twice an average atomic concentration of carbon in the second bonding dielectric layer 770.

[0064] In one embodiment, the first metal includes copper, and the second metal includes a noble metal. In Figure 10B In one embodiment shown, each of the interface alloy regions 999 includes a copper-rich intermediate region 999M between a bottom noble metal-rich region 999B and a top noble metal-rich region 999T. The copper content of the copper-rich intermediate region 999M is higher than the copper content of the bottom noble metal-rich region 999B and the top noble metal-rich region 999M. The noble metal content of the copper-rich intermediate region 999M is lower than the noble metal content of the bottom noble metal-rich region 999B and the top noble metal-rich region 999T.

[0065] In one embodiment, the atomic concentration of the second metal decreases with vertical distance from the interface alloy region 999 and the first metal bonding pads and the second metal bonding pads (988, 788). Optionally, a plurality of layers of interfaces can be present at the interface alloy region 999. In Figure 10A In one embodiment shown, a subset of the crystal grains vertically extend through the interface alloy region 999 into a proximal portion of a respective one of the first metal bonding pads and into a respective one of the second metal bonding pads. In one embodiment, the thickness of the interface alloy region 999 is less than 10% of the vertical thickness of the first metal bonding pads and the second metal bonding pads (988, 788).

[0066] In one embodiment, the first bonding dielectric layer 970 is bonded to the second bonding dielectric layer 770 by a dielectric-to-dielectric bond. In one embodiment, the first bonding dielectric layer and the second bonding dielectric layer include silicon oxide or silicon nitride. In another embodiment, the first bonding dielectric layer and the second bonding dielectric layer include silicon carbonitride. In one embodiment, the interface dielectric region 997 includes both carbon atoms and chlorine atoms at an average atomic concentration that is greater than twice the average atomic concentration of both carbon and chlorine in the first bonding dielectric layer 970 and greater than twice the average atomic concentration of both carbon and chlorine in the second bonding dielectric layer 770.

[0067] Various embodiments of the present disclosure can be employed to simultaneously provide metal-to-metal bonding and dielectric-to-dielectric bonding. The first metal liner 998 and the second metal liner 798 reduce or prevent oxidation of the surfaces of the first metal bonding pads 988 and the second metal bonding pads 788. Thus, hybrid bonding including metal-to-metal bonding can be performed at lower bonding temperatures and / or shorter durations. Reducing the thermal budget of hybrid bonding can reduce or avoid thinned semiconductor dies, wafer fragility, and performance degradation, while improving bonding alignment accuracy and avoiding compatibility issues with respect to the back end of line processes.

[0068] While specific embodiments are mentioned herein, it is understood that the present disclosure is not limited thereto. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. Such equivalents are considered to be within the scope of the present disclosure. Compatibility is assumed among all embodiments that are not alternatives to each other. Unless explicitly stated otherwise, the word "comprising" or "including" envisages all embodiments wherein the word "consisting essentially of or the word "consisting of is substituted for the word "comprising" or "including". Embodiments are shown in the present disclosure using specific structures and / or configurations, it is understood that the present disclosure can be practiced in any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise deemed impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A method of forming a bonded assembly, comprising: providing a first semiconductor die including a first semiconductor device, a first bonding dielectric layer, and first metal bonding pads including a first metal, the first metal bonding pads electrically connected to respective nodes of the first semiconductor device and embedded in the first bonding dielectric layer; selectively depositing a first nucleation-inhibiting layer including a self-assembly material on a surface of the first bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of the first metal bonding pads; selectively depositing a first metal liner including a second metal on the physically exposed surfaces of the first metal bonding pads without depositing the second metal on the first nucleation-inhibiting layer; providing a second semiconductor die including a second semiconductor device, a second bonding dielectric layer, and second metal bonding pads electrically connected to respective nodes of the second semiconductor device and embedded in the second bonding dielectric layer; selectively depositing a second nucleation-inhibiting layer including an additional self-assembly material on a surface of the second bonding dielectric layer without depositing the additional self-assembly material on physically exposed surfaces of the second metal bonding pads; selectively depositing a second metal liner including a third metal on the physically exposed surfaces of the second metal bonding pads without depositing the third metal on the second nucleation-inhibiting layer, wherein the third metal is different from the first metal and the same as or different from the second metal; bonding the second metal bonding pads with the first metal bonding pads by inducing metal-to-metal bonding between each mating pair of the first metal bonding pads and the second metal bonding pads; and forming an interfacial dielectric region at an interface between the first bonding dielectric layer and the second bonding dielectric layer, wherein the interfacial dielectric region includes carbon atoms at an average atomic concentration that is greater than twice an average atomic concentration of carbon in the first bonding dielectric layer and greater than twice an average atomic concentration of carbon in the second bonding dielectric layer.

2. The method of claim 1, wherein: the first metal includes copper; and the second metal includes a noble metal.

3. The method of claim 2, wherein the metal-to-metal bonding is induced by performing an annealing process at a temperature between 150 degrees Celsius and 300 degrees Celsius.

4. The method of claim 3, wherein during the annealing process, the copper diffuses from the respective first and second metal bonding pads through the respective first and second metal liners to form an interfacial alloy region between the respective first and second metal bonding pads.

5. The method of claim 4, wherein: the interfacial alloy region includes a copper-rich intermediate region between a bottom noble metal-rich region and a top noble metal-rich region; the copper content of the copper-rich intermediate region is higher than the copper content of the bottom noble metal-rich region and the top noble metal-rich region; and the noble metal content of the copper-rich intermediate region is lower than the noble metal content of the bottom noble metal-rich region and the top noble metal-rich region.

6. The method of claim 4, wherein a subset of the crystal grains extends vertically through the interface alloy region into a proximal portion of a respective one of the first metal bonding pads and into a respective one of the second metal bonding pads.

7. The method of claim 3, further comprising inducing a dielectric-to-dielectric bond between the first bonding dielectric layer and the second bonding dielectric layer during the annealing process.

8. The method of claim 1, wherein: the self-assembled material comprises a material selected from octadecyltrichlorosilane, decyltrichlorosilane, or octylsilane; and the first bonding dielectric layer and the second bonding dielectric layer comprise silicon oxide, silicon nitride, or silicon carbonitride.

9. The method of claim 1, wherein the first metal pad is deposited by performing an atomic layer deposition (ALD) process that employs a precursor gas that nucleates on a surface of the first metal without nucleating on a surface of the first nucleation-inhibiting layer.

10. A bonded assembly comprising: a first semiconductor die comprising first semiconductor devices, first metal interconnect structures embedded in a first dielectric material layer, and first metal bonding pads comprising a first metal and embedded in a first bonding dielectric layer; a second semiconductor die comprising second semiconductor devices, second metal interconnect structures embedded in a second dielectric material layer, and second metal bonding pads comprising the first metal and embedded in a second bonding dielectric layer and bonded to a respective one of the first metal bonding pads; an interface alloy region comprising an alloy of the first metal and a second metal different from the first metal, the interface alloy region located between each of the first metal bonding pads and each of the second metal bonding pads bonded to a respective one of the first metal bonding pads; and an interface dielectric region located at an interface between the first bonding dielectric layer and the second bonding dielectric layer, wherein the interface dielectric region comprises carbon atoms at an average atomic concentration that is greater than twice an average atomic concentration of carbon in the first bonding dielectric layer and greater than twice an average atomic concentration of carbon in the second bonding dielectric layer.

11. The bonded assembly of claim 10, wherein: the first metal comprises copper; and the second metal comprises a noble metal.

12. The bonded assembly of claim 11, wherein: each of the interface alloy regions comprises a copper-rich intermediate region located between a bottom noble metal-rich region and a top noble metal-rich region; the copper content of the copper-rich intermediate region is higher than the copper content of the bottom noble metal-rich region and the top noble metal-rich region; and the noble metal content of the copper-rich intermediate region is lower than the noble metal content of the bottom noble metal-rich region and the top noble metal-rich region. The copper-rich intermediate region has a lower noble metal content than the base noble metal-rich region and the top noble metal-rich region.

13. The bonded assembly of Claim 12, wherein an atomic concentration of the second metal decreases with vertical distance from the interface alloy region and the first and second metal bonding pads.

14. The bonded assembly of Claim 10, wherein a subset of crystal grains vertically extend through the interface alloy region into a proximal portion of a respective one of the first metal bonding pads and into a respective one of the second metal bonding pads.

15. The bonded assembly of Claim 10, wherein a thickness of the interface alloy region is less than 10% of a vertical thickness of the first and second metal bonding pads.

16. The bonded assembly of Claim 10, wherein the first bonding dielectric layer is bonded to the second bonding dielectric layer by a dielectric-to-dielectric bond.

17. The bonded assembly of Claim 16, wherein the first and second bonding dielectric layers comprise silicon oxide.

18. The bonded assembly of Claim 16, wherein the first and second bonding dielectric layers comprise silicon carbonitride.

19. The bonded assembly of Claim 10, wherein the interface dielectric region comprises both carbon and chlorine atoms at an average atomic concentration that is greater than twice an average atomic concentration of both carbon and chlorine in the first bonding dielectric layer and greater than twice an average atomic concentration of both carbon and chlorine in the second bonding dielectric layer.

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