Array substrate and manufacturing method thereof

Abstract

The application provides an array substrate and a manufacturing method thereof. The manufacturing method comprises the following steps: firstly, forming a light shielding layer, a source electrode and a drain electrode on a substrate by using a first mask process; then, forming a semiconductor layer, a gate insulating layer and a gate electrode in sequence on the source electrode, the drain electrode and the light shielding layer by using a second mask process; subsequently, forming a dielectric layer on the gate electrode and the substrate, and forming a via hole exposing the drain electrode on the dielectric layer by using a third mask process; finally, forming a pixel electrode on the dielectric layer by using a fourth mask process. The source electrode, the drain electrode and the light shielding layer of the array substrate are manufactured by using the first mask, and the semiconductor layer, the gate insulating layer and the gate electrode are manufactured by using the second mask, so that the manufacturing of the array substrate can be completed by using only four mask processes, the number of masks used is saved, the manufacturing process is simplified, and the production cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a manufacturing method thereof. BACKGROUND

[0002] With the development of display technology, flat panel display devices such as thin film transistor liquid crystal display (TFT-LCD) are widely applied to mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display devices.

[0003] At present, the size of display screens is getting larger and larger, and the carrier mobility of the traditional amorphous silicon (a-Si:H) thin film transistor is not high enough to drive large-size liquid crystal display panels. Generally, the carrier mobility of indium gallium zinc oxide (IGZO) thin film transistor is significantly higher than that of a-Si:H thin film transistor. In order to improve the charging rate of thin film transistor devices, IGZO semiconductor layers gradually replace a-Si:H semiconductor layers and are applied to the design of large-size liquid crystal panels.

[0004] However, at present, whether it is an array substrate containing an IGZO semiconductor layer or an array substrate containing a semiconductor layer formed by other metal oxides, each film layer needs to be deposited, exposed and developed, etched, stripped and other process procedures, and a large number of masks are used, which is high in production cost. Taking an array substrate with a top gate structure as an example, generally 6 mask process procedures are needed, which is complex in process and high in production cost.

[0005] Therefore, it is necessary to provide a technical solution to solve the above problems. SUMMARY

[0006] The present application provides an array substrate and a manufacturing method thereof, which can solve the technical problems of complex manufacturing process and high production cost of the existing array substrate.

[0007] To solve the above problems, the technical solution provided by the present application is as follows:

[0008] The manufacturing method of the array substrate provided by the present application comprises the following steps:

[0009] S1, providing a substrate, and using a first mask process to form a light shielding layer and a source electrode and a drain electrode on the side of the light shielding layer away from the substrate on the substrate;

[0010] S2, forming a stacked semiconductor layer, a gate insulating layer and a gate electrode on the source electrode, the drain electrode and the light shielding layer by using a second mask process;

[0011] S3, forming a dielectric layer on the gate electrode and the substrate, and forming a via hole exposing the drain electrode on the dielectric layer by using a third mask process;

[0012] S4, forming a pixel electrode on the dielectric layer by using a fourth mask process, the pixel electrode being electrically connected to the drain electrode through the via hole.

[0013] Optionally, in some embodiments of the present application, the S1 comprises the following steps:

[0014] S101, sequentially forming a light shielding film, a first metal film and a first photoresist film on the substrate;

[0015] S102, exposing the first photoresist film, the first metal film and the light shielding film by using a first mask; wherein the first mask comprises a completely transparent area, a partially transparent area and a non-transparent area;

[0016] S103, removing the first photoresist film and the first metal film corresponding to the completely transparent area and the partially transparent area, to form the source electrode and the drain electrode;

[0017] S104, removing the light shielding film corresponding to the completely transparent area, to form the light shielding layer;

[0018] S105, removing the remaining first photoresist film.

[0019] Optionally, in some embodiments of the present application, the material of the light shielding layer is a non-metal light shielding material.

[0020] Optionally, in some embodiments of the present application, the S2 comprises the following steps:

[0021] S201, forming a semiconductor film on the source electrode, the drain electrode, the light shielding layer and the substrate, the semiconductor film comprising a conductorized area corresponding to the source electrode and the drain electrode;

[0022] S202, conductorizing the part of the semiconductor film corresponding to the conductorized area, to form a conductor area;

[0023] S203, sequentially forming a gate insulating film, a second metal film and a second photoresist film on the semiconductor film;

[0024] S204, exposing the second photoresist film, the second metal film, the gate insulating film and the semiconductor film by using a second mask; wherein the second mask comprises a completely transparent region and a non-transparent region;

[0025] S205, removing the second photoresist film, the second metal film, the gate insulating film and the semiconductor film corresponding to the completely transparent region, to form the gate, the gate insulating layer and the semiconductor layer;

[0026] S206, removing the remaining second photoresist film.

[0027] Optionally, in some embodiments of the present application, the prepared gate, gate insulating layer and semiconductor layer form a stacked structure in a direction perpendicular to the substrate, and an edge of the stacked structure overlaps with the source and the drain.

[0028] wherein the gate insulating layer and the gate fall within the range of the semiconductor layer in the orthographic projection on the substrate.

[0029] The embodiments of the present application also provide an array substrate, comprising:

[0030] a substrate;

[0031] a source electrode disposed on the substrate;

[0032] a drain electrode disposed on the substrate and spaced apart from the source electrode;

[0033] a semiconductor layer disposed between the source electrode and the drain electrode and having an edge extending to a side of the source electrode and the drain electrode away from the substrate;

[0034] a gate insulating layer disposed on a side of the semiconductor layer away from the substrate;

[0035] a gate electrode disposed on a side of the gate insulating layer away from the substrate;

[0036] wherein the gate, the gate insulating layer and the semiconductor layer form a stacked structure in a direction perpendicular to the substrate, and an edge of the stacked structure overlaps with the source and the drain.

[0037] Optionally, in some embodiments of the present application, in a direction perpendicular to the substrate, edges of the semiconductor layer, the gate insulating layer and the gate all overlap with the source and the drain.

[0038] Optionally, in some embodiments of the present application, the gate insulating layer and the orthographic projection of the gate on the substrate all fall within the orthographic projection of the semiconductor layer on the substrate.

[0039] Optionally, in some embodiments of the present application, the array substrate further comprises a dielectric layer and a pixel electrode, the dielectric layer is arranged on the side of the gate away from the substrate, and the pixel electrode is arranged on the side of the dielectric layer away from the substrate.

[0040] The semiconductor layer comprises a channel region and a conductor region, the channel region is located between the source and the drain, and the conductor region is located on both sides of the channel region and contacts the source and the drain respectively.

[0041] The drain comprises a first contact region and a second contact region, the first contact region is spaced apart from the second contact region, and the second contact region is located on the side of the first contact region away from the source, wherein the conductor region corresponding to the drain contacts the first contact region, and the pixel electrode contacts the second contact region.

[0042] Optionally, in some embodiments of the present application, the array substrate further comprises a light shielding layer between the substrate and the source and the drain, and the source and the drain are arranged on the side surface of the light shielding layer away from the substrate.

[0043] The conductor region corresponding to the source contacts the light shielding layer from the surface of the source away from the substrate along the side of the source close to the drain, and the conductor region corresponding to the drain contacts the light shielding layer from the surface of the drain away from the substrate along the side of the drain close to the source.

[0044] The array substrate and the manufacturing method thereof provided by the present application have the following beneficial effects: the light shielding layer, the source and the drain are formed by using the first mask process, the semiconductor layer, the gate insulating layer and the gate are formed by using the second mask process, the via hole exposing the drain is formed on the dielectric layer by using the third mask process, and the pixel electrode is formed by using the fourth mask process. Since the source, the drain and the light shielding layer are manufactured by using the same mask, one mask process can be saved. Meanwhile, since the semiconductor layer, the gate insulating layer and the gate are also manufactured by using the same mask, one mask process can be saved again. Therefore, the manufacturing of the array substrate can be completed by using only four mask processes, the number of masks used is saved, the manufacturing process is simplified, and the production cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a flowchart of the method for manufacturing an array substrate provided in an embodiment of the present invention;

[0047] Figures 2A-2Q This is a schematic diagram of the fabrication process of the array substrate provided in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the structure of the array substrate provided in an embodiment of the present invention. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0050] Please see Figure 1 , Figures 2A-2Q This invention provides a method for fabricating an array substrate, comprising the following steps:

[0051] S1, a substrate is provided, and a light-shielding layer and a source and drain electrode located on the side of the light-shielding layer opposite to the substrate are formed on the substrate using a first photomask process.

[0052] Specifically, S1 includes the following steps:

[0053] S101, such as Figure 2A As shown, a light-shielding film 21, a first metal film 22 and a first photoresist film 23 are sequentially stacked on the substrate 11.

[0054] The light shielding film 21 is a non-metal light shielding material, such as a black matrix, but is not limited thereto. The thickness of the light shielding film 21 is 500A-2000A. The material of the first metal film 22 can be at least one of molybdenum, aluminum, copper and titanium, and the thickness of the first metal film 22 is 2000A-4000A. The first photoresist film 23 is a positive photoresist.

[0055] S102, as shown in the figure, the first light shielding film 23, the first metal film 22 and the light shielding film 21 are exposed by using the first mask 100. Figure 2B

[0056] The first mask 100 includes a completely transparent area 100a, a partially transparent area 100b and a non-transparent area 100c. The first mask 100 is placed above the substrate 11 formed with the first photoresist film 23, the first metal film 22 and the light shielding film 21. The non-transparent area 100c corresponds to the area where the source and the drain are to be formed. The partially transparent area 100b corresponds to the area between the source to be formed and the drain to be formed. The completely transparent area 100a corresponds to the area outside the light shielding layer to be formed.

[0057] S103, as shown in the figure, the first photoresist film 23 and the first metal film 22 corresponding to the completely transparent area 100a and the partially transparent area 100b are removed, and the source 13 and the drain 14 are formed. Figures 2B-2D

[0058] Specifically, as shown in the figure, after exposure, the first photoresist film 23 is developed, and the first photoresist film 23 corresponding to the completely transparent area 100a and the partially transparent area 100b is removed, and the first photoresist pattern 231 is formed. Figure 2C As shown in the figure, the first metal film 22 not covered by the first photoresist pattern 231 is subjected to a wet etching process with a corrosive solution (such as PPC acid, ENF acid, oxalic acid, etc.), and the corresponding part of the first metal film 22 not covered by the first photoresist pattern 231 is removed, and the source 13 and the drain 14 are formed.

[0059] Figure 2D S104, as shown in the figure, the light shielding film 21 corresponding to the completely transparent area 100a is removed, and the light shielding layer 12 is formed.

[0060] Specifically, the dry etching process can be used to remove the light shielding film 21 outside the light shielding layer 12. Figure 2B Figure 2E

[0061]

[0062] ​​​​​​Wherein, since the source 13 and the drain 14 of the embodiment are both directly in contact with the light shielding layer 12, if the light shielding layer 12 is made of metal material, the source 13 and the drain 14 will be directly conducted, which will affect the normal use of the device.

[0063] S105, removing the remaining first photoresist film.

[0064] Specifically, as shown in Figure 2F , the first photoresist pattern 231 can be removed by using an oxidizing gas (such as O2 and N2O, etc.) for ashing treatment.

[0065] The embodiment only needs to use the first mask process to form the patterned light shielding layer 12, as well as the source 13 and the drain 14 on the light shielding layer 12. Compared with the traditional manufacturing process, the above-mentioned method of the embodiment can save the use of one mask.

[0066] S2, using the second mask process to form a stacked semiconductor layer, gate insulating layer and gate on the source, the drain and the light shielding layer.

[0067] Wherein, the S2 includes the following steps:

[0068] S201, as shown in Figure 2G , a semiconductor film 24 is made on the source 13, the drain 14, the light shielding layer 12 and the substrate 11. The semiconductor film 24 includes a conductorized area 24a corresponding to the source 13 and the drain 14.

[0069] Wherein, the material of the semiconductor film 24 can be one of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO) or indium gallium zinc tin oxide (IGZTO). The thickness of the semiconductor film 24 is 100A-1000A.

[0070] S202, as shown in Figure 2H , the part of the semiconductor film 24 corresponding to the conductorized area 24a is conductorized to form a conductor area 152.

[0071] Specifically, the part of the semiconductor film 24 corresponding to the conductorized area 24a can be conductorized by using laser or ion doping to form the conductor area 152.

[0072] S203, as shown in Figure 2I , a gate insulating film 25, a second metal film 26 and a second photoresist film 27 are sequentially stacked on the semiconductor film 24.

[0073] The gate insulating film 25 can be made of at least one of silicon oxide and silicon nitride, and its thickness is 1000 Å-3000 Å. The second metal film 26 can be made of at least one of molybdenum, aluminum, copper, and titanium, and its thickness is 2000 Å-4000 Å. The second photoresist film 27 is a positive photoresist.

[0074] S204, such as Figure 2J As shown, the second photoresist film 27, the second metal film 26, the gate insulating film 25 and the semiconductor film 24 are exposed using a second photomask 200.

[0075] The second photomask 200 includes a fully transparent region 200a and an opaque region 200b. The second photomask 200 is placed above the substrate 11 on which the second photoresist film 27, the second metal film 26, the gate insulating film 25, and the semiconductor film 24 are formed. The opaque region 200b corresponds to the corresponding areas of the semiconductor layer, the gate insulating layer, and the gate to be formed, and the fully transparent region 200a corresponds to the area outside the semiconductor layer, the gate insulating layer, and the gate to be formed.

[0076] S205, please refer to Figures 2J-2M As shown, the second photoresist film 27, the second metal film 26, the gate insulating film 25 and the semiconductor film 24 corresponding to the fully transparent area 200a are removed to form the gate 17, the gate insulating layer 16 and the semiconductor layer 15.

[0077] Specifically, such as Figure 2K As shown, after exposure, the second photoresist film 27 is developed to remove the second photoresist film 27 corresponding to the fully transparent area 200a, forming a second photoresist pattern 271.

[0078] like Figure 2L As shown, a wet etching process is performed on the second metal film 26 that is not covered by the second photoresist pattern 271 using a corrosive solution (such as PPC acid, ENF acid, oxalic acid, etc.) to remove the corresponding portion of the second metal film 26 that is not covered by the second photoresist pattern 271, thereby forming the gate 17.

[0079] like Figure 2MAs shown, a dry etching process is used to etch the gate insulating film 25 and the semiconductor film 24 that are not covered by the gate 17, removing the corresponding portions of the gate insulating film 25 and the semiconductor film 24 that are not covered by the gate 17, thus forming the gate insulating layer 16 and the semiconductor layer 15. The gate insulating film 25 and the semiconductor film 24 can be etched using a single etching process or a two-step etching process.

[0080] S206, Remove the remaining second photoresist film.

[0081] Specifically, such as Figure 2N As shown, the second photoresist pattern 271 can be ashed using oxidizing gases (such as O2 and N2O) to remove the second photoresist pattern 271.

[0082] The gate 17, the gate insulating layer 16 and the semiconductor layer 15, which are formed by the second photomask 200, form a stacked structure (15, 16, 17) in a direction perpendicular to the substrate 11, and the edges of the stacked structure (15, 16, 17) overlap with the source 13 and the drain 14.

[0083] Furthermore, the orthographic projections of the gate electrode 17, the gate insulating layer 16, and the semiconductor layer 15 onto the substrate 11 all fall within the range of the orthographic projection of the light-shielding layer 12 onto the substrate 11. Specifically, the orthographic projections of the gate insulating layer 16 and the gate electrode 17 onto the substrate 11 all fall within the range of the orthographic projection of the semiconductor layer 15 onto the substrate 11. At least the edge of the semiconductor layer 15 overlaps with the source electrode 13 and the drain electrode 14.

[0084] In this embodiment, the edges of the semiconductor layer 15, the gate insulating layer 16, and the gate 17 formed by the second metal film 26, the gate insulating film 25, and the semiconductor film 24 after exposure and etching with the same photomask all overlap with the source 13 and the drain 14. This ensures that the contact area between the conductor region 152 and the source 13 and the drain 14 is not too small, thereby increasing the reliability of the contact between the conductor region 152 and the source 13 and the drain 14 and minimizing the contact impedance.

[0085] In this embodiment, the patterned gate 17, gate insulating layer 16 and semiconductor layer 15 can be formed by using only a second photomask process. Compared with the traditional manufacturing process, the above method of this embodiment can save the use of another photomask.

[0086] S3, as Figure 2OAs shown, a dielectric layer 18 is made on the gate 17 and the substrate 11, and a third mask process is used to form a via 181 exposing the drain 14 on the dielectric layer 18.

[0087] The material of the dielectric layer 18 can be at least one of silicon oxide and silicon nitride, and the thickness of the dielectric layer 18 is 5000A-8000A. The dielectric layer 18 completely covers the thin film transistor.

[0088] Specifically, the drain 14 includes a first contact area 141 and a second contact area 142, the first contact area 141 is spaced apart from the second contact area 142, and the second contact area 142 is located on the side of the first contact area 141 away from the source 13. It should be noted that the via 181 formed on the dielectric layer 18 by the third mask process exposes the second contact area 142 of the drain 14.

[0089] S4, as shown in Figures 2P-2Q A fourth mask process is used to form a pixel electrode 19 on the dielectric layer 18, and the pixel electrode 19 is electrically connected to the drain 14 through the via 181.

[0090] Specifically, as shown in Figure 2P A layer of electrode film 28 is made on the dielectric layer 18. The electrode film 28 is a transparent material, which can be Indium Gallium Zinc Oxide (IGZO), but is not limited thereto. The thickness of the electrode film 28 is 2000A-4000A.

[0091] As shown in Figure 2Q After the fourth mask process, the electrode film 28 forms a patterned pixel electrode 19, and the pixel electrode 19 is electrically connected to the drain 14 through the via 181. Thus, the manufacturing of the array substrate is completed.

[0092] The manufacturing method of the array substrate provided by the embodiment of the present application uses a first mask process to form a light shielding layer and a source and a drain, uses a second mask process to form a stacked semiconductor layer, a gate insulating layer and a gate, uses a third mask process to form a via exposing the drain on a dielectric layer, and uses a fourth mask process to form a pixel electrode. Since the source, the drain and the light shielding layer are manufactured by the same mask, one mask process is saved. Meanwhile, since the semiconductor layer, the gate insulating layer and the gate are also manufactured by the same mask, another mask process is saved. Therefore, the manufacturing of the array substrate can be completed by only four mask processes, the number of masks used is saved, the manufacturing process is simplified, and the production cost is reduced.

[0093] Please refer to Figure 3The array substrate provided by the embodiment of the present application can be applied to a liquid crystal display panel, but is not limited thereto. The array substrate comprises: a substrate 11; a source electrode 13 arranged on the substrate 11, and a drain electrode 14 arranged on the substrate 11 in the same layer as the source electrode 13, the drain electrode 14 being spaced apart from the source electrode 13; a semiconductor layer 15 arranged between the source electrode 13 and the drain electrode 14 and extending to a side of the source electrode 13 and the drain electrode 14 away from the substrate 11; a gate insulating layer 16 arranged on a side of the semiconductor layer 15 away from the substrate 11; and a gate electrode 17 arranged on a side of the gate insulating layer 16 away from the substrate 11. The gate electrode 17, the gate insulating layer 16 and the semiconductor layer 15 form a stacked structure in a direction perpendicular to the substrate 11, and an edge of the stacked structure overlaps with the source electrode 13 and the drain electrode 14.

[0094] The array substrate provided by the embodiment of the present application has a simple structure, can simplify the manufacturing process and reduce the production cost. The specific structure of the array substrate will be described as follows.

[0095] Please refer to Figure 3 The array substrate 1 comprises, from bottom to top, the substrate 11, the light shielding layer 12, the source electrode 13, the drain electrode 14, the semiconductor layer 15, the gate insulating layer 16, the gate electrode 17, the dielectric layer 18 and the pixel electrode 19.

[0096] The substrate 11 can be a rigid glass substrate or a flexible polyimide substrate, which is not limited herein.

[0097] The light shielding layers 12 are arranged on the substrate 11 in a spaced apart manner, and are made of a non-metal material, for example, a black matrix material, for shielding light from the side of the substrate 11 to the semiconductor layer 15.

[0098] The source electrode 13 and the drain electrode 14 are arranged on a side of the light shielding layer 12 away from the substrate 11, and the source electrode 13 is spaced apart from the drain electrode 14. Specifically, the source electrode 13 and the drain electrode 14 are both arranged on a surface of the light shielding layer 12 away from the substrate 11, and are arranged at opposite ends of the light shielding layer 12. Since the source electrode 13 and the drain electrode 14 of the embodiment are both directly in contact with the light shielding layer 12, if the light shielding layer 12 is made of a metal material, the source electrode 13 and the drain electrode 14 will be directly conducted, which will affect the normal use of the device.

[0099] The semiconductor layer 15 is arranged on the side surface of the source electrode 13, the drain electrode 14 and the light-shielding layer 12 exposed between the source electrode 13 and the drain electrode 14, which is opposite to the substrate 11. The gate insulating layer 16 is arranged on the side of the semiconductor layer 15 opposite to the substrate 11, and the gate electrode 17 is arranged on the side of the gate insulating layer 16 opposite to the substrate 11. The dielectric layer 18 is arranged on the gate electrode 17 and the substrate 11, i.e. the dielectric layer 18 is arranged on the whole surface, and the dielectric layer 18 is provided with a via hole penetrating the dielectric layer 18 at a position corresponding to the drain electrode 14. The pixel electrode 19 is arranged on the side of the dielectric layer 18 opposite to the substrate 11, and is electrically connected to the drain electrode 14 through the via hole.

[0100] The source electrode 13, the drain electrode 14, the semiconductor layer 15 and the gate electrode 17 constitute a thin film transistor. The source electrode 13, the drain electrode 14, the semiconductor layer 15, the gate insulating layer 16 and the gate electrode 17 are all in the range of the orthographic projection of the light-shielding layer 12 on the substrate 11.

[0101] Further, in the direction perpendicular to the substrate 11, the semiconductor layer 15, the gate insulating layer 16 and the gate electrode 17 form a stacked structure (15, 16, 17), and the edges of the stacked structure (15, 16, 17) overlap with the source electrode 13 and the drain electrode 14.

[0102] The orthographic projection of the gate insulating layer 16 and the gate electrode 17 on the substrate 11 is within the range of the orthographic projection of the semiconductor layer 15 on the substrate 11. Further, the orthographic projection of the gate electrode 17 on the substrate 11 is within the range of the orthographic projection of the gate insulating layer 16 on the substrate 11.

[0103] As an embodiment, the side surface of the stacked structure (15, 16, 17) formed by the semiconductor layer 15, the gate insulating layer 16 and the gate electrode 17 is arranged at a preset angle with the plane of the substrate 11. The preset angle is in the range of 20°-90°, and the preset angle can be 30°, 45°, 60° or 75°, etc. Alternatively, the edges of the semiconductor layer 15, the gate insulating layer 16 and the gate electrode 17 are arranged flush in the direction perpendicular to the substrate 11.

[0104] In the embodiment, the semiconductor layer 15, the gate insulating layer 16 and the gate 17 all have edges overlapping the source 13 and the drain 14. In this way, the contact area of the conductor region 152 with the source 13 and the drain 14 can be ensured not to be too small, thereby increasing the reliability of the contact between the conductor region 152 and the source 13 and the drain 14 and reducing the contact impedance as much as possible.

[0105] The semiconductor layer 15 includes a channel region 151 corresponding to a region between the source 13 and the drain 14 and conductor regions 152 on both sides of the channel region 151. The conductor regions 152 on both sides of the channel region 151 are in contact with the source 13 and the drain 14, respectively, to achieve electrical connection.

[0106] The conductor region 152 corresponding to the source 13 is in contact with the light shielding layer 12 along the side of the source 13 close to the side of the drain 14 from the surface of the source 13 away from the substrate 11. The conductor region 152 corresponding to the drain 14 is in contact with the light shielding layer 12 along the side of the drain 14 close to the side of the source 13 from the surface of the drain 14 away from the substrate 11. In this way, the contact area of the source 13 and the drain 14 with the conductor region 152 can be ensured to reduce the impedance of the contact between the source 13 and the drain 14 and the semiconductor layer 15 as much as possible.

[0107] The drain 14 includes a first contact region 141 and a second contact region 142, the first contact region 141 is spaced apart from the second contact region 142, and the second contact region 142 is located on the side of the first contact region 141 away from the source 13. The conductor region 152 of the semiconductor layer 15 is in contact with the first contact region 141, and the pixel electrode 19 is in contact with the second contact region 142 through a via hole. Since the first contact region 141 and the second contact region 142 are arranged in a spaced apart manner, the connection part of the pixel electrode 19 in the via hole will not be in direct contact with the conductor region 152 of the semiconductor layer 15, thereby avoiding affecting the thin film transistor.

[0108] In the embodiment, the conductor region 152 of the semiconductor layer 15 can completely cover the source 13 in a direction perpendicular to the substrate 11, or can partially cover the source 13, which is not limited here. To ensure good working performance of the semiconductor layer 15, the contact area of the conductor region 152 with the source 13 and the contact area of the conductor region 152 with the drain 14 are consistent.

[0109] It can be understood that the array substrate 1 of the embodiment of the present application can also include other conventional film layers, such as a buffer layer between the substrate 11 and the light shielding layer 12, a planarization layer on the side of the pixel electrode 19 away from the substrate 11, etc., which are not described here.

[0110] The above detailed the embodiments of the present application, the principles and implementation of the present application are described by applying specific examples; the above embodiment is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation and application range will be changed; in summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method for fabricating an array substrate, characterized in that, The method comprises the following steps: S101, providing a substrate, and sequentially laminating a light shielding film, a first metal film and a first photoresist film on the substrate; S102, exposing the first photoresist film, the first metal film and the light shielding film by using a first mask; wherein the first mask comprises a completely transparent area, a partially transparent area and a non-transparent area; S103, removing the first photoresist film and the first metal film corresponding to the completely transparent area and the partially transparent area, to form a source electrode and a drain electrode; S104, removing the light shielding film corresponding to the completely transparent area, to form a light shielding layer, and the material of the light shielding layer is a non-metal light shielding material; S105, removing the remaining first photoresist film; S2, forming a laminated semiconductor layer, a gate insulating layer and a gate electrode on the source electrode, the drain electrode and the light shielding layer by using a second mask process; S3, forming a dielectric layer on the gate electrode and the substrate, and forming a via hole exposing the drain electrode on the dielectric layer by using a third mask process; S4, forming a pixel electrode on the dielectric layer by using a fourth mask process, and the pixel electrode is electrically connected to the drain electrode through the via hole; The S2 comprises the following steps: S201, forming a semiconductor film on the source electrode, the drain electrode, the light shielding layer and the substrate, and the semiconductor film comprises a conductorized area corresponding to the source electrode and the drain electrode; S202, conductorizing a part of the semiconductor film corresponding to the conductorized area, to form a first conductor part and a second conductor part, and the part of the semiconductor film not being conductorized is a channel part, the first conductor part and the second conductor part are located on both sides of the channel part and are in contact with the source electrode and the drain electrode respectively, the first conductor part extends from the surface of the side of the source electrode away from the substrate to the side of the side of the source electrode close to the drain electrode and is in contact with the light shielding layer, the second conductor part extends from the surface of the side of the drain electrode away from the substrate to the side of the side of the drain electrode close to the source electrode and is in contact with the light shielding layer, and the channel part is connected between the first conductor part and the second conductor part in a bent manner and is arranged straightly; S203, sequentially laminating a gate insulating film, a second metal film and a second photoresist film on the semiconductor film; S204, exposing the second photoresist film, the second metal film, the gate insulating film and the semiconductor film by using a second mask; wherein the second mask comprises a completely transparent area and a non-transparent area; S205, removing the second photoresist film, the second metal film, the gate insulating film and the semiconductor film corresponding to the completely transparent area, to form the gate electrode, the gate insulating layer and the semiconductor layer; S206, removing the remaining second photoresist film.

2. The method of manufacturing an array substrate according to claim 1, wherein The gate electrode, the gate insulating layer and the semiconductor layer form a stacked structure in a direction perpendicular to the substrate, and the edge of the stacked structure overlaps with the source electrode and the drain electrode. The gate insulating layer and a projection of the gate on the substrate fall within a range of a projection of the semiconductor layer on the substrate.

3. An array substrate, characterized by, The array substrate comprises: a substrate; a source electrode disposed on the substrate; a drain electrode disposed on the substrate and spaced apart from the source electrode; a semiconductor layer disposed between the source electrode and the drain electrode and having an edge extending to a side of the source electrode and the drain electrode away from the substrate; a gate insulating layer disposed on a side of the semiconductor layer away from the substrate; a gate disposed on a side of the gate insulating layer away from the substrate; The gate, the gate insulating layer and the semiconductor layer form a stacked structure in a direction perpendicular to the substrate, and an edge of the stacked structure overlaps with the source electrode and the drain electrode. The array substrate further comprises a dielectric layer and a pixel electrode, and a light-shielding layer between the substrate and the source electrode and the drain electrode, the light-shielding layer being made of a non-metal light-shielding material, the source electrode and the drain electrode being disposed on a side surface of the light-shielding layer away from the substrate; the dielectric layer being disposed on a side of the gate away from the substrate, and the pixel electrode being disposed on a side of the dielectric layer away from the substrate. The semiconductor layer comprises a channel portion, a first conductor portion and a second conductor portion, the channel portion being located between the source electrode and the drain electrode, the first conductor portion and the second conductor portion being located on two sides of the channel portion and contacting the source electrode and the drain electrode respectively, the first conductor portion extending from a side surface of the source electrode away from the substrate to a side surface of the source electrode close to the drain electrode and contacting the light-shielding layer, the second conductor portion extending from a side surface of the drain electrode away from the substrate to a side surface of the drain electrode close to the source electrode and contacting the light-shielding layer, the channel portion being connected between the first conductor portion and the second conductor portion in a bent manner, and the channel portion being arranged in a straight manner. The drain electrode comprises a first contact area and a second contact area, the first contact area being spaced apart from the second contact area, and the second contact area being located on a side of the first contact area away from the source electrode, wherein the conductor portion corresponding to the drain electrode contacts the first contact area, and the pixel electrode contacts the second contact area. In the direction perpendicular to the substrate, edges of the semiconductor layer, the gate insulating layer and the gate overlap with the source electrode and the drain electrode.

4. The array substrate of claim 3, wherein, The gate insulating layer and a projection of the gate on the substrate fall within a range of a projection of the semiconductor layer on the substrate.

5. The array substrate of claim 4, wherein, ​

Images